JP5556584B2 - Inverter drive - Google Patents

Description

  The present invention relates to an inverter drive device in which power transmission and signal transmission are performed between electrically insulated circuits.

  Conventionally, power transformers for insulated switching power supplies such as push-pull converters and flyback converters have been used as power transmission means between electrically isolated circuits, and signal transmission between electrically isolated circuits As a means, an insulated communication element such as a photocoupler or a magnetic coupler has been used. That is, different insulating parts are used for each application of power transmission and signal transmission.

  For example, Patent Documents 1 and 2 are known as prior art documents disclosing a configuration capable of performing power transmission and signal transmission between electrically insulated circuits.

JP 58-103095 A JP 2009-44837 A

  Regardless of FA equipment or in-vehicle equipment, miniaturization of power electronics units is being promoted, and miniaturization of circuit boards inside the units is also required. However, in the power electronics unit, in order to prevent electric shock and leakage due to dielectric breakdown, a high voltage circuit unit such as a drive circuit for driving a motor, an actuator, etc., and a control circuit (for example, a microcomputer (hereinafter referred to as “microcomputer”)) It is necessary to electrically insulate the low voltage circuit part such as The distance required for insulation is standardized by JIS or the like, and the insulation distance becomes longer in proportion to the potential difference between the high voltage / low voltage circuit sections. Therefore, in power electronics units that handle high voltages, the insulation distance tends to be long, and the insulation components on the circuit board inside the unit must also use large physiques to secure the insulation distance, It is not easy to reduce the size of the circuit board inside the unit.

  An example of such a power electronics unit is an inverter driving device. FIG. 1 shows an example of an inverter driving device. The inverter driving device 100 shown in FIG. 1 has a low voltage circuit 11 as a low voltage circuit unit, and has a lower arm circuit 12 and an upper arm circuit 13 as a high voltage circuit unit.

  The power supply IC 2A of the low voltage circuit 11 generates the power supply voltage VB1 on the lower arm circuit 12 side via the transformer 10A by controlling the driving of the transistors 3A and 4A. The power supply voltage VB1 is an operation power supply for the drive circuit 19A that drives the semiconductor switching element 17A such as an IGBT. Similarly, the power supply IC 2B of the low-voltage circuit 11 generates the power supply voltage VB2 on the upper arm circuit 13 side via the transformer 10B by controlling the driving of the transistors 3B and 4B. The power supply voltage VB2 is an operation power supply for the drive circuit 19B that drives the semiconductor switching element 17B such as an IGBT.

  On the other hand, the microcomputer 1 of the low-voltage circuit 11 controls the operation of the drive circuit 19A that drives the semiconductor switching element 17A via the photocoupler 11A by PWM control of the drive of the transistor 5A. The photocoupler 11A is a signal transmission element for transmitting a drive signal for the semiconductor switching element 17A. Similarly, the microcomputer 1 controls the operation of the drive circuit 19B that drives the semiconductor switching element 17B via the photocoupler 11B by PWM control of the drive of the transistor 5B. The photocoupler 11B is a signal transmission element for transmitting a drive signal for the semiconductor switching element 17B.

  As described above, the inverter driving apparatus 100 includes the transformer 10A and the photocoupler 11A as the power transmission means and the signal transmission means between the low voltage circuit 11 and the lower arm circuit 12, and the low voltage circuit 11 and the upper arm circuit 13 are connected to each other. A transformer 10B and a photocoupler 11B are provided as power transmission means and signal transmission means.

  However, in the configuration of the inverter driving apparatus illustrated in FIG. 1, it is difficult to reduce the size of the circuit board because a power transmission unit and a signal transmission unit are required for each arm circuit.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an inverter drive device that can easily realize downsizing of a circuit board even if it has a configuration for transmitting power and signals between electrically isolated circuits. .

In order to achieve the above object, an inverter drive device according to the present invention includes:
A conversion circuit for converting an input signal into two complementary waveform signals;
A lower arm circuit for transmitting a drive signal to the first semiconductor switching element;
An upper arm circuit for transmitting a drive signal to the second semiconductor switching element;
A transformer for supplying power to the lower arm circuit and the upper arm circuit;
The two waveform signals are biphase encoded signals,
The transformer transmits one of the two waveform signals to the lower arm circuit, and transmits the other waveform signal to the upper arm circuit ,
Each of the lower arm circuit and the upper arm circuit,
Decoding means for decoding the bi-phase encoded signal;
The present invention is characterized by comprising a dead time giving means for giving a dead time to the decoded signal using a clock component included in the biphase encoded signal .

  According to the present invention, it is possible to easily reduce the size of the circuit board even when the power transmission and the signal transmission are performed between electrically insulated circuits.

1 is a configuration diagram of an inverter drive device 100. FIG. It is a block diagram of the inverter drive device 200 which is one Embodiment of this invention. It is a signal waveform of each part of the inverter drive device 200. 2 is a configuration diagram of a dead time generation circuit 60. FIG. It is a signal waveform when dead times DT1 and DT2 are given. It is a block diagram of the motor drive device 300 which is an Example of the inverter drive device of this invention.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. FIG. 2 is a configuration diagram of an inverter driving device 200 according to an embodiment of the present invention. FIG. 3 is a signal waveform of each part of the inverter driving device 200. Each component shown in FIG. 2 is mounted on a substrate to constitute a circuit board.

  The inverter driving device 200 using SiC includes a half bridge circuit composed of the semiconductor switching elements 17A and 17B, and drives the semiconductor switching elements 17A and 17B, thereby causing the node 56, which is a connection point between 17A and 17B, to be connected to the node 56. A current flowing through a load (not shown) to be connected is controlled. The semiconductor switching elements 17A and 17B and other transistors described later are semiconductor elements capable of conducting and interrupting current. Specific examples thereof include transistors such as IGBTs, MOSFETs, and bipolar transistors. Hereinafter, the semiconductor switching element 17A is referred to as a lower arm element 17A, and the semiconductor switching element 17B is referred to as an upper arm element 17B.

  The inverter driving device 200 includes a low voltage circuit 211 as a low voltage circuit unit, and a lower arm circuit 212 and an upper arm circuit 213 as a high voltage circuit unit. More specifically, the inverter drive device 200 includes a microcomputer 31, a transmission circuit 61, a push-pull converter 62, and a reception circuit 63.

  The microcomputer 31 is a control unit that outputs a PWM signal S1 for driving the lower arm element 17A and the upper arm element 17B as an input signal input to the encoding IC 32 of the transmission circuit 61.

  The encoding IC 32 of the transmission circuit 61 includes a biphase encoding circuit 33 that biphase encodes the PWM signal S1 in accordance with the clock signal CLK1. The encoding IC 32 of the transmission circuit 61 outputs a biphase encoded signal S2A obtained by the biphase encoding circuit 33 biphase encoding the PWM signal S1 as a drive signal for the low-side MOSFET 35A of the push-pull converter 62. To do. The encoding IC 32 outputs a complementary signal S2B (biphase encoded signal S2B) obtained by inverting the biphase encoded signal S2A by the inverting circuit 34 as a drive signal for the high-side MOSFET 35B of the push-pull converter 62 (FIG. 5). 3).

  The low side MOSFET 35A outputs a biphase encoded signal S3A obtained by inverting the level of the biphase encoded signal S2A as a low side input voltage signal applied to the low side primary winding 37A of the transformer 36. On the other hand, the high side MOSFET 35B outputs a biphase encoded signal S3B obtained by inverting the level of the biphase encoded signal S2B as a high side input voltage signal applied to the high side primary winding 37B of the transformer 36.

  That is, the PWM signal S1 is converted into two biphase-encoded signals S3A and S3B that are complementary to each other by the transmission circuit 61, the low-side MOSFET 35A, and the high-side MOSFET 35B.

  The push-pull converter 62 includes a power transformer 36 having one input and two outputs so that power and signals can be transmitted to the lower arm circuit 212 and the upper arm circuit 213, respectively. The input voltage VC is supplied to the center tap on the primary side of the transformer 36. The input voltage VC is a power supply voltage on the low voltage circuit 211 side. The anodes of diodes 42A and 43A are connected to both ends of the secondary low-side winding (38A, 39A) on the secondary side of the transformer 36, and the secondary winding on the secondary side of the transformer 36 (38B, 39B). ) Are connected to the anodes of diodes 42B and 43B. The negative side terminal of the electrolytic capacitor 44A and the emitter of the lower arm element 47A are connected to the low-side center tap on the secondary side of the transformer 36, and the high-side center tap on the secondary side of the transformer 36 is connected to the electrolytic capacitor 44B. The negative terminal and the emitter of the upper arm element 47B are connected. The positive terminal of the electrolytic capacitor 44A is connected to the cathodes of the diodes 42A and 43A, and the positive terminal of the electrolytic capacitor 44B is connected to the cathodes of the diodes 42B and 43B.

  Therefore, according to this configuration, the transformer 35 transmits the power of the power supply voltage VB1 on the secondary lower arm circuit 212 side based on the primary input voltage VC and the biphase encoded signals S3A and S3B, Power transmission of the power supply voltage VB2 on the secondary side upper arm circuit 213 side can be performed. The transformer 36 capable of supplying power to both the lower arm circuit 212 and the upper arm circuit 213 uses the biphase encoded signal S3A as the output waveform signal S4A output from the low-side secondary winding (38A, 39A). The bi-phase encoded signal S3B can be transmitted to the upper arm circuit 213 as the output waveform signal S4B output from the high-side secondary winding (38B, 39B) as well as being transmitted to the arm circuit 212 (see FIG. 3).

  The receiving circuit 63 includes a low-side drive IC 49A that drives the lower arm element 47A according to the output waveform signal S4A, and a high-side drive IC 49B that drives the upper arm element 47B according to the output waveform signal S4B. The drive IC 49A includes a bi-phase decoding circuit 48A that decodes the bi-phase encoded output waveform signal S4A, and the drive IC 49B includes a bi-phase decoding circuit 48B that decodes the bi-phase encoded output waveform signal S4B. Yes.

  The drive IC 49A of the lower arm circuit 212 outputs a gate signal S7A obtained by the biphase decoding circuit 48A demodulating the output waveform signal S4A as a drive signal of the lower arm element 47A. The biphase decoding circuit 48A demodulates the output waveform signal S4A to generate a predrive signal S6A. The high side transistor 46A is turned on / off based on the pre-drive signal S6A. When the high side transistor 46A is on, the lower arm element 47A is on, and when the high side transistor 46A is off, the lower arm element 47A is off. The same applies to the upper arm circuit 213. That is, the drive IC 49B outputs the gate signal S7B obtained by the biphase decoding circuit 48B demodulating the output waveform signal S4B as a drive signal for the upper arm element 47B (see FIG. 3).

  Therefore, according to the configuration of FIG. 2, the photocouplers 17A and 17B exemplified as signal transmission means in FIG. 1 can be eliminated. Further, power transmission and signal transmission to the upper arm circuit and the lower arm circuit can be performed by one transformer 36. That is, the circuit board can be easily reduced in size, and the number of parts and cost can be easily reduced.

  By the way, if each of the lower arm circuit and the upper arm circuit of the inverter driving device according to the present invention is provided with a dead time giving means, it is preferable in that it prevents generation of a through current flowing through the upper arm element and the lower arm element. is there. This dead time giving means gives a dead time to a signal obtained by decoding a biphase encoded signal by using a clock component included in the biphase encoded signal.

  For example, in the case of FIG. 2, the phase difference of bi-phase encoded output waveform signals S4A and S4B transmitted from the secondary side of the transformer 36 to the lower arm circuit 212 and the upper arm circuit 213 is inverted by 180 °. However, the phase difference between the clock components is zero. Therefore, the phase difference of the clock signal (hereinafter referred to as “clock signal CLK2”) generated by extracting from the clock component is also zero. That is, if the dead time is generated using the clock signal CLK2, the dead time can be given to each of the gate signals S7A and S7B without delay. A specific example of the dead time giving means is shown in FIG.

  FIG. 4 is a configuration diagram of the dead time generation circuit 50. The dead time generation circuit 50 is a dead time giving means including two stages of D flip-flops 61 and 62 and an AND circuit 63. Depending on the number of D flip-flops, the length of the dead time can be expanded and contracted, and the length of the dead time can be increased by the increased number. The output signal S9 of the dead time generation circuit 50 is generated as the above-described gate signals S7A and S7B (or predrive signals S6A and S6B).

  FIG. 5 shows signal waveforms when dead times DT1 and DT2 are given. The lower-arm biphase decoding circuit 48A demodulates the biphase-encoded output waveform signal S4A to generate a demodulated PWM signal S8A. The lower arm side dead time generation circuit 50A generates a dead time giving PWM signal S9A delayed by a dead time DT2 from the rising edge of the demodulated PWM signal S8A. The drive IC 49A outputs a dead time giving PWM signal S9A as a gate signal S7A applied to the gate of the lower arm element 47A. When the dead time giving PWM signal S9A is at a high level, the lower arm element 47A is turned on, and when the dead time giving PWM signal S9A is at a low level, the lower arm element 47A is turned off.

  Similarly, the bi-phase decoding circuit 48B on the upper arm side demodulates the bi-phase encoded output waveform signal S4B to generate a demodulated PWM signal S8B. The dead time generating circuit 50B on the upper arm side generates a dead time giving PWM signal S9B delayed by a dead time DT1 from the rising edge of the demodulated PWM signal S8B. The drive IC 49B outputs a dead time giving PWM signal S9B as the gate signal S7B applied to the gate of the upper arm element 47B. When the dead time giving PWM signal S9B is at a high level, the upper arm element 47B is turned on, and when the dead time giving PWM signal S9B is at a low level, the upper arm element 47B is turned off.

  Therefore, in general, a clock circuit using an oscillator such as a crystal is required to give an accurate dead time. However, by providing the above-described dead time providing means, an accurate dead time can be obtained even without such a clock circuit. Can be given a dead time.

  FIG. 6 is a configuration diagram of a motor driving device 300 that is an embodiment of the inverter driving device of the present invention. The motor drive device 300 is a drive device that drives the motor 80, and includes an inverter circuit composed of semiconductor switching elements SW1 to SW6 (for example, IGBT) and a drive circuit unit 70 that drives the inverter circuit. Yes. The drive circuit unit 70 includes an MCU 71, a P / S-IC (72U, 72V, 72W), a transformer (73U, 73V, 73W), and a pre-driver (74U, 74V, 74W).

  The MCU 71 is a microcomputer that outputs a PWM signal for driving the motor 80 to the P / S-IC of each phase. The P / S-IC 72U is a power supply IC that bi-phase encodes the PWM signal output from the MCU 71 and drives the transformer 73U with the bi-phase encoded signal. The pre-drivers 74U1 and 74U2 are operated with the power output from the transformer 73U. Further, the pre-drivers 74U1 and 74U2 that receive and decode the signal output from the transformer 73U give dead time to drive the semiconductor switching elements SW1 and SW2 such as IGBTs. The same applies to the other V and W phases. According to such a configuration, the motor 80 can be driven by the three-phase alternating current generated by the switching operation of the semiconductor switching elements SW1 to SW6 using the power supply voltage E1 as the operation power supply voltage.

  This configuration can also be applied to driving devices such as motors for FA devices, motors for household electrical appliances such as air conditioners and refrigerators, and so-called hybrid vehicles that use a motor and an engine together, and vehicle motors such as electric vehicles.

  The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the present invention. Can be added.

  For example, as an example of the present invention, the case of a motor drive device has been described as an example, but the present invention can also be applied to a switching power supply device.

10A, 10B Transformer 11A, 11B Photocoupler 17A, 47A Lower arm element (semiconductor switching element)
17B, 47B Upper arm element (semiconductor switching element)
19A, 19B Drive circuit 31 Microcomputer 32 Encoding IC
33 Biphase encoding circuit 33
36 transformer 49A, 49B drive IC
50 Dead time generation circuit 61, 62 D flip-prop 70 Drive circuit section 80 Motor 100, 200 Inverter drive device 300 Motor drive device S1 PWM signal S2A, S2B, S3A, S3B, S4A, S4B Biphase encoded signal S7A, S7B Gate signal

Claims (1)

A conversion circuit for converting an input signal into two complementary waveform signals;
A lower arm circuit for transmitting a drive signal to the first semiconductor switching element;
An upper arm circuit for transmitting a drive signal to the second semiconductor switching element;
A transformer for supplying power to the lower arm circuit and the upper arm circuit;
The two waveform signals are biphase encoded signals,
The transformer transmits one of the two waveform signals to the lower arm circuit, and transmits the other waveform signal to the upper arm circuit ,
Each of the lower arm circuit and the upper arm circuit,
Decoding means for decoding the bi-phase encoded signal;
An inverter drive device comprising: a dead time giving means for giving a dead time to a decoded signal using a clock component included in a biphase encoded signal .

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