JP5545106B2 - Amplifier circuit and radio receiving apparatus having the same - Google Patents

Description

  The present invention relates to an amplifier circuit and a wireless receiver having the amplifier circuit.

  The amplifier circuit is provided, for example, in the RF circuit unit of the wireless receiver, and amplifies the RF reception signal to a desired amplitude. For this purpose, the RF gain control circuit detects the output level of the amplifier circuit and automatically controls the gain of the amplifier circuit so as to obtain a desired amplitude.

  That is, the RF gain control circuit increases the gain of the amplifier circuit when the input level of the received signal is small, and controls the gain of the amplifier circuit small when the input level is high.

  Such a variable gain amplifier circuit is described in Patent Documents 1-3 and Non-Patent Document 1.

Japanese Patent Laid-Open No. 2003-243554 JP 2007-259409 A JP-A-8-307159

Takae Sakai, et al. "A Digital TV Receiver RF and BB Chipset with Adaptive Bias- Current Control for Mobile Applications," ISSCC Dig. Tech. Papers, pp. 212-213, Feb., 2007.

  However, the RF reception signal may include an interference wave in the vicinity of the desired wave band in addition to the desired wave. If the input level of the disturbing wave is larger than the desired wave, it is necessary to control the gain of the amplifier circuit according to the input level of the disturbing wave. At the same time, if the input level of the interference wave is large, it is desirable to increase the maximum input amplitude (dynamic range) at which the amplifier circuit can amplify the input signal without losing the linearity. Conversely, it is desirable to reduce the maximum input amplitude.

  However, if the gain changes at the same time when the maximum input amplitude of the amplifier circuit is controlled, reception is temporarily disabled before the gain returns.

  Accordingly, an object of the present invention is to provide an amplifier circuit capable of independently controlling the gain and the maximum input amplitude, and a wireless receiver using the amplifier circuit.

A first aspect of the amplifier circuit includes a common source transistor having an input signal input to a gate and a variable gate width, a variable current source provided between a drain of the common source transistor and a power source, An amplifier having an output terminal connected to a connection node with a current source, and a variable resistance load provided between the output terminal and a reference DC power source;
An amplifier control circuit for controlling a gate width of the common source transistor, a current value of the variable current source, and a resistance value of the variable resistance load based on a gain control signal and a maximum input amplitude control signal;
The amplifier control circuit controls the current value in proportion to the gain control signal and the maximum input amplitude control signal, and is proportional to the gain control signal and in inverse proportion to the maximum input amplitude control signal. A first control is performed to control the width and keep the resistance value constant regardless of the gain control signal and the maximum input amplitude control signal.

  According to the first aspect, the gain and the maximum input amplitude can be controlled independently.

It is a block diagram of the radio | wireless receiver which has an amplifier circuit in 1st this Embodiment. It is a figure which shows the electromagnetic wave condition of an input signal. It is a figure which shows the example of a characteristic of the preferable amplifier according to a radio wave condition. It is a block diagram of the amplifier circuit in this Embodiment. It is a relationship diagram of the drain current with respect to the gate voltage of a common source transistor. It is a figure which shows the relationship between the gain and current consumption in an amplifier. It is a figure which shows the control type | formula of each control circuit 14A, 14B, 14C of the amplifier control circuit in 1st Embodiment. It is a figure which shows the characteristic of the gain and maximum input amplitude V1dB in 1st Embodiment. It is a figure which shows the change by the control of KV1dB performed corresponding to the change of a certain radio wave state. It is a block diagram of the receiver in 2nd Embodiment. It is a figure which shows the control type | formula of each control circuit 15A, 15B, 15C of the control circuit 15 of the amplifier in 2nd Embodiment. It is a figure which shows the characteristic of the gain G1 and the largest input amplitude increase / decrease KV1dB in 2nd Embodiment.

  FIG. 1 is a configuration diagram of a radio reception apparatus having an amplifier circuit according to the first embodiment. The high frequency input signal RFin received by the antenna is input to the amplifier 12 of the RF amplifier circuit 10 and amplified. The output S12 of the amplifier 12 is multiplied by the local clock LO by the mixer 16 and down-converted. The mixer output S16 is extracted only in a desired frequency band by a channel selection filter 18 made of, for example, an LPF that passes a low frequency. The output S18 of the filter is amplified by the IF amplifier circuit 20 and converted into a digital signal S20d by the AD conversion circuit 22. This digital signal S20d is demodulated and decoded by the demodulator 24 at the subsequent stage.

  The RF amplifier circuit 10 includes an amplifier 12 composed of a common source transistor, which will be described later, and an amplifier control circuit 14 that supplies the amplifier 12 with a resistance control signal R_CN, a current control signal IB_CN, and a gate width control signal β_CN. Based on the gain control signal G1 and the maximum input amplitude control signal V1dB, the amplifier control circuit 14 generates a resistance control signal R_CN, a current control signal IB_CN, and a gate width control signal β_CN by an algorithm described later. Thereby, the gain of amplifier 12 and the maximum input amplitude can be controlled independently.

  The RF level detection circuit 26 detects the amplitude of the output signal S16 of the mixer 16, and supplies the detected RF level to the RF gain control circuit 28. The RF gain control circuit 28 generates gain control signals G1 and G2 so that the signal level of the mixer output signal S16 becomes a desired RF target level RFT, and outputs the gain control signals G1 and G2 to the amplifier control circuit 14 and the mixer 16, respectively. The amplifier 12 is controlled to a gain corresponding to the gain control signal G1 from the amplifier control circuit 14, and similarly, the mixer 16 is also controlled to a gain corresponding to the gain control signal G2.

  The output signal S20 of the IF amplifier circuit 22 is digitized, and the IF level detection circuit 30 detects the signal level of the output signal S20 from the digitized signal S20d. Then, the IF gain control circuit 32 generates the second gain control signals G3 and G4 according to the detected signal level so that the signal level becomes a desired target level, and the filter 18 and the IF amplification circuit. 20 is output.

  The maximum input amplitude increase / decrease control circuit 34 generates a signal level of the output signal S16 detected by the RF level detection circuit 26, a signal level of the output signal S20 detected by the IF level detection circuit 30, and a first level generated by the IF gain control circuit 32. Based on the gain control signals G3 and G4 of 2, the ratio UDR of the interference wave to the desired wave is obtained, and the maximum input amplitude increase / decrease control signal KV1dB is generated according to the ratio UDR. As will be described later, when the interference wave is large and the ratio UDR is large, the maximum input amplitude increase / decrease control signal KV1dB is increased, and when the interference wave is small and the ratio UDR is small, KV1dB is decreased.

  The maximum input amplitude increase / decrease control circuit 34 controls the RF target level RFT in accordance with the control of the maximum input amplitude increase / decrease control signal KV1dB. In other words, when KV1dB is reduced, the RF target level RFT is also reduced, and when KV1dB is increased, RFT is also increased.

  The maximum input amplitude calculation circuit 36 calculates the maximum input amplitude control signal V1dB based on the gain control signal G1 and the maximum input amplitude increase / decrease control signal KV1dB, and outputs the maximum input amplitude control signal V1dB to the amplifier control circuit 14.

  FIG. 2 is a diagram illustrating a radio wave condition of the input signal. FIG. 2 shows four radio wave conditions. FIG. 3 is a diagram showing an example of a preferable amplifier characteristic corresponding to the radio wave condition. In FIG. 3, the radio wave conditions (1) to (4) of FIG. 2 are shown. In FIG. 3, the horizontal axis represents the gain G1, and the vertical axis represents the maximum input amplitude V1dB.

  Here, the maximum input amplitude V1dB is as follows. When the input level inputted to the amplifier 14 is increased, the output level becomes an amplified level according to the gain. The relationship between the input level and the output level is a linear relationship with the gain as the slope. However, the output level begins to saturate when the input level exceeds a certain value. Therefore, the input level at which the output level decreases by 1 dB from the linear output level due to the saturation characteristic of the output level is referred to as input P1dB, and this input P1dB is the maximum input amplitude V1dB. In other words, the maximum input amplitude V1dB corresponds to the dynamic range of the input signal that provides linear characteristics.

  FIG. 2 (1) shows a radio wave situation where the level of the desired wave is small and there is no interference wave. In this case, it is necessary to increase the gain of the amplifier 12, but the maximum input amplitude V1dB of the amplifier 12 may be small. This is because the amplifier does not distort even if the maximum input amplitude V1dB is lowered because the input level is low.

  FIG. 2 (2) shows a radio wave situation where the level of the desired wave is large and there is no interfering wave. In this case, the gain of the amplifier 12 can be lowered, but the maximum input amplitude V1dB needs to be increased.

  On the other hand, FIGS. 2 (3) and 2 (4) are cases where a large disturbance wave exists. In this case, since both input levels are high, it is necessary to increase the maximum input amplitude V1dB. However, any gain may be small. In this case, it is assumed that the level of the desired wave in FIG. 2 (3) is higher than the level of the desired wave in (1).

  Therefore, it is preferable to control the gain G1 and the maximum input amplitude V1dB of the amplifier according to the four radio wave conditions (1) to (4) in FIG. 2 as in the characteristic A shown in FIG. Furthermore, when the interference wave disappears from the state of the radio wave condition (3) and (4) and the radio wave condition becomes (1) and (2), the maximum input amplitude V1dB is lowered as much as possible, and the characteristic B ( It is desirable to control as in 1A) and 2A. Conversely, when the radio wave condition (1) (2) changes to the radio wave condition (3) (4), it is desirable to increase the maximum input amplitude V1dB corresponding to the high level of the interference wave.

  Thus, in order to change the gain G1 and the maximum input amplitude V1dB of the amplifier according to various radio wave conditions, it is desirable that the gain G1 and the maximum input amplitude V1dB of the amplifier can be controlled independently.

  FIG. 4 is a configuration diagram of the amplifier circuit in the present embodiment. The amplifier circuit 14 includes an amplifier 12 composed of a common source transistor, and an amplifier control circuit 14 that supplies the amplifier 12 with a resistance control signal R_CN, a current control signal IB_CN, and a gate width control signal β_CN. The amplifier 12 includes a common-source transistor NMOS having a high-frequency input signal RFin input to the gate, a switch SW, a variable current source IB provided between a node Nd on the drain side of the transistor NMOS and the power supply VDD, a drain And a variable resistor R provided between the output terminal OUT connected to the side node Nd and a predetermined DC voltage V1. The transistor NMOS is composed of a plurality of parallel N-channel MOS transistor groups, and the total gate width of the transistor NMOS can be variably controlled by controlling the switch group SW provided in each drain.

  Note that an impedance matching circuit (not shown) and a gate bias circuit are provided at the gate of the transistor NMOS.

  The amplifier control circuit 14 includes a current control circuit 14A that generates a current control signal IB_CN based on the maximum input amplitude control signal V1dB and the gain control signal G1, and a resistance control circuit that generates a resistance control signal R_CN based on the gain control signal G1. 14B, and a gate width control circuit 14C that generates a gate width control signal β_CN based on the maximum input amplitude control signal V1dB and the gain control signal G1. The control method of these control circuits will be described below.

  FIG. 5 is a relationship diagram of the drain current with respect to the gate voltage of the common source transistor. The horizontal axis is the gate-source voltage Vgs, and the vertical axis is the drain-source current Ids. Since the source is grounded, the gate-source voltage Vgs becomes the gate voltage Vg. Since the source is grounded, the drain-source current Ids becomes the drain current Ids.

  When the gate-source voltage Vgs is increased from 0 V and exceeds the threshold voltage Vth, the drain current Ids begins to flow. Furthermore, when the gate-source voltage Vgs is increased, the drain current Ids increases rapidly.

  In the amplifier 12 using the common source transistor of FIG. 4, it is known that the following relationship exists between the gate-source voltage Vgs and the drain current Ids.

Here, W is the gate width, L is the gate length, μ is the mobility, and Cox is the gate oxide film capacitance per unit area. Equation 1 is known as the square law. In the Vgs-Ids characteristic of FIG. 5, the drain current Ids is proportional to the square of the gate overdrive voltage (Vgs-Vth), and the proportionality constant β depends on the gate width of the transistor. . FIG. 5A shows the case where the gate width of the transistor is narrow and β is small, and FIG. 5B shows the case where the gate width of the transistor is wide and β is large. Therefore, the drain current Ids is larger in FIG. 5B, and the slope of the quadratic curve is larger.

  The high-frequency input signal RFin is input as a change in the gate-source voltage, while the output signal RFout at the output terminal OUT is amplified according to the gain G1, which is the slope at the operating point of the Vgs-Ids characteristic.

And since the gain G of the common source amplifier is the slope of the Vgs-Ids characteristic that is a quadratic curve,
G = R × (dIds / dVgs)
According to Equation 1, the gain G is

It becomes. Here, R is the load resistance, and the current IB is the drain-source current Ids when the high-frequency input signal is in the no-signal state. That is, the current IB is the drain-source current Ids at the gate bias voltage Vgb, and the intersection of IB and Vgb is the operating point, and the slope of the operating point is the gain G.

  According to the equation of gain G in Equation 3, it can be understood that if the current IB is increased, the operating point in FIG. 5 becomes higher and the gain G increases. Further, it can be understood that if β proportional to the gate width is increased, the Vgs-Ids characteristic is changed as shown in FIG. 5B, and the gain G is similarly increased. Furthermore, if the variable resistance value R is increased, the product of the change in drain current caused by the change in the input signal and the variable resistance value R increases, and the amplitude of the output signal RFout increases, resulting in an increase in gain. .

  Next, the maximum input amplitude V1dB is the range of the gate-source voltage Vgs that can be linearly amplified from the gate bias voltage Vgb in FIG. 5, and is generally about 1/2 of (Vgb-Vth). is there. The maximum input amplitude V1dB is as follows.

Here, the constant α is generally ½.

  As is apparent from Equation 4 and FIG. 5, if the current IB is increased, the gate bias voltage Vgb at the operating point increases, and the maximum input amplitude V1dB increases. Conversely, if β that is proportional to the gate width is increased, the Vgs-Ids characteristic as shown in FIG. 5 (2) is obtained, so the gate bias voltage Vgs decreases and the maximum input amplitude V1dB decreases.

  Returning to FIG. 4, when the variable current IB is set to a predetermined value, the current IB flows through the transistor NMOS in the no-signal input state. When the input signal RFin is input, the drain current Ids of the transistor NMOS increases or decreases accordingly, and the increased or decreased drain current Ids flows through the load resistor R, and the output signal RFout is generated. Therefore, it can be understood that setting the current IB small leads to a reduction in the current consumption of the amplifier 12.

  Based on the above description, a control method of each control circuit 14A, 14B, 14C in the amplifier control circuit 14 will be described.

  First, in order to increase only the gain G1 by k without changing the maximum input amplitude V1dB, from equations (3) and (4), β and current IB proportional to the gate length may be increased by k. That is, the gate length is increased by k (the number of transistor NMOSs is increased by k), β is increased by k, and the current IB is correspondingly increased by k. As a result, although the operating point in FIG. 5 is not changed, the change in the drain current Ids generated in response to the change in the input signal RFin increases, the change in the output signal RFout generated by the load resistance R also increases, and the maximum input The amplitude V1dB does not change and only the gain G1 increases.

  Making the gain G1 only k times without changing the maximum input amplitude V1dB means that the control is performed in the horizontal axis direction in the characteristic diagram of FIG.

  As another method, in order to increase only the gain G1 by k without changing the maximum input amplitude V1dB, it is only necessary to increase only the resistance R by k from Equations (3) and (4). That is, in the case of k> 1, if the load resistance R is increased in the amplifier 12 of FIG. 4, the amplitude of the output RFout increases and consequently the gain G1 increases.

  Secondly, in order to increase only the maximum input amplitude V1dB k times without changing the gain G1, the current IB is increased k times and the gate length is 1 / k times (number of transistors NMOS) from Equations 3 and 4. To 1 / k times) and β to 1 / k times. In other words, if the current IB is increased by k times, the operating point in FIG. 5 is increased and the gain is increased when k> 1, but in order to increase β to 1 / k times, the state is changed from (2) to (1) in FIG. The gain increase is offset. However, it can be understood that the maximum input amplitude V1dB increases as the operating point increases.

  To increase only the maximum input amplitude V1dB by k without changing the gain G1 means to control in the vertical axis direction in the characteristic diagram of FIG. For example, control between (2) and (2A).

Third, in order to increase the gain G1 by k times and the maximum input amplitude V1dB by 1 / k times, that is, to increase only the gain G1 by k times without changing G1 * V1dB (= KV1dB), From equations (3) and (4), β may be multiplied by k ² without changing the current IB. That is, if k> 1, β is increased without changing the current IB as shown in FIGS. 5 (1) to (2), and the gain G1 increases and the maximum input amplitude V1dB decreases. Recognize.

  The gain G1 is multiplied by k and the maximum input amplitude V1dB is increased by 1 / k. In other words, the gain G1 only is multiplied by k without changing G1 * V1dB (= KV1dB). Means controlling gain on A or B.

  FIG. 6 is a diagram showing the relationship between gain and current consumption in the amplifier. The horizontal axis shows gain and the vertical axis shows current consumption. As described above, there are a method for increasing and decreasing the gain, a method for increasing and decreasing both IB and β, and a method for increasing and decreasing the resistance R. Therefore, considering the case of decreasing from a high gain to a low gain, first reducing both IB and β to reduce the gain, and then reducing the resistance R after IB and β reach the limits; There is a second method in which the resistance R is first decreased, and after the resistance R reaches the limit, both IB and β are decreased to decrease the gain. When increasing from a low gain to a high gain, the reverse is true.

  In the present embodiment, the gain G1 and the maximum input amplitude V1dB are independently controlled by the first method or the second method.

  However, if the first method and the second method shown in FIG. 6 are compared, it is clear that the second method is advantageous in order to save the current consumption of the amplifier 12. That is, firstly, reducing the current IB leads to power saving.

  Therefore, in a more preferred embodiment, the resistance R is varied when the gain G1 is controlled with G1 <G0 with the reference gain G0 as a boundary, and both IB and β are controlled when the gain G1 is controlled with G1 ≧ G0. Is variable. By controlling in this way, power saving can be achieved particularly during gain reduction control.

  FIG. 7 is a diagram illustrating control expressions of the control circuits 14A, 14B, and 14C of the amplifier control circuit according to the first embodiment. In each of the control circuits 14A, 14B, and 14C, there are shown control expressions when the gain G is larger and smaller than the reference value G0. R0, β0, and V0 are respective reference values. The amplifier control circuit 14 is supplied with a gain control signal G1, which is described as gain G in the control equation in the control circuit.

Solving the simultaneous equations of Equations 3 and 4 is as follows.
IB = G * V1dB / 2Rα
β = αRG / V1dB
Therefore, as shown in FIG. 6, when G = G0 and R = constant control, the current IB is controlled in proportion to the gain G and in proportion to the maximum input amplitude V1dB, and the gate width corresponding to β is proportional to the gain G. However, it is understood that the control should be performed in inverse proportion to the maximum input amplitude V1dB. In that case, the resistance R is controlled to a constant value R0.

  To control R while maintaining IB * β constant at G <G0 as shown in Fig. 6, the resistance R is controlled in proportion to the gain G, the current IB is proportional to V1dB, and β is inversely proportional to V1dB. And control.

  As described above, the gain G1 and the maximum input amplitude V1dB may be controlled independently only by the control with G ≧ G0 shown in FIG. Alternatively, the gain G1 and the maximum input amplitude V1dB may be controlled independently only by the control with G <G0 shown in FIG. Of course, it is more preferable to switch both control methods at the upper limit of G0 as shown in FIG.

  FIG. 8 is a diagram showing the characteristics of the gain and the maximum input amplitude V1 dB in the first embodiment. As in FIG. 3, the horizontal axis represents the gain G1, and the vertical axis represents the maximum input amplitude V1dB. As shown in FIG. 7, the amplifier circuit 12 can independently control the gain G1 and the maximum input amplitude V1dB. Therefore, it is possible to control to any gain and maximum input amplitude in the characteristics A and B shown in FIG.

The maximum input amplitude calculation circuit 36 in the receiver of FIG. 1 calculates the maximum input amplitude control signal V1dB from the maximum input amplitude increase / decrease control signal KV1dB and the gain control signal G1. The calculation formula is
V1dB = V1dB0 * (G0 / G1) * (KV1dB / KV1dB0) (Equation 5)
V1dB = V1dB0 + (G0 / G1) + (KV1dB / KV1dB0) (in dB notation)
It is. Here, V1dB0, G0, and KV1dB0 are respective reference values.

Next, the maximum input amplitude increase / decrease control circuit 34 in the receiving apparatus of FIG. 1 calculates the total of the RF level (V _RF ) of the signal S16, the IF level (V _IF ) of the signal S20 (S20d), and the gains G3 and G4. The ratio UDR (Undesired Desired Ratio) of the disturbing wave U to the desired wave D is obtained from the gain G _IF . Since the channel selection filter 18 removes the interference wave from the signal S16, and the IF level (V _IF ) of the signal S20 is amplified by the IF amplifier 20 and the filter 18 by a factor of G _IF , only the desired wave in the signal S16 is obtained. The signal level is V _IF / G _IF . Therefore, the ratio UDR of the disturbing wave to the desired wave is as follows.
UDR = V _RF / (V _IF / G _IF ) = V _RF * G _IF / V _IF
UDR = V _RF + G _IF −V _IF (in dB notation)
The maximum input amplitude increase / decrease control circuit 34 increases / decreases the maximum input amplitude increase / decrease control signal KV1dB corresponding to the increase / decrease of the ratio UDR, and the RF target signal RFT also increases / decreases as KV1dB increases / decreases. Increase and decrease respectively. For example, if the maximum value of KV1dB is KV1dBmax and the maximum allowable value of the ratio UDR is UDRmax, when KV1dB is controlled in three stages, KV1dB is controlled based on UDR as follows.
KV1dB = KV1dBmax (when UDRmax>UDR> UDRmax / 2)
KV1dB = KV1dBmax / 2 (when UDRmax / 2>UDR> UDRmax / 4)
KV1dB = KV1dBmax / 4 (when UDRmax / 4> UDR)
The above is expressed in dB as follows.
KV1dB = KV1dBmax (when UDRmax>UDR> UDRmax-6dB)
KV1dB = KV1dBmax-6dB (when UDRmax-6dB>UDR> UDRmax-12dB)
KV1dB = KV1dBmax-12dB (when UDRmax-12dB> UDR)
Further, assuming that the maximum value of the RF target level RFT is RFTmax, the maximum input amplitude increase / decrease control circuit 34 increases / decreases the RF target level RFT as follows according to the increase / decrease of KV1 dB.
RFT = RFTmax * (KV1dB / KV1dBmax)
RFT = RFTmax + (KV1dB-KV1dBmax) (in dB notation)
That is, the maximum input amplitude increase / decrease control circuit 34 similarly increases / decreases the RF target level RFT corresponding to the increase / decrease of KV1 dB.

From the above equation (5), the following relationship exists between the maximum input amplitude V1dB and the maximum input amplitude increase / decrease KV1dB.
(KV1dB / KV1dB0) = (V1dB / V1dB0) * (G1 / G0) (Equation 6)
Therefore, the maximum input amplitude increase / decrease control circuit 34 controls the characteristics A and B by controlling the maximum input amplitude increase / decrease KV1dB based on the ratio UDR (presence / absence of interference wave) of the interference wave to the desired wave. At that time, the maximum input amplitude increase / decrease control circuit 34 also increases / decreases the RF target level RFT in accordance with the increase / decrease of KV1 dB. Based on the RF target level RFT, the RF gain control circuit 28 controls the gain G1 and outputs it to the amplifier control circuit 14. Then, the maximum input amplitude calculation circuit 36 calculates the maximum input amplitude V1dB by Equation 5 based on the gain G1 and KV1dB, and outputs it to the amplifier control circuit 14.

  FIG. 9 is a diagram showing a change in a certain radio wave state and a change due to control of KV1 dB performed correspondingly. FIG. 9 shows a state (b) in which only the disturbing wave is halved and reduced by 6 dB from the state in which a strong disturbing wave exists in the initial state (a), and the maximum input amplitude increase / decrease control circuit 34 is KV1 dB accordingly. The control is shown in which ½ is reduced by 6 dB.

  FIG. 8 shows transitions of the gain G1 and the maximum input amplitude V1dB in three states (a), (b), and (c). The three states will be described below with reference to this as well.

  In the initial state (a), the interference wave level of the mixer output S16 is controlled to the RF target level due to the presence of a strong interference wave. On the other hand, the desired wave level of the IF output S20 is controlled to the IF target level. Therefore, when only the interference wave is reduced by 6 dB as shown in (b), the RF gain control circuit 28 increases the RF gains G1 and G2 to maintain the RF target level. In order to compensate for this, the IF gain control circuit 32 decreases the IF gains G3 and G4. The maximum input amplitude calculation circuit 36 decreases the maximum input amplitude V1dB according to the increase of the gain G1 when the state (a) is changed to (b). As shown in FIG. 8, by changing from (a) to (b), the gain G1 increases and the maximum input amplitude V1dB decreases.

  In the state (b), the maximum input amplitude increase / decrease control circuit 34 decreases KV1dB to -6 dB in response to the decrease of the ratio UDR. At the same time, the RF target level RFT is reduced by -6 dB. This enters state (c). As a result, the RF gain control circuit 28 decreases the RF gains G1 and G2 in response to the decrease in RFT, and the level of the mixer output S16 decreases by -6 dB. Further, the maximum input amplitude calculation circuit 36 controls the maximum input amplitude V1dB by Equation 5 in response to the decrease of -6 dB of KV1dB and the decrease of gain G1. That is, the maximum input amplitude calculation circuit 36 decreases the maximum input amplitude V1dB according to the increase in the gain G1 when the state (a) is changed to (b), but the decrease in KV1dB in the state (c) As the gain G1 decreases, the reduced maximum input amplitude V1dB is maintained. As shown in FIG. 8, only the gain G1 increases due to the change from (b) to (c).

  As shown in FIG. 8, after the interference wave is reduced, the state (a) is changed to (c), the gain G1 is kept constant, and only the maximum input amplitude V1dB is reduced. The power consumption can be reduced.

[Second Embodiment]
FIG. 10 is a configuration diagram of a receiving device according to the second embodiment. 1 differs from the first embodiment in that the maximum input amplitude increase / decrease control circuit 34 outputs the maximum input amplitude increase / decrease control signal KV1dB directly to the amplifier control circuit 15, and the amplifier control circuit 15 has the gain G1 and KV1dB. Based on the above, a resistance control signal R_CN, a current control signal I_CN, and a gate width control signal β_CN are generated. The rest of the configuration is the same as in FIG.

  FIG. 11 is a diagram illustrating control expressions of the control circuits 15A, 15B, and 15C of the amplifier control circuit 15 according to the second embodiment. As in FIG. 7, the control circuits 15A, 15B, and 15C show control formulas when the gain G is greater than and smaller than the reference value G0.

  Unlike FIG. 7, in the second embodiment, the maximum input amplitude increase / decrease control signal KV1dB is directly supplied to the amplifier control circuit 14, and each of the control circuits 15A, 15B, and 15C has their respective values based on KV1dB and the gain G. A current IB, a resistance R, and a gate width β are generated and supplied to the amplifier 14.

  The control equation of FIG. 11 is based on the equation (KV1dB / KV1dB0) = (V1dB / V1dB0) * (G1 / G0). It has been converted to a control expression. That is, the amplifier control circuit 15 in FIG. 7 is obtained by integrating the maximum input amplitude calculation circuit 36 and the amplifier control circuit 14 in the first embodiment in FIG.

  As shown in FIG. 11, when G = G0 and R = constant control as shown in FIG. 6, the current IB is controlled in proportion to the maximum input amplitude increase / decrease KV1dB, and the gate width corresponding to β is the gain G It can be seen that the control should be performed in proportion to the square and in inverse proportion to the maximum input amplitude amplification KV1 dB. In that case, the resistance R is controlled to a constant value R0.

  In addition, as shown in FIG. 6, in order to control R while maintaining IB * β constant at G1 <G0, resistance R is controlled in proportion to gain G, and current IB is proportional to KV1dB and inversely proportional to gain G. Β may be controlled in inverse proportion to KV1dB and in proportion to gain G.

  Similarly to the first embodiment, the gain G1 and the maximum input amplitude V1dB may be controlled independently only by the control with G ≧ G0 shown in FIG. Alternatively, the gain G1 and the maximum input amplitude V1dB may be controlled independently only by the control with G <G0 shown in FIG. Of course, it is more preferable to switch both control methods at the upper limit of G0 as shown in FIG.

  FIG. 12 is a diagram illustrating the characteristics of the gain G1 and the maximum input amplitude increase / decrease KV1dB in the second embodiment. 3 and 8, the horizontal axis represents the gain G1, and the vertical axis represents the maximum input amplitude V1dB. Further, FIG. 12 also shows an oblique axis of the maximum input amplitude increase / decrease KV 1 dB. Also in the second embodiment, as shown in FIG. 12, the amplifier circuit 12 can independently control the gain G1 and the maximum input amplitude increase / decrease KV1dB. As a result, the maximum input amplitude V1dB can be controlled independently. Can be controlled. Therefore, it is possible to control to an arbitrary gain and maximum input amplitude in the characteristics A and B shown in FIG.

  FIG. 12 shows the initial state (a) in FIG. 9, a state (b) in which only the interference wave is reduced by −6 dB, and a controlled state (c) in which the KV1dB is reduced by −6 dB and the RF target level RFT is also reduced by −6 dB. It is shown.

  In the receiving apparatus of FIG. 10, when the transition is made from the initial state (a) to the state (b) in which only the interference wave is −6 dB, the RF gain control circuit 28 tries to maintain the level of the output signal S16 of the mixer 16 at the RF target level RFT. As the gain G1 is increased. In response to this, the IF gain control circuit 32 decreases the IF gains G3 and G4. In state (b), since KV1dB has not been changed, the amplifier control circuit 15 controls the current IB and the gate width β so as to decrease the maximum input amplitude V1dB as the gain G1 increases.

  Then, in response to the state (b), the maximum input amplitude increase / decrease control circuit 34 decreases KV1 dB by -6 dB and RF target level RFT by -6 dB as the ratio UDR of the disturbing wave to the desired wave decreases. This is state (c). In the state (c), the RF gain control circuit 28 decreases the gains G1 and G2 due to a decrease in RFT of −6 dB. However, the amplifier control circuit 15 controls the current IB and the gate width β so that the maximum input amplitude V1dB does not change due to the decrease of the gain G1 and the decrease of −6 dB of KV1dB.

  As a result, as shown in FIG. 12, from state (a) to state (c), only the maximum input amplitude V1dB is reduced, and gain G1 is maintained. In other words, V1dB and G1 are controlled independently.

  As described above, only the conventional gain can be controlled, and the maximum input amplitude also fluctuates at the same time during gain control. However, according to the amplifier circuit of this embodiment, the gain and the maximum input amplitude can be controlled independently. . Therefore, by using such an amplifier circuit for the receiving device, it is possible to control the gain and the maximum input amplitude that are optimal for the radio wave condition.

  The above embodiment is summarized as follows.

(Appendix 1)
An input signal is input to the gate and connected to a common source transistor having a variable gate width, a variable current source provided between a drain and a power source of the common source transistor, and a connection node between the drain and the variable current source. And an amplifier having a variable resistance load provided between the output terminal and a reference DC power source,
An amplifier control circuit for controlling a gate width of the common source transistor, a current value of the variable current source, and a resistance value of the variable resistance load based on a gain control signal and a maximum input amplitude control signal;
The amplifier control circuit includes:
Controlling the current value in proportion to the gain control signal and the maximum input amplitude control signal, controlling the gate width in proportion to the gain control signal and inversely proportional to the maximum input amplitude control signal, An amplifier circuit that performs a first control to keep the resistance value constant regardless of a gain control signal and a maximum input amplitude control signal.

(Appendix 2)
In Appendix 1,
The amplification control circuit performs the first control when the gain control signal is greater than or equal to a reference gain,
When the gain control signal is less than the reference gain, the current value is controlled in proportion to the maximum input amplitude control signal, the gate width is controlled in inverse proportion to the maximum input amplitude control signal, and the gain control is performed. An amplifier circuit that performs a second control for controlling the resistance value in proportion to a signal.

(Appendix 3)
An input signal is input to the gate and connected to a common source transistor having a variable gate width, a variable current source provided between a drain and a power source of the common source transistor, and a connection node between the drain and the variable current source. And an amplifier having a variable resistance load provided between the output terminal and a reference DC power source,
An amplifier control circuit for controlling a gate width of the common source transistor, a current value of the variable current source, and a resistance value of the variable resistance load based on a gain control signal and a maximum input amplitude control signal;
The amplifier control circuit includes:
An amplifier circuit that controls the current value in proportion to the maximum input amplitude control signal, controls the gate width in inverse proportion to the maximum input amplitude control signal, and controls the resistance value in proportion to the gain control signal .

(Appendix 4)
In Appendix 1, 2, or 3,
A first gain control circuit that generates the gain control signal so as to keep the signal level of the first output signal generated at the output terminal at a desired target level, and outputs the gain control signal to the amplifier control circuit. An amplifier circuit.

(Appendix 5)
An input signal is input to the gate and connected to a common source transistor having a variable gate width, a variable current source provided between a drain and a power source of the common source transistor, and a connection node between the drain and the variable current source. And an amplifier having a variable resistance load provided between the output terminal and a reference DC power source,
Based on the gain control signal and the maximum input amplitude increase / decrease control signal proportional to the product of the gain control signal and the maximum input amplitude control signal, the gate width of the common source transistor, the current value of the variable current source, An amplifier control circuit for controlling the resistance value of the variable resistance load;
The amplifier control circuit includes:
Controlling the current value in proportion to the maximum input amplitude increase / decrease control signal, controlling the gate width in proportion to the square of the gain control signal and inversely proportional to the maximum input amplitude increase / decrease control signal, and An amplifier circuit that performs a first control to make the resistance value constant regardless of a control signal and a maximum input amplitude increase / decrease control signal.

(Appendix 6)
In Appendix 5,
The amplification control circuit performs the first control when the gain control signal is greater than or equal to a reference gain,
When the gain control signal is less than the reference gain, the current value is controlled in proportion to the maximum input amplitude increase / decrease control signal and inversely proportional to the gain control signal, and inversely proportional to the maximum input amplitude increase / decrease control signal. An amplifier circuit that controls the gate width in proportion to a control signal and performs second control to control the resistance value in proportion to the gain control signal.

(Appendix 7)
An input signal is input to the gate and connected to a common source transistor having a variable gate width, a variable current source provided between a drain and a power source of the common source transistor, and a connection node between the drain and the variable current source. And an amplifier having a variable resistance load provided between the output terminal and a reference DC power source,
Based on the gain control signal and the maximum input amplitude increase / decrease control signal proportional to the product of the gain control signal and the maximum input amplitude control signal, the gate width of the common source transistor, the current value of the variable current source, An amplifier control circuit for controlling the resistance value of the variable resistance load;
The amplifier control circuit includes:
Controlling the current value in proportion to the maximum input amplitude increase / decrease control signal and inversely proportional to the gain control signal; controlling the gate width inversely proportional to the maximum input amplitude increase / decrease control signal; An amplifier circuit that controls the resistance value in proportion to the gain control signal.

(Appendix 8)
In Appendix 5, 6 or 7,
A first gain control circuit that generates the gain control signal so as to keep the signal level of the first output signal generated at the output terminal at a desired target level, and outputs the gain control signal to the amplifier control circuit. An amplifier circuit.

(Appendix 9)
An amplifier circuit according to any one of appendices 1-4;
A mixer for multiplying a first output signal of the amplifier circuit by a local clock;
A channel selection filter that passes low frequency components of the second output signal of the mixer;
The maximum input amplitude increase / decrease control signal as the ratio of the disturbing wave to the desired wave obtained based on the signal level of the second output signal of the mixer and the signal level of the third output signal that has passed through the channel selection filter decreases. A maximum input amplitude increase / decrease control circuit which increases the maximum input amplitude increase / decrease control signal and increases the target level as the ratio increases,
And a maximum input amplitude generation circuit that generates the maximum input amplitude control signal proportional to the maximum input amplitude increase / decrease control signal and inversely proportional to the gain control signal.

(Appendix 10)
In Appendix 9,
A second amplifier for amplifying a third output signal of the channel selection filter;
A second gain control circuit that generates a second gain control signal and supplies the second gain control signal to the second amplifier so as to bring the fourth output signal of the second amplifier to a desired level;
The maximum input amplitude increase / decrease control circuit controls the desired wave of the interference wave based on the second gain control signal in addition to the signal level of the second output signal and the signal level of the third output signal. Receiving device for determining the ratio.

(Appendix 11)
An amplifier circuit according to any one of appendices 5 to 8,
A mixer for multiplying a first output signal of the amplifier circuit by a local clock;
A channel selection filter that passes low frequency components of the second output signal of the mixer;
The maximum input amplitude increase / decrease control signal as the ratio of the disturbing wave to the desired wave obtained based on the signal level of the second output signal of the mixer and the signal level of the third output signal that has passed through the channel selection filter decreases. And a maximum input amplitude increase / decrease control circuit for increasing the maximum input amplitude increase / decrease control signal and increasing the target level as the ratio increases.

(Appendix 12)
In Appendix 11,
A second amplifier for amplifying a third output signal of the channel selection filter;
A second gain control circuit that generates a second gain control signal and supplies the second gain control signal to the second amplifier so as to bring the fourth output signal of the second amplifier to a desired level;
The maximum input amplitude increase / decrease control circuit controls the desired wave of the interference wave based on the second gain control signal in addition to the signal level of the second output signal and the signal level of the third output signal. Receiving device for determining the ratio.

10: RF amplifier circuit 12: Amplifier 14: Amplifier control circuit 28: RF gain control circuit 34: Maximum input amplitude increase / decrease control circuit 36: Maximum input amplitude calculation circuit
G1: Gain V1dB: Maximum input amplitude
KV1dB: Maximum input amplitude increase / decrease RFT: Target level

Claims (6)

An input signal is input to the gate and connected to a common source transistor having a variable gate width, a variable current source provided between a drain and a power source of the common source transistor, and a connection node between the drain and the variable current source. And an amplifier having a variable resistance load provided between the output terminal and a reference DC power source,
An amplifier control circuit for controlling a gate width of the common source transistor, a current value of the variable current source, and a resistance value of the variable resistance load based on a gain control signal and a maximum input amplitude control signal;
The amplifier control circuit includes:
Controlling the current value in proportion to the gain control signal and the maximum input amplitude control signal, controlling the gate width in proportion to the gain control signal and inversely proportional to the maximum input amplitude control signal, An amplifier circuit that performs a first control to keep the resistance value constant regardless of a gain control signal and a maximum input amplitude control signal. An input signal is input to the gate and connected to a common source transistor having a variable gate width, a variable current source provided between a drain and a power source of the common source transistor, and a connection node between the drain and the variable current source. And an amplifier having a variable resistance load provided between the output terminal and a reference DC power source,
An amplifier control circuit for controlling a gate width of the common source transistor, a current value of the variable current source, and a resistance value of the variable resistance load based on a gain control signal and a maximum input amplitude control signal;
The amplifier control circuit includes:
An amplifier circuit that controls the current value in proportion to the maximum input amplitude control signal, controls the gate width in inverse proportion to the maximum input amplitude control signal, and controls the resistance value in proportion to the gain control signal . An input signal is input to the gate and connected to a common source transistor having a variable gate width, a variable current source provided between a drain and a power source of the common source transistor, and a connection node between the drain and the variable current source. And an amplifier having a variable resistance load provided between the output terminal and a reference DC power source,
Based on the gain control signal and the maximum input amplitude increase / decrease control signal proportional to the product of the gain control signal and the maximum input amplitude control signal, the gate width of the common source transistor, the current value of the variable current source, An amplifier control circuit for controlling the resistance value of the variable resistance load;
The amplifier control circuit includes:
Controlling the current value in proportion to the maximum input amplitude increase / decrease control signal, controlling the gate width in proportion to the square of the gain control signal and inversely proportional to the maximum input amplitude increase / decrease control signal, and An amplifier circuit that performs a first control to make the resistance value constant regardless of a control signal and a maximum input amplitude increase / decrease control signal. An input signal is input to the gate and connected to a common source transistor having a variable gate width, a variable current source provided between a drain and a power source of the common source transistor, and a connection node between the drain and the variable current source. And an amplifier having a variable resistance load provided between the output terminal and a reference DC power source,
Based on the gain control signal and the maximum input amplitude increase / decrease control signal proportional to the product of the gain control signal and the maximum input amplitude control signal, the gate width of the common source transistor, the current value of the variable current source, An amplifier control circuit for controlling the resistance value of the variable resistance load;
The amplifier control circuit includes:
Controlling the current value in proportion to the maximum input amplitude increase / decrease control signal and inversely proportional to the gain control signal; controlling the gate width inversely proportional to the maximum input amplitude increase / decrease control signal; An amplifier circuit that controls the resistance value in proportion to the gain control signal.   In claim 1 or 2, further,
  A first gain control circuit that generates the gain control signal so as to keep the signal level of the first output signal generated at the output terminal at a desired target level, and outputs the gain control signal to the amplifier control circuit. An amplifier circuit. An amplifier circuit according to claim 5 ;
A mixer for multiplying a first output signal of the amplifier circuit by a local clock;
A channel selection filter that passes low frequency components of the second output signal of the mixer;
The maximum input amplitude increase / decrease control signal as the ratio of the disturbing wave to the desired wave obtained based on the signal level of the second output signal of the mixer and the signal level of the third output signal that has passed through the channel selection filter decreases. A maximum input amplitude increase / decrease control circuit which increases the maximum input amplitude increase / decrease control signal and increases the target level as the ratio increases,
And a maximum input amplitude generation circuit that generates the maximum input amplitude control signal proportional to the maximum input amplitude increase / decrease control signal and inversely proportional to the gain control signal.

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