JP5534566B2 - 3-terminal capacitor mounting structure - Google Patents

Description

The present invention relates to a three-terminal capacitor mounting structure provided on a circuit board on which a BGA (Ball Grid Array) type IC (Integrated Circuit) is mounted.

In a digital IC or the like, on and off operations of current and voltage are repeated, and a sudden intermittent current flows through the power supply line of the IC. When this intermittent current flows, back electromotive force is generated due to the inductance of the power supply line and the ground line and the inductance of the via hole, and the power supply voltage supplied to the IC repeatedly rises and falls to generate noise. It becomes.
For this reason, in the conventional technology, a bypass capacitor is interposed between the power supply terminal and the ground terminal of the IC, and the occurrence of noise is suppressed by absorbing the change in the intermittent current by the bypass capacitor (for example, Patent Document 1 and Patent Document 2).

JP 2003-297963 A Japanese Patent Laid-Open No. 2004-006488

In the conventional noise countermeasure technology, a power supply terminal connection via hole connected to the power supply terminal of the IC and a ground terminal connection via hole connected to the ground terminal are drawn to the back surface side of the circuit board, and between the pair of via holes. In this configuration, a two-terminal capacitor for bypass is connected.
However, an IC has several tens of power supply terminals and ground terminals, and there are dozens of via holes connected to these power supply terminals and ground terminals. Therefore, in such a conventional technique, a bypass capacitor is provided for each of a very large number of via hole pairs. As a result, a large number of capacitors are required, and accordingly, the number of parts is increased, leading to an increase in the cost of the noise countermeasure structure.

The present invention has been made to solve the above-described problems, and an object thereof is to provide a three-terminal capacitor mounting structure capable of achieving a highly accurate noise countermeasure structure at low cost.

In order to solve the above-mentioned problems, according to the invention of claim 1, a three- terminal capacitor is formed on a chip body including one or more pairs of a signal electrode and a ground electrode opposed in the vertical direction, and an outer surface of the chip body. And first and second external electrodes electrically connected to both ends of the signal electrode, and third and third electrodes formed on the outer surface of the chip body and electrically connected to both ends of the ground electrode, respectively. A three-terminal capacitor including a fourth external electrode, wherein the chip body is formed in a square shape in plan view, and the length between both ends of the signal electrode and the length between both ends of the ground electrode are set to be substantially equal. The signal electrode and the ground electrode are arranged to face each other so that the straight line connecting both ends of the signal electrode and the straight line connecting both ends of the ground electrode are orthogonal to each other at substantially the center of each straight line. Dew on the outside The first and second external electrodes are connected to both ends of the signal electrode, and the third and fourth external electrodes are connected to both ends of the ground electrode exposed on the outer surface of the chip body. Yes, an IC having a BGA type terminal in which a plurality of terminals are arranged in a square lattice pattern is mounted on the surface of the circuit board, and a three-terminal capacitor is mounted on the back surface of the circuit board and almost directly behind the IC. In the three-terminal capacitor mounting structure, in at least one minimum square constituting the BGA type terminal, a pair of power supply terminals are respectively arranged at the vertices on one diagonal line, and a pair at the vertices on the other diagonal line A ground terminal is provided, and a plurality of via holes are provided through the circuit board vertically and exposed on the back surface in a state where the ground terminal is connected to the BGA type terminal. The first and second external electrodes connected to both ends of the pole are electrically connected to the first and second via holes connected to a pair of power supply terminals of the smallest square, respectively, and the three-terminal capacitor A three-terminal capacitor mounting structure in which the third and fourth external electrodes connected to both ends of the ground electrode are electrically connected to the third and fourth via holes connected to a pair of ground terminals of the smallest square, respectively. In each of the first to fourth via holes, each via hole is most closely connected to each via hole through a pair of patterns extending separately from the respective via holes to the outside in the side direction of the first to fourth via holes. It was set as the structure each connected to a near pair of via hole.
With such a configuration, a pair of separate via holes are connected to each of the first to fourth via holes, and the via holes connected to the power supply terminals of the IC form a three-unit parallel connection structure. Since the via holes connected to each other also form a parallel connection structure in units of three, the cross-sectional area of the via holes increases three times, and the inductance decreases accordingly.

According to a second aspect of the present invention, in the three-terminal capacitor mounting structure according to the first aspect, the three-terminal capacitor has both ends of the signal electrode positioned at opposite corners on one diagonal line of the chip body, and a ground electrode. And the first and second external electrodes are electrically connected to both ends of the signal electrode at one corner of the chip body, respectively. The third and fourth external electrodes are three-terminal capacitors that are electrically connected to both ends of the ground electrode at the other two corners of the chip body.

The invention according to claim 3, in the three-terminal capacitor mounting structure according to請Motomeko 1, 3 terminal capacitor, both ends of the signal electrodes, ground electrodes together are positioned respectively at the center of the opposite sides of the chip body Both end portions are respectively positioned at the centers of the opposite opposing side surfaces, and the first and second external electrodes are electrically connected to both end portions of the signal electrode at the center of the both side surfaces of the chip body, and the first The third and fourth external electrodes are three-terminal capacitors that are electrically connected to both ends of the ground electrode at the center of the other side surfaces of the chip body.

A fourth aspect of the present invention, the three-terminal capacitor mounting structure according to請Motomeko 2 or claim 3, the three-terminal capacitor, the first additional electrode of the plurality, directly above the one end of the signal electrode or The first additional electrodes are laminated at equal intervals directly below or both, and the ends of the first additional electrodes are connected to the first external electrodes, and the plurality of first additional electrodes are connected by one or more via holes. A first additional electrode group configured by connecting electrodes and connecting one end of the via hole facing the signal electrode to one end of the signal electrode, and a plurality of second additional electrodes, The signal electrodes are laminated at equal intervals directly above or below the other end of the signal electrode, and the ends of the second additional electrodes are connected to the second external electrode, and one or more The plurality of second additional electrodes are connected to each other by via holes. In addition, a second additional electrode group configured by connecting one end portion of the via hole facing the signal electrode side to the other end portion of the signal electrode, and a plurality of third additional electrodes are connected to one of the ground electrodes. Laminate at equal intervals either directly above or below the edge, or both, and connect the edge of the third additional electrode to the third external electrode, and use one or more via holes to A plurality of third additional electrodes are connected to each other, and one end portion of the via hole facing the ground electrode side is connected to one end portion of the ground electrode. 4 additional electrodes are laminated at equal intervals either directly above or directly below the other end of the ground electrode, or both, and the ends of these fourth additional electrodes are connected to the fourth external electrode, And one or more via holes A number of fourth additional electrodes connected to each other, and a third terminal provided with a fourth additional electrode group configured by connecting one end of the via hole facing the ground electrode side to the other end of the ground electrode The configuration is a capacitor.

According to a fifth aspect of the present invention, in the three-terminal capacitor mounting structure according to the fourth aspect, the three-terminal capacitor extends the other end of the via hole provided in the first additional electrode group, and By connecting to the upper end or lower end of the first external electrode located on the upper surface or the lower surface, the first external electrode and the first additional electrode group are connected in parallel, and the second additional electrode group By extending the other end of the via hole provided in the upper and lower ends of the second external electrode located on the upper surface or the lower surface of the chip body, the second external electrode and A third external electrode which is connected to the second additional electrode group in parallel and has the other end of the via hole provided in the third additional electrode group extended to be located on the upper surface or the lower surface of the chip body By connecting to the upper end or lower end of the third external The pole and the third additional electrode group are connected in parallel, and the other end of the via hole provided in the fourth additional electrode group is extended to be positioned on the upper surface or the lower surface of the chip body. By connecting to the upper end part or lower end part of the external electrode, the fourth external electrode and the fourth additional electrode group are connected in parallel to form a three-terminal capacitor.

The invention of claim 6 is the three-terminal capacitor mounting structure according to claim 4 , wherein the size of the three-terminal capacitor is set as follows. The first and second external electrodes of the three-terminal capacitor are connected to first and second via holes connected to a pair of power supply terminals of the smallest square, respectively, The third and fourth external electrodes are connected to the third and fourth via holes connected to a pair of ground terminals having a minimum square shape, respectively.

The invention of claim 7 is the three-terminal capacitor mounting structure according to claim 4 , wherein the size of the three-terminal capacitor is set as follows. The first land and the second land of a predetermined length are respectively set from the first and second via holes connected to the pair of power supply terminals of the minimum square on the back surface of the circuit board. In addition, by pulling out the third and fourth lands having a predetermined length from the third and fourth via holes connected to the pair of ground terminals, respectively, squares substantially equal to the size of the three-terminal capacitor are formed. The first and second external electrodes of the three-terminal capacitor are connected to the first and second lands, respectively, and the third and fourth external electrodes are connected to the first land. And a structure in which respectively connected to the fourth land.

The invention of claim 8 is the three-terminal capacitor mounting structure according to claim 4 , wherein the size of the three-terminal capacitor is set as follows. The first and second external electrodes of the three-terminal capacitor are connected to the first and second via holes connected to the pair of power supply terminals of the smallest square, respectively. The third and fourth external electrodes are connected to the third and fourth via holes connected to a pair of ground terminals having a minimum square shape, respectively.

The invention of claim 9 is the three-terminal capacitor mounting structure according to claim 4 , wherein the size of the three-terminal capacitor is set as follows. Each side surface is set to a size passing through a pair of via holes connected through a pair of patterns extending separately in the lateral direction of the first to fourth via holes, and a circuit is provided between the pair of via holes. Connected by lands formed on the back side of the substrate, the first external electrode of the three-terminal capacitor is connected on the lands connecting the tip portions of a pair of patterns separately extending outward in the side direction of the first via hole. Then, the second external electrode is connected to the land connecting the tip portions of the pair of patterns separately extending outward in the side direction of the second via hole, and the third external electrode is connected to the third external electrode. Separately extending to the outside in the side direction of the via hole The pair of pattern tips are connected to each other on a land that is connected, and the fourth external electrode is connected between the tip ends of the pair of patterns that are separately extended to the outside in the side direction of the fourth via hole. It is configured to be connected on the land.
With such a configuration, the three terminals having a size such that the external electrode at the center of the side surface is connected to the land connecting the tip portions of the pair of patterns separately extending outward in the side direction of the first to fourth via holes. Capacitors can be used. For example, a three-terminal capacitor having an area about seven times the minimum square can be mounted. Furthermore, since the three-terminal capacitor can be mounted on the land by soldering or the like, the three-terminal capacitor must be securely mounted by soldering or the like even if the first to fourth via holes are misaligned. Can do.

The invention according to claim 10 is a chip body in which a three- terminal capacitor includes one or more pairs of a signal electrode and a ground electrode facing each other in the vertical direction, and each of both ends of the signal electrode formed on the outer surface of the chip body. And first and second external electrodes electrically connected to each other, and third and fourth external electrodes formed on the outer surface of the chip body and electrically connected to both ends of the ground electrode, respectively. The chip body is formed in a square shape in plan view, the length between both ends of the signal electrode and the length between both ends of the ground electrode are set substantially equal, and the straight line connecting both ends of the signal electrode and the ground electrode The signal electrode and the ground electrode are arranged so as to face each other so that the straight line connecting both end portions is orthogonal to each other at substantially the center of each straight line. And a second external electrode Together to continue, at both ends of the ground electrode exposed on the outer surface of the chip body, a three-terminal capacitor connected to the third and fourth external electrodes, both ends of the signal electrodes, on one diagonal line of the chip body And both ends of the ground electrode are positioned at both corners facing each other on the other diagonal line, and the first and second external electrodes are signal electrodes at one corner of the chip body. at both ends with is electrically connected, the third and fourth external electrodes, on the other two corners of the chip body, a three terminal capacitor electrically connected to both ends of the ground electrode, one且The three-terminal capacitor has a plurality of first additional electrodes stacked at equal intervals directly above or directly below one end of the signal electrode, and the ends of the first additional electrodes are , The plurality of first additional electrodes are connected to each other by one or more via holes, and one end portion of the via hole facing the signal electrode side is connected to one end portion of the signal electrode. The first additional electrode group configured to be connected to each other and a plurality of second additional electrodes are stacked at equal intervals either directly above or directly below the other end of the signal electrode, or both. One end of each of the two additional electrodes is connected to the second external electrode, and the plurality of second additional electrodes are connected to each other by one or more via holes, while facing the signal electrode side of the via holes. The second additional electrode group configured by connecting the end portion to the other end portion of the signal electrode, and the plurality of third additional electrodes are either directly above or directly below one end portion of the ground electrode, or both. Are laminated at equal intervals, and the third additional The end of the additional electrode is connected to the third external electrode, and the plurality of third additional electrodes are connected to each other by one or more via holes, and one end of the via hole facing the ground electrode side Are connected to one end of the ground electrode, and the third additional electrode group and the plurality of fourth additional electrodes are directly above or below the other end of the ground electrode, etc. In addition to stacking at intervals, the ends of the fourth additional electrodes are connected to the fourth external electrode, and the plurality of fourth additional electrodes are connected to each other by one or more via holes. A three-terminal capacitor provided with a fourth additional electrode group configured by connecting one end facing the ground electrode side to the other end of the ground electrode, and a plurality of terminals are square on the surface of the circuit board Arranged in a grid of A three-terminal capacitor mounting structure in which an IC having a BGA type terminal is mounted, and a three-terminal capacitor is mounted on the back surface of the circuit board and almost directly behind the IC, and at least one minimum square constituting the BGA type terminal A pair of power supply terminals are arranged at the vertices on one diagonal line, a pair of ground terminals are arranged at the vertices on the other diagonal line, and the circuit board is connected to the BGA type terminals, A plurality of via holes that vertically penetrate the circuit board and are exposed on the back surface are provided, and the first and second external electrodes connected to both ends of the signal electrode of the three-terminal capacitor are used as a pair of power supply terminals having a minimum square shape. The third and fourth external electrodes connected to both ends of the ground electrode of the three-terminal capacitor are electrically connected to the connected first and second via holes, respectively. In the third and fourth 3-terminal capacitor mounting structure which is electrically connected to the via hole of which is connected to the ground terminal of a pair of rectangular, 3 the first to fourth external electrode terminal capacitor, the back surface of the circuit board Are connected to each of the first to fourth lands arranged in a square shape, and are connected to at least some of the plurality of via holes respectively connected to the plurality of power supply terminals and the plurality of ground terminals. At least a part of the plurality of connected via holes is arranged inside a square defined by the first to fourth lands, and the third of the plurality of via holes connected to the power supply terminal. The via hole located on the first land side is connected to the first land through the first pattern with the diagonal line connecting the second land and the fourth land as a boundary. The via hole located on the second land side is connected to the second land through the second pattern, and among the plurality of via holes connected to the ground, the first via the diagonal line connecting the first land and the second land. The via hole located on the third land side is connected to the third land through the third pattern, and the via hole located on the fourth land side is connected to the fourth land through the fourth pattern.
With this configuration, the intermittent current generated at the power supply terminal of the IC reaches the first pattern (second pattern) through the via hole. The intermittent current flows through the first pattern (second pattern) to the first land (second land), and is connected to the first land (second land). Input from the electrode (second external electrode) to the first additional electrode group (second additional electrode group) or the signal electrode.
At this time, at least a part of the via holes connected to the power supply terminal is arranged inside the square defined by the first to fourth lands. The intermittent current flowing through the via hole located on the side of the land (second land) from the via hole located immediately below the three-terminal capacitor is changed from the first pattern (second pattern) to the first external electrode (second Flows toward the external electrode). That is, the intermittent current from these via holes flows toward the outside of the three-terminal capacitor.
The intermittent current input to the first external electrode (second external electrode) is generated on each first additional electrode (second additional electrode) of the first additional electrode group (second additional electrode group). Flows toward the inside of the three-terminal capacitor.
Therefore, the direction of the intermittent current flowing through the first pattern (second pattern) from the via hole inside the square and the direction of the intermittent current flowing through each first additional electrode (second additional electrode) are reversed. As a result, a negative mutual inductance is generated between the first pattern (second pattern) and the first additional electrode (second additional electrode), and the first pattern (second pattern) and the first pattern The total inductance with one additional electrode (second additional electrode) is reduced.
On the other hand, the intermittent current from the ground electrode flows through each third additional electrode (third additional electrode) of the third additional electrode group (fourth additional electrode group) to form a third external electrode (fourth electrode). External electrode). The intermittent current flows through the third pattern (fourth pattern) through the third land (fourth land) to which the third external electrode (fourth external electrode) is connected, and through the via hole. , Feedback to the IC ground terminal.
At this time, the intermittent current from the ground electrode is directed toward the third external electrode (fourth external electrode) on each third additional electrode (third additional electrode), that is, outside the three-terminal capacitor. It flows toward.
However, since a part of the via hole connected to the ground terminal is arranged inside the square defined by the first to fourth lands, the third external electrode (the fourth external electrode) The intermittent current flowing on the third pattern (fourth pattern) from the electrode) toward these via holes flows in the inner direction of the three-terminal capacitor.
Therefore, the direction of the intermittent current flowing on each third additional electrode (third additional electrode) and the direction of the intermittent current flowing on these third patterns (fourth pattern) are reversed. Negative additional inductance occurs between the third additional electrode (fourth additional electrode) and the third pattern (fourth pattern), and the third additional electrode (fourth additional electrode) and the third pattern The total inductance with the pattern (fourth pattern) will decrease.

The invention according to claim 11 is a chip body in which a three- terminal capacitor includes one or more pairs of a signal electrode and a ground electrode facing each other in the vertical direction; And first and second external electrodes electrically connected to each other, and third and fourth external electrodes formed on the outer surface of the chip body and electrically connected to both ends of the ground electrode, respectively. The chip body is formed in a square shape in plan view, the length between both ends of the signal electrode and the length between both ends of the ground electrode are set substantially equal, and the straight line connecting both ends of the signal electrode and the ground electrode The signal electrode and the ground electrode are arranged so as to face each other so that the straight line connecting both end portions is orthogonal to each other at substantially the center of each straight line. And a second external electrode Together to continue, at both ends of the ground electrode exposed on the outer surface of the chip body, both sides a 3-terminal capacitor connected to the third and fourth external electrodes, the two ends of the signal electrodes, facing the chip body And both ends of the ground electrode are respectively positioned at the centers of the opposite opposing side surfaces, and the first and second external electrodes are positioned at both ends of the signal electrode at the center of the both side surfaces of the chip body. And a third terminal capacitor in which the third and fourth external electrodes are electrically connected to both ends of the ground electrode at the center of the other side surfaces of the chip body , and A three-terminal capacitor stacks a plurality of first additional electrodes at equal intervals directly above or directly below one end of the signal electrode, and at the ends of these first additional electrodes, Connected to the first external electrode; The first additional electrode is configured by connecting the plurality of first additional electrodes to each other by one or more via holes and connecting one end portion of the via hole facing the signal electrode side to one end portion of the signal electrode. The additional electrode group and a plurality of second additional electrodes are laminated at equal intervals directly above or directly below the other end of the signal electrode, and the ends of the second additional electrodes are The second additional electrodes are connected to each other by one or more via holes, and one end of the via hole facing the signal electrode side is connected to the other of the signal electrodes. The second additional electrode group configured to be connected to the end portion and the plurality of third additional electrodes are laminated at equal intervals either directly above or directly below one end portion of the ground electrode, or both, The ends of these third additional electrodes are connected to the third outer The plurality of third additional electrodes are connected to each other by one or more via holes, and one end of the via hole facing the ground electrode is connected to one end of the ground electrode. The third additional electrode group configured as described above and a plurality of fourth additional electrodes are laminated at equal intervals either directly above or directly below the other end of the ground electrode, or both. The end of the additional electrode is connected to the fourth external electrode, and the plurality of fourth additional electrodes are connected to each other by one or more via holes, and one end of the via hole facing the ground electrode side is connected. A three-terminal capacitor provided with a fourth additional electrode group configured to be connected to the other end of the ground electrode, and a plurality of terminals arranged in a square lattice pattern on the surface of the circuit board I with A three-terminal capacitor mounting structure in which a three-terminal capacitor is mounted on the back surface of the circuit board and at a position almost directly behind the IC, on one diagonal line in at least one minimum square constituting the BGA type terminal A pair of power supply terminals are arranged at the top of each of the terminals, and a pair of ground terminals are arranged at the other top of the diagonal line, and the circuit board is vertically connected to the BGA type terminal while being connected to the circuit board. A plurality of via holes exposed on the back surface are provided, and the first and second external electrodes connected to both ends of the signal electrode of the three-terminal capacitor are connected to a pair of power supply terminals having a minimum square. The third and fourth external electrodes that are electrically connected to the second via holes and connected to both ends of the ground electrode of the three-terminal capacitor are connected to a pair of ground ends of a minimum square. In the connected third and third terminal capacitor mounting structure which is electrically connected to the fourth via holes, 3 the first to fourth external electrode terminal capacitors, they are arranged in a square shape on the back surface of the circuit board A plurality of via holes connected to the first to fourth lands and connected to the plurality of power supply terminals, respectively, and at least some of the via holes connected to the plurality of power supply terminals. At least some of the via holes are arranged inside a square defined by the first to fourth lands, and the third land and the fourth land among the plurality of via holes connected to the power supply terminal. A via hole located on the first land side is connected to the first land through the first pattern at the diagonal line connecting the two and the second land side. The hole is connected to the second land through the second pattern, and the plurality of via holes connected to the ground are located on the third land side with the diagonal line connecting the first land and the second land as a boundary. The via hole is connected to the third land through the third pattern, and the via hole located on the fourth land side is connected to the fourth land through the fourth pattern.

The invention of claim 12 is the three-terminal capacitor mounting structure according to請Motomeko 10 or claim 11, the three-terminal capacitor is, the other end of the via hole provided in the first additional electrode group, extends The first external electrode and the first additional electrode group are connected in parallel by connecting to the upper end portion or the lower end portion of the first external electrode located on the upper surface or the lower surface of the chip body, By extending the other end portion of the via hole provided in the second additional electrode group and connecting it to the upper end portion or the lower end portion of the second external electrode located on the upper surface or the lower surface of the chip body, The second external electrode and the second additional electrode group are connected in parallel, and the other end of the via hole provided in the third additional electrode group is extended to be positioned on the upper surface or the lower surface of the chip body. By connecting to the upper end or lower end of the third external electrode The third external electrode and the third additional electrode group are connected in parallel, and the other end of the via hole provided in the fourth additional electrode group is extended to be on the upper surface or the lower surface of the chip body. By connecting to the upper end part or the lower end part of the fourth external electrode located at, a configuration of a three-terminal capacitor in which the fourth external electrode and the fourth additional electrode group are connected in parallel.

More detail As described, according to the three-terminal capacitor mounting structure according to the invention of claim 1 to claim 8, the inductance of the via hole between the IC and the three-terminal capacitor can be small fence.

According to the ninth aspect of the present invention, it is possible to mount a three-terminal capacitor having an area approximately seven times as large as a normal one, and it is possible to dramatically increase the capacity. Furthermore, even if the via hole is misaligned, the three-terminal capacitor can be mounted reliably, and the yield can be improved accordingly.

Furthermore, according to the tenth to twelfth inventions, the noise countermeasure effect can be further enhanced.

It is a disassembled perspective view which shows the 3 terminal capacitor | condenser mounting structure which concerns on the reference technical example of this invention. FIG. 2 is an IC rear view showing an IC terminal arrangement applied to the three-terminal capacitor mounting structure of FIG. 1. It is a board | substrate back view which shows the arrangement | sequence of the via hole of a circuit board back surface. It is a schematic sectional drawing which shows a 3 terminal capacitor mounting structure. It is a schematic perspective view which shows the external appearance of a 3 terminal capacitor | condenser, and the positional relationship of the terminal of IC, and the via hole of a circuit board. It is a top view of a 3-terminal capacitor. It is a disassembled perspective view of a 3 terminal capacitor. It is a top view which shows a signal electrode. It is a top view which shows a ground electrode. It is an electric circuit diagram showing typically a 3 terminal capacitor mounting structure. It is a schematic perspective view for demonstrating the total inductance of a via hole at the time of connecting a 2 terminal capacitor | condenser. It is a schematic perspective view for demonstrating the total inductance of a via hole at the time of connecting a 3 terminal capacitor. It is a top view which shows the terminal arrangement of IC applied to the 3 terminal capacitor | condenser mounting structure which concerns on 1st Example of this invention. It is a top view which shows the via hole arrangement | sequence of a circuit board. It is the elements on larger scale which show the principal part of the 3 terminal capacitor | condenser mounting structure which concerns on 2nd Example of this invention. It is a partial enlarged plan view which shows the mounting state of a 3-terminal capacitor. It is an external view of the 3 terminal capacitor which is the principal part of the 3 terminal capacitor mounting structure based on 3rd Example of this invention. It is a top view of a 3-terminal capacitor. It is a disassembled perspective view of a 3 terminal capacitor. It is a top view which shows a signal electrode. It is a top view which shows a ground electrode. It is a schematic plan view which shows the state which mounted the 3 terminal capacitor. It is a top view which shows the via hole arrangement | sequence which is the principal part of the 3 terminal capacitor | condenser mounting structure which concerns on 4th Example of this invention. It is a top view for demonstrating the mounting method of a 3 terminal capacitor. It is a perspective view which permeate | transmits and shows the 3 terminal capacitor applied to the 3 terminal capacitor mounting structure which concerns on 5th Example of this invention. FIG. 26 is an exploded perspective view of the three-terminal capacitor of FIG. 25. It is arrow AA sectional drawing of FIG. It is arrow BB sectional drawing of FIG. It is a top view which shows arrangement | positioning of the land and via hole for mounting a 3 terminal capacitor | condenser. It is a schematic sectional drawing which shows a 3 terminal capacitor mounting structure. It is sectional drawing which shows the electric current input into a signal electrode. It is a partial expanded sectional view for demonstrating the effect at the time of the electric current input to a signal electrode. It is sectional drawing which shows the electric current output from a ground electrode. It is a partial expanded sectional view for demonstrating the effect at the time of the electric current output from a ground electrode. It is sectional drawing which shows the signal electrode side of the 3 terminal capacitor | condenser applied to the 3 terminal capacitor | condenser mounting structure which concerns on 6th Example of this invention. It is sectional drawing which shows the ground electrode side of a three-terminal capacitor. It is a diagram which shows the result of simulation. It is a perspective view which permeate | transmits and shows the 3 terminal capacitor applied to the 3 terminal capacitor mounting structure which concerns on 7th Example of this invention. It is a top view which shows the positional relationship of the land for mounting a 3-terminal capacitor | condenser, and an external electrode. It is a top view which permeate | transmits the inside and shows one modification of a 3 terminal capacitor | condenser. It is a top view of the modification of 3 terminal capacitor | condenser mounting structure.

  The best mode of the present invention will be described below with reference to the drawings.

(Reference technology example)
FIG. 1 is an exploded perspective view showing a three-terminal capacitor mounting structure according to a reference technical example of the present invention, and FIG. 2 is an IC rear view showing an IC terminal arrangement applied to the three-terminal capacitor mounting structure of FIG. FIG. 3 is a backside view showing the arrangement of via holes on the backside of the circuit board, and FIG. 4 is a schematic cross-sectional view showing a three-terminal capacitor mounting structure.
As shown in FIG. 1, the three-terminal capacitor mounting structure of this reference technical example has a structure in which IC1 is mounted on the front surface 2a of the circuit board 2 and the three-terminal capacitor 3-1 is mounted on the back surface 2b of the circuit board 2. .
In FIG. 1, as shown by a dashed box D, a partial view clearly showing the mounting state of the three-terminal capacitor 3-1 with the back surface 2b of the circuit board 2 reversed is shown for easy understanding. .

The IC 1 is an integrated circuit having a BGA type terminal arrangement, and a plurality of terminals such as a power supply terminal, a ground terminal, and a signal terminal are arranged in a square lattice pattern on the back surface 1a.
Specifically, as shown in FIG. 2, the BGA terminal array has a shape in which a minimum square A is defined by four terminals and a plurality of minimum squares A are aligned. In FIG. 2, the power supply terminals 11 and 12 are indicated by white circles, and the ground terminals 13 and 14 are indicated by black circles. In each minimum square A, a pair of power supply terminals 11 and 12 are arranged at the vertices on one diagonal of the minimum square A, and a pair of ground terminals 13 and 14 are arranged at the vertices on the other diagonal. Yes.
Technically, the minimum square A in which the power supply terminals 11 and 12 and the ground terminals 13 and 14 are arranged diagonally in this way is at least one of the plurality of minimum squares A constituting the BGA terminal array. In other minimum squares A, the power terminals 11 and 12 and the ground terminals 13 and 14 may be arranged at any vertex. However, in this reference technical example, in order to facilitate understanding, the IC 1 of the BGA terminal arrangement in which the power supply terminals 11 and 12 and the ground terminals 13 and 14 are arranged diagonally in all the minimum squares A is applied.
Further, in the drawings, the minimum square A and the following minimum square B are shown by solid lines, but there are actually no members corresponding to this solid line, and the minimum squares are terminals 11-14 and via holes 21-24. It is mentioned here that it is only defined in

As shown in FIG. 1, the circuit board 2 has a number of via holes 21 to 24 corresponding to the power supply terminals 11 and 12 and the ground terminals 13 and 14 of the IC 1.
Specifically, as shown in FIGS. 1 and 4, the via holes 21 to 24 penetrate perpendicularly from the front surface 2 a to the back surface 2 b of the circuit board 2 in the same arrangement as the BGA terminal arrangement. And the part exposed to the surface 2a of the circuit board 2 is connected to the power supply terminals 11 and 12 and the ground terminals 13 and 14 of IC1. In the drawing, the via holes 21 and 22 shown in white are connected to the power supply terminals 11 and 12, respectively, and the via holes 23 and 24 shown in black are connected to the ground terminals 13 and 14, respectively. Therefore, as shown in FIG. 3, the minimum square B formed by these via holes 21 to 24 is substantially the same shape as the minimum square A.

The three-terminal capacitor 3-1 is mounted on the back surface 2b of the circuit board 2 and at a position directly behind the IC 1.
FIG. 5 is a schematic perspective view showing the appearance of the three-terminal capacitor 3-1, the positional relationship between the terminals of the IC 1 and the via holes of the circuit board 2, and FIG. 6 is a plan view of the three-terminal capacitor 3-1. FIG. 7 is an exploded perspective view of the three-terminal capacitor 3-1.
As shown in FIG. 5, the three-terminal capacitor 3-1 includes a chip body 30 and external electrodes 4-1 to 4-4 as first to fourth external electrodes.
Specifically, as shown in FIG. 6, the chip body 30 forms a square in plan view, and four corners 30 a to 30 d are rounded. As shown in FIG. 5, the size of the three-terminal capacitor 3-1 is set to be approximately equal to the size of the minimum square A described above.
The three-terminal capacitor 3-1 having such an appearance is a multilayer capacitor as shown in FIG.
FIG. 8 is a plan view showing the signal electrode 31, and FIG. 9 is a plan view showing the ground electrode 32.
As shown in FIG. 8, the signal electrode 31 is formed on the diagonally downward diagonal line on the insulating layer 33, and both end portions 31 a and 31 b are located at both corner portions 30 a and 30 b of the insulating layer 33. On the other hand, as shown in FIG. 9, the ground electrode 32 is formed on a diagonal line rising to the right on the insulating layer 33, and both end portions 32 a and 32 b are located at both corner portions 30 c and 30 d of the insulating layer 33. Therefore, the length m1 between the both end portions 31a and 31b of the signal electrode 31 is equal to the length m2 of the both end portions 32a and 32b of the ground electrode 32. In addition, as shown in FIG. 7, in the state where the signal electrode 31 and the ground electrode 32 are stacked via the insulating layer 33, the pair of signal electrodes 31 and the ground electrode 32 face each other in the vertical direction of the chip body 30. In addition, a straight line m1 (see FIG. 8) connecting both end portions 31a and 31b of the signal electrode 31 and a straight line m2 (see FIG. 9) connecting both end portions 32a and 32b of the ground electrode 32 are orthogonal to each other.
In this way, the chip body 30 is assembled with a plurality of pairs of signal electrodes 31 and ground electrodes 32 facing each other.

Further, as shown in FIGS. 5 and 6, the external electrodes 4-1 to 4-4 are respectively formed on the outer surface of the chip body 30, and the exposed end portions 31 a and 31 b of the plurality of signal electrodes 31 (see FIG. 7). ) And the exposed end portions 32a and 32b (see the figure) of the plurality of ground electrodes 32.
Specifically, as shown in FIG. 8, the external electrodes 4-1 and 4-2 are connected to both end portions 31 a and 31 b of each signal electrode 31. On the other hand, the external electrodes 4-3 and 4-4 are formed at the respective corner portions of the insulating layer 33 so as to be electrically connected to both end portions 32 a and 32 b of the ground electrode 32 as shown in FIG. 30c and 30d are formed.

As shown in FIGS. 4 and 5, the three-terminal capacitor 3-1 having such a configuration is mounted on the back surface 2 b of the circuit board 2, and the external electrodes 4-1 and 4-2 are first and second via holes. The external electrodes 4-3 and 4-4 are connected to via holes 23 and 24 which are third and fourth via holes.
Specifically, as shown in FIG. 5, the external electrodes 4-1 and 4-2 are electrically connected to the power supply terminals 11 and 12 of the IC 1 by being connected to the via holes 21 and 22. The external electrodes 4-3 and 4-4 are electrically connected to the ground terminals 13 and 14 of the IC 1 by being connected to the via holes 23 and 24. As a result, the signal electrode 31 having both end portions 31a and 31b connected to the external electrodes 4-1 and 4-2 is connected to the pair of power supply terminals 11 and 12 of the smallest square A of the IC 1 through the via holes 21 and 22. At the same time, the ground electrode 32 having both end portions 32a and 32b connected to the external electrodes 4-3 and 4-4 is connected to the pair of ground terminals 13 and 14 of the smallest square A through the via holes 23 and 24. The plurality of opposed signal electrodes 31 and ground electrodes 32 function as capacitors.

Next, the operation and effect of the three-terminal capacitor mounting structure of this reference technical example will be described.
FIG. 10 is an electric circuit diagram schematically showing a three-terminal capacitor mounting structure.
As shown in FIG. 10, the external electrodes 4-1 and 4-2 of the three-terminal capacitor 3-1 are connected to the power supply terminals 11 and 12 of the IC 1 through the via holes 21 and 22. The external electrodes 4-1 and 4-2 are also connected to a power supply device 100 that supplies power to the power supply terminals 11 and 12 of the IC1.
On the other hand, the external electrodes 4-3 and 4-4 are connected to the ground terminals 13 and 14 through the via holes 23 and 24. The external electrodes 4-3 and 4-4 are connected to the ground 110.

When a power supply is supplied from the power supply apparatus 100 to the IC 1 and an intermittent current is generated by the switching operation of the IC 1 or the like, the current is supplied from the power supply terminals 11 and 12 to the via holes 21 and 22 and the external electrodes 4-1 and 4-4. 2 and flows into the 3-terminal capacitor 3-1. As a result, a voltage is generated between the signal electrode 31 and the ground electrode 32 facing the signal electrode 31, and the current flows out to the external electrodes 4-3 and 4-4, the ground terminals 13 and 14, and the via holes 23 and 24 connected to the ground 110. The three-terminal capacitor 3-1 functions as a bypass capacitor.
At this time, if the inductance of the via holes 21 to 24 and the inductance of the bypass capacitor are large, the counter electromotive force due to the intermittent current increases in proportion to the magnitude of these inductances, and a large amount of noise radiation may occur. .
However, in the three-terminal capacitor mounting structure of this reference technical example, as shown in FIG. 4 and the like, the linear via holes 21 to 24 are penetrated and mounted on the three-terminal capacitor 3-1 directly behind IC1. Therefore, the length of the path from the IC 1 including the via holes 21 to 24 to the three-terminal capacitor 3-1 is the shortest. Further, a three-terminal capacitor 3-1 having a very small residual inductance is used as a bypass capacitor. Therefore, the inductance of the via holes 21 to 24 and the inductance of the bypass three-terminal capacitor 3-1 are very small. As a result, the back electromotive force generated by the product of the temporal change of the intermittent current from the IC 1 and the inductance is extremely low, and noise radiation is reduced.
Further, since the three-terminal capacitor 3-1 is mounted in this reference technical example, as shown in FIG. 4, a pair of the power supply terminal 11 and the ground terminal 13 and a pair of the power supply terminal 12 and the ground terminal 14 are arranged. One capacitor can be used for processing. On the other hand, in the above-described conventional technique, it is necessary to connect a two-terminal capacitor to the pair of the power supply terminal 11 and the ground terminal 13 and to connect another two-terminal capacitor to the pair of the power supply terminal 12 and the ground terminal 14. And the number of parts increases.

Finally, the characteristic operation and effect of this reference technical example will be described.
FIG. 11 is a schematic perspective view for explaining the total inductance of the via hole when a two-terminal capacitor is connected.
In order to connect the two-terminal capacitor to the via holes 21 to 24 of this reference technique and use it as a bypass capacitor, as shown in FIG. 11, the external electrode 51 of the first two-terminal capacitor 5 (5-1). , 52 are connected to the via holes 21, 23, and the external electrodes 51, 52 of the second two-terminal capacitor 5 (5-2) are connected to the via holes 22, 24.
In such a connection structure, the current I1 in the via hole 21 flows out to the via hole 23 through the two-terminal capacitor 5 (5-1) as indicated by an arrow. Accordingly, since the current I1 having the same potential flows in the opposite direction between the via holes 21 and 23, a negative mutual inductance M13 is generated between the via holes 21 and 23. Therefore, assuming that the inductances of the via holes 21 and 23 are L1 and L3, the inductances of the via holes 21 and 23 when a current flows are L1 + L3−2 × M13. On the other hand, the current I2 in the via hole 22 flows out to the via hole 24 through the two-terminal capacitor 5 (5-2). Therefore, since the current I2 having the same potential flows in the opposite direction between the via holes 22 and 24, the inductance of the via holes 22 and 24 is L2 and L4, and the mutual inductance M24, the inductance of the via holes 22 and 24 is L2 + L4-2 × M24.
Therefore, when two two-terminal capacitors 5 (5-1, 5-2) are connected to the via holes 21 to 24, the total inductance of the via holes 21 to 24 is L1 + L2 + L3 + L4-2 × (M13 + M24).

FIG. 12 is a schematic perspective view for explaining the total inductance of the via hole when a three-terminal capacitor is connected.
In this reference technical example, as shown in FIG. 12, the external electrodes 4-1 and 4-2 of the three-terminal capacitor 3-1 are connected to the via holes 21 and 22, and the external electrodes 4-3 and 4-4 are connected to the via holes. 23, 24.
In such a connection structure, the current I1 in the via hole 21 flows out to the via hole 23 and the via hole 24 through the three-terminal capacitor 3-1, as indicated by the solid line arrow. Therefore, since the current I1 having the same potential flows in the opposite direction between the via hole 21 and the via holes 23 and 24, negative mutual inductances M13 and M14 are provided between the via holes 21 and 23 and between the via holes 21 and 24, respectively. Arise. For this reason, the inductance of the via holes 21, 23, and 24 when a current flows is L1 + L3-2 × M13-2 × M14. On the other hand, the current I2 in the via hole 22 also flows out to the via hole 23 and the via hole 24 through the three-terminal capacitor 3-1, as indicated by the two-dot chain line arrow. Accordingly, since the current I2 having the same potential flows in the opposite direction between the via hole 22 and the via holes 23 and 24, negative mutual inductances M23 and M24 are provided between the via holes 22 and 23 and between the via holes 22 and 24, respectively. Arise. For this reason, the inductance of the via holes 22, 23, and 24 when the current flows is L2 + L3 + -2 × M13-2 × M14.
As described above, the total inductance of the via holes 21 to 24 when a current flows through the three-terminal capacitor 3-1 is L1 + L2 + L3 + L4-2 × (M13 + M14 + M23 + M24).
On the other hand, the total inductance of the via holes 21 to 24 when the two-terminal capacitor 5 (5-1, 5-2) is used is L1 + L2 + L3 + L4-2 × (M13 + M24). According to the terminal capacitor mounting structure, by using one three-terminal capacitor, the inductance can be made smaller than when two two-terminal capacitors are used, and the number of parts can be reduced accordingly. In addition, since the 3-terminal capacitor 3-1 having a low residual inductance is used, the inductance can be further reduced as compared with the case where a 2-terminal capacitor is used.

Example 1
Next, a first embodiment of the present invention will be described.
FIG. 13 is a plan view showing the terminal arrangement of the IC 1 applied to the three-terminal capacitor mounting structure according to the first embodiment of the present invention, and FIG. 14 is a plan view showing the via hole arrangement of the circuit board.
In this embodiment, the terminal arrangement around the smallest square A of the IC 1 is different from the above-mentioned reference technique example.
In the reference technical example, the terminal arrangement of the IC 1 is an arrangement in which the minimum square A defined by the power supply terminals 11 and 12 and the ground terminals 13 and 14 is spread as shown in FIG. In the embodiment, as shown by a box C in FIGS. 13 and 13, the power supply terminals 11 and 11 (12 , 12), and ground terminals 13, 13 (14, 14) on the outer side in the sides b and c (a, d) from the ground terminal 13 (14) at the apex of the minimum square A, respectively. . That is, at each vertex of the minimum square A, three terminals 11, 11, 11 (12, 12, 12-14, 14, 14) are arranged in an L shape. Reference numeral 15 denotes a terminal other than the power supply terminal and the ground terminal, for example, a signal terminal.

And the arrangement of the via holes 21 to 24 exposed on the back surface 2b of the circuit board 2 also corresponds to the arrangement of the terminals 11 to 14 of the IC 1, as shown in FIG. 14, but each via hole arranged in an L shape. Groups 21, 21, 21 (22, 22, 22-24, 24, 24) are connected by a pattern.
Specifically, as shown in a box C ′ in FIG. 14, the patterns 21 a and 21 b (22 a and 22 b) are moved outward from the via hole 21 (22) at the apex of the minimum square B in the sides a and b (c and d). The via holes 21 and 21 (22 and 22) at the extension destinations were separately extended. Further, the patterns 23a and 23b (24a and 24b) are separately extended outward from the via hole 23 (24) at the apex of the minimum square B in the side b and c (a and d) directions, and the via hole 23 at the extension destination is provided. , 23 (24, 24). Note that the via hole denoted by reference numeral 25 is a via hole connected to the terminal 15.

With this configuration, the three via holes 21 (22 to 24) are connected in parallel by the patterns 21a and 21b (22a, 22b to 24a, and 24b). As a result, the via holes connected to the terminals of the IC 1 are formed. The cross-sectional area increases three times, and the inductance decreases accordingly.
Other configurations, operations, and effects are the same as those in the above-described reference technical example, and thus description thereof is omitted.

(Example 2)
Next explained is the second embodiment of the invention.
FIG. 15 is a partially enlarged plan view showing a main part of the three-terminal capacitor mounting structure according to the second embodiment of the present invention, and FIG. 16 is a partially enlarged plan view showing a mounted state of the three-terminal capacitor.
This embodiment is different from the first embodiment in that it has a via hole structure that can mount even a small three-terminal capacitor.
As shown in FIG. 15, the arrangement of the via holes 21 to 24 that define the minimum square B corresponding to the minimum square A is the same as that in the first embodiment. However, in the case of the arrangement of this size, the three-terminal capacitor 3-1 smaller than the minimum square B (A) cannot be mounted. Therefore, in this embodiment, on the back surface 2b of the circuit board 2, the lands 21c and 22c as first and second lands having a predetermined length are drawn out from the via holes 21 and 22, respectively, and the predetermined length from the via holes 23 and 24 is obtained. By extracting the lands 23c and 24c as the third and fourth lands, a square B 'smaller than the minimum square B was defined by the lands 21c to 24c.
Then, as shown in FIG. 16, a small three-terminal capacitor 3-1 substantially equal to the square B ′ is placed on the lands 21c to 24c, and the external electrodes 4-1 and 4-2 are connected to the lands 21c and 22c. The external electrodes 4-3 and 4-4 were mounted by soldering to the lands 23c and 24c.
Since other configurations, operations, and effects are the same as those in the first embodiment, description thereof is omitted.

(Example 3)
Next explained is the third embodiment of the invention.
17 is an external view of a three-terminal capacitor, which is a main part of a three-terminal capacitor mounting structure according to a third embodiment of the present invention, FIG. 18 is a plan view of the three-terminal capacitor, and FIG. It is a disassembled perspective view of a terminal capacitor.
As shown in FIGS. 17 and 18, the three-terminal capacitor 3-2 of this example is that the external electrodes 4-1 to 4-4 are positioned at the center of the side surface of the chip body 30. And different from the second embodiment.
That is, as shown in FIG. 19, the three-terminal capacitor 3-2 is also a multilayer capacitor, and has a structure in which the signal electrode 31 and the ground electrode 32 are stacked via the insulating layer 33.

20 is a plan view showing the signal electrode 31, and FIG. 21 is a plan view showing the ground electrode 32.
As shown in FIG. 20, the signal electrode 31 is formed from the front side to the rear side of the insulating layer 33, and both end portions 31 a and 31 b are located at the front and rear central portions of the insulating layer 33, respectively. On the other hand, as shown in FIG. 21, the ground electrode 32 is formed across the left and right sides of the insulating layer 33, and its both end portions 32 a and 32 b are located at the right and left central portions of the insulating layer 33.
The external electrodes 4-1 and 4-2 are formed at the center of the front and rear side surfaces of the chip body 30, respectively, and are connected to the exposed end portions 31 a and 31 b of the plurality of signal electrodes 31. The external electrodes 4-3 and 4-4 are formed at the center of the right and left side surfaces of the chip body 30, respectively, and are connected to both exposed end portions 32 a and 32 b of the plurality of ground electrodes 32.

FIG. 22 is a schematic plan view showing a state in which the three-terminal capacitor 3-2 of this embodiment is mounted.
When the three-terminal capacitor 3-2 is configured as described above, the front and rear side external electrodes 4-1 and 4-2 are connected to the via holes 21 and 22 as shown in FIG. By connecting 4-3 and 4-4 to the via holes 23 and 24, the three-terminal capacitor 3-2 having a size twice as large as the minimum square B (A) can be mounted. That is, according to the three-terminal capacitor mounting structure of this embodiment, it is possible to mount the three-terminal capacitor 3-2 having a capacity twice as large as that of the three-terminal capacitor 3-1 of the first and second embodiments. it can.
Other configurations, operations, and effects are the same as those in the first and second embodiments, and thus description thereof is omitted.

Example 4
Next explained is the fourth embodiment of the invention.
FIG. 23 is a plan view showing a via hole arrangement which is a main part of the three-terminal capacitor mounting structure according to the fourth embodiment of the present invention.
In this embodiment, the arrangement of the via holes used in the first embodiment is improved, and a larger three-terminal capacitor can be mounted. Different.

  Specifically, as shown in FIG. 23, between the via holes 21, 21 (22, 22) to which the patterns 21a, 21b (22a, 22b) extending from the via hole 21 (22) at the apex of the minimum square B are connected. Are connected by the lands 21d (22d) and between the via holes 23, 23 (24, 24) connected to the patterns 23a, 23b (24a, 24b) extending from the via holes 23 (24), the lands 23d (24d) are connected. ).

FIG. 24 is a plan view for explaining a method of mounting a three-terminal capacitor.
In the arrangement pattern of the via holes 21 to 24 as described above, the size of the three-terminal capacitor 3-2 shown in the third embodiment is set to a size connectable to the via hole shown in FIG.
Specifically, as shown by a two-dot chain line in FIG. 24, the length of each side surface of the three-terminal capacitor 3-2 is set to a length that passes through each land 21d to 24d, and the outside of the center of the front and rear side surfaces is set. The electrodes 4-1 and 4-2 were placed on the lands 21d and 22d, and the outer electrodes 4-3 and 4-4 at the center of the left and right side surfaces were placed on the lands 23d and 24d. Then, the external electrodes 4-1 to 4-4 were connected to the lands 21d to 22d by the solder 120.

By adopting the structure as in this embodiment, it is possible to mount a large-capacity three-terminal capacitor 3-2 having an area approximately seven times the minimum square B (A) defined by the apex via holes 21-24. it can.
Other configurations, operations, and effects are the same as those in the first to third embodiments, and thus description thereof is omitted.

(Example 5)
Next explained is the fifth embodiment of the invention.
25 is a perspective view showing a three-terminal capacitor applied to the three-terminal capacitor mounting structure according to the fifth embodiment of the present invention, and FIG. 26 is an exploded perspective view of the three-terminal capacitor shown in FIG. 27 is a cross-sectional view taken along the line AA in FIG. 25, and FIG. 28 is a cross-sectional view taken along the line BB in FIG.
This embodiment is different from the first to fourth embodiments in the structure of a three-terminal capacitor.

As shown in FIG. 25, the three-terminal capacitor 3-3 applied to the three-terminal capacitor mounting structure of this embodiment includes an additional electrode group 6 as a first additional electrode group and a second additional electrode group. It has the additional electrode group 7, the additional electrode group 8 as a 3rd additional electrode group, and the additional electrode group 9 as a 4th additional electrode group.
Specifically, as shown in FIG. 26, the pair of additional electrode groups 6 are respectively disposed directly above and directly below the end portion 31 a of the signal electrode 31, and the pair of additional electrode groups 7 are formed of the signal electrode 31. A pair of additional electrode groups 8 are respectively disposed directly above and directly below the end portion 31b of the ground electrode 32, and a pair of additional electrode groups 9 are disposed directly above and directly below the end portion 32a of the ground electrode 32. The electrodes 32 are disposed directly above and directly below the end 32b of the electrode 32, respectively.
More specifically, as shown in FIG. 27, in the additional electrode group 6 (7), additional electrodes 61 (71) as first additional electrodes (second additional electrodes) are stacked at equal intervals in the vertical direction. The end 61a (71a) of each additional electrode 61 (71) is connected to the external electrode 4-1 (4-2). The plurality of additional electrodes 61 (71) are skewered by the two via holes 62, 62 (72, 72), and end portions 62a, 62a (72a, 72a) of the via holes 62, 62 (72, 72). ) Is connected to the end 31 a (31 b) of the signal electrode 31.
On the other hand, in the additional electrode group 8 (9), as shown in FIG. 28, an additional electrode 81 (91) as a third additional electrode (fourth additional electrode) is laminated at equal intervals in the vertical direction. An end 81a (91a) of the electrode 81 (91) is connected to the external electrode 4-3 (4-4). The plurality of additional electrodes 81 (91) are skewered by two via holes 82 and 82 (92 and 92), and end portions 82a and 82a (92a and 92a) of the via holes 82 and 82 (92 and 92) are inserted. ) Is connected to the end portion 32 a (32 b) of the ground electrode 32.

FIG. 29 is a plan view showing an arrangement of lands and via holes for mounting a three-terminal capacitor, and FIG. 30 is a schematic cross-sectional view showing a three-terminal capacitor mounting structure.
As shown in FIG. 29, the three-terminal capacitor 3-3 having the above structure is mounted on lands 41 to 44 as first to fourth lands.
These lands 41 to 44 are arranged in a square shape on the back surface 2 b of the circuit board 2, but are not directly connected to the via holes connected to the power supply terminal and the ground terminal of the IC 1. The lands 41 to 44 are connected to the via holes 26 to 29 through patterns 26a to 29a as first to fourth patterns.
Specifically, as shown in FIG. 30, the via hole 26 (27) is connected to the power supply terminal 16 of the IC1, and as shown in FIG. In addition, a plurality of them are arranged at positions on the land 41 (42) side with a diagonal line (not shown) connecting the lands 43 and 44 as a boundary. Each via hole 26 (27) is connected to the land 41 (42) through the pattern 26a (27a). On the other hand, the via hole 28 (29) is connected to the ground terminal 17 of the IC 1 as shown in FIG. 30, and is inside the square G and connects the lands 41 and 42 as shown in FIG. A plurality of lines are arranged at positions on the land 43 (44) side with a diagonal line (not shown) as a boundary. Each via hole 28 (29) is connected to a land 43 (44) through a pattern 28a (29a).
The three-terminal capacitor 3-3 is mounted on these lands 41 to 44, and the external electrodes 4-1 to 4-24 are connected to the lands 41 to 44 by soldering or the like, respectively.

Next, the operation and effect of the three-terminal capacitor mounting structure of this embodiment will be described.
FIG. 31 is a cross-sectional view showing a current input to the signal electrode, and FIG. 32 is a partially enlarged cross-sectional view for explaining an effect when a current is input to the signal electrode.

When the intermittent current I is generated at the power supply terminal 16 of the IC 1 shown in FIG. 30, the intermittent current I reaches the pattern 26a (27a) through the via hole 26 (27) as shown in FIG. The intermittent current I flows on the pattern 26a (27a) toward the land 41 (42) and is input from the land 41 (42) to the external electrode 4-1 (4-2).
Then, the intermittent current I includes the signal electrode 31 connected in parallel to the external electrode 4-1 (4-2), and the additional electrode 61 (71) positioned above and below the end 31a (31b) of the signal electrode 31. To the inside of the three-terminal capacitor 3-3. Then, the intermittent current I flowing through each additional electrode 61 (71) of the additional electrode 61 (71) merges with the signal electrode 31 through the via hole 62 (72).
Incidentally, as described above, in the three-terminal capacitor 3-3 of this embodiment, the additional electrode group 6 (7) and the signal electrode 31 are connected in parallel to the external electrode 4-1 (4-2). Therefore, the inductance of the path from the external electrode 4-1 (4-2) to the signal electrode 31 with respect to the intermittent current I is reduced.
The additional electrode group 6 (7) also has a parallel connection structure in which a plurality of additional electrodes 61 (71) are connected in a skewered manner by one or more via holes 62 (72). 7) The inductance itself is small.

Further, as described above, the intermittent current I from the power supply terminal 16 to the via hole 26 (27) flows toward the land 41 (42) on the pattern 26a (27a).
At this time, as shown in FIG. 29, the via hole 26 (27) is located inside the square G defined by the lands 41 to 44, and the external electrode 4-1 (4- 2) is located on the land 41 (42). Then, the additional electrode 61 (71) of the additional electrode group 6 (7) faces the inside of the three-terminal capacitor 3-3 in a state where it is connected to the external electrode 4-1 (4-2).
Therefore, as shown in FIG. 32, the direction of the intermittent current I flowing on the pattern 26a (27a) and the direction of the intermittent current I flowing on the additional electrode 61 (71) of the additional electrode group 6 (7) are reversed. It has become. Therefore, for example, if the inductance of the pattern 26a (27a) is L6, the inductance of the additional electrode 61 (71) is L7, and the mutual inductance is M67, the total inductance is L6 + l7-2 × M67, and 2 × M67. As a result, the inductance decreases.

FIG. 33 is a cross-sectional view showing a current output from the ground electrode 32, and FIG. 34 is a partially enlarged cross-sectional view for explaining an effect when a current is output from the ground electrode 32.
When the intermittent current I flows into the signal electrode 31, it reaches the ground electrode 32 as shown in FIG. 33, and this intermittent current I flows toward the end 32 a (32 b) of the ground electrode 32.
Then, the intermittent current I is directly output from the end portion 32a (32b) of the ground electrode 32 to the external electrode 4-3 (4-4) and input to the additional electrode group 8 (9) through the via hole 82 (92). Then, it outputs to the external electrode 4-3 (4-4) through the additional electrode 81 (91).
Even in such a state, since the additional electrode group 8 (9) and the ground electrode 32 are connected in parallel to the external electrode 4-3 (4-4), the additional electrode for the intermittent current I is provided. The inductance of the path from the group 8 (9) and the ground electrode 32 to the external electrode 4-3 (4-4) is also small.
Further, since the additional electrode group 8 (9) has a parallel connection structure in which a plurality of additional electrodes 81 (91) are connected by one or more via holes 82 (92), the additional electrode group 8 (9) itself The inductance of is also small.

Then, as shown in FIG. 34, the intermittent current I output to the external electrode 4-3 (4-4) travels from the land 43 (44) to the via hole 28 (29) on the pattern 28a (29a). As shown in FIG. 29, the external electrode 4-3 (4-4) of the three-terminal capacitor 3-3 is located on the land 43 (44), and the via hole 28 (29) is formed on the lands 41 to 44. 34, the intermittent current I flowing through the additional electrode 81 (91) of the additional electrode group 8 (9) is directed to the outside of the three-terminal capacitor 3-3 as shown in FIG. The direction of the intermittent current I flowing on the pattern 28a (29a) is reversed. As a result, as in the case of the additional electrode group 6 (7) and the pattern 26a (27a), a negative mutual inductance is generated between the additional electrode group 8 (9) and the pattern 28a (29a). The minute inductance will decrease.
When the intermittent current I flowing through the pattern 28a (29a) reaches the via hole 28 (29), it returns to the ground terminal 17 of the IC1 shown in FIG. 30 through the via hole 28 (29).
Since other configurations, operations, and effects are the same as those in the first to fourth embodiments, description thereof is omitted.

(Example 6)
Next explained is the sixth embodiment of the invention.
FIG. 35 is a sectional view showing the signal electrode side of a three-terminal capacitor applied to the three-terminal capacitor mounting structure according to the sixth embodiment of the present invention, and FIG. 36 is a sectional view showing the ground electrode side of the three-terminal capacitor. FIG.
This embodiment differs from the fifth embodiment in that the via hole of the additional electrode group is also connected to the external electrode.

Specifically, as shown in FIG. 35, the end 62b (72b) of the via hole 62 (72) provided in the additional electrode group 6 (7) of the three-terminal capacitor 3-4 is connected to the external electrode 4-1 ( 4-2) It extended to the side. Then, the end 62b (72b) is connected to the upper end 4-1a (4-2a) and the lower end 4- 1b (4-2b).
That is, the external electrode 4-1 (4-2) and the additional electrode group 6 (7) were connected in parallel.

On the other hand, in the additional electrode group 8 (9) of the three-terminal capacitor 3-4, as shown in FIG. 36, the end portion 82b (92b) of the via hole 82 (92) is connected to the external electrode 4-3 (4-4) side. The end 82b (92b) was connected to the upper end 4-3a (4-4a) and the lower end 4-3b (4-4b) of the external electrode 4-3 (4-4).
That is, the external electrode 4-3 (4-4) and the additional electrode group 8 (9) were connected in parallel.

  With this configuration, the additional electrode group 6 (7) and the external electrode 4-1 (4-2) are combined by the parallel connection effect of the external electrode 4-1 (4-2) and the additional electrode group 6 (7). The inductance is reduced, and the additional electrode group 8 (9) and the external electrode 4-3 (4-4) are caused by the parallel connection effect of the external electrode 4-3 (4-4) and the additional electrode group 8 (9). And the total inductance decreases.

Inventors etc. performed the following simulations in order to confirm this effect.
FIG. 37 is a diagram showing the results of simulation.
First, in the three-terminal capacitor 3-3 applied in the fifth embodiment, the three-terminal capacitors excluding the additional electrode groups 6 to 9 are mounted on the lands 41 to 44 shown in FIG. 29, and a current with a frequency of 100 MHz to 3 GHz is applied. The impedance was input to the via holes 26 and 27 and the impedance of the via holes 26 and 27 was measured. Then, a curve S1 indicated by a one-dot chain line in FIG. 37 was obtained.
Next, the three-terminal capacitor 3-3 of the fifth embodiment having the additional electrode groups 6 to 9 is mounted on the lands 41 to 44, and a current having a frequency of 100 MHz to 3 GHz is input to the via holes 26 and 27. , 27 impedance was measured. Then, a curve S2 indicated by a two-dot chain line in FIG. 37 was obtained.
As is apparent from these curves S1 and S2, the impedance of the via holes 26 and 27 is lower when the three-terminal capacitor of the fifth embodiment having the additional electrode groups 6 to 9 is used, and the additional electrode groups 6 to 9 are used. It can be seen that there is a noise suppression effect as compared with the case of using a three-terminal capacitor without any.
Further, the three-terminal capacitor 3-4 of the sixth embodiment having additional electrode groups 6 to 9 and via holes 62 to 92 connected to the external electrodes 4-1 to 4-4 is mounted on the lands 41 to 44. A current of a frequency of 100 MHz to 3 GHz was input to the via holes 26 and 27, and the impedance of the via holes 26 and 27 was measured. Then, a curve S3 indicated by a solid line in FIG. 37 was obtained.
As is apparent from the curve S3, it is found that when the three-terminal capacitor 3-5 of this embodiment is used, the impedance of the via holes 26 and 27 is the lowest, and the highest noise suppression effect can be obtained. It was.
Other configurations, operations, and effects are the same as those in the fifth embodiment, and thus description thereof is omitted.

(Example 7)
Next, a seventh embodiment of the present invention will be described.
FIG. 38 is a perspective view showing a three-terminal capacitor applied to the three-terminal capacitor mounting structure according to the seventh embodiment of the present invention, and FIG. 39 shows a land for mounting the three-terminal capacitor and an external portion. It is a top view which shows the positional relationship with an electrode.
This embodiment differs from the fifth and sixth embodiments in the arrangement of external electrodes.
That is, as shown in FIG. 38, in the three-terminal capacitor 3-5, the signal electrode 31 and the ground electrode 32 are arranged so as to face the center of the side surface of the chip body 30. Then, the external electrodes 4-1 and 4-2 are disposed and connected to the side surfaces corresponding to the end portions 31a and 31b of the signal electrode 31, respectively, and the external electrodes 4-3 and 4-3 are connected to the ground electrode 32. The side portions corresponding to the end portions 32a and 32b are disposed and connected. The additional electrode group 6 (7) is provided directly above and directly below the end 31a (31b) of the signal electrode 31, and the additional electrode group 8 (9) is directly above the end 32a (32b) of the ground electrode 32. And just below.

With this configuration, as shown in FIG. 39, the three-terminal capacitors 3-5 can be mounted on the lands 41 to 44 by connecting the external electrodes 4-1 to 4-4 to the lands 41 to 44.
Other configurations, operations, and effects are the same as those in the fifth and sixth embodiments, and thus description thereof is omitted.

In addition, this invention is not limited to the said Example, A various deformation | transformation and change are possible within the range of the summary of invention.
For example, in the above-described embodiment, the example in which the three-terminal capacitors 3-1 to 3-5 in which the signal electrode 31 and the ground electrode 32 pass through the corners and the center of the side surface of the chip body 30 is described. The structure of is not limited to this. That is, as shown in FIG. 40, the lengths of the signal electrode 31 and the ground electrode 32 facing each other in the vertical direction of the square chip body 30 are equal, and the straight line m1 connecting both ends 31a and 31b of the signal electrode 31 and the ground If the straight line m2 connecting both end portions 32a and 32b of the electrode 32 is orthogonal to each other at the center, the signal electrode 31 and the ground electrode 32 are shifted from the corners and the center of the chip body 30. Even a three-terminal capacitor is included in the scope of the present invention.
In the fifth embodiment, as shown in FIG. 29, all of the plurality of via holes 26 (27) connected to the power supply terminal 16 and the plurality of via holes 28 (29) connected to the ground terminal 17 are used. However, the present invention is not limited to this, and at least one of the plurality of via holes connected to the power supply terminal 16 is not limited to this. The invention of a structure in which a part of the via holes and at least a part of the via holes connected to the ground terminal 17 are arranged inside the square G is also included in the scope of the present invention. Therefore, for example, as shown in FIG. 41, two via holes 26 and 27 among the six via holes respectively connected to the power supply terminal 16 and two via holes among the six via holes respectively connected to the ground terminal 17 28 and 29 are arranged inside the square G, the via hole 26 is connected to the land 41 through the pattern 26a, the via hole 27 is connected to the land 42 through the pattern 27a, and the via hole 28 is connected to the land 43 through the pattern 28a, An invention in which the via hole 29 is connected to the land 44 through the pattern 29a is also included in the scope of the three-terminal capacitor mounting structure of the present invention.
Further, the three-terminal capacitor 3-3 of the fifth embodiment, the three-terminal capacitor 3-4 of the sixth embodiment, and the three-terminal capacitor 3-5 of the seventh embodiment are used as the via holes 21 to 24 of the first embodiment. Obviously, each can be implemented.

  DESCRIPTION OF SYMBOLS 1 ... IC, 2 ... Circuit board, 2a ... Front surface, 2b ... Back surface, 3-1 to 3-5 ... 3-terminal capacitor, 4-1 to 4-4 ... External electrode, 5 ... 2-terminal capacitor, 6-9 ... Additional electrode group, 11, 12, 16 ... power supply terminal, 13, 14, 17 ... ground terminal, 21-24, 26-29, 62, 72, 82, 92 ... via hole, 21a-24a, 21b-24b, 26a- 29a ... pattern, 21c-24c, 21d-24d, 41-44d ... land, 30 ... chip body, 30a-30d ... corner, 31 ... signal electrode, 32 ... ground electrode, 33 ... insulating layer, 31a, 31b, 32a 32b, 61a, 62a, 62b, 71a, 72a, 72b, 81a, 82a, 82b, 91a, 92a, 92b ... end, 61, 71, 81, 91 ... additional electrode, 00 ... power supply 110 ... ground, 120 ... solder, A, B, B '... minimum square, to d ... sides.

Claims (12)

A three-terminal capacitor is formed on the outer surface of the chip body including a pair of signal electrodes and ground electrodes facing each other in the vertical direction, and is electrically connected to both ends of the signal electrode. A three-terminal capacitor comprising: first and second external electrodes; and third and fourth external electrodes formed on the outer surface of the chip body and electrically connected to both ends of the ground electrode. The chip body is formed in a square shape in plan view, the length between both ends of the signal electrode and the length between both ends of the ground electrode are set to be approximately equal, and both ends of the signal electrode are The signal electrode and the ground electrode are arranged to face each other so that the straight line connecting and the straight line connecting both ends of the ground electrode are orthogonal to each other at substantially the center of each straight line, and exposed to the outer surface of the chip body. Three terminals in which the first and second external electrodes are connected to both ends of the signal electrode, and the third and fourth external electrodes are connected to both ends of the ground electrode exposed on the outer surface of the chip body. A capacitor,
An IC having BGA type terminals in which a plurality of terminals are arranged in a square lattice shape is mounted on the surface of the circuit board,
A three-terminal capacitor mounting structure in which the three-terminal capacitor is mounted on the back surface of the circuit board and at a position almost directly behind the IC,
In at least one minimum square constituting the BGA type terminal, a pair of power supply terminals are arranged at the vertices on one diagonal line, and a pair of ground terminals are arranged at the vertices on the other diagonal line, respectively.
In the circuit board, a plurality of via holes that are vertically connected to the circuit board and exposed on the back surface are provided in a state of being connected to the BGA type terminals.
The first and second external electrodes connected to both ends of the signal electrode of the three-terminal capacitor are electrically connected to the first and second via holes connected to the pair of power supply terminals of the minimum square, respectively. The third and fourth external electrodes connected to both ends of the ground electrode of the three-terminal capacitor are connected to the third and fourth via holes connected to the pair of ground terminals of the smallest square, respectively. In the electrically connected 3-terminal capacitor mounting structure,
Each via hole of the first to fourth via holes is closest to each via hole through a pair of patterns separately extending from the respective via holes to the outside in the side direction of the first to fourth via holes on the back surface of the circuit board. Each connected to a pair of via holes,
A three-terminal capacitor mounting structure. In the three-terminal capacitor mounting structure according to claim 1,
The three-terminal capacitor has both ends of the signal electrode positioned at opposite corners on one diagonal of the chip body, and both ends of the ground electrode are positioned at opposite corners on the other diagonal. The first and second external electrodes are electrically connected to both ends of the signal electrode at the one corner of the chip body, and the third and fourth external electrodes are connected to the chip body. A three-terminal capacitor electrically connected to both ends of the ground electrode at the other two corners of
A three-terminal capacitor mounting structure. In the three-terminal capacitor mounting structure according to claim 1,
The three-terminal capacitor has both ends of the signal electrode positioned at the centers of the opposite side surfaces of the chip body, and both ends of the ground electrode are positioned at the centers of the other opposite side surfaces, The first and second external electrodes are electrically connected to both ends of the signal electrode at the center of both side surfaces of the chip body, and the third and fourth external electrodes are connected to the other of the chip body. A three-terminal capacitor electrically connected to both ends of the ground electrode at the center of both side surfaces of
A three-terminal capacitor mounting structure. In the three-terminal capacitor mounting structure according to claim 2 or claim 3,
The three-terminal capacitor
A plurality of first additional electrodes are stacked at equal intervals directly above or directly below one end of the signal electrode, and the ends of the first additional electrodes are connected to the first electrode. A plurality of first additional electrodes are connected to each other by one or more via holes, and one end portion of the via hole facing the signal electrode side is connected to the one end portion of the signal electrode. A first additional electrode group configured by connection;
A plurality of second additional electrodes are stacked at equal intervals directly above or directly below the other end of the signal electrode, and the ends of the second additional electrodes are stacked at the second end. The plurality of second additional electrodes are connected to each other by one or more via holes, and one end portion of the via hole facing the signal electrode side is connected to the other end portion of the signal electrode. A second additional electrode group configured in a connected manner;
A plurality of third additional electrodes are laminated at equal intervals directly above or directly below one end of the ground electrode, and the ends of the third additional electrodes are connected to the third electrode. The plurality of third additional electrodes are connected to each other by one or more via holes, and one end portion of the via hole facing the ground electrode side is connected to the one end portion of the ground electrode. A third additional electrode group configured in a connected manner;
A plurality of fourth additional electrodes are laminated at equal intervals directly above or directly below the other end of the ground electrode, and the ends of the fourth additional electrode are connected to the fourth electrode. Connect to the external electrode and connect the plurality of fourth additional electrodes to each other by one or more via holes, and connect one end of the via hole facing the ground electrode to the other end of the ground electrode. A three-terminal capacitor provided with a fourth additional electrode group configured as described above,
A three-terminal capacitor mounting structure. In the three-terminal capacitor mounting structure according to claim 4,
The three-terminal capacitor
The other end portion of the via hole provided in the first additional electrode group is extended and connected to the upper end portion or the lower end portion of the first external electrode located on the upper surface or the lower surface of the chip body. By connecting the first external electrode and the first additional electrode group in parallel,
The other end portion of the via hole provided in the second additional electrode group is extended and connected to the upper end portion or the lower end portion of the second external electrode located on the upper surface or the lower surface of the chip body. By connecting the second external electrode and the second additional electrode group in parallel,
The other end portion of the via hole provided in the third additional electrode group is extended and connected to the upper end portion or the lower end portion of the third external electrode located on the upper surface or the lower surface of the chip body. By connecting the third external electrode and the third additional electrode group in parallel,
The other end portion of the via hole provided in the fourth additional electrode group is extended and connected to the upper end portion or the lower end portion of the fourth external electrode located on the upper surface or the lower surface of the chip body. This is a three-terminal capacitor in which the fourth external electrode and the fourth additional electrode group are connected in parallel.
A three-terminal capacitor mounting structure. In the three-terminal capacitor mounting structure according to any one of claims 4 and 5 that cites claim 2 and claim 2 ,
The size of the three-terminal capacitor is set approximately equal to the size of the minimum square,
The first and second external electrodes of the three-terminal capacitor are respectively connected to the first and second via holes connected to the pair of power supply terminals of the minimum square, and the third and fourth external electrodes are connected to the first and second via holes. , Respectively connected to the third and fourth via holes connected to the pair of ground terminals of the minimum square,
A three-terminal capacitor mounting structure. In the three-terminal capacitor mounting structure according to any one of claims 4 and 5 that cites claim 2 and claim 2 ,
The size of the three-terminal capacitor is set smaller than the size of the minimum square,
On the back surface of the circuit board, the first and second lands having a predetermined length are drawn out from the first and second via holes connected to the pair of power supply terminals of the minimum square, and connected to the pair of ground terminals. By extracting the third and fourth lands having a predetermined length from the formed third and fourth via holes, a square substantially equal to the size of the three-terminal capacitor is defined by the first to fourth lands. ,
The first and second external electrodes of the three-terminal capacitor are connected to the first and second lands, respectively, and the third and fourth external electrodes are connected to the third and fourth lands, respectively.
A three-terminal capacitor mounting structure. In the three-terminal capacitor mounting structure according to any one of claims 4 and 5 quoting claim 3 and claim 3 ,
Set the size of the three-terminal capacitor larger than the size of the minimum square,
The first and second external electrodes of the three-terminal capacitor are respectively connected to the first and second via holes connected to the pair of power supply terminals of the minimum square, and the third and fourth external electrodes are connected to the first and second via holes. , Respectively connected to the third and fourth via holes connected to the pair of ground terminals of the minimum square,
A three-terminal capacitor mounting structure. In the three-terminal capacitor mounting structure according to any one of claims 4 and 5 quoting claim 3 and claim 3 ,
The size of the three-terminal capacitor is set to a size that passes through the pair of via holes connected through a pair of patterns in which each side surface separately extends outward in the side direction of the first to fourth via holes. The pair of via holes are connected by a land formed on the back surface of the circuit board,
A first external electrode of the three-terminal capacitor is connected to a land connecting the tip portions of the pair of patterns separately extending outward in the side direction of the first via hole;
The second external electrode is connected to a land connecting the tip portions of the pair of patterns separately extending to the outside in the side direction of the second via hole,
The third external electrode is connected to a land connecting the tip portions of the pair of patterns separately extending outward in the side direction of the third via hole,
The fourth external electrode was connected to a land connecting the tip portions of the pair of patterns separately extending to the outside in the side direction of the fourth via hole.
A three-terminal capacitor mounting structure. A three-terminal capacitor is formed on the outer surface of the chip body including a pair of signal electrodes and ground electrodes facing each other in the vertical direction, and is electrically connected to both ends of the signal electrode. First and second external electrodes, and third and fourth external electrodes formed on the outer surface of the chip body and electrically connected to both ends of the ground electrode, respectively, Are formed in a square shape in plan view, the length between both ends of the signal electrode and the length between both ends of the ground electrode are set substantially equal, and a straight line connecting both ends of the signal electrode and the ground electrode The signal electrode and the ground electrode are arranged to face each other so that a straight line connecting both ends of each of the straight lines is orthogonal to each other at substantially the center of each straight line. ,the above A three-terminal capacitor for connecting the first and second external electrodes and connecting the third and fourth external electrodes to both ends of the ground electrode exposed on the outer surface of the chip body, Both end portions are positioned at both corner portions facing on one diagonal line of the chip body, and both end portions of the ground electrode are positioned at both corner portions facing on the other diagonal line, respectively. An electrode is electrically connected to both ends of the signal electrode at the one corner of the chip body, and the third and fourth external electrodes are connected to the ground at the other corner of the chip body. A three-terminal capacitor electrically connected to both ends of the electrode, wherein the three-terminal capacitor connects a plurality of first additional electrodes directly above or directly below one end of the signal electrode. The first additional electrodes are stacked at equal intervals on either or both sides, and the end portions of the first additional electrodes are connected to the first external electrode, and one or more via holes are used to connect the end portions of the first additional electrodes. A first additional electrode group configured by connecting one end of the via hole facing the signal electrode side to the one end of the signal electrode, and a plurality of second additional electrodes, The signal electrodes are laminated at equal intervals directly above or below the other end of the signal electrode, and the ends of the second additional electrodes are connected to the second external electrode, and The plurality of second additional electrodes are connected to each other by the via hole, and the second additional electrode is configured by connecting one end of the via hole facing the signal electrode side to the other end of the signal electrode. A group and a plurality of third additional electrodes The ground electrodes are stacked at equal intervals directly above or both below one end of the ground electrode, and the ends of the third additional electrodes are connected to the third external electrode, The plurality of third additional electrodes are connected to each other by the via hole, and a third additional electrode configured by connecting one end of the via hole facing the ground electrode to the one end of the ground electrode. A group and a plurality of fourth additional electrodes are laminated at equal intervals directly above or directly below the other end of the ground electrode, or at the ends of the fourth additional electrode. The plurality of fourth additional electrodes are connected to each other by one or more via holes, and one end portion of the via hole facing the ground electrode side is connected to the other end of the ground electrode. Connected to A fourth three-terminal capacitor is provided an additional electrode group configured Te,
An IC having a BGA type terminal in which a plurality of terminals are arranged in a square lattice pattern is mounted on the surface of the circuit board, and the three-terminal capacitor is mounted on the back surface of the circuit board and at a position almost directly behind the IC. In the three-terminal capacitor mounting structure, in at least one minimum square constituting the BGA type terminal, a pair of power supply terminals are arranged at one of the diagonal lines, and 1 is set at the other diagonal line. A pair of ground terminals are provided, and a plurality of via holes are formed in the circuit board so as to penetrate the circuit board vertically and exposed on the back surface in a state of being connected to the BGA type terminal. The first and second external electrodes connected to both ends are electrically connected to the first and second via holes connected to the pair of power supply terminals of the smallest square, respectively. In addition, the third and fourth external electrodes connected to both ends of the ground electrode of the three-terminal capacitor are electrically connected to the third and fourth via holes connected to the pair of ground terminals of the minimum square, respectively. In the three-terminal capacitor mounting structure connected to
The first to fourth external electrodes of the three-terminal capacitor are mounted on and connected to first to fourth lands arranged in a square shape on the back surface of the circuit board, respectively.
At least some of the plurality of via holes connected to the plurality of power supply terminals, and at least some of the plurality of via holes connected to the plurality of ground terminals. Or placed inside the square defined by the 4th land,
Among the plurality of via holes connected to the power supply terminal, via holes located on the first land side with the diagonal line connecting the third land and the fourth land as a boundary to the first land through the first pattern And connecting the via hole located on the second land side to the second land through the second pattern,
Of the plurality of via holes connected to the ground, a via hole located on the third land side is connected to the third land through a third pattern with a diagonal line connecting the first land and the second land as a boundary. And via holes located on the fourth land side are connected to the fourth lands through a fourth pattern.
A three-terminal capacitor mounting structure. A three-terminal capacitor is formed on the outer surface of the chip body including a pair of signal electrodes and ground electrodes facing each other in the vertical direction, and is electrically connected to both ends of the signal electrode. First and second external electrodes, and third and fourth external electrodes formed on the outer surface of the chip body and electrically connected to both ends of the ground electrode, respectively, Are formed in a square shape in plan view, the length between both ends of the signal electrode and the length between both ends of the ground electrode are set substantially equal, and a straight line connecting both ends of the signal electrode and the ground electrode The signal electrode and the ground electrode are arranged to face each other so that a straight line connecting both ends of each of the straight lines is orthogonal to each other at substantially the center of each straight line. ,the above A three-terminal capacitor for connecting the first and second external electrodes and connecting the third and fourth external electrodes to both ends of the ground electrode exposed on the outer surface of the chip body, Both end portions are positioned at the centers of the opposing side surfaces of the chip body, and both end portions of the ground electrode are positioned at the centers of the other opposing side surfaces, and the first and second external electrodes are positioned The third and fourth external electrodes are electrically connected to both ends of the signal electrode at the center of both side surfaces of the chip body, and the ground electrode is connected to the center of the other side surfaces of the chip body. A three-terminal capacitor electrically connected to both ends of the first electrode, and the three-terminal capacitor includes a plurality of first additional electrodes, either directly above or directly below one end of the signal electrode, or both Product at equal intervals At the same time, the end portions of the first additional electrodes are connected to the first external electrode, and the plurality of first additional electrodes are connected to each other by one or more via holes. A first additional electrode group configured by connecting one end portion facing the signal electrode side to the one end portion of the signal electrode, and a plurality of second additional electrodes are connected to the other end portion of the signal electrode. The second additional electrodes are laminated at equal intervals on either or both of the upper and lower sides, and the ends of the second additional electrodes are connected to the second external electrode, and the plurality of second electrodes are connected by one or more via holes. A second additional electrode group configured by connecting two additional electrodes to each other and connecting one end of the via hole facing the signal electrode to the other end of the signal electrode, and a plurality of third electrodes Connect the additional electrode to the true end of one end of the ground electrode. Laminate the upper and / or lower layers at equal intervals, connect the end of the third additional electrode to the third external electrode, and connect the plurality of second electrodes by one or more via holes. A third additional electrode group configured by connecting the three additional electrodes to each other and connecting one end portion of the via hole facing the ground electrode side to the one end portion of the ground electrode, and a plurality of fourth electrodes The additional electrode is laminated at equal intervals directly above or directly below the other end of the ground electrode, and the end of the fourth additional electrode is connected to the fourth external electrode. A plurality of fourth additional electrodes are connected to each other by one or more via holes, and one end portion of the via hole facing the ground electrode side is connected to the other end portion of the ground electrode. Additional electrode group A 3-terminal capacitor provided with,
An IC having a BGA type terminal in which a plurality of terminals are arranged in a square lattice pattern is mounted on the surface of the circuit board, and the three-terminal capacitor is mounted on the back surface of the circuit board and at a position almost directly behind the IC. In the three-terminal capacitor mounting structure, in at least one minimum square constituting the BGA type terminal, a pair of power supply terminals are arranged at one of the diagonal lines, and 1 is set at the other diagonal line. A pair of ground terminals are provided, and a plurality of via holes are formed in the circuit board so as to penetrate the circuit board vertically and exposed on the back surface in a state of being connected to the BGA type terminal. The first and second external electrodes connected to both ends are electrically connected to the first and second via holes connected to the pair of power supply terminals of the smallest square, respectively. In addition, the third and fourth external electrodes connected to both ends of the ground electrode of the three-terminal capacitor are electrically connected to the third and fourth via holes connected to the pair of ground terminals of the minimum square, respectively. In the three-terminal capacitor mounting structure connected to
The first to fourth external electrodes of the three-terminal capacitor are mounted on and connected to first to fourth lands arranged in a square shape on the back surface of the circuit board, respectively.
At least some of the plurality of via holes connected to the plurality of power supply terminals, and at least some of the plurality of via holes connected to the plurality of ground terminals. Or placed inside the square defined by the 4th land,
Among the plurality of via holes connected to the power supply terminal, via holes located on the first land side with the diagonal line connecting the third land and the fourth land as a boundary to the first land through the first pattern And connecting the via hole located on the second land side to the second land through the second pattern,
Of the plurality of via holes connected to the ground, a via hole located on the third land side is connected to the third land through a third pattern with a diagonal line connecting the first land and the second land as a boundary. And via holes located on the fourth land side are connected to the fourth lands through a fourth pattern.
A three-terminal capacitor mounting structure. In the three-terminal capacitor mounting structure according to claim 10 or 11,
The three-terminal capacitor
The other end portion of the via hole provided in the first additional electrode group is extended and connected to the upper end portion or the lower end portion of the first external electrode located on the upper surface or the lower surface of the chip body. By connecting the first external electrode and the first additional electrode group in parallel,
The other end portion of the via hole provided in the second additional electrode group is extended and connected to the upper end portion or the lower end portion of the second external electrode located on the upper surface or the lower surface of the chip body. By connecting the second external electrode and the second additional electrode group in parallel,
The other end portion of the via hole provided in the third additional electrode group is extended and connected to the upper end portion or the lower end portion of the third external electrode located on the upper surface or the lower surface of the chip body. By connecting the third external electrode and the third additional electrode group in parallel,
The other end portion of the via hole provided in the fourth additional electrode group is extended and connected to the upper end portion or the lower end portion of the fourth external electrode located on the upper surface or the lower surface of the chip body. This is a three-terminal capacitor in which the fourth external electrode and the fourth additional electrode group are connected in parallel.
A three-terminal capacitor mounting structure.

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