JP5482400B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device, for example, a method for manufacturing a semiconductor device on which a semiconductor element is mounted.

  In recent years, techniques for mounting semiconductor elements in three dimensions have been developed. For example, a technique is known in which a first electronic component is mounted in a recess on the upper surface of a substrate, and a second electronic component is mounted on the recess (for example, Patent Document 1). For example, a technique is known in which an IC chip is mounted in a recess on the upper surface of a substrate, and an IC module is mounted on the recess (for example, Patent Document 2).

Japanese Utility Model Publication No. 7-42165 JP 2004-265955 A

  When a semiconductor element is mounted three-dimensionally, it is required to mount the semiconductor element at a low cost. For example, when a semiconductor element is mounted by applying a load to the semiconductor element on the recess for cost reduction, the semiconductor element may be damaged. The manufacturing method of this semiconductor device aims at suppressing damage to a semiconductor element.

For example, a step of mounting a first semiconductor element face up on the bottom surface of the recess of a substrate having a recess on the top surface, a step of disposing an elastic sheet as an elastic body on the top surface of the first semiconductor element, A step of applying a load to the upper surface of the second semiconductor element so that the lower surface of the semiconductor element is in contact with the upper surface of the elastic body, and bonding the second semiconductor element to the substrate. The manufacturing method can be used.

  According to the method for manufacturing a semiconductor device, damage to the semiconductor element can be suppressed.

FIG. 1A to FIG. 1D are diagrams illustrating a method for manufacturing a semiconductor device according to the first embodiment. FIG. 2A to FIG. 2D are cross-sectional views (part 1) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 3A to FIG. 3C are cross-sectional views (part 2) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 4A to FIG. 4D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the third embodiment.

  Embodiments will be described below with reference to the drawings.

  FIG. 1A to FIG. 1D are diagrams illustrating a method for manufacturing a semiconductor device according to the first embodiment. As shown in FIG. 1A, a recess 18 is formed on the upper surface of the insulating substrate 10. The substrate 10 is, for example, a ceramic substrate or a resin substrate. As shown in FIG. 1B, the first semiconductor element 30 is mounted in the recess 18. For example, the first semiconductor element 30 is mounted face up on the bottom surface of the recess 18. As shown in FIG. 1C, the elastic body 40 is disposed on the upper surface of the first semiconductor element 30. As shown in FIG. 1D, a load 60 is applied to the upper surface of the second semiconductor element 50 so that the lower surface of the second semiconductor element 50 is in contact with the upper surface of the elastic body 40, and the second semiconductor element 50 is bonded to the substrate 10. . For example, the second semiconductor element 50 is flip-chip mounted on the substrate 10 using the bumps 52. The first semiconductor element 30 and the second semiconductor element 50 may be silicon chips such as an LSI (Large Scale Integrated Circuit), for example.

  According to the first embodiment, since the load 60 is applied to the upper surface of the second semiconductor element 50 and the second semiconductor element 50 and the substrate 10 are joined, the second semiconductor element 50 can be mounted on the recess 18 at low cost. it can. Furthermore, since the elastic body is disposed between the first semiconductor element 30 and the second semiconductor element 50, the second semiconductor element 50 is prevented from being damaged due to the load 60 in FIG. be able to. In particular, when the semiconductor device is downsized, the thickness of the second semiconductor element 50 is reduced, and the second semiconductor element 50 is easily damaged. In the first embodiment, even in such a case, damage to the second semiconductor element 50 is suppressed, and the semiconductor device can be downsized.

  As the substrate 10, a ceramic substrate or a resin substrate can be used. When a load is applied to the upper surface of the second semiconductor element 50 to bond the second semiconductor element 50 to the substrate 10, it is preferable that there is a repulsive force of the substrate 10. Therefore, the substrate 10 preferably includes a resin layer. More preferably, at least the upper part of the substrate 10 above the bottom surface of the recess 18 is a resin layer.

  Further, as shown in FIG. 1D, by applying a load to the upper surface of the second semiconductor element 50 and flip-chip bonding the second semiconductor element 50 to the substrate 10, low-cost bonding can be performed.

  Example 2 is an example using a resin sheet as an elastic body. FIG. 2A to FIG. 3C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment. As shown in FIG. 2A, the substrate 10 is provided with a multilayer wiring layer 12, a core layer 14, and a multilayer wiring layer 16 laminated. Here, the surface and the inside of the multilayer wiring layer 12 and the wiring layer formed inside the multilayer wiring layer 12 are omitted. The multilayer wiring layer 12 includes one in which only one layer of wiring is formed on the surface. The film thicknesses of the multilayer wiring layer 12, the core layer 14, and the multilayer wiring layer 16 can be set to, for example, 0.4 mm, 0.3 mm, and 0.6 mm, respectively. The substrate 10 is provided with a recess 18. The recess 18 includes a step whose upper width is larger than the lower width. The size of the lower side of the recess 18 is, for example, 6 mm × 6 mm, and the size of the upper side is 8 mm × 8 mm. The recess 18 can be formed using a router processing method or a laser processing method. For example, a laser method can be used. Thereafter, the remaining shavings are washed. Ni is plated on the wiring of the substrate 10 exposed on the surface and the core layer 14 on the bottom surface 26 of the recess 18, and then Au plating. A metal layer 20 is provided as a pad outside the recess 18 on the upper surface of the substrate 10. A metal layer 22 is provided as a pad on the step surface 24 of the step in the recess 18. The multilayer wiring layers 12 and 16 are, for example, ceramic layers or resin layers, and preferably resin layers. The core layer 14 is a metal layer for heat dissipation of the first semiconductor element 30, for example, and is a metal containing Cu, for example. Since the core layer 14 is used for heat dissipation, it is preferable that the bottom surface 26 of the recess 18 reaches the core layer 14, for example. The metal layers 20 and 22 are, for example, a metal containing Au.

  As shown in FIG. 2B, for example, an adhesive is applied to the bottom surface 26 of the recess 18 as the die bond agent 28. As shown in FIG. 2C, the first semiconductor element 30 is mounted face up on the bottom surface 26 of the recess 18 via a die bond agent 28. The size of the first semiconductor element 30 is, for example, 5 mm × 5 mm, and the thickness is, for example, 200 μm. The pads of the first semiconductor element 30 and the metal layers 20 and 22 are cleaned using, for example, an oxygen asher. The pads of the first semiconductor element 30 and the metal layer 22 of the substrate 10 are connected using bonding wires 32. The pads of the first semiconductor element 30 are terminals for inputting / outputting power and input / output signals to / from the first semiconductor element 30. As the wire 32, for example, a wire containing at least Au or Cu can be used. The diameter of the wire 32 can be set to 25 μm, for example. The depth of the recess 18 is, for example, 600 μm, and the height from the bottom surface 26 to the step surface 24 is, for example, 200 μm. The depth of the recess 18 is preferably set to such a depth that the uppermost portion of the bonding wire 32 does not become higher than the upper surface of the substrate 10. Thereby, it can suppress that the upper part of the wire 32 contacts the 2nd semiconductor element 50 grade | etc.,.

  As shown in FIG. 2D, a sheet-like elastic body 40 is disposed on the first semiconductor element 30 and cured as necessary. The curing conditions are, for example, a temperature of 150 ° C. to 250 ° C. and a time of 10 minutes to 60 minutes, for example, 200 ° C. and 30 minutes. The size of the elastic body 40 is, for example, 2 mm × 2 mm. By disposing the elastic body 40 at the center of the first semiconductor element 30, it is possible to suppress damage to the wires 32 disposed around the first semiconductor element 30. The thickness of the elastic body 40 is preferably substantially equal to the height from the bottom surface 26 of the recess 18 to the lower surface of the second semiconductor element 50 described with reference to FIG. For example, it can be 400 μm. As the elastic body 40, a resin sheet containing at least one of a polyimide resin, an epoxy resin, and an acrylic resin, or a resin sheet obtained by curing these resins can be used. Further, a rubber filler may be included in at least one of a polyimide resin, an epoxy resin, and an acrylic resin. Further, an inorganic filler may be included. For example, when the elastic modulus of the resin sheet is 5 GPa or more, the second semiconductor element 50 may be damaged when the second semiconductor element 50 is bonded to the substrate 10. Therefore, the elastic modulus of the elastic body 40 is preferably less than 5 GPa.

  As shown in FIG. 3A, NCP42 (Non Conductive Paste) is applied so as to cover the metal layer 20. NCP is, for example, an underfill agent, which is an insulating resin such as epoxy containing an inorganic filler. Further, as NCP, a conductive resin in which insulation is secured in the lateral direction can also be used.

  As shown in FIG. 3B, bumps 52 are formed on the lower surface of the second semiconductor element 50. The size of the second semiconductor element 50 is, for example, 11 mm × 11 mm, and the thickness is, for example, 200 μm. The bumps 52 are terminals for inputting / outputting power and input / output signals to / from the second semiconductor element 50. The bump 52 is a metal bump such as an Au bump, for example, and is a bump formed by a stud bump method or a plating method. For example, Cu can be used as the bump 52 in addition to Au. The height of the bump 52 is, for example, 50 μm. The bump 52 and the metal layer 20 are aligned. A load 60 is applied to the upper surface of the second semiconductor element 50. The magnitude of the load 60 is, for example, 10 to 50 gf per bump 52. For example, it is 35 gf per bump. Further, for example, the second semiconductor element 50 is heated at a temperature of 120 to 250 ° C. for 3 to 30 seconds. For example, heating is performed at a temperature of 210 ° C. for 20 seconds. Thereby, the second semiconductor element 50 and the substrate 10 can be electrically bonded via the bump 52 and the metal layer 20. Further, by using NCP42 as a thermosetting resin, the NCP42 can be cured when the second semiconductor element 50 is heated, and the mechanical bonding between the second semiconductor element 50 and the substrate 10 can be strengthened. As a method of applying the load 60 from the upper surface of the second semiconductor element 50 and bonding the second semiconductor element 50 to the substrate 10, for example, ultrasonic bonding, pressure welding, or thermocompression bonding can be used. Thus, the semiconductor device according to Example 2 is completed as shown in FIG.

  As in the second embodiment, an elastic sheet can be arranged as the elastic body 40 on the first semiconductor element 30. Thereby, damage to the second semiconductor element 50 can be easily suppressed.

  Further, when the second semiconductor element 50 is bonded to the substrate 10, the metal bumps 52 formed on the second semiconductor element 50 and the metal layer 20 formed on the upper surface outside the recess 18 of the substrate 10 are connected. Thus, by joining the metal bump 52 and the metal layer 20 with the load 60, the electrical and mechanical joining between the second semiconductor element 50 and the substrate 10 can be more easily performed. Note that a metal layer (for example, a bad) may be provided on the second semiconductor element 50, and metal bumps may be provided outside the recess 18 of the substrate 10. That is, the metal bump 52 formed on one of the lower surface of the second semiconductor element 50 and the upper surface outside the recess 18 of the substrate 10, and the lower surface of the second semiconductor element 50 and the upper surface outside the recess 18 of the substrate 10. What is necessary is just to join the metal layer 20 formed in the other.

  Furthermore, when mounting the first semiconductor element 30 in the recess 18, the first semiconductor element 30 can be mounted face up on the bottom surface 26 of the recess 18. Thereby, the lower surface of the first semiconductor element 30 is joined to the entire bottom surface 26 of the recess 18. Therefore, even if the load 60 is applied to the first semiconductor element 30 through the elastic body 40, the first semiconductor element 30 can be prevented from being damaged.

  Further, the recess 18 includes a step whose upper width is larger than the lower width, and the first semiconductor element 30 and the step surface 24 formed at the step can be connected using the wire 32. Thereby, the 1st semiconductor element 30 and the board | substrate 10 can be electrically connected using the short wire 32. FIG.

  Further, the substrate 10 includes a core layer 14 and a multilayer wiring layer 16 formed on the core layer 14, and the recess 18 reaches the core layer 14, and the first semiconductor element 30 is placed on the core layer 14. It is preferable to implement. Thereby, the heat of the first semiconductor element 30 can be released through the core layer 14. Note that the multilayer wiring layer 12 under the core layer 14 may not be provided.

  Example 3 is an example in which a potting agent is used as an elastic body. FIG. 4A to FIG. 4D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the third embodiment. The same steps as those in FIGS. 2A to 2C are performed. In FIG. 2A, the recess 18 is formed by using the router method. The lower size of the recess 18 is, for example, 7 mm × 7 mm, and the upper size is, for example, 9 mm × 9 mm. In FIG. 2B, the first semiconductor element 30 having a size of 6 mm × 6 mm and a thickness of 300 μm is mounted face up on the bottom surface 26. The other steps are the same as those in FIG. 2A to FIG. 2C of the first embodiment, and a description thereof will be omitted. As shown in FIG. 4A, a liquid member 41 that is a liquid thermosetting resin is disposed on the first semiconductor element 30. As the liquid member 41, for example, a potting agent such as at least one of a polyimide resin, an epoxy resin, and an acrylic resin can be used. For example, the liquid member 41 containing an epoxy resin is used. The liquid member 41 is disposed so as to cover the wire 32. For example, the liquid member 41 is heat-treated at a temperature of 150 ° C. for 30 minutes to be cured. Thereby, the elastic body 40 is formed from the liquid member 41. As shown in FIG. 4B, the NCP 42 is provided so as to cover the metal layer 20 as in FIG. 3A of the second embodiment.

  As shown in FIG. 4C, a load 60 is applied to the upper surface of the second semiconductor element 50 in the same manner as in FIG. The size of the second semiconductor element 50 is, for example, 11.5 mm × 11.5 mm, and the thickness is, for example, 200 μm. The magnitude of the load 60 is 40 gf per bump, for example. The second semiconductor element 50 is heated through the NCP 42 at a temperature of, for example, 200 ° C. for 10 seconds. Thereby, the second semiconductor element 50 and the substrate 10 can be connected via the bumps 52. Thus, the semiconductor device according to Example 3 is completed as shown in FIG.

  4A to 4D, a semiconductor device according to a comparative example was manufactured in which the liquid member 41 was not applied and the other steps were the same as the method illustrated in Example 3. In the comparative example, when the load 60 in FIG. 4C was applied, the second semiconductor element 50 was cracked. On the other hand, in the semiconductor device manufactured by the method illustrated in Example 3, the second semiconductor element 50 did not crack. Thus, according to the third embodiment, damage to the second semiconductor element 50 can be suppressed.

  Further, as shown in FIG. 4A, a thermosetting resin is disposed on the first semiconductor element 30. By applying heat to the thermosetting resin, the thermosetting resin can be cured to form the elastic body 40. Thereby, the elastic body 40 can be formed. Further, as shown in FIG. 4A, the liquid member 41 covers the wire 32 so that the wire 32 can be protected.

  In the first to third embodiments, a heat release conductive layer may be brought into contact with the upper surface of the second semiconductor element 50. Furthermore, one or more semiconductor elements may be stacked on the first semiconductor element 30. For example, one or more other semiconductor elements may be stacked face up on the first semiconductor element 30 and the elastic body 40 may be disposed on the uppermost semiconductor element. One or more semiconductor elements may be stacked on the second semiconductor element 50. For example, one or more other semiconductor elements may be stacked face up on the upper surface of the second semiconductor element 50.

  Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

The following additional remarks are disclosed regarding the embodiment including Examples 1 to 3.
(Additional remark 1): The process of mounting a 1st semiconductor element in the said recessed part of the board | substrate provided with a recessed part on the upper surface, the process of arrange | positioning an elastic body on the upper surface of the said 1st semiconductor element, The lower surface of a 2nd semiconductor element is Applying a load to the upper surface of the second semiconductor element so as to be in contact with the upper surface of the elastic body, and bonding the second semiconductor element to the substrate.
(Additional remark 2): The said board | substrate contains a resin layer, The manufacturing method of the semiconductor device of Additional remark 1 characterized by the above-mentioned.
(Appendix 3): The step of bonding the second semiconductor element to the substrate includes the step of flip-chip bonding the second semiconductor element to the substrate. Method.
(Supplementary Note 4): The step of bonding the second semiconductor element to the substrate includes metal bumps formed on one of a lower surface of the second semiconductor element and an upper surface outside the concave portion of the substrate; 4. The semiconductor device according to claim 1, further comprising a step of bonding a lower surface of the semiconductor element and a metal layer formed on the other of the upper surface outside the concave portion of the substrate. Production method.
(Supplementary note 5): The step of disposing an elastic body on the first semiconductor element includes a step of disposing an elastic sheet on the first semiconductor. Semiconductor device manufacturing method.
(Additional remark 6): The process of arrange | positioning an elastic body on the said 1st semiconductor element is the process of arrange | positioning a thermosetting resin on the said 1st semiconductor, and adding the heat to the said thermosetting resin, and the said thermosetting resin. The method for manufacturing a semiconductor device according to any one of appendices 1 to 4, further comprising: forming the elastic body by curing.
(Appendix 7): The step of mounting the first semiconductor element is a step of mounting the first semiconductor element face up on the bottom surface of the recess. The manufacturing method of the semiconductor device of description.
(Supplementary Note 8): The concave portion includes a step in which an upper width is larger than a lower width, and includes a step of connecting the first semiconductor element and a step surface formed in the step using a wire. The method for manufacturing a semiconductor device according to appendix 7.
(Supplementary Note 9): The substrate includes a core layer and a multilayer wiring layer formed on the core layer, the recess reaches the core layer, and the step of mounting the first semiconductor element includes The method for manufacturing a semiconductor device according to any one of appendices 1 to 8, further comprising a step of mounting the first semiconductor element on the core layer.

DESCRIPTION OF SYMBOLS 10 Board | substrate 12, 16 Multilayer wiring layer 14 Core layer 18 Recessed part 20, 22 Metal layer 24 Step surface 30 1st semiconductor element 32 Wire 40 Elastic body 50 2nd semiconductor element 52 Bump 60 Load

Claims (5)

Mounting the first semiconductor element face up on the bottom surface of the recess of the substrate having a recess on the top surface;
Disposing an elastic sheet as an elastic body on the upper surface of the first semiconductor element;
Applying a load to the upper surface of the second semiconductor element so that the lower surface of the second semiconductor element is in contact with the upper surface of the elastic body, and bonding the second semiconductor element to the substrate;
A method for manufacturing a semiconductor device, comprising: Mounting the first semiconductor element face up on the bottom surface of the recess of the substrate having a recess on the top surface;
Disposing a liquid member which is a thermosetting resin on the upper surface of the first semiconductor element;
Forming the elastic body by thermosetting the liquid member;
Applying a load to the upper surface of the second semiconductor element so that the lower surface of the second semiconductor element is in contact with the upper surface of the elastic body, and flip-chip bonding the second semiconductor element to the substrate;
A method for manufacturing a semiconductor device, comprising:   3. The method for manufacturing a semiconductor device according to claim 1, wherein the substrate includes a resin layer. The second step of bonding the semiconductor element to the substrate, a method of manufacturing a semiconductor device according to claim 1, comprising the step of flip-chip bonding the second semiconductor element to the substrate.   The concave portion includes a step in which an upper width is larger than a lower width, and includes a step of connecting the first semiconductor element and a step surface formed in the step using a wire. 5. A method for manufacturing a semiconductor device according to any one of claims 1 to 4.

Images