JPH098222A - Electronic component device with mounted semiconductor device - Google Patents
Electronic component device with mounted semiconductor deviceInfo
- Publication number
- JPH098222A JPH098222A JP14753695A JP14753695A JPH098222A JP H098222 A JPH098222 A JP H098222A JP 14753695 A JP14753695 A JP 14753695A JP 14753695 A JP14753695 A JP 14753695A JP H098222 A JPH098222 A JP H098222A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- electronic component
- semiconductor
- component device
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置を搭載した電
子部品装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic component device equipped with a semiconductor device.
【０００２】[0002]
【従来の技術】従来から半導体チップ等の半導体装置を
多層プリント基板に搭載したＰＧＡ（ピングリッドアレ
イ）、ＢＧＡ（ボールグリッドアレイ）等の電子部品装
置が知られている。上記電子部品装置はさらにマザーボ
ードに実装され電子装置として用いられる。近年の電子
装置は高機能化と小型化が要求されている。この高機能
化から半導体装置は多数搭載する必要が生まれ、これら
半導体装置を搭載する面積を確保するために広い多層プ
リント基板が必要であった。そのため電子部品装置が大
型化する問題を生じている。2. Description of the Related Art Conventionally, electronic component devices such as PGA (pin grid array) and BGA (ball grid array) in which a semiconductor device such as a semiconductor chip is mounted on a multilayer printed circuit board are known. The electronic component device is further mounted on a motherboard and used as an electronic device. In recent years, electronic devices are required to have higher functionality and smaller size. Due to this high functionality, it is necessary to mount a large number of semiconductor devices, and a wide multilayer printed circuit board is necessary to secure an area for mounting these semiconductor devices. Therefore, there is a problem that the electronic component device becomes large.
【０００３】[0003]
【発明が解決しようとする課題】本発明は上述の事実に
鑑みてなされたもので、その目的とするところは、高機
能化と小型化を実現した半導体装置を搭載した電子部品
装置を提供することにある。SUMMARY OF THE INVENTION The present invention has been made in view of the above facts, and an object of the present invention is to provide an electronic component device equipped with a semiconductor device which is highly functional and compact. Especially.
【０００４】[0004]
【課題を解決するための手段】本発明の請求項１に係る
半導体装置を搭載した電子部品装置は、絶縁層４毎に上
に広がった階段状に設けられた窪み５を有する多層プリ
ント基板３、上記窪み５の底６に搭載された第１の半導
体装置１、及び、上記底６を囲む一の踏み板７に着設
し、上記窪み５の底６を架橋する第２の半導体装置２を
備えることを特徴とする。An electronic component device equipped with a semiconductor device according to claim 1 of the present invention has a multi-layer printed circuit board 3 having stepwise recesses 5 that spread upward for each insulating layer 4. The first semiconductor device 1 mounted on the bottom 6 of the recess 5 and the second semiconductor device 2 which is attached to the one step plate 7 surrounding the bottom 6 and bridges the bottom 6 of the recess 5. It is characterized by being provided.
【０００５】本発明の請求項２に係る半導体装置を搭載
した電子部品装置は、請求項１記載の半導体装置を搭載
した電子部品装置において、第１、及び、第２の半導体
装置１、２が半導体チップ、ＱＦＰ（クウァドフラット
パッケジ）、ＰＬＣＣ（プラスチックリードチップキャ
リアー）のいずれかであることを特徴とする。An electronic component device equipped with a semiconductor device according to claim 2 of the present invention is an electronic component device equipped with the semiconductor device according to claim 1, wherein the first and second semiconductor devices 1 and 2 are It is characterized by being any one of a semiconductor chip, a QFP (quad flat package), and a PLCC (plastic lead chip carrier).
【０００６】[0006]
【作用】本発明の請求項１又は請求項２に係る半導体装
置を搭載した電子部品装置は、階段状に設けられた窪み
５に第１の半導体装置１と、第１の半導体装置１が搭載
された窪み５の底６を囲む一の踏み板７に上記窪み５の
底６を架橋する第２の半導体装置２とを備えるので、第
１の半導体装置１の上方に第２の半導体装置２を立体的
に設置するため、多層プリント基板３面の搭載個所の面
積が少なくてよい。In the electronic component device mounting the semiconductor device according to claim 1 or claim 2 of the present invention, the first semiconductor device 1 and the first semiconductor device 1 are mounted in the recesses 5 provided in a stepwise manner. Since the one step plate 7 surrounding the bottom 6 of the recess 5 provided with the second semiconductor device 2 bridging the bottom 6 of the recess 5, the second semiconductor device 2 is provided above the first semiconductor device 1. Since it is installed three-dimensionally, the area of the mounting portion on the surface of the multilayer printed circuit board 3 may be small.
【０００７】[0007]
【実施例】以下、本発明を図面を参照しながら説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.
【０００８】図１は本発明の一実施例に係る半導体装置
を搭載した電子部品装置の要部を拡大した断面図であ
り、図２は図１の電子部品装置に用いられる多層プリン
ト基板の要部を拡大した断面図であり、図３は本発明の
他の実施例に係る半導体装置を搭載した電子部品装置の
要部を拡大した断面図である。FIG. 1 is an enlarged cross-sectional view of an essential part of an electronic component device having a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a schematic diagram of a multilayer printed circuit board used in the electronic component device of FIG. FIG. 3 is an enlarged cross-sectional view of a part, and FIG. 3 is an enlarged cross-sectional view of a main part of an electronic component device including a semiconductor device according to another embodiment of the present invention.
【０００９】本発明を構成する多層プリント基板３は、
図２に示す如く、複数の絶縁層４を有し、絶縁層４毎に
上に広がった階段状に設けられた窪み５を備える。上記
絶縁層４は、基材に樹脂を含浸乾燥して得られるプリプ
レグの樹脂を硬化させた基板が用いられる。上記樹脂と
してはエポキシ樹脂、ポリイミド樹脂、フッソ樹脂、フ
ェノール樹脂、不飽和ポリエステル樹脂、ＰＰＯ樹脂等
の単独、変性物、混合物等が用いられる。上記基材とし
ては、特に限定するものではないが、ガラス繊維等の無
機材料の方が耐熱性、耐湿性等に優れて好ましい。ま
た、耐熱性に優れる有機繊維布基材及びこれらの混合物
を用いることもできる。上記絶縁層４の表面は導体回路
８が形成されている。上記導体回路８の形成は多層プリ
ント基板３で汎用されるエッチング、メッキ等により作
製すればよい。The multilayer printed circuit board 3 constituting the present invention is
As shown in FIG. 2, a plurality of insulating layers 4 are provided, and each insulating layer 4 is provided with a stepwise recess 5 that spreads upward. As the insulating layer 4, a substrate obtained by curing a resin of a prepreg obtained by impregnating a base material with a resin and drying is used. As the resin, an epoxy resin, a polyimide resin, a fluorine resin, a phenol resin, an unsaturated polyester resin, a PPO resin, or the like alone, a modified product, a mixture, or the like is used. The base material is not particularly limited, but an inorganic material such as glass fiber is preferable because it is superior in heat resistance and moisture resistance. Further, an organic fiber cloth base material having excellent heat resistance and a mixture thereof can also be used. A conductor circuit 8 is formed on the surface of the insulating layer 4. The conductor circuit 8 may be formed by etching, plating or the like which is commonly used in the multilayer printed board 3.
【００１０】本発明の電子部品装置は、図１に示す如
く、半導体チップ９ａからなる第１の半導体装置１を上
記多層プリント基板３の窪み５の底６に備える。上記半
導体チップ９ａはワイヤー１０ａを介して、絶縁層４上
に形成された導体回路８ａに接続される。さらに、エポ
キシ樹脂組成物等の封止材１１で封止される。As shown in FIG. 1, the electronic component device of the present invention is provided with a first semiconductor device 1 comprising a semiconductor chip 9a on the bottom 6 of the recess 5 of the multilayer printed board 3. The semiconductor chip 9a is connected to the conductor circuit 8a formed on the insulating layer 4 via the wire 10a. Further, it is sealed with a sealing material 11 such as an epoxy resin composition.
【００１１】さらに、本発明の電子部品装置は、上記底
６を囲む一の踏み板７上に着設した半導体チップ９ｂか
らなる第２の半導体装置２を備える。この第２の半導体
装置２は上記窪み５の底６を架橋し、上記第１の半導体
装置１の上方に位置する。上記第２の半導体装置２であ
る半導体チップ９ｂはワイヤー１０ｂを介して、絶縁層
４上に形成された導体回路８ｂと接続される。さらに、
エポキシ樹脂組成物等の封止材１１で封止される。Further, the electronic component device of the present invention comprises a second semiconductor device 2 comprising a semiconductor chip 9b mounted on one step plate 7 surrounding the bottom 6. The second semiconductor device 2 bridges the bottom 6 of the recess 5 and is located above the first semiconductor device 1. The semiconductor chip 9b which is the second semiconductor device 2 is connected to the conductor circuit 8b formed on the insulating layer 4 via the wire 10b. further,
It is sealed with a sealing material 11 such as an epoxy resin composition.
【００１２】本発明においては、階段状に設けられた窪
み５に、第１の半導体装置１と、第１の半導体装置１が
搭載された窪み５の底６を囲む一の踏み板７に着設し、
上記窪み５の底６を架橋する第２の半導体装置２とを備
えるので、第１の半導体装置１の上方に第２の半導体装
置２が立体的に設置している。従って、本発明の電子部
品装置は多層プリント基板３面に半導体装置１、２を複
数搭載する個所の面積が少ないので、高機能化と小型化
を実現できる。In the present invention, the stepped recess 5 is attached to the first semiconductor device 1 and the one step plate 7 surrounding the bottom 6 of the recess 5 on which the first semiconductor device 1 is mounted. Then
Since the second semiconductor device 2 that bridges the bottom 6 of the recess 5 is provided, the second semiconductor device 2 is three-dimensionally installed above the first semiconductor device 1. Therefore, since the electronic component device of the present invention has a small area where a plurality of semiconductor devices 1 and 2 are mounted on the surface of the multilayer printed circuit board 3, high functionality and miniaturization can be realized.
【００１３】なお、本発明の電子部品装置を構成する第
１、及び、第２の半導体装置１、２は半導体チップ９
ａ、９ｂに限定されず、ＱＦＰ（クウァドフラットパッ
ケジ）、ＰＬＣＣ（プラスチックリードチップキャリア
ー）等でもよい。図３に第１の半導体装置１に半導体チ
ップ９ａを、第２の半導体装置２にＱＦＰ（クウァドフ
ラットパッケジ）９ｃを備えた電子部品装置を示す。Ｑ
ＦＰ（クウァドフラットパッケジ）９ｃは半田を介し
て、踏み板７上に形成した導体回路８ｃと接続してい
る。The first and second semiconductor devices 1 and 2 constituting the electronic component device of the present invention are semiconductor chips 9.
It is not limited to a and 9b, but may be QFP (quad flat package), PLCC (plastic lead chip carrier), or the like. FIG. 3 shows an electronic component device including a semiconductor chip 9a in the first semiconductor device 1 and a QFP (quad flat package) 9c in the second semiconductor device 2. Q
The FP (quad flat package) 9c is connected to the conductor circuit 8c formed on the step board 7 via solder.
【００１４】さらに、本発明の電子部品装置は上記実施
例に限定されず、例えば、階段状に設けられた絶縁層４
をより多数有し、第２の半導体装置２を複数備えること
により、多層プリント基板３面に３個以上の半導体装置
１、２を立体的に搭載したものでもよいし、多層プリン
ト基板３に形成された窪み５を基板の両面に備え、多層
プリント基板３の両面に第１の半導体装置１と第２の半
導体装置２を搭載したものでもよい。Further, the electronic component device of the present invention is not limited to the above-mentioned embodiment, and for example, the insulating layer 4 provided in a step shape.
And a plurality of second semiconductor devices 2 are provided, three or more semiconductor devices 1 and 2 may be three-dimensionally mounted on the surface of the multilayer printed circuit board 3 or may be formed on the multilayer printed circuit board 3. It is also possible to provide the recesses 5 formed on both sides of the substrate and mount the first semiconductor device 1 and the second semiconductor device 2 on both sides of the multilayer printed circuit board 3.
【００１５】本発明の電子部品装置は、ピンを用いたＰ
ＧＡ（ピングリッドアレイ）、リードフレイムを用いた
ＱＦＰ（クウァドフラットパッケジ）、ＴＡＢ（テープ
オートメイテッドボンディング）、多層プリント配線板
の端面に外部接続端子を有するＬＣＣ（リードレスチッ
プキャリアー）、半田ボールを有するＢＧＡ（ボールグ
リッドアレイ）等として用いることができる。上記電子
部品装置はマザーボードに実装され電子装置として使用
される。本発明の電子部品装置を用いた電子装置も高機
能化と小型化が可能になる。The electronic component device of the present invention is a P using a pin.
GA (pin grid array), QFP (quad flat package) using lead frame, TAB (tape automated bonding), LCC (leadless chip carrier) having external connection terminals on the end face of a multilayer printed wiring board, solder It can be used as a BGA (ball grid array) having a ball. The electronic component device is mounted on a motherboard and used as an electronic device. The electronic device using the electronic component device of the present invention can also have higher functionality and smaller size.
【００１６】[0016]
【発明の効果】本発明の請求項１又は請求項２に係る半
導体装置を搭載した電子部品装置は、階段状に設けられ
た窪み５に第１の半導体装置１と、第１の半導体装置１
が搭載された窪み５の底６を囲む一の踏み板７に上記窪
み５の底６を架橋する第２の半導体装置２とを備えるの
で、第１の半導体装置１の上方に第２の半導体装置２が
立体的に設置している。従って、多層プリント基板３面
の半導体装置１、２を複数搭載する個所の面積が少なく
いので、高機能化と小型化を実現できる。本発明の電子
部品装置を実装した電子装置は高機能化と小型化が可能
になる。According to the electronic component device having the semiconductor device according to the first or second aspect of the present invention, the first semiconductor device 1 and the first semiconductor device 1 are provided in the recess 5 provided in a stepwise manner.
Since the second semiconductor device 2 bridging the bottom 6 of the depression 5 is provided on the one step plate 7 surrounding the bottom 6 of the depression 5 in which is mounted, the second semiconductor device is provided above the first semiconductor device 1. 2 is installed three-dimensionally. Therefore, the area of the part where the plurality of semiconductor devices 1 and 2 are mounted on the surface of the multilayer printed circuit board 3 is small, so that high functionality and miniaturization can be realized. The electronic device mounted with the electronic component device of the present invention can be highly functionalized and downsized.
【図１】本発明の一実施例に係る半導体装置を搭載した
電子部品装置の要部を拡大した断面図である。FIG. 1 is an enlarged cross-sectional view of a main part of an electronic component device equipped with a semiconductor device according to an embodiment of the present invention.
【図２】図１の電子部品装置に用いられる多層プリント
基板の要部を拡大した断面図である。FIG. 2 is an enlarged sectional view of a main part of a multilayer printed circuit board used in the electronic component device of FIG.
【図３】本発明の他の実施例に係る半導体装置を搭載し
た電子部品装置の要部を拡大した断面図である。FIG. 3 is an enlarged cross-sectional view of an essential part of an electronic component device equipped with a semiconductor device according to another embodiment of the present invention.
１ 第１の半導体装置 ２ 第２の半導体装置 ３ 多層プリント基板 ４ 絶縁層 ５ 窪み ６ 底 ７ 踏み板 ８，８ａ，８ｂ，８ｃ 導体回路 ９ａ，９ｂ 半導体チップ ９ｃ ＱＦＰ（クウァドフラットパッケジ） １０ａ，１０ｂ ワイヤー １１ 封止剤 DESCRIPTION OF SYMBOLS 1 1st semiconductor device 2 2nd semiconductor device 3 Multilayer printed circuit board 4 Insulating layer 5 Indentation 6 Bottom 7 Tread plate 8, 8a, 8b, 8c Conductor circuit 9a, 9b Semiconductor chip 9c QFP (Quad flat package) 10a, 10b wire 11 sealant
Claims (2)
設けられた窪み（５）を有する多層プリント基板
（３）、上記窪み（５）の底（６）に搭載された第１の
半導体装置（１）、及び、上記底（６）を囲む一の踏み
板（７）に着設し、上記窪み（５）の底（６）を架橋す
る第２の半導体装置（２）を備えることを特徴とする半
導体装置を搭載した電子部品装置。1. A multi-layer printed circuit board (3) having stepwise recesses (5) spreading upward for each insulating layer (4), mounted on the bottom (6) of the recesses (5). The semiconductor device (1) of No. 1 and the second semiconductor device (2) which is attached to the one step plate (7) surrounding the bottom (6) and bridges the bottom (6) of the recess (5). An electronic component device equipped with a semiconductor device, which comprises:
（１）、（２）が半導体チップ、ＱＦＰ（クウァドフラ
ットパッケジ）、ＰＬＣＣ（プラスチックリードチップ
キャリアー）のいずれかであることを特徴とする請求項
１記載の半導体装置を搭載した電子部品装置。2. The first and second semiconductor devices (1) and (2) are any one of a semiconductor chip, a QFP (quad flat package), and a PLCC (plastic lead chip carrier). An electronic component device equipped with the semiconductor device according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14753695A JPH098222A (en) | 1995-06-14 | 1995-06-14 | Electronic component device with mounted semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14753695A JPH098222A (en) | 1995-06-14 | 1995-06-14 | Electronic component device with mounted semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH098222A true JPH098222A (en) | 1997-01-10 |
Family
ID=15432540
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14753695A Withdrawn JPH098222A (en) | 1995-06-14 | 1995-06-14 | Electronic component device with mounted semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH098222A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006278401A (en) * | 2005-03-28 | 2006-10-12 | Denso Corp | Semiconductor device |
| JP2008204462A (en) * | 2007-02-21 | 2008-09-04 | Samsung Electronics Co Ltd | Semiconductor package, integrated circuit card having the semiconductor package and manufacturing method therefor |
| WO2009147036A1 (en) * | 2008-06-03 | 2009-12-10 | Siemens Aktiengesellschaft | Led lighting array |
| JP2011228521A (en) * | 2010-04-21 | 2011-11-10 | Fujitsu Ltd | Manufacturing method of semiconductor device |
| JP4946872B2 (en) * | 2006-02-02 | 2012-06-06 | パナソニック株式会社 | Memory card manufacturing method |
-
1995
- 1995-06-14 JP JP14753695A patent/JPH098222A/en not_active Withdrawn
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006278401A (en) * | 2005-03-28 | 2006-10-12 | Denso Corp | Semiconductor device |
| JP4556732B2 (en) * | 2005-03-28 | 2010-10-06 | 株式会社デンソー | Semiconductor device and manufacturing method thereof |
| JP4946872B2 (en) * | 2006-02-02 | 2012-06-06 | パナソニック株式会社 | Memory card manufacturing method |
| JP2008204462A (en) * | 2007-02-21 | 2008-09-04 | Samsung Electronics Co Ltd | Semiconductor package, integrated circuit card having the semiconductor package and manufacturing method therefor |
| US8329507B2 (en) | 2007-02-21 | 2012-12-11 | Samsung Electronics Co., Ltd. | Semiconductor package, integrated circuit cards incorporating the semiconductor package, and method of manufacturing the same |
| WO2009147036A1 (en) * | 2008-06-03 | 2009-12-10 | Siemens Aktiengesellschaft | Led lighting array |
| JP2011228521A (en) * | 2010-04-21 | 2011-11-10 | Fujitsu Ltd | Manufacturing method of semiconductor device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20020903 |