JP5412717B2 - Trench type insulated gate semiconductor device - Google Patents

Description

  The present invention relates to a trench type insulated gate semiconductor device.

2. Description of the Related Art In recent years, in the field of power devices used for power conversion devices and the like, attention has been focused on trench insulated gate bipolar transistors (hereinafter referred to as trench IGBTs) in which an insulated gate structure is formed in a trench formed in a semiconductor substrate. The trench IGBT has an advantage that when the channel density is increased, the voltage drop Vce (sat) in the ON state can be reduced, and the steady loss can be reduced. On the other hand, as the channel density increases, the capacitance between the gate electrode and the emitter electrode and the capacitance between the gate electrode and the collector electrode (hereinafter referred to as the gate-collector capacitance) also increase. There is a disadvantage that switching loss at turn-off increases.
By the way, in the trench IGBT, by newly providing a p-well region (p base region) that is not in electrical contact with the emitter electrode, the concentration of accumulated carriers on the emitter electrode side increases, and the saturation voltage-turn-off of the trench IGBT. There is a report that the trade-off characteristic between losses is improved (for example, refer to Patent Document 1). A number of patent applications have been filed for such trench IGBTs having a p-well region that is not in electrical contact with the emitter electrode, including those by the present inventors (Patent Document 2, Patent Document 2). 3, Patent Document 4, Patent Document 5, etc.).

6 and 7 are a plan view and a cross-sectional view schematically showing a trench IGBT having such a p-well region (p-type base region) structure, respectively. In the plan view of FIG. 6, the narrow p-type base region 9, the wide p-type base region 10, the n-type source region 3, and the gate electrode 5 embedded in the trench 21 in the active region of such a trench IGBT. Only the gate runners 13 and 14 are shown. The gate insulating film 4, the interlayer insulating film 6, and the emitter electrode 7 are omitted in order to avoid complication of the drawing. 7 is a cross-sectional view taken along line AA ′ shown in FIG. FIG. 7 shows the gate insulating film 4, the interlayer insulating film 6, and the emitter electrode 7 omitted in FIG.
In FIG. 7, the n-type drift layer 2 is provided on the p-type collector layer 1, and the p-well region 20 is further provided thereon. The p-well region 20 is divided into a plurality of narrow p-type base regions 9 and a wide p-type base region 10 by a trench 21. The n-type source region 3 is provided on the side of the trench 21 on the surface of the narrow p-type base region 9. The wide p-type base region 10 is not provided with the n-type source region 3.
In the narrow p-type base region 9 having the n-type source region 3, the emitter electrode 7 is in common contact with the surfaces of both the n-type source region 3 and the p-type base region 9. The wide p-type base region 10 without the n-type source region 3 is insulated from the emitter electrode 7 by interposing the interlayer insulating film 6. The trench 21 is filled with a gate electrode 5 made of a conductive layer such as low-resistance polysilicon via the gate insulating film 4.

The collector electrode 8 is provided so as to be in contact with the surface of the p-type collector layer 1 on the opposite side (back side) from the emitter electrode. On the other hand, the gate electrode 5 filling the trench has a gate runner 13 such as a metal film disposed on the surface along the outer periphery of the active region so as to interconnect the plurality of trenches 21 at both ends of the stripe-like planar shape. And a pattern connected to a gate pad (not shown).
Further, in the configuration of the trench IGBT described above, when the chip size is increased, an active region that is a region where a main current flows from the gate runner as a semiconductor device only by providing gate runners at both ends of the stripe-shaped planar trench 21. The distance to the center of the region becomes long, and the resistance of the gate electrode increases. Therefore, in order to avoid an increase in gate resistance, gate runners 14 may be provided in the active region at intervals of about 2 to 4 mm as shown in FIG. Although not shown, a pressure-resistant structure made of a guard ring or the like is provided on the outermost periphery of the chip outside the gate runner on the outer periphery of the active region.
In the conventional trench IGBT described above, the trench 21, that is, the surface structure including the gate electrode 5 embedded in the trench 21 is optimally set, so that a low steady loss (that is, a low on-state voltage) and a low switching loss (a high speed). Switching) is possible. However, in recent years, in the power device field, in addition to low steady-state loss and low switching loss, it is required to further reduce radiation noise generated during switching.
JP 2000-228519 A (the first line from the lower left column on page 4) JP 2001-308327 A (FIGS. 1 and 7) Japanese Patent Laid-Open No. 9-331063 (FIG. 42) Japanese Patent Laid-Open No. 2002-100770 (FIG. 22) Japanese Patent Laid-Open No. 2002-16252 (FIG. 1)

However, in order to reduce the radiation noise, it is necessary to reduce the voltage drop rate (dV / dt) and the current increase rate (di / dt) at the time of turn-on, and this increases the turn-on loss. Thus, generally, there is a trade-off relationship between the turn-on loss and the magnitude of radiation noise. Therefore, the reduction of radiation noise and low switching loss are future issues.
By the way, regarding the radiation noise at the time of switching of the IGBT, it has been reported that the element characteristic at the time of low current turn-on, which is about 1/10 of the rated current, greatly affects the radiation noise (S. Momota, M. Otsuki). , K. Ishii, H. Takubo, and Y. Seki, "Analysis on the Low Cu
rent Turn-On behavior of IGBT Modules, "

in Proc. ISPSD2000, pp. 359-362 (2000)).
In particular, it is known that a great deal of effort is required to keep radiation noise in a frequency band of 30 MHz or higher below a reference value. The cause of radiation noise in this frequency band is said to be high dV / dt containing high frequency components. Therefore, in order to keep dV / dt at the time of switching of the inverter below the target value, the value of the gate resistance or the like is controlled, and the rising speed of the main current at turn-on, that is, the slope (dIc / dt in the rising waveform of the current) ) Is kept low.
However, increasing the gate resistance is preferable in terms of radiation noise, as described above, but increases the voltage tail, and thus increases the turn-on loss of the IGBT. Therefore, it is desired that the trench IGBT has a low di / dt and a dV / dt below the target value without increasing the gate resistance as much as possible.
Moreover, if the feedback capacity of the IGBT is large, not only the switching loss increases, but also causes unstable operation. Thus, it is known that the feedback capacitance has a great influence on the switching characteristics of the element. Several methods have already been known for reducing radiation noise while reducing turn-on loss by reducing gate feedback and obtaining low di / dt while reducing the feedback capacitance of these IGBTs. For example, a method of measuring the stabilization of the operation by controlling the potential of the wide floating mesa region (the former method), or an emitter electrode that operates equivalently as a shield layer between the gate electrode and the gate oxide film A method of providing an electrode connected to the electrode (referred to as the latter method). Both are effective in capacity reduction and stable operation. However, according to the inventors' experiment, the former method is accompanied by an undesirable phenomenon such as an ON voltage increase of about 0.2V in an IGBT with a breakdown voltage of 1200V. On the other hand, the latter method has a problem that the method of forming the shield electrode is very complicated, the productivity is poor, and it is difficult to obtain a high gate breakdown voltage.

  The present invention has been made in view of the above-described points, and an object of the present invention is to suppress an increase in on-voltage even when both turn-on loss and radiation noise are reduced, and there is a problem in gate breakdown voltage. It is an object to provide an insulated gate semiconductor device that does not exist.

According to the first aspect of the present invention, the first conductivity type drift layer, the second conductivity type base region formed in one surface of the drift layer, and the surface of the base region A trench-type insulated gate semiconductor device comprising a plurality of trenches having a conductive layer embedded in a gate oxide film and having a depth that reaches the drift layer and is embedded through the gate oxide film. have three different kinds of the base region of a second conductivity type having a width that is sandwiched between, has a second base region> the first base region> third base region becomes relationship in descending order of the width, the among second second trenches trenches sandwiching the base region, the first base region trenches sandwiching the first trench, a trench sandwiching the third base region when said second trench and said first trench With said first base region only the first conductivity-type source region that are selectively formed from the surface along the inner wall surface of the first trench, both surfaces of the emitter electrode and the first base region and the source region The conductive layer embedded in the first trench is connected to the gate electrode, the conductive layer embedded in the second trench is connected to the same potential as the emitter electrode, and the second base region surface of the third base region and trench-type insulated gate semiconductor device having a trench-type insulated gate structure that is covered with an insulating film.
According to a second aspect of the present invention, the trench type insulated gate semiconductor device according to the first aspect of the present invention is such that the width of the third base region is 2.4 μm or less.

According to the invention of claim 3, wherein the appended claims, the depth of the second base region deeper than the depth of the trench, the depth of the first base region is shallower patent than the depth of the trench A trench-type insulated gate semiconductor device according to claim 1 or 2.

  According to the present invention, it is an object to provide a trench type insulated gate semiconductor device that can suppress an increase in on-voltage and has no problem in gate breakdown voltage even when both turn-on loss and radiation noise are reduced.

  Exemplary embodiments of an insulated gate semiconductor device according to the present invention will be explained below in detail with reference to the accompanying drawings. In the following description, the first conductivity type is assumed to be n-type, and the second conductivity type is assumed to be p-type. Note that the same reference numerals are given to the same components in all the attached drawings, and redundant description is omitted.

1 is a cross-sectional view schematically showing an insulated gate semiconductor device (IGBT) according to Example 1 of the present invention.
In the insulated gate semiconductor device shown in FIG. 1, the n-type drift layer 2 is provided on the p-type collector layer 1 in the same manner as the conventional semiconductor device shown in FIG. ) Is formed with a collector electrode 8. The p-well region 20 is formed by ion implantation of boron or the like from the surface of the n-type drift layer 2. The p-well region 20 includes a plurality of p-type base regions 9 having different widths by trenches 21 and 22 formed at a depth reaching the n-type drift layer 2 from the surface of the semiconductor substrate through the p-well region 20. It is divided into 10 and 12. The trenches 21 and 22 have no particular difference in the shape of the trenches themselves, and have different functions when a conductive layer is buried inside through a gate oxide film.
Of these p-type base regions 9, 10, and 12, the first p-type base region 10 has an n-type source region 3. The n-type source region 3 is provided on the side of the first trench 21 in the surface layer of the first p-type base region 10. The low resistance polysilicon gate electrode 5 embedded in the first trench 21 via the gate oxide film 4 is connected to a gate runner made of a metal film such as aluminum (not shown) on the surface. The n-type source region 3 is not provided in the second p-type base region 9 and the third p-type base region 12.

The emitter electrode 7 is in common contact with both surfaces of the first p-type base region 10 and the n-type source region 3 on the surface of the first p-type base region 10. The emitter electrode 7 is also in contact with the surface of the low resistance polysilicon layer 11 embedded in the second trench 22 via a gate oxide film. On the surfaces of the second p-type base region 9 and the third p-type base region 12, the emitter electrode 7 is insulated by an interlayer insulating film sandwiched therebetween. On the other hand, the collector electrode 8 is in contact with the front surface (back surface) of the p-type collector layer 1 provided on the side opposite to the trench type insulated gate structure.
Next, the relationship between the width a of the first p-type base region 10 and the width b of the third p-type base region 12 will be described. FIG. 3 is a diagram showing the IGBT turn-on current waveform in an inductive load in comparison with the IGBT of the present invention shown in FIG. 1 and the conventional IGBT shown in FIGS. This FIG. 3 shows that for each IGBT, the width a of the first p-type base region 10 is 3.0 μm, the width b of the third p-type base region 12 is 1.0 μm, and two types of 12Ω and 64Ω. When the gate resistance is used, the slope of the small current turn-on (di / dt) and the controllability of the peak current due to the gate resistance Rg are shown. As can be seen from FIG. 3, at the gate resistance Rg = 12Ω, the IGBT having the conventional trench type insulated gate structure and the IGBT of the present invention have a relatively similar turn-on current waveform, and the peak current is 51A. However, a large change is seen at the gate resistance Rg = 64Ω. In the conventional IGBT, the delay time increases, but the slope di / dt of the current rise does not change much, the peak current is 43 A, and the current decrease is 15.9%. On the other hand, in the IGBT of the present invention, the slope of increase in current (di / dt) is clearly reduced, the peak current is 36 A, and the current decrease is 28.0%, which is about 1.9 compared with the conventional IGBT. It can be seen that the control can be doubled.

FIG. 4 is a result of predicting by simulation the relationship between the turn-on peak current and the width b of the third p-type base region 12 at the gate resistance Rg of 64Ω for the IGBT according to the present invention. When the width p <2.4 μm of the third p-type base region 12 shown on the horizontal axis, the turn-on peak current is lower than the turn-on peak current 43A (vertical axis) of the conventional IGBT described above. An advantage is seen. The lower limit of the width b is not particularly defined, but when the width b of the third p-type base region 12 shown on the horizontal axis indicated as Mesa-b width in FIG. 4 is 1 μm or less, the turn-on peak current is about 36 A. As a result, the extreme miniaturization in which the width b of the third p-type base region 12 is set to 1 μm or less shows a limit that no particular effect is produced as compared with the case where the width b is 1 μm. Yes.
As a result, in the IGBT according to the first embodiment, the on-resistance does not increase, and the turn-on loss and the radiation noise can be reduced while maintaining the same gate breakdown voltage as the conventional one.

FIG. 2 is a cross-sectional view schematically showing an insulated gate semiconductor device (IGBT) according to Example 2 of the present invention.
The difference between the insulated gate semiconductor device shown in FIG. 1 according to the first embodiment and FIG. 2 according to the second embodiment is that only the depth of the second p-type base region 9 in FIG. It ’s deep. Thus, by making only the depth of the second p-type base region 9 deeper than the trench 22, the IGBT shown in the second embodiment has a higher breakdown voltage without losing the turn-on characteristics described in the first embodiment. Is obtained. For example, as shown in FIG. 5 which compares the breakdown voltage of the IGBT of FIG. 1 and the IGBT of FIG. 2, the IGBT of FIG. 2 according to the second embodiment has a breakdown voltage higher by about 120V than the IGBT of FIG. It has become. As a specific example of the depth of the second p-type base region 9, the first p-type base region 10 including the second p-type base region 9 with respect to the trench 22 in the IGBT of FIG. The depth of the three p-type base region 12 is reduced by 1.0 μm, and in the IGBT of FIG. 2, conversely, only the second p-type base region 9 is deeper by 1.0 μm than the trench 22. 10. The depth of the third p-type base region 12 was compared with the depth of 1.0 μm as in the conventional case.

  As described above, the insulated gate semiconductor device according to the present invention is useful in the field of power devices used in power converters and the like.

It is sectional drawing which shows typically trench IGBT concerning Example 1 of this invention. It is sectional drawing which shows typically trench IGBT concerning Example 2 of this invention. It is a turn-on waveform diagram of the present invention and a conventional trench IGBT. FIG. 4 is a relationship diagram between a turn-on peak current and a third base region width according to the present invention. FIG. 4 is a current / voltage waveform diagram of a trench IGBT according to the present invention. It is a top view which shows the conventional trench IGBT typically. It is sectional drawing in the AA 'line of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 p-type collector layer 2 1st conductivity type drift layer, n-type drift layer 3 1st conductivity type source region, n-type source region 4 Gate insulating film 5 Conductive layer 6 Interlayer insulating film 7 Emitter electrode 8 Collector electrode 9 Second p-type base region 10 first p-type base region 11 conductive layer 12 third p-type base region 13, 14 gate runner 21 first trench 22 second trench.

Claims (3)

A first conductivity type drift layer; a second conductivity type base region formed in one surface of the drift layer; and a depth formed from the surface of the base region and reaching the drift layer, with a gate inside In a trench-type insulated gate semiconductor device comprising a plurality of trenches having a conductive layer embedded via an oxide film, the plurality of trenches are of three types of second conductivity types having different widths sandwiched between the plurality of trenches. has a base region having a second base region> the first base region> third base region becomes relationship in order of width, these trenches sandwiching the second base region second trench, said first base region first trench trenches sandwiching, the third the trenches sandwiching the base region and the second trench and the first trench, the first tray from the first base region only surface A source region of a first conductivity type selectively formed along the inner wall surface of the first electrode, and an emitter electrode is in common contact with both surfaces of the first base region and the source region, and is in contact with the first trench. The buried conductive layer is connected to the gate electrode, the conductive layer buried in the second trench is connected to the same potential as the emitter electrode, and the surfaces of the second base region and the third base region are insulating films. trench-type insulated gate semiconductor device characterized by having a covered have that trench type insulated gate structure. 2. The trench type insulated gate semiconductor device according to claim 1, wherein the width of the third base region is 2.4 [mu] m or less. The depth of the second base region is deeper than the depth of the trench, the depth of the first base region is a trench-type insulated gate according to claim 1 or 2, characterized in that shallower than the depth of the trench Semiconductor device.

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