JP5410133B2 - Semiconductor device and control method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a control method thereof, and more particularly to a semiconductor device having a trench gate structure and a control method thereof.

  An insulated gate bipolar transistor (IGBT) can achieve a lower loss than the conventional one by adopting a trench gate structure as a surface structure.

FIG. 7 is a cross-sectional view schematically showing a conventional semiconductor device having a trench gate structure. On the front surface of the semiconductor device 2000 shown in FIG. 7, a p-type semiconductor region 104 is provided on the surface of the semiconductor substrate 1000 to be the n ⁻ drift region 101. An n-type emitter region 105 is selectively provided on the surface of the p-type semiconductor region 104. A trench 106 that penetrates through n-type emitter region 105 and p-type semiconductor region 104 and reaches n ⁻ drift region 101 is also provided. A gate electrode 108 is provided inside the trench 106 through a gate insulating film 107.

  The p-type semiconductor region 104 is separated by a trench 106, and a fixed potential region 102 provided with an n-type emitter region 105 and a floating potential region 103 provided with no n-type emitter region 105 are alternately and repeatedly formed. It has a configuration. An interlayer insulating film 109 is provided on the surfaces of the trench 106 and the floating potential region 103. Emitter electrode 110 is provided on the front surface of semiconductor device 2000 so as to be in contact with n-type emitter region 105 and fixed potential region 102. The fixed potential region 102 is a channel formation region. The floating potential region 103 is electrically insulated from the emitter electrode 110.

  On the back surface of the semiconductor device 2000, an n-type field stop region 111 is provided on the front surface of the semiconductor substrate 1000. A p-type collector region 112 is provided on the surface of the n-type field stop region 111. A collector electrode 113 is provided on the surface of the p-type collector region 112. In the semiconductor device 2000, when the semiconductor device 2000 is in an on state, holes injected from the p-type collector region 112 are accumulated in the floating potential region 103, whereby the on-voltage of the semiconductor device 2000 is reduced.

  FIG. 8 is a cross-sectional view schematically showing a semiconductor device having a conventional dummy trench. In the semiconductor device 2100 illustrated in FIG. 8, a trench 114 (hereinafter referred to as a dummy trench) that does not contact the n-type emitter region 105 is provided in part of the surface of the floating potential region 103. An electrode (hereinafter referred to as a dummy gate electrode) 116 provided inside the dummy trench 114 via an insulating film (hereinafter referred to as a dummy gate insulating film) 115 is electrically floating. Other configurations are the same as those of the semiconductor device 2000. In the semiconductor device 2100, by separating the floating potential region 103 into a plurality of regions by the dummy trench 114, the electric field concentration in the vicinity of the trench 106 is alleviated and the breakdown voltage is improved as compared with the semiconductor device 2000. In addition, holes accumulated in the floating potential region 103 are not easily discharged, conduction loss is reduced, and an on-voltage is reduced as compared with the semiconductor device 2000.

  As another semiconductor device having a dummy trench, the following device has been proposed. A high-resistance first conductivity type base layer, a second conductivity type base layer formed on the surface of the first conductivity type base layer, a band-like pattern with a closed planar pattern, and the second conductivity type base A gate electrode embedded through a gate insulating film in a groove having a depth reaching the first conductivity type base layer from the surface of the layer (hereinafter referred to as a trench groove), and a band-like pattern in which the planar pattern is closed A first conductivity type emitter layer selectively formed on and in contact with the groove on the surface of the second conductivity type base layer in a region surrounded by the groove, and the first conductivity type emitter layer and the groove And a second main electrode formed on the surface of the first conductivity type base layer opposite to the second conductivity type base layer. Conductive emitter layer and the second conductive emitter layer Second and a main electrode. In this semiconductor device, a plurality of trench grooves are formed. Further, among these trench grooves, the planar pattern of the trench groove at the end of the element is a ladder pattern, and the planar pattern of the other trench grooves is a stripe pattern. The n-type emitter layer is not formed on the surface of the p-type base layer where the planar pattern is in contact with the trench groove of the stripe pattern. In addition, the p-type base layer in this portion is insulated from the cathode electrode by an interlayer insulating film (see, for example, Patent Document 1 below).

As another semiconductor device having a dummy trench, an n ⁻ layer, a gate electrode formed in a direction perpendicular to the first main surface of the n ⁻ layer, a p base layer disposed between the gate electrodes, and a p base and n emitter region and the back gate region arranged in layers, n ^- and the gate electrode in the layer ^- and p collector region arranged on the second main surface of the layer, n without arranging the p base layer between the gate electrode A p region formed to the same or deeper depth, a dummy trench gate which is disposed in a direction perpendicular to the first main surface in the p region and is made of a dummy trench filling material and an insulating film, and a gate electrode A gate insulating film formed at the interface between the emitter region, the base layer and the n ⁻ layer, an emitter electrode in electrical contact with the emitter region and the back gate region, and an electrical contact with the collector region. A semiconductor device including a collector electrode is proposed (for example, see Patent Document 2 below).

  Further, as another semiconductor device that realizes a low on-state voltage, the following device has been proposed. A first conductivity type emitter layer; a second conductivity type base layer formed in contact with the first conductivity type emitter layer; a first conductivity type base layer formed in contact with the second conductivity type base layer; A gate electrode embedded in a groove formed at a depth reaching the second conductivity type base layer in the first conductivity type base layer via a gate insulating film, and the first electrode so as to be in contact with a side surface of the groove A second conductivity type source layer selectively formed on a surface of the one conductivity type base layer; the second conductivity type source layer; the first conductivity type base layer; the second conductivity type base layer; and the gate insulating film. And the first MOS transistor composed of the gate electrode, the gate electrode is common to the gate electrode of the first conductivity type emitter layer, and the first conductivity type emitter layer. Of the same polarity as the majority carrier A second MOS transistor for discharging the carrier out of the device, a first main electrode provided in the first conductivity type emitter layer, the first conductivity type base layer, and the second conductivity type source layer A second main electrode in contact with the second main electrode. When the semiconductor device is turned on, positive or 0V voltage is applied to the gate of the second MOS transistor to turn it off, so that holes in the semiconductor device are not discharged, so that holes are accumulated in the semiconductor device. A low on-state voltage is realized (for example, see Patent Document 3 below).

Japanese Patent Laid-Open No. 10-163483 JP 2005-294649 A Japanese Patent No. 3367747

FIG. 6 is a characteristic diagram showing current-voltage characteristics of a semiconductor device having a conventional dummy trench. A simulation result showing fluctuation in the breakdown voltage of the semiconductor device 2100 when charges are accumulated in the dummy gate electrode 116 of the semiconductor device 2100 is shown. When the negative charge of −1 × 10 ⁻¹⁴ to −1 × 10 ⁻¹² C is accumulated in the dummy gate electrode 116, the semiconductor device 2100 is compared with the case where no charge is accumulated in the dummy gate electrode 116 (0C). The withstand pressure is high. On the other hand, when positive charges (holes) of + 1 × 10 ⁻¹⁴ and + 1 × 10 ⁻¹³ C are accumulated in the dummy gate electrode 116, the breakdown voltage of the semiconductor device 2100 is accumulated in the dummy gate electrode 116. Compared to the case where it is not done, it is greatly reduced.

  In the semiconductor device 2100, the charge accumulated in the dummy gate electrode 116 is difficult to be released because the dummy gate electrode 116 is electrically floating. Therefore, when holes are accumulated in the dummy gate electrode 116, there arises a problem that the breakdown voltage of the semiconductor device 2100 is greatly reduced as shown in FIG. Such a problem does not occur in a semiconductor device having a configuration in which the dummy gate electrode is connected to another electrode. However, if the dummy gate electrode is connected to the gate electrode, the gate capacitance becomes large. The operating speed of the device becomes slow. In addition, when the dummy gate electrode is connected to the emitter electrode, the switching operation of the semiconductor device forcibly cuts off the current flowing through the semiconductor device or abruptly changes the voltage applied to the semiconductor device. The hard switching operation of the semiconductor device itself causes excessive load on the semiconductor device itself and the circuit in which the semiconductor device is installed.

  In addition to the above-described problems, in the semiconductor device 2100, the dummy gate insulating film 115 cannot be applied with voltage because the dummy gate electrode 116 is electrically floating. Therefore, for example, a static characteristic test (hereinafter referred to as a gate shock test) using a bidirectional Zener characteristic proposed in Japanese Patent Laid-Open No. 2005-150426 is performed, and the trench is interrupted or the trench is too shallow. There is a problem that it becomes difficult to detect and discriminate trench formation defects at the wafer stage. When trench formation defects exist in a semiconductor device, there is a possibility that desired electrical characteristics may not be obtained, and the cost of other components incorporated with this semiconductor device and the cost required for assembly are wasted. In addition, there arises a problem that the yield and reliability of the product are lowered.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a control method thereof that can improve the breakdown voltage of the semiconductor device in order to solve the above-described problems caused by the prior art. Another object of the present invention is to provide a semiconductor device and a control method thereof that can improve yield and reliability. It is another object of the present invention to provide a semiconductor device and a control method thereof that can reduce costs.

To solve the above problems and achieve an object, a semiconductor device according to this invention includes a first semiconductor region of a first conductivity type, a second conductivity type provided in the surface of said first semiconductor region A second semiconductor region, a third semiconductor region of a first conductivity type provided in a part of the surface of the second semiconductor region, and the second semiconductor region in contact with the third semiconductor region A first trench provided so as to penetrate the first semiconductor region, a first electrode provided in the first trench via a first insulating film, and the first trench A second electrode which is in contact with the third semiconductor region and a floating potential region of the second semiconductor region separated by the first trench, and is provided so as to separate the floating potential region A trench, and a second insulating film provided in the second trench. A third electrode of the floating potential was, the third electrode, and having a, a switch for shorting the low conductivity region potential than the third electrode.

In the semiconductor device according to the present invention, the holes accumulated in the third electrode are discharged to an external device by short-circuiting the third electrode and the conductive region by the switch. It is characterized by doing. Further, the semiconductor device according to this invention, in the invention described above, the switch is characterized in that it is integrally formed on a semiconductor substrate having a first semiconductor region.

In the invention a semiconductor device according to this, in the invention described above, the switch is characterized in that provided within the second trench.

The semiconductor device according to this invention is the invention described above, the conductive region, wherein said a first electrode or the second electrode.

The semiconductor device according to this invention is the invention described above, the switch, characterized in that an external connecting portion to be connected to the conductive area of the external.

Further, the semiconductor device according to this invention, in the invention described above, the switch is characterized in that operate in synchronization with the operation of the first electrode.

The semiconductor device according to this invention is the invention described above, the switch is characterized in that turns on in synchronization with the OFF operation of the first electrode.

Further, the semiconductor device according to this invention, in the invention described above, the switch, the potential difference of the second electrode and the third electrode is operative when it is more than a preset value Features.

The semiconductor device according to this invention is the invention described above, the switch, characterized in that it operates in synchronization with the period set in advance.

The semiconductor device according to this invention is the invention described above, the switch is characterized in that the MOSFET is used.

The semiconductor device includes a first semiconductor region of a first conductivity type, said second semiconductor region of a second conductivity type provided in the surface of the first semiconductor region, the second according to this invention A third semiconductor region of a first conductivity type provided in a part of the surface of the semiconductor region, and in contact with the third semiconductor region, through the second semiconductor region, and into the first semiconductor region A first trench provided to reach the first trench, a first electrode provided in the first trench via a first insulating film, and a second electrode in contact with the third semiconductor region, A second trench provided so as to penetrate the floating potential region of the second semiconductor region separated by the first trench and to isolate the floating potential region; and in the second trench a third electrode at a floating potential, which is provided through the second insulating film, the third Outside of the switch for short-circuiting the low conductivity region potential than the electrode, and wherein the obtaining Bei electrically connectable external connection portion, the said third electrode.

In the semiconductor device according to the present invention, the holes accumulated in the third electrode are discharged to an external device by short-circuiting the third electrode and the conductive region by the switch. It is characterized by doing. The semiconductor device according to this invention is the invention described above, the external connection section is characterized in that it comprises pads.

The semiconductor device according to this invention is the invention described above, the first trench and the second trench, characterized in that it is the same size.

The semiconductor device according to this invention is the invention described above, the first trench and the second trench, characterized in that it has the same structure.

Further, the semiconductor device according to this invention, in the invention described above, the floating potential region, by the second trench, characterized in that it is separated into a plurality of regions having the same width.

A control method of a semiconductor device according to this invention includes a first semiconductor region of a first conductivity type, said second semiconductor region of a second conductivity type provided in the surface of the first semiconductor region, A third semiconductor region of a first conductivity type provided in a part of a surface of the second semiconductor region; and a contact with the third semiconductor region; the second semiconductor region; A first trench provided to reach the semiconductor region; a first electrode provided in the first trench through a first insulating film; and a second electrode in contact with the third semiconductor region. A second trench provided so as to penetrate the floating potential region of the second semiconductor region separated by the first trench and to isolate the floating potential region, and the second trench A third electrode having a floating potential provided through the second insulating film, A control method of a semiconductor device having a switch wherein a third electrode, and the first state of floating potential, and a second state of being short-circuited to the low conductivity region potential than said third electrode It is characterized by that.

According to the method for controlling a semiconductor device according to the present invention, in the above-described invention, the holes accumulated in the third electrode are transferred to an external device by switching between the first state and the second state. It is characterized by discharging. A control method of a semiconductor device according to this invention is the invention described above, the conductive region, wherein said a first electrode or the second electrode.

The control method of a semiconductor device according to the invention of this, in the invention described above, the conductive region is characterized by a fourth electrode provided on the outside of the semiconductor substrate.

A control method of a semiconductor device according to this invention is the invention described above, wherein the first state and the second state, characterized in that switched in synchronization with the operation of the first electrode .

A control method of a semiconductor device according to this invention is the invention described above, the first state and said second state, and wherein the switched in synchronism with the off operation of the first electrode To do.

A control method of a semiconductor device according to this invention is the invention described above, wherein the first state and the second state, the potential difference between the second electrode and the third electrode is preset It changes when it becomes more than the value which was done.

A control method of a semiconductor device according to this invention is the invention described above, wherein the first state and the second state, and wherein the switched in synchronism with the period set in advance.

  According to the above-described invention, the switch that electrically connects the third electrode and the other conductive region is operated to electrically connect the third electrode to the other conductive region in the semiconductor device or the conductive region of the external device. Thus, the charge accumulated in the third electrode can be released. Further, by operating the switch at a desired timing, the third electrode can be in an electrically floating state when the switch is turned off, and the electric field concentration in the vicinity of the first trench can be reduced. it can. In addition, when the third electrode is in an electrically floating state, the operation speed of the semiconductor device, which is generated when the third electrode is always connected to the gate electrode or the emitter electrode, is slowed down. Problems and hard switching operations can be avoided. Further, by providing such a switch and operating the switch, the third electrode can be connected to another electrically conductive region that is electrically fixed. Therefore, the third electrode is electrically fixed. Can be in a state. Since the voltage can be applied to the third electrode and the second insulating film by making the third electrode electrically fixed, a static characteristic test such as a gate shock test can be performed. .

  According to the semiconductor device and the control method thereof according to the present invention, there is an effect that the breakdown voltage of the semiconductor device can be improved. In addition, the yield and reliability of the semiconductor device can be improved. Moreover, there exists an effect that cost can be reduced.

1 is a cross-sectional view showing a semiconductor device according to a first embodiment; FIG. 6 is a cross-sectional view showing a semiconductor device according to a second embodiment; FIG. 6 is a sectional view showing a semiconductor device according to a third embodiment; FIG. 6 is a plan view showing a semiconductor device according to a fourth embodiment; FIG. 9 is a plan view showing a semiconductor device according to a fifth embodiment; It is a characteristic view which shows the current-voltage characteristic of the semiconductor device which has the conventional dummy trench. It is sectional drawing which shows typically the semiconductor device of the conventional trench gate structure. It is sectional drawing which shows typically the semiconductor device which has the conventional dummy trench.

  Hereinafter, preferred embodiments of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. Further, + and − attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region where it is not attached. Note that, in the description of each embodiment and all the attached drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

(Embodiment 1)
FIG. 1 is a cross-sectional view of the semiconductor device according to the first embodiment. On the front surface of the semiconductor device 200 shown in FIG. 1, a p-type semiconductor region 4 having a uniform thickness is provided on the surface of the semiconductor substrate 100 to be the n ⁻ drift region 1. An n-type emitter region 5 is selectively provided on the surface of the p-type semiconductor region 4. The n ⁻ drift region 1 corresponds to a first semiconductor region. The p-type semiconductor region 4 corresponds to a second semiconductor region. The n-type emitter region 5 corresponds to a third semiconductor region.

A trench 6 penetrating the n-type emitter region 5 and the p-type semiconductor region 4 and reaching the n ⁻ drift region 1 is provided. A gate electrode 8 is provided inside the trench 6 via a gate insulating film 7. The trench 6 corresponds to a first trench. The gate insulating film 7 corresponds to a first insulating film. The gate electrode 8 corresponds to the first electrode.

  The p-type semiconductor region 4 is separated by a trench 6 into a fixed potential region 2 where the n-type emitter region 5 is provided and a floating potential region 3 where the n-type emitter region 5 is not provided. The fixed potential region 2 is in contact with one side surface of the trench 6 and the floating potential region 3 is in contact with the other side surface.

A trench (hereinafter referred to as a dummy trench) 14 that penetrates the floating potential region 3 and reaches the n ⁻ drift region 1 is provided. The dummy trench 14 is formed so as to satisfy, for example, the same size as the trench 6, the same configuration as the trench 6, or both. The floating potential region 3 is separated into a plurality of regions having the same width, for example, by the trench 6 and the dummy trench 14. For example, when the floating potential region 3 is separated into three regions, the p-type semiconductor region 4 includes the fixed potential region 2, the trench 6, the floating potential region 3, the dummy trench 14, the floating potential region 3, the dummy trench 14, The floating potential region 3 and the trench 6 are repeatedly formed in this order. The dummy trench 14 corresponds to a second trench.

  An electrically floating electrode (hereinafter referred to as a dummy gate electrode) 16 is provided inside the dummy trench 14 via an insulating film (hereinafter referred to as a dummy gate insulating film) 15. On the dummy gate electrode 16, a switch (hereinafter referred to as a shorting switch) that is in contact with a part of the surface of the dummy gate electrode 16 and short-circuits the dummy gate electrode 16 and a region having a different potential from the dummy gate electrode 16. ) 20 is provided. The dummy gate insulating film 15 corresponds to a second insulating film. The dummy gate electrode 16 corresponds to a third electrode.

  Emitter electrode 10 is provided on the front surface of semiconductor device 200 so as to be in contact with n-type emitter region 5 and fixed potential region 2. An interlayer insulating film 9 is provided on the surfaces of the floating potential region 3, the trench 6 and the dummy trench 14. The floating potential region 3 is electrically insulated from the emitter electrode 10 by the interlayer insulating film 9. The fixed potential region 2 is a channel formation region. The emitter electrode 10 corresponds to a second electrode.

  An n-type field stop region 11 is provided on the front surface of the semiconductor substrate 100 on the back surface of the semiconductor device 200. A p-type collector region 12 is provided on the surface of the n-type field stop region 11. A collector electrode 13 is provided on the surface of the p-type collector region 12.

  The shorting switch 20 has, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure. This MOSFET includes a gate electrode (hereinafter referred to as a short-circuit gate electrode) 21, a drain electrode (hereinafter referred to as a short-circuit drain electrode) 22, a source region (hereinafter referred to as a short-circuit source region) 23, a well region (hereinafter referred to as a short-circuit source electrode). , A short-circuit well region) 24 and a drain region (hereinafter referred to as a short-circuit drain region) 25. The shorting switch 20 is provided, for example, for each dummy trench 14 inside the portion of the dummy gate insulating film 15 above the dummy gate electrode 16.

  In the shorting switch 20, the shorting source region 23 is provided in contact with the dummy gate electrode 16. The short-circuit drain region 25 is provided apart from the short-circuit source region 23 via the short-circuit well region 24. The short-circuit drain electrode 22 is provided in contact with the short-circuit drain region 25. The short-circuit gate electrode 21 is provided facing the short-circuit well region 24 between the short-circuit source region 23 and the short-circuit drain electrode 22. The short-circuit gate electrode 21 is insulated from the dummy gate electrode 16, the short-circuit drain electrode 22, and the short-circuit well region 24 by the dummy gate insulating film 15. The short-circuit gate electrode 21 and the short-circuit drain electrode 22 are connected to, for example, a pad through a contact region (not shown) provided in the dummy gate insulating film 15, for example, and are connected to the outside of the semiconductor device 200 by wiring drawn from the pad. It is connected to an external device (not shown) provided. This pad corresponds to an external connection portion.

  In such a semiconductor device 200, the shorting switch 20 operates in synchronization with the operation of the external device. When the short-circuit switch 20 is turned on, for example, the dummy gate electrode 16 is electrically connected to an external device via the short-circuit switch 20, so that the holes accumulated in the dummy gate electrode 16 pass through the short-circuit switch 20. To be released to an external device. The state in which the dummy gate electrode 16 has a floating potential corresponds to the first state. The state in which the dummy gate electrode 16 is electrically connected to the external device corresponds to the second state. By the ON operation of the short-circuit switch 20, the first state and the second state are switched.

  The on-operation of the short-circuit switch 20 may be periodically performed by providing a timer in the external device. Further, the ON operation of the shorting switch 20 may be synchronized with, for example, the OFF operation of the gate electrode 8 of the semiconductor device 200. Alternatively, the potential of the dummy gate electrode 16 may be detected, and the shorting switch 20 may be turned on when, for example, the potential difference between the emitter electrode 10 and the dummy gate electrode 16 exceeds a value set in advance in an external device. Further, two or more ON operations of the short-circuit switch 20 described above may be combined.

  As described above, according to the first embodiment, the short-circuit switch 20 is turned on, and the dummy gate electrode 16 is electrically connected to the conductive region of the external device, whereby the dummy gate electrode 16 is accumulated. Can be released to an external device. Further, by making the shorting switch 20 conductive at a desired timing, the dummy gate electrode 16 can be in an electrically floating state when the shorting switch 20 is turned off. Thereby, the electric field concentration near the trench 6 can be relaxed, and the breakdown voltage of the semiconductor device 200 can be improved. In addition, when the dummy gate electrode 16 is in an electrically floating state, the operation speed of the semiconductor device is reduced because the dummy gate electrode is always connected to the gate electrode or the emitter electrode. In addition, it is possible to avoid the problem of the hard switching operation. In addition, by providing the shorting switch 20 and making the shorting switch 20 conductive, the dummy gate electrode 16 can be connected to another electrically conductive region that is electrically fixed. It can be fixed. By placing the dummy gate electrode 16 in an electrically fixed state, a voltage can be applied to the dummy gate electrode 16 and the dummy gate insulating film 15, so that a static characteristic test such as a gate shock test can be performed. . Thereby, the yield and reliability of the semiconductor device 200 can be improved. In addition, the cost of the semiconductor device 200 can be reduced.

(Embodiment 2)
FIG. 2 is a cross-sectional view of the semiconductor device according to the second embodiment. In the semiconductor device 210 shown in FIG. 2, the contact portion 26 is provided inside the interlayer insulating film 9. The contact portion 26 connects the short-circuit drain electrode 22 and the emitter electrode 10. Other configurations of the semiconductor device 210 are the same as those of the semiconductor device 200. The timing of the ON operation of the shorting switch 20 is the same as in the first embodiment.

  The contact portion 26 may be configured to connect the short-circuit drain electrode 22 and the gate electrode 8.

  As described above, according to the second embodiment, the same effect as in the first embodiment can be obtained.

(Embodiment 3)
FIG. 3 is a sectional view of the semiconductor device according to the third embodiment. In the semiconductor device 220 shown in FIG. 3, for example, a shorting switch 20 is provided inside the interlayer insulating film 9 on the floating potential region 3 sandwiched between the trench 6 and the dummy trench 14. In the shorting switch 20, the shorting well region 24 is provided apart from the floating potential region 3. The short-circuit source region 23 and the short-circuit drain region 25 are provided apart from each other via the short-circuit well region 24. The shorting gate electrode 21 is provided between the floating potential region 3 and the shorting well region 24, and is insulated from the floating potential region 3 and the shorting well region 24 by the interlayer insulating film 9.

  Further, a contact region is provided in contact with the gate electrode 8 and the short-circuit drain region 25 inside the gate insulating film 7 and the interlayer insulating film 9 between the gate electrode 8 and the short-circuit drain region 25. This contact region is a short-circuit drain electrode (hereinafter referred to as a short-circuit drain contact electrode) 28. The dummy gate insulating film 15 and the interlayer insulating film 9 between the dummy gate electrode 16 and the short-circuit source region 23 are in contact with each dummy gate electrode 16 and the short-circuit source region 23 (hereinafter referred to as a short-circuit source region). 27 as a source contact region). In addition, a contact region (not shown) is provided inside the interlayer insulating film 9 so as to be in contact with the short-circuit gate electrode 21 and to connect, for example, a pad for drawing the wiring of the short-circuit gate electrode 21 to the outside of the semiconductor device 220. ing. Other configurations of the semiconductor device 220 are the same as those of the semiconductor device 200. The timing of the ON operation of the shorting switch 20 is the same as in the first embodiment.

  The contact region that becomes the short-circuit drain contact electrode 28 may be configured to be in contact with the short-circuit drain region 25 and the emitter electrode 10. Further, the short-circuit drain contact electrode 28 may be connected to, for example, a pad to draw out a wiring and connect to an external device.

  As described above, according to the third embodiment, the same effects as those of the first and second embodiments can be obtained.

(Embodiment 4)
FIG. 4 is a plan view of the semiconductor device according to the fourth embodiment. In the semiconductor device 230 shown in FIG. 4, the breakdown voltage structure 32 is provided on the semiconductor substrate 100 so as to surround the active region 31 in which the emitter electrode and the like are formed. The cross-sectional structure of the active region 31 is the same as that of the semiconductor device shown in the first embodiment (see FIG. 1) in which no shorting switch is provided.

  The shorting switch is provided in a driving circuit integrated device (not shown) different from the semiconductor device 230. On the semiconductor substrate 100 outside the breakdown voltage structure portion 32 of the semiconductor device 230, for example, a connection portion (for example, a pad) for connecting the dummy gate electrode (see FIG. 1) of the semiconductor device 230 and an external shorting switch (hereinafter referred to as a pad). , A dummy gate electrode connection portion) 37 is provided. The dummy gate electrode connection portion 37 corresponds to an external connection portion.

  For example, all the dummy gate electrodes of the semiconductor device 230 are connected to the dummy gate electrode connection portion 37 in parallel. The dummy gate electrode connection portion 37 is disposed in the same manner as the gate pad 33, the current sense emitter pad 34, the temperature sensor diode cathode 35, the temperature sensor diode anode 36, and the like, which are other connection portions of the semiconductor device 230. The wiring drawn out from the dummy gate electrode connection portion 37 is connected to an external device (not shown) for timing the on operation of the shorting switch, for example.

  The gate electrode or emitter electrode of the semiconductor device 230 may be connected to the shorting switch so that the dummy gate electrode and the gate electrode or emitter electrode of the semiconductor device 230 are electrically short-circuited when the shorting switch is turned on. good. Further, instead of the gate electrode or the emitter electrode of the semiconductor device 230, a gate electrode or an emitter electrode of another semiconductor device provided outside the semiconductor device 230 may be connected. A gate electrode or an emitter electrode of another semiconductor device provided outside the semiconductor device 230 corresponds to a fourth electrode. The timing of the ON operation of the shorting switch is the same as in the first embodiment. Further, for example, a MOSFET may be used as the shorting switch.

  Note that the gate electrode of the semiconductor device 230 is connected to the gate pad 33. A part of the n-type emitter region 5 is separated from the current sense emitter pad 34, and the separated part of the n-type emitter region 5 is connected to shunt a part of the current flowing in the semiconductor device 230. It can be detected. The temperature sensor diode cathode 35 and the temperature sensor diode anode 36 are connected to the cathode and anode of a diode for measuring the temperature of the semiconductor device 230, respectively. For example, a forward current is measured by passing a constant current through the diode. Thus, the temperature change of the semiconductor device 230 can be calculated. A mechanism for detecting current and temperature is not necessarily provided in the semiconductor device 230.

  As described above, according to the fourth embodiment, the same effect as in the first embodiment can be obtained. Further, the dummy gate electrode connection portion 37 can be provided in the same manner as in the process of manufacturing the conventional semiconductor device.

(Embodiment 5)
FIG. 5 is a plan view of the semiconductor device according to the fifth embodiment. On the semiconductor substrate 100 outside the breakdown voltage structure portion 32 of the semiconductor device 230, a short-circuit gate pad 38 to which the MOSFET 39 and the gate electrode of the MOSFET 39 are connected is provided as a short-circuit switch. The configuration of the semiconductor device 230 is the same as that in the fourth embodiment. All the dummy gate electrodes of the semiconductor device 230 are connected to the source electrode of the MOSFET 39. The emitter electrode or gate electrode of the semiconductor device 230 is connected to the drain electrode of the MOSFET 39. The gate electrode of the MOSFET 39 is connected to the short-circuit gate pad 38. The wiring drawn out from the short-circuit gate pad 38 is connected to, for example, an external device for timing the ON operation of the MOSFET 39. The on-operation timing of the MOSFET 39 is the same as that of the short-circuit switch of the first embodiment.

  As described above, according to the fifth embodiment, the same effects as those of the first and fourth embodiments can be obtained.

  In the above description, the lateral MOSFET is used as the short-circuit switch in the present invention. However, a vertical MOSFET or IGBT may be used.

  As described above, the semiconductor device according to the present invention is useful for a power semiconductor device used for a power conversion device or the like.

1 n ⁻ drift region 2 fixed potential region 3 floating potential region 4 p-type semiconductor region 5 n-type emitter region 5
6 trench 7 gate insulating film 8 gate electrode 9 interlayer insulating film 10 emitter electrode 11 n-type field stop region 12 p-type collector region 13 collector electrode 14 dummy trench 15 dummy gate insulating film 16 dummy gate electrode 20 short-circuit switch 21 short-circuit switch 22 Short-circuiting switch drain region 23 Short-circuiting switch source region 24 Short-circuiting switch well region 25 Short-circuiting switch drain region 100 Semiconductor substrate 200 Semiconductor device

Claims (25)

A first semiconductor region of a first conductivity type;
A second semiconductor region of a second conductivity type provided on the surface of the first semiconductor region;
A third semiconductor region of a first conductivity type provided on a part of the surface of the second semiconductor region;
A first trench provided in contact with the third semiconductor region, penetrating through the second semiconductor region, and reaching the first semiconductor region;
A first electrode provided in the first trench via a first insulating film;
A second electrode in contact with the third semiconductor region;
A second trench provided so as to penetrate the floating potential region of the second semiconductor region separated by the first trench and to isolate the floating potential region;
A third electrode having a floating potential provided in the second trench via a second insulating film;
A switch for short-circuiting the third electrode to a conductive region having a lower potential than the third electrode;
A semiconductor device comprising: 2. The semiconductor device according to claim 1, wherein holes accumulated in the third electrode are discharged to an external device by short-circuiting the third electrode and the conductive region by the switch. 3. The semiconductor device according to claim 1, wherein the switch is integrally formed on a semiconductor substrate having the first semiconductor region. The semiconductor device according to claim 3, wherein the switch is provided in the second trench. The semiconductor device according to claim 1, wherein the conductive region is the first electrode or the second electrode. The semiconductor device according to claim 1, further comprising an external connection portion that connects the switch to the external conductive region. The semiconductor device according to claim 1, wherein the switch operates in synchronization with the operation of the first electrode. The semiconductor device according to claim 7, wherein the switch is turned on in synchronization with an off operation of the first electrode. 7. The switch according to claim 1, wherein the switch operates when a potential difference between the second electrode and the third electrode becomes equal to or greater than a preset value. 8. Semiconductor device. The semiconductor device according to claim 1, wherein the switch operates in synchronization with a preset period. The semiconductor device according to claim 1, wherein a MOSFET is used for the switch. A first semiconductor region of a first conductivity type;
A second semiconductor region of a second conductivity type provided on the surface of the first semiconductor region;
A third semiconductor region of a first conductivity type provided on a part of the surface of the second semiconductor region;
A first trench provided in contact with the third semiconductor region, penetrating through the second semiconductor region, and reaching the first semiconductor region;
A first electrode provided in the first trench via a first insulating film;
A second electrode in contact with the third semiconductor region;
A second trench provided so as to penetrate the floating potential region of the second semiconductor region separated by the first trench and to isolate the floating potential region;
A third electrode having a floating potential provided in the second trench via a second insulating film;
An external connection that can electrically connect the third electrode to an external switch that is short-circuited to a conductive region having a lower potential than the third electrode;
A semiconductor device comprising: The semiconductor device according to claim 12, wherein the holes accumulated in the third electrode are discharged to an external device by short-circuiting the third electrode and the conductive region by the switch. The semiconductor device according to claim 12, wherein the external connection portion includes a pad. The semiconductor device according to claim 1, wherein the first trench and the second trench have the same size. The semiconductor device according to claim 1, wherein the first trench and the second trench have the same structure. The semiconductor device according to claim 1, wherein the floating potential region is separated into a plurality of regions having the same width by the second trench. A first conductivity type first semiconductor region, a second conductivity type second semiconductor region provided on the surface of the first semiconductor region, and a portion of the surface of the second semiconductor region. A third semiconductor region of the first conductivity type, a first trench provided in contact with the third semiconductor region, penetrating through the second semiconductor region, and reaching the first semiconductor region; The first electrode provided in the first trench through the first insulating film, the second electrode in contact with the third semiconductor region, and the first trench separated by the first trench A second trench provided so as to penetrate the floating potential region of the second semiconductor region and isolate the floating potential region, and provided in the second trench via a second insulating film A method of controlling a semiconductor device having a third electrode having a floating potential,
A method for controlling a semiconductor device, wherein the third electrode is switched between a first state having a floating potential and a second state short-circuited to a conductive region having a lower potential than the third electrode. 19. The method of controlling a semiconductor device according to claim 18, wherein the holes accumulated in the third electrode are discharged to an external device by switching between the first state and the second state. . The method for controlling a semiconductor device according to claim 18, wherein the conductive region is the first electrode or the second electrode. The method for controlling a semiconductor device according to claim 18, wherein the conductive region is a fourth electrode provided outside the semiconductor substrate. The method for controlling a semiconductor device according to any one of claims 18 to 21, wherein the first state and the second state are switched in synchronization with an operation of the first electrode. 23. The method of controlling a semiconductor device according to claim 22, wherein the first state and the second state are switched in synchronization with an off operation of the first electrode. The first state and the second state are switched when a potential difference between the second electrode and the third electrode becomes equal to or higher than a preset value. 22. A method for controlling a semiconductor device according to any one of 21. The method of controlling a semiconductor device according to any one of claims 18 to 21, wherein the first state and the second state are switched in synchronization with a preset period.

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