CN109244127A - Insulated gate bipolar transistor and manufacturing method thereof - Google Patents

Abstract

The invention provides an insulated gate bipolar transistor and a manufacturing method thereof, comprising: a substrate; a buffer layer is formed on the substrate; an epitaxial layer is formed on the buffer layer; a buried layer base region is formed in the epitaxial layer; The gate is formed in the epitaxial layer; the Dummy region is formed between the trench gates and is electrically connected to the trench gate, and the Dummy region is a non-conductive region; the buried base region is located on one side of the trench gate , the buried layer base region is located below the source region, and in the vertical distribution, the depth of the buried layer base region is greater than the depth of the trench gate; in this way, the electric field at the bottom corner of the trench gate can be reduced strength, improve the reliability and stability of the gate dielectric layer; the transistor has a vertical channel due to the trench gate, which can eliminate the resistance of the JFET region and reduce the forward conduction voltage; the Dummy region can improve the breakdown voltage and increase the transistor's The cell pitch and optimized channel orientation further reduce the forward conduction voltage.

Description

An insulated gate bipolar transistor and method of making the same

technical field

The present invention relates to the technical field of semiconductor devices, in particular to an insulated gate bipolar transistor and a manufacturing method thereof.

Background technique

Silicon carbide (SiC), the third-generation semiconductor material, has the advantages of large band gap, high critical breakdown field strength, high thermal conductivity and high electron saturation rate, and is very suitable for making high-voltage, high-temperature, high-frequency, and high-power semiconductor devices.

There are many challenges in the design and fabrication of silicon carbide insulated gate bipolar transistors. The withstand voltage and reliability of the gate dielectric layer, the breakdown voltage of the device, the forward voltage drop, and the dynamic characteristics all need attention, but In the prior art, while ensuring the breakdown voltage of the device, it is impossible to ensure that the forward voltage drop of the device can be reduced, and the withstand voltage and reliability of the gate dielectric layer can be improved.

SUMMARY OF THE INVENTION

In view of the problems existing in the prior art, the embodiments of the present invention provide an insulated gate dual transistor and a manufacturing method thereof, which are used to solve the problem that the insulated gate dual transistor in the prior art cannot simultaneously ensure the breakdown voltage of the device and the forward conduction of the device. Technical issues of voltage drop and the withstand voltage and reliability of the gate dielectric layer.

The present invention provides an insulated gate bipolar transistor, the insulated gate bipolar transistor comprising:

substrate;

a buffer layer formed on the substrate;

an epitaxial layer formed on the buffer layer;

a buried layer base region, formed in the epitaxial layer;

a trench gate, formed in the epitaxial layer;

The Dummy region is formed between the trench gates and is electrically connected to the trench gate, and the Dummy region is a non-conductive region; wherein, the buried base region is located in the trench gate On one side of the gate, the buried base region is located below the source region, and in the vertical distribution, the depth of the buried base region is greater than the depth of the trench gate.

In the above solution, in terms of lateral distribution, a predetermined lateral distance is set between the buried layer Base region and the trench gate.

In the above solution, the bottom of the trench gate is smooth and arc-shaped.

In the above solution, the Dummy region includes: a plurality of non-conductive trench structures, the sidewalls and bottoms of the non-conductive trench structures are provided with a dielectric layer, and the interior of the non-conductive trench structure is filled with polysilicon or metal aluminum .

In the above scheme, the insulated gate bipolar transistor further includes:

A Base region is formed in the epitaxial layer, and the Base region is located above the Base region of the buried layer;

a gate, formed on the epitaxial layer, the edge of the gate is connected to the trench gate;

a source region, formed in the epitaxial layer, the source region is located above the base region;

a source ohmic contact region, formed in the epitaxial layer, the source ohmic contact region is located on one side of the source region;

A source electrode is formed on the epitaxial layer, and the source electrode is respectively connected with the source ohmic contact region and the source region.

The present invention also provides a method for fabricating an insulated gate bipolar transistor, the method comprising:

epitaxially growing the buffer layer on the substrate;

epitaxially growing an epitaxial layer on the buffer layer;

A buried layer base region is formed in the epitaxial layer by ion implantation and annealing process;

A trench gate and a Dummy region are formed in the epitaxial layer, the Dummy region is formed between the trench gates and is electrically connected to the trench gate, and the Dummy region is a non- Conductive region; wherein, the buried layer Base region is located on one side of the trench gate, the buried layer Base region is located below the source region, and in the vertical distribution, the depth of the buried layer Base region is greater than the depth of the trench gate.

In the above solution, after forming the base region of the buried layer through ion implantation and annealing in the epitaxial layer, the method includes:

At a preset temperature, a base region, a source region and a source ohmic contact region are formed in the epitaxial layer through ion implantation and annealing processes.

In the above solution, after the trench gate and the Dummy region are formed in the epitaxial layer, the steps include:

depositing an isolation dielectric on the gate on the epitaxial layer;

A source electrode is formed on the epitaxial layer by a photolithography process and a sputtering process.

In the above solution, the base region, the source region and the source ohmic contact region are formed in the epitaxial layer by ion implantation and annealing processes at a preset temperature, including:

When the temperature is 400°C to 500°C, an ion implantation process is used in the epitaxial layer to form the Base region;

When the temperature is 400°C to 500°C, an ion implantation process is used in the epitaxial layer to form the source ohmic contact region;

When the temperature is between 400°C and 500°C, an ion implantation process is used in the epitaxial layer to form the source region;

When the temperature is 1500°C to 1700°C, activation annealing is performed on the epitaxial layer after ion implantation in an inert gas atmosphere.

In the above solution, the formation of the trench gate and the Dummy region in the epitaxial layer includes:

A trench is formed in the epitaxial layer by an etching process, the trench includes a first trench and a second trench;

forming a gate dielectric layer on the sidewalls and the bottom of the first trench and the second trench;

Simultaneously deposit polysilicon inside the first trench and inside the second trench to form the trench gate in the first trench, and form the trench gate in the second trench Dummy region; the first trench is located on both sides of the epitaxial layer, and the second trench is located between the first trenches, so that the Dummy region is located between the trench gates.

The invention provides an insulated gate bipolar transistor and a manufacturing method thereof. The insulated gate bipolar transistor comprises: a substrate; a buffer layer formed on the substrate; an epitaxial layer formed on the buffer layer; The buried layer base region is formed in the epitaxial layer; the trench gate is formed in the epitaxial layer; the Dummy region is formed between the trench gate and the trench Type gate is electrically connected, and the Dummy region is a non-conductive region; wherein, the buried layer Base region is located on one side of the trench gate, the buried layer Base region is located below the source region, and is in the vertical direction In terms of distribution, the depth of the buried base region is greater than the depth of the trench gate; thus, because the buried base region is located on one side of the trench gate, and the buried base region is located at the source The buried layer Base region can disperse the electric field at the bottom corner of the trench gate, thereby reducing the electric field intensity at the bottom corner of the trench gate and improving the reliability and stability of the gate dielectric layer; The trench gate allows the transistor to have a vertical channel, so it can eliminate the resistance of the JFET region and reduce the forward voltage of the transistor; because the Dummy region is non-conductive and can optimize the electric field distribution, it can improve the breakdown voltage; and because the Dummy region The cell pitch of the transistor can be increased and the crystal orientation of the channel can be optimized, which can further reduce the forward conduction voltage; in this way, the forward conduction voltage drop of the device can be reduced while ensuring the breakdown voltage of the device, and the gate dielectric layer can be improved. pressure and reliability.

Description of drawings

1 is a schematic structural diagram of an insulated gate bipolar transistor according to Embodiment 1 of the present invention;

FIG. 2 is a schematic flowchart of a method for fabricating an insulated gate bipolar transistor according to Embodiment 2 of the present invention.

Detailed ways

In order to solve the technical problem that the insulated gate dual transistor in the prior art cannot simultaneously guarantee the breakdown voltage of the device, the forward conduction voltage drop of the device, and the withstand voltage and reliability of the gate dielectric layer, the present invention provides an insulated gate dual transistor. A polar transistor and a manufacturing method thereof, the insulated gate bipolar transistor comprises: a substrate; a buffer layer, formed on the substrate; an epitaxial layer, formed on the buffer layer; a buried layer base area, formed on the Inside the epitaxial layer; a trench gate is formed in the epitaxial layer; a Dummy region is formed between the trench gates and is electrically connected to the trench gate, the Dummy region The area is a non-conductive area; wherein, the buried layer Base area is located on one side of the trench gate, the buried layer Base area is located below the source area, and in the longitudinal distribution, the buried layer Base area is The depth is greater than that of the trench gate.

The technical solutions of the present invention will be further described in detail below through the accompanying drawings and specific embodiments.

Example 1

This embodiment provides an insulated gate bipolar transistor. As shown in FIG. 1 , the insulated gate bipolar transistor includes: a substrate 101 ; a buffer layer 102 , an epitaxial layer 103 , a buried base region 104 , a trench type Gate 105, Dummy region 106; wherein,

The substrate 101 is a first heavily doped SiC substrate, and the first heavily doped type may be N-type or P-type. The substrate 101 in this embodiment may be an N-type SiC substrate or a P-type SiC substrate, the doping concentration is 10 ¹⁸ -10 ¹⁹ cm ^-3 .

The buffer layer 102 is a SiC buffer layer of the second doping type, which is epitaxially formed on the substrate 101 ; the second doping type may be P-type or N-type, and the buffer layer 102 in this embodiment is a P-type SiC buffer Floor. The doping level and thickness of the buffer layer 102 can be specifically set according to the breakdown voltage, forward voltage drop and dynamic characteristics of the transistor device, and the dynamic characteristics refer to the switching characteristics and capacitance characteristics of the transistor. Wherein, for a transistor whose application field is 10 kV, the doping concentration of the buffer layer 102 may be 1*10 ¹⁷ -2*10 ¹⁷ cm ^-3 , and the thickness may be 1-3 μm.

The epitaxial layer 103 is a SiC epitaxial layer of the second doping type, and epitaxial growth is formed on the buffer layer 102 . Specifically, the epitaxial layer 103 is epitaxially grown by chemical vapor deposition (CVD, Chemical Vapor Deposition) method on the front surface of the buffer layer 102; Forward conduction pressure drop and dynamic characteristics are specified. Generally speaking, when the transistor is applied in the high voltage field of 10kV, the doping concentration of the epitaxial layer 103 is 1.5*10 ¹⁴ -5*10 ¹⁴ cm ^-3 , preferably 2*10 ¹⁴ cm ^-3 , and the thickness is 100-150 μm .

When the substrate 101 is an N-type SiC substrate, after the epitaxial layer 103 is implanted with high-energy (Mev level) nitrogen ions, the epitaxial layer 103 after the N ion implantation is annealed by an annealing process to form a buried layer base region Base region, At this time, the buried layer Base region 104 is an N-type buried layer Base region.

Here, the base region 107 is formed by implanting N ions into the epitaxial layer 103 by using an N ion implantation process at a temperature of 400° C.˜500° C. and performing annealing. Therefore, the base region 107 is an N-type base region.

When the temperature is 400°C to 500°C, N ions are implanted into the epitaxial layer 103 by an N ion implantation process to form an N-type source ohmic contact region 108 , and when the temperature is 400°C to 500°C, an Al ion implantation process is used to the epitaxial layer 103 . Al ions are implanted inside to form a P-type source region 109 ; in the temperature range of 1500°C to 1700°C, activation annealing is performed on the ion-implanted epitaxial layer 103 in an inert gas atmosphere (eg, argon).

When the substrate 101 is a P-type SiC substrate, after the epitaxial layer 103 is implanted with high-energy (Mev level) Al ions, the epitaxial layer 103 after the Al ion implantation is annealed by an annealing process to form a buried layer base region Base region, At this time, the buried layer Base region 104 is a P-type buried layer Base region.

The base region 107 is formed by implanting Al ions into the epitaxial layer 103 through an Al ion implantation process at a temperature of 400° C.˜500° C. and performing annealing. Therefore, the base region 107 is a P-type base region.

When the temperature is 400°C to 500°C, Al ions are implanted into the epitaxial layer 103 by an Al ion implantation process to form a P-type source ohmic contact region 108. When the temperature is 400°C to 500°C, an N ion implantation process is used to the epitaxial layer 103 N ions are implanted inside to form an N-type source region 109 ; and the ion-implanted epitaxial layer 103 is activated and annealed in an inert gas atmosphere (eg, argon) within a temperature range of 1500° C. to 1700° C.

Then, trenches are formed in the epitaxial layer 103 by an etching process, the trenches include a first trench and a second trench; the sidewalls and bottoms of the first trench and the second trench, and adjacent trenches On the epitaxial layer 103 between the trenches, a gate dielectric layer 110 with low interface state and high quality is formed on the sidewall and bottom of the trench through a gate oxide oxidation process and a post-processing process. The thickness of the gate dielectric layer 110 is 50-60 nm; using Low pressure chemical vapor deposition (LPCVD, Low Pressure Chemical Vapor Deposition) process simultaneously depositing polysilicon inside the first trench and the second trench, and depositing polysilicon on the epitaxial layer 103, and using photolithography and etching The etching process simultaneously forms the trench gate 105 in the first trench, forms the Dummy region 106 in the second trench, and forms the gate 111 on the epitaxial layer 103, the edge of the gate 111 and the trench gate 105 is connected. The first trench is located on both sides of the epitaxial layer 103, and the second trench is located between the first trenches, so that the Dummy region 106 is formed between the trench gates 105, and the Dummy region 106 passes through the gate on the epitaxial layer The electrode 111 is electrically connected to the trench gate 105 .

Here, the post-treatment process refers to the high-temperature heat treatment and high-temperature thermal annealing process in a certain gas atmosphere such as N ₂ , Ar, NO, NO ₂ , POCl ₃ after the gate oxide is oxidized on the epitaxial layer 103 , so that the gate can be improved. The quality of the dielectric layer 110 and the effective passivation of interface states and traps in the gate dielectric layer 110 .

In order to reduce the peak value of the electric field, the bottom of the trench gate 105 is smooth and arc-shaped. The depth and width of the trench gate 105 are set according to specific device parameter performance and process level. Generally, the depth of the trench gate 105 is 1-4 μm, and the width is 1-2 μm.

In order to disperse the electric field distribution at the bottom corner of the trench gate, reduce the electric field intensity at the bottom corner of the trench gate and the gate dielectric layer, and improve the withstand voltage and reliability of the gate dielectric layer, the buried base region 104 is located in the trench gate 105 On one side, the buried base area 104 is located below the base area 107 , and the base area 107 is located below the source area 109 . In the lateral direction, a certain distance d is set between the buried base region 104 and the trench gate 105 , and the distance d is generally 1˜5 μm. In the vertical direction, the depth of the buried base region 104 is greater than the depth of the trench gate 105 , and the difference between the depth of the buried base region 104 and the depth of the trench gate 105 is generally 1˜3 μm.

The trench gate 105 also enables the transistor device to have a vertical channel, thereby eliminating the resistance of the JFET region and reducing the forward voltage drop of the device. The depth of the vertical channel is the difference between the thickness of the base region 107 and the thickness of the source region 109 .

The Dummy region 106 is a non-conductive region; the Dummy region 106 includes: a plurality of non-conductive trench structures, the non-conductive trenches are electrically connected to the trench gate 105 through the gate 111 on the epitaxial layer 103 , and the non-conductive trench structures The sidewalls and the bottom are provided with gate dielectric layers, and the interior of the non-conductive trench structure is filled with polysilicon or metal aluminum. Here, since the Dummy region 106 is a non-conductive region and the electric field distribution can be optimized, the breakdown voltage of the transistor device can be improved; and the Dummy region 106 can increase the cell pitch of the transistor device, and the presence of the Dummy region 106 makes the figure The conductive channel of 1 includes two, one of which is located on the left side of the left trench gate 105, and the other conductive channel is located on the right side of the right channel gate 105, so the crystal orientation of the conductive channel can be optimized, Reduces the forward voltage drop of transistor devices.

Here, referring to FIG. 1 , the transistor further includes: an isolation medium 112 , which is deposited on the gate electrode 111 by a low pressure chemical vapor deposition LPCVD process; the isolation medium 112 may include: silicon dioxide, silicon nitride, boron phosphorus Any one or any combination of silica glass.

A source electrode 113 is formed on the epitaxial layer 103 by a photolithography process and a sputtering process or a photolithography process and an evaporation process, and the source electrode 113 is connected to the source ohmic contact region 108 and the source region 109 respectively.

Embodiment 2

This embodiment provides a method for fabricating an insulated gate bipolar transistor, as shown in FIG. 2 , the method includes:

S110, epitaxially growing a buffer layer on the substrate;

In this embodiment, the substrate is a SiC substrate of the first heavily doped type, and the first heavily doped type may be N-type or P-type. The substrate in this embodiment may be an N-type SiC substrate, or may be The P-type SiC substrate has a doping concentration of 10 ¹⁸ to 10 ¹⁹ cm ^-3 .

The buffer layer is a SiC buffer layer of the second doping type, which is epitaxially formed on the substrate; the second doping type may be P-type or N-type, and the buffer layer in this embodiment is a P-type SiC buffer layer. The doping level and thickness of the buffer layer can be specifically set according to the breakdown voltage, forward voltage drop and dynamic characteristics of the transistor device. Dynamic characteristics refer to transistor switching characteristics and capacitance characteristics. Wherein, for a transistor whose application field is 10 kV, the doping concentration of the buffer layer 102 may be 1*10 ¹⁷ -2*10 ¹⁷ cm ^-3 , and the thickness may be 1-3 μm.

S111, epitaxially growing an epitaxial layer on the buffer layer;

The epitaxial layer is epitaxially grown by chemical vapor deposition (CVD) on the front side of the buffer layer. The doping concentration and thickness of the epitaxial layer should be set according to the breakdown voltage, forward voltage drop and dynamic characteristics of the silicon carbide insulated gate bipolar transistor. . Generally speaking, when the transistor is applied in the high voltage field of 10kV, the doping concentration of the epitaxial layer is 1.5*10 ¹⁴ cm ^-3 -5*10 ¹⁴ cm ^-3 , preferably 2*10 ¹⁴ cm ^-3 , and the thickness is 100 μm ~150μm.

S112, forming a buried layer base region Base region in the epitaxial layer by ion implantation and annealing process;

When the substrate is an N-type SiC substrate, after the epitaxial layer is implanted with high-energy (Mev level) nitrogen ions, an annealing process is used to anneal the N ion-implanted epitaxial layer to form the base region of the buried layer. At this time, the buried layer Base region is an N-type buried layer Base region.

After the buried layer Base region is formed, at a preset temperature, a Base region, a source region and a source ohmic contact region are formed in the epitaxial layer through ion implantation and annealing processes. The specific implementation is as follows:

Then at a temperature of 400°C to 500°C, N ions are implanted into the epitaxial layer to form an N-type source ohmic contact region, and at a temperature of 400°C to 500°C, an Al ion implantation process is used to implant into the epitaxial layer. Al ions form a P-type source region; in the temperature range of 1500° C.˜1700° C., in an inert gas atmosphere (eg, argon), the ion-implanted epitaxial layer is subjected to activation annealing.

When the substrate is a P-type SiC substrate, after the epitaxial layer is implanted with high-energy (Mev-level) Al ions, the epitaxial layer after the Al ion implantation is annealed by an annealing process to form a buried base region Base region. The layer Base area is a P-type buried layer Base area.

The Base region is formed by implanting Al ions into the epitaxial layer by using an Al ion implantation process at a temperature of 400° C. to 500° C. and performing annealing, so the Base region is a P-type Base region.

When the temperature is 400℃～500℃, the Al ion implantation process is used to implant Al ions into the epitaxial layer to form a P-type source ohmic contact region. When the temperature is 400℃～500℃, the N ion implantation process is used to implant N into the epitaxial layer. ions to form an N-type source region; in the temperature range of 1500° C.˜1700° C., in an inert gas atmosphere (eg, argon), the ion-implanted epitaxial layer is activated and annealed.

S113, forming a trench gate and a Dummy region in the epitaxial layer, the Dummy region is formed between the trench gates, and is electrically connected to the trench gate, and the Dummy region is a non-conductive region.

In this step, a trench is formed in the epitaxial layer by an etching process, and the trench includes a first trench and a second trench; the sidewalls and bottoms of the first trench and the second trench, and the adjacent On the epitaxial layer between the trenches, a gate dielectric layer with low interface state and high quality is formed on the sidewalls and bottom of the trench through gate oxide oxidation and post-processing processes. The thickness of the gate dielectric layer is 50-60 nm; using the LPCVD process simultaneously Polysilicon is deposited inside the first trench and the second trench, polysilicon is deposited on the epitaxial layer, and a trench gate is formed in the first trench by photolithography and etching at the same time. A Dummy region is formed in the second trench, and a gate is formed on the epitaxial layer, and the edge of the gate is connected to the trench gate. The first trench is located on both sides of the epitaxial layer, and the second trench is located between the first trenches, so that the Dummy region is formed between the trench gates, and the Dummy region passes through the gate and the trench on the epitaxial layer type gate electrical connection.

Here, the post-processing process refers to the high-temperature thermal treatment and high-temperature thermal annealing process in a certain gas atmosphere such as N ₂ , Ar, NO, NO ₂ , POCl ₃ after the gate oxide is oxidized in the epitaxial layer, which can improve the gate dielectric. Layer quality, and effective passivation of interface states and traps in gate dielectric layers.

In order to reduce the peak value of the electric field, the bottom of the trench gate is smooth and arc-shaped. The depth and width of the trench gate are set according to specific device parameter performance and process level. Generally, the depth of the trench gate is 1-4 μm, and the width is 1-2 μm.

In order to disperse the electric field distribution at the bottom corners of the trench gate, reduce the electric field strength at the bottom corners of the trench gate and the gate dielectric layer, and improve the withstand voltage and reliability of the gate dielectric layer, the base region of the buried layer is located at a portion of the trench gate. side, and the buried layer Base area is located below the Base area, the Base area is located below the source area, and in the lateral direction, there is a certain distance d between the buried layer Base area and the trench gate, and the distance d is generally 1～5μm. In the vertical direction, the depth of the buried base region is greater than that of the trench gate, and the difference between the depth of the buried base region 104 and the depth of the trench gate is generally 1-3 μm.

The trench gate also enables the transistor device to have a vertical channel, thereby eliminating the JFET region resistance and reducing the forward voltage drop of the device. The depth of the vertical channel is the difference between the thickness of the base region and the thickness of the source region.

The Dummy area is a non-conductive area; the Dummy area includes: a plurality of non-conductive trench structures, the non-conductive trenches are electrically connected to the trench gate through the gate on the epitaxial layer, and the sidewalls and bottom of the non-conductive trench structure are provided There is a dielectric layer, and the interior of the non-conductive trench structure is filled with polysilicon or metal aluminum. Here, since the Dummy region is a non-conductive region and can optimize the electric field distribution, the breakdown voltage of the transistor device can be improved; and the Dummy region can increase the cell pitch of the transistor device, and due to the existence of the Dummy region, the conduction in Figure 1 can be achieved. The channel includes two channels, one of which is located on the left side of the left trench gate, and the other conductive channel is located on the right side of the right channel gate, so the crystal orientation of the channel can be optimized and the forward conduction of the transistor device can be reduced. through pressure drop.

After the trench gate and the Dummy region are formed in the epitaxial layer, it includes:

A low-pressure chemical vapor deposition LPCVD process is used to deposit an isolation medium on the gate on the epitaxial layer; the isolation medium may include: any one or any of several of silicon dioxide, silicon nitride, and borophosphosilicate glass;

A source electrode is formed on the epitaxial layer by using a photolithography process and a sputtering process or a photolithography process and an evaporation process, and the source electrode is respectively connected to the source ohmic contact region and the source region.

The beneficial effects brought by an insulated gate bipolar transistor and a manufacturing method thereof provided by the embodiments of the present application are at least as follows:

The invention provides an insulated gate bipolar transistor and a manufacturing method thereof. The insulated gate bipolar transistor comprises: a substrate; a buffer layer formed on the substrate; an epitaxial layer formed on the buffer layer; The buried layer base region is formed in the epitaxial layer; the trench gate is formed in the epitaxial layer; the Dummy region is formed between the trench gates and is connected with the trench Type gate is electrically connected, and the Dummy region is a non-conductive region; wherein, the buried layer Base region is located on one side of the trench gate, the buried layer Base region is located below the source region, and is in the vertical direction In terms of distribution, the depth of the buried base region is greater than the depth of the trench gate; thus, because the buried base region is located on one side of the trench gate, and the buried base region Located below the source region, the buried layer Base region can disperse the electric field at the bottom corner of the trench gate, thereby reducing the electric field intensity at the bottom corner of the trench gate and improving the reliability and stability of the gate dielectric layer; Because the trench gate makes the transistor have a vertical channel, it can eliminate the resistance of the JFET region and reduce the forward voltage of the transistor; because the Dummy region is non-conductive and can optimize the electric field distribution, it can improve the breakdown voltage; The Dummy region can increase the cell pitch and channel orientation of the transistor, which can further reduce the forward conduction voltage; in this way, while ensuring the breakdown voltage of the device, the forward conduction voltage drop of the device can be reduced, and the gate dielectric can be improved. The voltage and reliability of the layer.

The above are only preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention shall be included in the within the protection scope of the present invention.

Claims (10)

1. An insulated gate bipolar transistor, comprising:

a substrate;

a buffer layer formed on the substrate;

an epitaxial layer formed on the buffer layer;

the Base region of the buried layer is formed in the epitaxial layer;

the groove type grid is formed in the epitaxial layer;

the Dummy area is formed between the groove type grid electrodes and is electrically connected with the groove type grid electrodes, and the Dummy area is a non-conductive area; the buried layer Base region is located on one side of the groove-type grid electrode, the buried layer Base region is located below the source region and is longitudinally distributed, and the depth of the buried layer Base region is larger than that of the groove-type grid electrode.

2. The insulated gate bipolar transistor of claim 1, wherein a predetermined lateral distance is provided between the buried Base region and the trench gate in the lateral profile.

3. The insulated gate bipolar transistor according to claim 1, wherein a bottom of the trench-type gate is smooth and rounded.

4. The insulated gate bipolar transistor of claim 1, wherein the Dummy region comprises: the structure comprises a plurality of non-conductive groove structures, wherein dielectric layers are arranged on the side walls and the bottoms of the non-conductive groove structures, and polycrystalline silicon or metal aluminum is filled in the non-conductive groove structures.

5. The insulated gate bipolar transistor according to claim 1, further comprising:

a Base region formed in the epitaxial layer, the Base region being located above the buried layer Base region;

the grid electrode is formed on the epitaxial layer, and the edge of the grid electrode is connected with the groove type grid electrode;

the source region is formed in the epitaxial layer and is positioned above the Base region;

the source ohmic contact region is formed in the epitaxial layer and is positioned on one side of the source region;

and the source electrode is formed on the epitaxial layer and is respectively connected with the ohmic contact area and the source area of the source electrode.

6. A method of fabricating an insulated gate bipolar transistor, the method comprising:

epitaxially growing a buffer layer on the substrate;

epitaxially growing an epitaxial layer on the buffer layer;

forming a Base region of a buried layer in the epitaxial layer through ion implantation and annealing process;

forming a groove type grid electrode and a Dummy area in the epitaxial layer, wherein the Dummy area is formed between the groove type grid electrodes and is electrically connected with the groove type grid electrode, and the Dummy area is a non-conductive area; the buried layer Base region is located on one side of the groove-type grid electrode, the buried layer Base region is located below the source region and is longitudinally distributed, and the depth of the buried layer Base region is larger than that of the groove-type grid electrode.

7. The method of claim 6, wherein the forming of the Base region of the buried Base region in the epitaxial layer by the ion implantation and annealing process comprises:

and forming a Base region, a source region and a source ohmic contact region in the epitaxial layer by ion implantation and annealing at a preset temperature.

8. The method of claim 6, wherein after forming the trench gate and Dummy regions in the epitaxial layer, comprising:

depositing an isolation medium on the grid electrode on the epitaxial layer;

and forming a source electrode on the epitaxial layer by utilizing a photoetching process and a sputtering process.

9. The method of claim 7, wherein forming a Base region, a source region, and a source ohmic contact region in the epitaxial layer by an ion implantation and annealing process at a predetermined temperature comprises:

forming the Base area in the epitaxial layer by adopting an ion implantation process at the temperature of 400-500 ℃;

forming the source ohmic contact region in the epitaxial layer by adopting an ion implantation process at the temperature of 400-500 ℃;

forming the source region in the epitaxial layer by adopting an ion implantation process at the temperature of 400-500 ℃;

and performing activation annealing on the epitaxial layer after ion implantation in an inert gas atmosphere at the temperature of 1500-1700 ℃.

10. The method of claim 6, wherein forming trench gates and Dummy regions in the epitaxial layer comprises:

forming a groove in the epitaxial layer through an etching process, wherein the groove comprises a first groove and a second groove;

forming gate dielectric layers on the side walls and the bottoms of the first groove and the second groove;

simultaneously depositing polycrystalline silicon in the first groove and the second groove to form the groove type grid in the first groove and form the Dummy area in the second groove; the first grooves are located on two sides of the epitaxial layer, and the second grooves are located between the first grooves, so that the Dummy areas are located between the groove-type gates.