JP5408713B2 - Cache memory control system and cache memory control method - Google Patents

Description

  The present invention relates to a cache memory control system and a cache memory control method, and more particularly, to a cache memory control system and a cache memory control method for request processing when a memory data access conflict occurs in an information processing apparatus.

  Patent Document 1 discloses a technique related to a memory controller that controls data input / output between a plurality of processors including a cache and a memory. When receiving a read request, the memory controller according to Patent Document 1 starts a data read process for a memory before receiving a snoop result regarding the request from each processor. Waits for the snoop result for the request to be notified, and starts data write processing to the memory.

  Patent Document 2 discloses a technology related to a memory cache system managed to improve performance in a multiprocessor environment. In the memory cache system according to Patent Document 2, the first processor accesses data using the first level 1 cache, and the second processor accesses data using the second level 1 cache. The storage control circuit is disposed between the first and second level 1 caches, the level 2 caches, and the main memory. Level 2 caches manage copies of data in main storage, and further manage whether those level 1 caches have copies of data and whether these copies have been modified.

  Japanese Patent Application Laid-Open No. 2004-228561 discloses a technique for allowing the advance of main memory access according to the processing state of a node and improving the performance of the multiprocessor system. The multiprocessor system according to Patent Document 3 not only selects and orders data read access synchronously on all nodes, but also selects and orders data writeback completion notifications synchronously on all nodes, so that The observed data reading order and data writing back completion order are made unique. Further, each node compares the target address of the ordered data read access and the ordered data write back completion notification, and detects the data read of the same address that is overtaken by the completion of the data write back. Determine the data write-back order. At this time, the coherency of the data is maintained by transmitting a coherency response that prompts the rereading of data to the node that has transmitted the data read access of the same address that has been overtaken by the completion of the data write back.

  Patent Document 4 discloses a technique related to a cache memory control system that achieves high system performance by eliminating extra snoop processing in a shared memory multiprocessor system having a write-back cache memory. In the cache memory control method according to Patent Document 4, the processor has a copy tag including a state unit that takes four states of an invalid state, a shared state, an exclusive match state, and an exclusive change state. When the cache memory changes to the exclusive change state, it notifies the copy tag to match the state of the cache memory, detects a read request to the shared memory on the shared bus by the bus monitoring circuit, and checks the copy tag. The access to the cache memory is reduced, and only when a block in the exclusive change state is hit, the change signal line is output to make the shared memory stand by, and the cache memory is snooped.

  Patent Document 5 discloses a technique related to a multiprocessor system that prevents the occurrence of a situation that hinders the processing of a system such as a timeout by efficiently arbitrating exclusive control. In the multiprocessor system according to Patent Document 5, a card on which a processor is mounted, a bus that interconnects the cards, an exclusive control flag that indicates the presence of a processor that is executing exclusive control, and an exclusive control request for each processor And a success flag indicating that the reissued exclusive control request was successful, and the other card receives the exclusive control request from each card and puts it in the common arbitration logic. Based on the distributed arbitration method in which each card determines and executes the same request processing order based on each card, the exclusive control arbitration is performed.

  Patent Document 6 discloses a technology related to a multiprocessor system configured in a tag and address crossbar system and a data crossbar system that interconnect a plurality of nodes having a local memory in each node and all the nodes. It is disclosed. The multiprocessor system according to U.S. Pat. No. 6,057,051 uses a global snoop to provide a single point of data tag serialization. The central crossbar controller examines the cache status tags for a given address line on all nodes simultaneously, maintains cache coherence, and others to the other nodes in the system to supply the requested data An appropriate response is issued to the node requesting the data while generating the data request. The system takes advantage of such memory by partitioning memory local to each node into mutually exclusive local and remote categories for a given cache line. This disclosure provides third level remote cache support for each node.

JP 2000-250811 A JP 2000-250812 A JP 2006-323432 A Japanese Patent Laid-Open No. 10-222423 Japanese Patent No. 3560534 JP 2005-539282 Gazette

  However, even when the techniques according to Patent Documents 1 to 6 described above are used, in an address conflict state in which accesses to a cache line address on one main memory from a plurality of processors in a multiprocessor system occur at the same time. There is a problem that the time taken to process the last address conflict request increases. This is because, first, when processing a processor-issued request in an address conflict state, the latency of the snoop request from the cache coherency control unit to the target processor and the latency of its completion are always required. In addition, the number of processors in the current multiprocessor system generally reaches several tens to several hundreds. This is because when the number of processors in the multiprocessor system is large, the latency between the cache coherency control unit and the processors increases due to physical restrictions for configuring the information processing apparatus. Such address conflict processing is generally performed in semaphore lock operations in a multiprocessor system.

  Here, generation | occurrence | production of the subject mentioned above is illustrated and demonstrated below. First, an SMP (Symmetric Multi-Processor) system to be described below is a CPU or an I / F equipped with a store-in cache memory that employs a general protocol such as MESI that temporarily stores main memory data therein. Cache coherency control that guarantees inter-cache coherency between CPUs and I / O processors using a directory system that registers a plurality of / O processors and the CPU and I / O processor caches in which the main storage data to be managed is stored. A memory control circuit that receives a memory access request from the CPU and the I / O processor via the cache coherency control circuit, writes it to a subordinate main memory, and instructs a read operation. Connected by connection, bus connection, star connection, etc. Than is.

  Here, consider a case where there is an address conflict state in which accesses from a plurality of processors to a cache line address on one main memory are generated at the same time. In this case, in Patent Document 5 described above, in order to guarantee the cache coherency in the system while avoiding a so-called live block state in which a specific processor cannot access the memory, the cache coherency control unit is provided. . Alternatively, a cache coherency control unit that operates in a completely synchronized manner while being distributed at a plurality of locations is provided. The cache coherency control unit must sequentially process requests that have address conflicts one by one.

  According to this, when a plurality of processors issue a main memory read request for updating the same memory address at the same time, the following operation is performed. Here, it is assumed that the data in the main memory is the only data in the system.

  First, the cache coherency control unit described above returns the main memory read data to the processor that issued the request that is determined to be processed first. Next, in order to process the request of the processor that has been determined to be processed second, the cache coherency control unit issues an in-cache data sweep instruction request (cache snoop request) to the processor that issued the request that has been processed first. As a result, the completion processing for the cached data and the cache snoop request is issued from the processor that issued the request processed first.

  Then, the in-cache data is returned to the processor that issued the request determined to be processed second, and the completion is returned to the cache coherency control unit.

  Subsequently, the cache coherency control unit that received the completion from the processor that issued the request that was processed first, that the data in the cache was swept out from the processor that issued the request that was processed first, and that the data It knows that it has been passed to the processor that issued the request decided to be processed second. The cache coherency control unit issues a cache snoop request to the processor that issued the second processed request in order to process the request that is determined to be processed third in response to the request. Thereafter, the same operation as when the second request is processed is performed, and further, if there is a processor that has issued a contention request, the same operation is repeated. As described above, in the address conflict state of the multiprocessor system, there arises a problem that the time taken to process the last address conflict request increases.

  The present invention has been made in order to solve such a problem, and a cache memory control system and a cache memory capable of reducing the time taken to process the last address conflict request in an address conflict state. It is an object to provide a control method.

  A cache memory control system according to a first aspect of the present invention includes: a transmission / reception control unit connected to a plurality of processors each having a cache memory; and access to a main memory, and consistency between cache memories of the plurality of processors. A coherency control unit that maintains a plurality of accesses in a case where target addresses in a plurality of access requests including at least exclusive data reading from the plurality of processors to the main memory compete with each other. A response instruction including contention information that is information related to request contention is transmitted to the transmission / reception control unit, and the transmission / reception control unit uses the exclusive data read as an access request based on the contention information included in the response instruction. For the return target processor determined from among the processors Te, and returns the data corresponding to the access request, subsequently, it transmits a snoop request for requesting acquisition of data in the cache memory of the processor of the reply subject has.

  A cache memory control method according to a second aspect of the present invention includes: a transmission / reception control unit connected to a plurality of processors each having a cache memory; and access to a main memory, and consistency between the cache memories of the plurality of processors. A cache memory control method in a multiprocessor system comprising: a coherency control unit that keeps performance; and a plurality of access requests including at least exclusive data reading from the plurality of processors to the main memory in the transmission / reception control unit And when the target addresses in the plurality of access requests compete with each other, the coherency control unit transmits a response instruction including contention information that is information regarding the competition of the plurality of access requests to the transmission / reception control unit. In the transmission / reception control unit, Based on the contention information included in the response instruction, the data corresponding to the access request is returned to the return target processor determined from among the processors that made the exclusive data read access request. The transmission / reception control unit transmits a snoop request for requesting acquisition of data in the cache memory of the processor to be returned.

  According to the present invention, it is possible to reduce the time taken to process the last address conflict request in the address conflict state.

It is a block diagram which shows the structure of the cache memory control system concerning Embodiment 1 of this invention. It is a flowchart figure which shows the flow of the control method of the cache memory concerning Embodiment 1 of this invention. It is a block diagram which shows the structure of the multiprocessor system concerning Embodiment 2 of this invention. The meaning of each status of the MESI protocol which is one of the cache protocols used in the second embodiment of the present invention will be described. It is a block diagram of the directory mounted for the cache status management function concerning Embodiment 2 of this invention. It is description of the directory cache status concerning Embodiment 2 of this invention. It is description of the caching agent information concerning Embodiment 2 of this invention. It is description of the messages concerning Embodiment 2 of this invention. It is the list of the request and response from the processor concerning Embodiment 2 of this invention, and the status transition of the cache in a processor. 10 is a list of requests and responses from a system interface according to a second embodiment of the present invention, and status transition of an in-processor cache. It is a block diagram which shows the structure of the competition information concerning Embodiment 2 of this invention. It is description of the content of the competition information concerning Embodiment 2 of this invention. It is a table | surface which shows the transition of the internal information of the address conflict control part at the time of EBR and SBR reception in the coherency control part concerning Embodiment 2 of this invention. It is a table | surface explaining the response production | generation in the coherency control part concerning Embodiment 2 of this invention. It shows an internal configuration of Rsp_Data_E and Rsp_Data_S which are responses according to the second embodiment of the present invention. It shows an internal configuration of Rsp_Data_Cnflt which is a response according to the second exemplary embodiment of the present invention. It is a flowchart figure which shows the flow of a process of the coherency control part at the time of address conflict concerning Embodiment 2 of this invention. It is a flowchart figure which shows the flow of a process in which the coherency control part concerning Embodiment 2 of this invention produces | generates Rsp_Data_Cnflt which is a response. It is a flowchart figure which shows the flow of the first half of a process in case the response / snoop control part concerning Embodiment 2 of this invention receives Rsp_Data_Cnflt. It is a flowchart figure which shows the flow of the latter half of a process when the response / snoop control part concerning Embodiment 2 of this invention receives Rsp_Data_Cnflt.

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. In the drawings, the same elements are denoted by the same reference numerals, and redundant description will be omitted as necessary for the sake of clarity.

<Embodiment 1 of the Invention>
FIG. 1 is a block diagram showing the configuration of the cache memory control system according to the first embodiment of the present invention. The cache memory control system 15 is connected to the processor 11, the processor 12, and the main memory 18, and manages the cache memories 13 and 14 included in the processors 11 and 12, respectively.

  The processor 11 is a CPU and an I / O processor on which the cache memory 13 is mounted. For example, it is a store-in type requester that employs a general cache protocol such as the MESI protocol. The processor 12 is a CPU and an I / O processor on which the cache memory 14 is mounted, and the others are the same as the processor 11. Note that the number of processors according to the first exemplary embodiment of the present invention may be at least two.

  The cache memory control system 15 includes a transmission / reception control unit 16 and a coherency control unit 17. The transmission / reception control unit 16 is connected to the processors 11 and 12, receives requests from the processors 11 and 12, and transfers the requests to the coherency control unit 17. In addition, the transmission / reception control unit 16 receives an instruction from the coherency control unit 17 and transmits a predetermined response to the processor 11 or 12. When the target addresses in a plurality of access requests including at least exclusive data reading from the processors 11 and 12 to the main memory 18 compete with each other, the coherency control unit 17 displays contention information that is information regarding contention of the plurality of access requests. The included response instruction is transmitted to the transmission / reception control unit 16. Then, the transmission / reception control unit 16 sends an access request to the return target processor determined from among the processors having the exclusive data read access request based on the contention information included in the response instruction from the coherency control unit 17. Is returned, and subsequently a snoop request for requesting acquisition of data in the cache memory of the processor to be returned is transmitted.

  The main memory 18 returns data at the target address in response to a data read request specifying the target address from the coherency control unit 17. Further, the main memory 18 updates the data at the target address in response to the data write request specifying the target address from the coherency control unit 17, and returns a message to that effect.

  FIG. 2 is a flowchart showing the flow of the cache memory control method according to the first embodiment of the present invention.

  First, the transmission / reception control unit 16 receives a plurality of access requests to the main memory 18 from the processors 11 and 12 (S11). Here, it is assumed that the plurality of access requests include at least exclusive data reading. Further, it is assumed that a plurality of access requests are directed to the same address in the main memory 18. The transmission / reception control unit 16 transfers the received access request to the coherency control unit 17.

  Next, when the target addresses in the plurality of access requests compete, the coherency control unit 17 transmits a response instruction including contention information that is information regarding the competition of the plurality of access requests to the transmission / reception control unit 16 (S12). ).

  Then, the transmission / reception control unit 16 returns the data corresponding to the access request to the reply target processor determined from among the processors having the exclusive data read as the access request based on the conflict information included in the response instruction. (S13).

  Subsequently, the transmission / reception control unit 16 transmits a snoop request for requesting acquisition of data in the cache memory of the processor to be returned (S14).

  Thereby, the completion time from the transmission / reception control unit 16 to the coherency control unit 17 and the snoop transmission / reception time from the coherency control unit 17 to the transmission / reception control unit 16 can be shortened. As described above, according to the first embodiment of the present invention, it is possible to reduce the time taken to process the last address conflict request in the address conflict state.

<Embodiment 2 of the Invention>
FIG. 3 is a block diagram showing a configuration of the multiprocessor system 100 according to the second embodiment of the present invention. The multiprocessor system 100 is an example of the cache memory control system according to the first embodiment of the present invention described above. Although the multiprocessor system 100 shows an example in which a plurality of processors are connected to two node controllers on a one-to-one basis, the method of connecting the node controller and the processor is not limited to this. For example, the connection method between the node controller and the processor may be bus connection or star connection.

  The processors 101 to 108 are CPUs and I / O processors equipped with store-in cache memories 111 to 118 that employ a general cache protocol such as the MESI protocol. The processors 101 to 108 serve as requesters for main memory access requests. Since the processors 101 to 108 used in the second embodiment of the present invention are known, detailed description thereof will be omitted. The number of processors is not limited to this, and may be at least two. FIG. 4 explains the meaning of each status of the MESI protocol, which is an example of the cache protocol used in the second embodiment of the present invention.

  The main memory management system 151 includes a main memory 153 and a main memory controller 155. The main memory management system 152 includes a main memory 154 and a main memory controller 156. The main memory management systems 151 and 152 appropriately read main memory data and update main memory data in response to main memory access requests from the processors 101 to 108 received via the coherency controllers 143 and 144. Since the main memory management systems 151 and 152 used in the second embodiment of the present invention are known, detailed description thereof is omitted.

  The node controller 121 is connected to the processors 101 to 104 and controls access to the main memory management system 151. Further, the node controller 121 performs access control from the processors 105 to 108 to the main memory management system 151 via the node controller 122, and transmits an access request to the processors 101 to 104 main memory management system 152. The node controller 121 includes response / snoop control units 131 to 134, a crossbar 141, and a coherency control unit 143.

  Similarly, the node controller 122 is connected to the processors 105 to 108 and performs access control to the main memory management system 152. Further, the node controller 122 performs access control from the processors 101 to 104 to the main memory management system 152 via the node controller 121 and transmits an access request to the processors 105 to 108 main memory management system 151. The node controller 122 includes response / snoop control units 135 to 138, a crossbar 142, and a coherency control unit 144. Note that the number of node controllers used in Embodiment 2 of the present invention is not limited to two.

  The crossbar 141 is a general crossbar circuit, and connects the response / snoop control units 131 to 134, the coherency control unit 143, and the crossbar 142. Similarly, the crossbar 142 is a general crossbar circuit, and connects the response / snoop control units 135 to 138, the coherency control unit 144, and the crossbar 141.

  The response / snoop control unit 131 is directly connected to the processor 101 and makes a predetermined response to the main memory access request issued by the processor 101. Further, the response / snoop control unit 131 can communicate with the coherency control unit 143, the response / snoop control units 132 to 134 and the node controller 122 via the crossbar 141.

  Here, in particular, a case where access requests to the same address in the main memory 153 are made from a plurality of processors including the processor 101, that is, an address conflict will be described. Here, it is assumed that the main memory access request from the processor 101 is exclusive data reading. In this case, the response / snoop control unit 131 receives a response instruction from either the coherency control unit 143 or 144 or the other response / snoop control units 132 to 138. Then, the response / snoop control unit 131 returns data corresponding to the main memory access request to the processor 101 based on the contention information included in the response instruction, and then continues in the cache memory 111 of the processor 101. Send a snoop request to request data acquisition. The competition information will be described later.

  Further, the response / snoop control unit 131 determines a processor to be returned next to the processor 101 to be returned based on the conflict information included in the response at the time of address conflict detection, and sends a response to the snoop request from the processor 101. After the reception, the data corresponding to the access request is returned to the processor to be returned next. As a result, data can be continuously sent back to the processor having address conflict without using the coherency control unit 143 or 144, and the transmission / reception time with the coherency control unit 143 or 144 can be shortened.

  Since the response / snoop control units 132 to 138 operate in the same manner as the response / snoop control unit 131, detailed description thereof is omitted.

  The coherency control unit 143 accesses the main memory 153 and the main memory controller 155 in the connected main memory management system 151, and maintains the consistency of the cache memories 111 to 118 included in the processors 101 to 108. That is, the coherency control unit 143 controls the main memory access request for the main memory management system 151. The coherency control unit 143 receives access requests from the processors 101 to 108 via the crossbar 141, and accesses the main memory management system 151 in response to the access requests. Also, the coherency control unit 143 returns the access result from the main memory management system 151 to a predetermined processor via the crossbar 141. The coherency control unit 143 includes a cache status management function 145 and an address conflict control unit 147.

  The cache status management function 145 is a circuit that realizes a general in-system cache status management function such as a directory system. FIG. 5 is a diagram showing an example of a directory configuration implemented for the cache status management function according to the second embodiment of the present invention. In the following description, it is assumed that a full directory system capable of managing all main memories for each cache line size is adopted. That is, each entry always corresponds to a unique main memory address, but the present invention can be realized even if a directory system that uses a set associative method and does not manage all main memory addresses at the same time. The cache status management function 145 holds information that associates the cache status 301 with the caching agent information 302 for each entry. FIG. 6 is an explanation of the directory cache status 301 according to the second embodiment of the present invention. The cache status 301 is cache status information of the main storage address, and indicates what cache status the processor in the system holds the data. FIG. 7 illustrates the caching agent information 302 according to the second embodiment of the present invention. The caching agent information 302 is caching agent information indicating a processor that holds data with a cache status. Note that the cache status management function 145 is not limited to this, and other functions may be used.

  The address contention control unit 147 holds contention information, which is information related to access request contention, for each target address to be accessed, for the access requests from the processors 101 to 108 received by the coherency control unit 143. That is, the address conflict control unit 147 includes a conflict information storage unit that stores conflict information for each target address.

  The coherency control unit 143 includes contention information that is information regarding contention of the plurality of access requests when the target addresses in the plurality of access requests including at least exclusive data read from the plurality of processors to the main memory 153 compete. The response instruction is transmitted to the crossbar 141.

  Further, the coherency control unit 143 determines the first reply target processor based on the competition information, and transmits it to one of the response / snoop control units 131 to 138 as a response instruction to the determined reply target processor. Thus, as in the multiprocessor system 100 according to the second embodiment of the present invention, when a plurality of response / snoop control units are connected one-to-one with a plurality of processors, the first reply target is determined based on the conflict information. Thus, it can be transmitted to an appropriate response destination.

  Note that the coherency control unit 144 and the cache status management function 146 and the address conflict control unit 148 included in the coherency control unit 144 are equivalent to the coherency control unit 143, the cache status management function 145, and the address conflict control unit 147 described above. Detailed description is omitted.

  System interfaces 161 to 168 are system interfaces for connecting the processors 101 to 108 and the response / snoop control units 131 to 138, respectively. The system interfaces 161 to 168 send access requests to the main memories 153 and 154 from the processors 101 to 108 and data replies thereof, and cache state inquiry requests for main memory data from the node controllers 121 and 122 to the processors 101 to 108 (hereinafter, snoops). (Referred to as a request) and its reply.

  Interfaces 171 to 174 are interfaces in the node controller 121 that connect the response / snoop control units 131 to 134 and the crossbar 141. The interface 181 is an interface in the node controller 121 that connects the crossbar 141 and the coherency control unit 143.

  Interfaces 175 to 178 are interfaces in the node controller 122 that connect the response / snoop control units 135 to 138 and the crossbar 142. The interface 182 is an interface in the node controller 122 that connects the crossbar 142 and the coherency control unit 144.

  The memory interface 183 is a memory interface that connects the main memory management system 151 and the coherency control unit 143. The memory interface 183 transfers a main memory access request from the coherency control unit 143 and a data reply from the main memory management system 151.

  The memory interface 184 is a memory interface that connects the main memory management system 152 and the coherency control unit 144. The memory interface 184 delivers a main memory access request from the coherency control unit 144 and a data reply from the main memory management system 152.

  The node interface 185 is an interface that connects the crossbar 141 in the node controller 121 and the crossbar 142 in the node controller 122. The node interface 185 exchanges the main memory access request and its data reply and the snoop request and its reply between the response / snoop control unit and the coherency control unit mounted on different node controllers.

  Here, the types and explanation of messages according to the second embodiment of the present invention are shown in FIG. FIG. 8 shows a processor, response / snoop control unit, crossbar and coherency control unit, coherency control unit, and main memory management required for realizing the inside of the multiprocessor system 100 according to the second embodiment of the present invention. A request message between systems, a response and a completion message are shown. In particular, Rsp_Data_Cnflt shown in FIG. 8 is a response message having, in addition to Rsp_Data_E and Rsp_Data_S, the same address conflict state of EBR detected by the coherency controller, the same address conflict state of SBR, and the request ID information of conflicting EBR or SBR. .

  FIG. 9 is a list of requests and responses from the processor and status transitions of the cache in the processor according to the second embodiment of the present invention. FIG. 10 is a list of requests and responses from the system interface according to the second embodiment of the present invention and status transitions of the processor cache.

  For example, reference numeral 903 in FIG. 9 indicates that when a certain processor issues an EBR, the initial cache status of the issuing processor is S, and in this case, a response that may be received is Rsp_Data_E. Upon receiving this, the processor stores the data attached thereto in its own cache, completes the process with the status as E.

  Although 901, 902, 904, 906 to 909, and 913 to 915 in FIG. 9 are listed as combinations of requests and statuses, they are combinations that cannot actually occur.

  916 in FIG. 10 indicates that an EBR issued by a processor (provisionally B) different from a certain processor (provisionally A) is received by the cache coherency control unit, and as a result of indexing the directories in the processor A, the processor A stores the data as M This shows the state transition when it is found that the data is held. Then, a case where Snp_E is issued to the processor A on the condition is shown. At this time, since the cache status of the processor A is M, the cache status transits to I, and at the same time, Cmp_I and Rsp_Data_E are issued to the system interface to complete the processing.

  In the SMP system mentioned in the above-mentioned problem, Cmp_I is transferred to the coherency control unit, knows the completion of processing in the processor A, triggers the start of processing of the next same address request, and Rsp_Data_E is returned to the processor B. . In contrast, in the second embodiment of the present invention, the response / snoop management unit that manages the processor A receives both Cmp_I and Rsp_Data_E, generates Rsp_Data_Cnflt therefrom, and transfers it to the processor B. As a result, the cache status can be changed, and the consistency of the cache memory can be maintained. That is, since the Cmp_I transfer to the coherency control unit is not performed, the processing time corresponding to the transfer time can be shortened.

  FIG. 11 is a block diagram showing a configuration of contention information according to the second exemplary embodiment of the present invention. FIG. 12 is a diagram for explaining the content of contention information according to the second embodiment of the present invention. The conflict information is obtained by associating the Valid bit 701, the EBR conflict detection flag 702, the EBR conflict detection flag 703, and the request ID 704 with each target address. When the Valid bit 701 is 1, it indicates that the set is in use. The EBR conflict detection flag 702 is set to 1 when the coherency control unit receives an EBR, and the bit corresponding to the request source of the EBR. If the coherency control unit receives an SBR, the EBR conflict detection flag 703 is set to 1 in the bit corresponding to the request source of the SBR. The request ID 704 is a field for setting and holding the request ID of the request at the same time that the EBR conflict detection flag 702 and the EBR conflict detection flag 703 are set.

  FIG. 11 shows one set corresponding to one main memory address, and the main memory address is managed for each piece of contention information. That is, the conflict information includes a conflict presence flag, an access request type, and identification information of the access request in units of main memory addresses. As a result, address conflicts can be appropriately managed, and reference is facilitated.

  FIG. 13 is a table showing the transition of internal information of the address conflict control units 147 and 148 at the time of EBR or SBR reception in the coherency control unit according to the second embodiment of the present invention. Hereinafter, the operation in the address conflict control unit 147 will be described. Reference numeral 1301 in FIG. 13 is the one when the EBR is accepted. At this time, the address conflict control unit 147 sets the bit of the EBR conflict detection flag corresponding to the EBR request source to 1, and simultaneously sets the request ID field of the EBR to the corresponding request ID field. Reference numeral 1302 in FIG. 13 is the one when the SBR is accepted. At this time, the address conflict control unit 147 sets the bit of the SBR conflict detection flag corresponding to the SBR request source to 1, and simultaneously sets the request ID field of the SBR to the corresponding request ID field.

  FIG. 14 is a table illustrating response generation in the coherency control unit according to the second embodiment of the present invention. FIG. 14 shows combinations of responses to be made when the coherency control unit issues a reply to EBR / SBR to the request source processor. That is, the coherency control unit returns a normal response (Rsp_Data_E or Rsp_Data_S) or generates Rsp_Data_Cnflt according to the combination of the request type and the valid bit of the conflict information held by the address conflict control unit before update. Decide whether to make a response.

  FIG. 15 shows an internal configuration of Rsp_Data_E and Rsp_Data_S which are responses according to the second embodiment of the present invention. As shown in FIG. 15, Rsp_Data_E and Rsp_Data_S include a command code, a destination ID, an original request ID, and data. In addition, a well-known thing may be used for the internal structure of Rsp_Data_E and Rsp_Data_S. FIG. 16 shows the internal structure of Rsp_Data_Cnflt, which is a response according to the second embodiment of the present invention. As shown in FIG. 16, Rsp_Data_Cnflt includes an EBR conflict detection flag, an SBR conflict detection flag, and a request ID in addition to the configuration of FIG.

  FIG. 17 is a flowchart showing a processing flow of the coherency control unit at the time of address conflict according to the second embodiment of the present invention. It is assumed that the main memory target addresses treated in the following description are the same. The target address is assumed to be the address of the main memory 153. Further, as an initial state, it is assumed that the data in the main memory 153 corresponding to the target address is not cached in any of the cache memories 111 to 118 of the processors 101 to 108.

  First, it is assumed that the processors 101, 103, and 106 issued EBR and the processors 104 and 107 issued SBR at the same time. At this time, the node controllers 121 and 122 receive conflicting access requests from a plurality of processors (S21). Specifically, the response / snoop control units 131, 133, and 136 receive EBR that is an access request from the processors 101, 103, and 106. Similarly, the response / snoop control units 134 and 137 receive SBR that is an access request from the processors 104 and 107. Then, the response / snoop control units 131, 133, and 134 transmit the received access request to the crossbar 141. In addition, the response / snoop control units 136 and 137 transmit the received access request to the crossbar 142. Here, since all the target addresses of the received access request are addresses of the main memory 153, the crossbar 142 transmits the received access request to the crossbar 141. Thereafter, the crossbar 141 serializes the received access request and transmits it to the coherency control unit 143 via the interface 181. Here, it is assumed that the coherency control unit 143 receives the EBR from the processor 101, the EBR from the processor 103, the SBR from the processor 104, the EBR from the processor 106, and the SBR from the processor 107.

  Next, the coherency control unit 143 registers competition information (S22). Specifically, the coherency control unit 143 updates the conflict information stored in the address conflict control unit as shown in FIG. 13 by using the plurality of received EBRs and SBRs. That is, when a plurality of access requests are received, the coherency control unit associates the processor that has made the plurality of access requests with the type of the access request, and stores them in the conflict information storage unit as the conflict information. As a result, the competition information is appropriately registered and can be referred to easily.

  Here, after the coherency control unit 143 receives all access requests, the contention information includes Valid = 1, EBR contention detection flag (7: 0) = 0x25, SBR contention detection flag (7: 0) = 0x48, and request ID_0, request ID_2, request ID_3, request ID_5, and request ID_6 include an EBR request ID from the processor 101, an EBR request ID from the processor 103, an SBR request ID from the processor 104, and an EBR request ID from the processor 106, respectively. , The SBR request ID from the processor 107 is set.

  Subsequently, the coherency control unit 143 reads the data of the target address from the main memory 153 (S23). Specifically, the coherency control unit 143 sends MEM_RQ_R to the main memory management system 151 via the memory interface 183 in this state, and receives MEM_RSP_D from the main memory management system 151.

  Thereafter, the coherency control unit 143 determines whether or not the Valid bit of the target address is 1 (S24). If it is determined that the Valid bit of the target address is 1, the coherency control unit 143 generates Rsp_Data_Cnflt (S25). That is, the coherency control unit refers to the address conflict control unit 147 to determine whether or not the target address in the plurality of access requests conflicts, and when it is determined that the target address conflicts, the response instruction is sent to the crossbar 141. Send.

  Here, since the Valid bit of the conflict information stored in the address conflict control unit 147 is 1, the operation of 1402 in FIG. 14 is performed. The process of generating Rsp_Data_Cnflt will be described later with reference to FIG. Then, the coherency control unit 143 updates the directory (S27). That is, the coherency control unit 143 generates Rsp_Data_Cnflt for the first reply target processor determined in step S25, and sets the cache status management function 145 to an appropriate state as the final form when the processing of this Rsp_Data_Cnflt is completed. Update the directory. At this time, the directory status is S, and the caching agent information is 0x48 indicating that the processors 104 and 107 cache.

  If it is determined in step S24 that the Valid bit of the target address is not 1, the coherency control unit 143 issues Rsp_Data_E or Rsp_Data_S (S26). Thereafter, step S27 is similarly executed.

  FIG. 18 is a flowchart showing a flow of processing in which the coherency control unit according to the second embodiment of the present invention generates Rsp_Data_Cnflt as a response.

  First, the coherency control unit 143 refers to the conflict information stored in the address conflict control unit 147 and determines whether or not all the EBR conflict detection flags are 0 (S31). When it is determined that the EBR contention detection flags are all 0, the coherency control unit 143 determines the processor corresponding to the smallest bit among the bits whose SBR contention detection flag is 1 as the first return target processor (S32). ). If it is determined that all of the EBR conflict detection flags are not 0, the coherency control unit 143 determines the processor corresponding to the smallest bit among the bits whose EBR conflict detection flag is 1 as the first return target processor. (S33). Here, since the EBR conflict detection flag = 0x25, the processor 101 corresponding to bit 0 is determined as the first reply target. Note that the above-described method of determining the processor to be returned is not limited to this. That is, the return target processor may be a method that finally selects all the processors by an arbitrary algorithm. In other words, the return target processor is determined based on a predetermined order in the plurality of processors. The predetermined order is, for example, an arbitrary algorithm. For example, it is desirable that the coherency control unit 143 requires an algorithm that determines the processor with the shortest latency. Thereby, the processor with the shortest delay can be selected. Here, for the sake of simplification of description, a method of simply giving priority to a processor corresponding to a small bit has been described.

  Thereafter, the coherency control unit 143 sets an ID indicating the determined first reply target processor in the destination ID field of Rsp_Data_Cnflt (S34). Thus, the crossbars 141 and 142 can appropriately route by referring to the destination ID field of Rsp_Data_Cnflt. Then, the coherency control unit 143 sets the determined request ID of the first reply target processor in the original request ID field of Rsp_Data_Cnflt (S35). Thus, the processor that is the final arrival point in the reply can recognize to which request the reply is issued. Subsequently, the coherency control unit 143 sets all the EBR conflict detection flag, all SBR conflict detection flag, and all request ID information of the address conflict control unit in the EBR conflict detection flag field, the SBR conflict detection flag field, and the request ID field of Rsp_Data_Cnflt. (S36).

  Finally, the coherency control unit 143 issues Rsp_Data_Cnflt and transmits the Rsp_Data_Cnflt to the response / snoop control unit 131 to which the processor 101 as the determined first reply target processor is connected (S37). That is, the coherency control unit associates a processor that has made a plurality of access requests with the type of the access request, and includes it in Rsp_Data_Cnflt that is a response instruction as contention information. Thereby, various flags in the conflict information stored in the address conflict control unit are set. Then, since the response / snoop control unit can determine the next reply target processor without returning to the coherency control unit, the processing time can be further shortened.

  FIG. 19 is a flowchart showing the first half of the process when the response / snoop control unit according to the second embodiment of the present invention receives Rsp_Data_Cnflt. FIG. 20 is a flowchart showing the latter half of the process when the response / snoop control unit according to the second embodiment of the present invention receives Rsp_Data_Cnflt. 19 and 20 are flowcharts showing a response return method, a snoop request issue method, a new Rsp_Data_Cnflt generation method, and a Cmp_I and WB generation method in the response / snoop control unit that has received Rsp_Data_Cnflt. It is.

  First, the response / snoop control unit 131 receives Rsp_Data_Cnflt from the coherency control unit 143 via the crossbar 141 (S41). Next, the response / snoop control unit 131 determines whether or not the bit corresponding to the processor connected to the own response / snoop control unit in the EBR conflict detection flag of Rsp_Data_Cnflt is 1 (S42). Specifically, the response / snoop control unit 131 refers to the bit corresponding to the processor 101 in the EBR conflict detection flag and the SBR conflict detection flag of Rsp_Data_Cnflt, and the Rsp_Data_Cnflt responds to the EBR issued by the processor 101. Or a response corresponding to SBR. Here, since bit 0 of the EBR conflict detection flag is 1, the response / snoop control unit 131 identifies it as a response to EBR.

  If it is determined in step S42 that the bit corresponding to the processor to which the own response / snoop control unit is connected is 1, the response / snoop control unit 131 returns Rsp_Data_E to the processor 101 to which it is connected ( S43). That is, it can be said that the response / snoop control unit 131 converts the received Rsp_Data_Cnflt into Rsp_Data_E that can be processed by the processor 101. As a result, as described above, the processors 101 to 108 according to the second embodiment of the present invention are not a special processor for the present invention, and a general processor can be used.

  Subsequently, the response / snoop control unit 131 transmits Snp_E to the processor 101 (S44).

  When applied to the SMP system mentioned in the above-mentioned problem, Cmp is returned from the response / snoop control unit 131 to the coherency control unit 143 to notify that the response to the processor 101 is completed. Subsequently, with the reception of the Cmp, the coherency control unit 143 receives the Snp_E that is generated and issued to cause the processor 103 to eject the data in the cache memory 111 of the processor 101 to the processor 101. I had to wait. That is, Cmp and Snp_E reciprocate between the response / snoop control unit 131 and the coherency control unit 143 until Snp_E is issued to the processor 101 in order to pass data to the processor 103 that is the issuer of the next request to be processed. It took time to do just that.

  In the second embodiment of the present invention, the coherency control unit 143 and the response / snoop control unit 131 are configured as the same node controller or a node controller that is one step across. This is because an actual large-scale computer may require a multistage node controller during this period. In that case, the round trip time of Cmp and Snp_E between the response / snoop control unit 131 and the coherency control unit 143 may be even longer.

  Therefore, the second embodiment of the present invention aims to shorten the response latency from the processor 101 to other processors than the processor 101 by this reciprocation. That is, the response / snoop control unit 131 that has made a response to the processor 101 returns Cmp to the coherency control unit 143 and does not wait for subsequent Snp_E arrival. Instead, the response / snoop control unit 131 voluntarily generates Snp_E and issues it to the processor 101 in step S44. Then, the processor 103 waits for Cmp_I and Rsp_Data_E as a result to be returned from the processor 101.

  Thereafter, the response / snoop control unit 131 determines whether or not Cmp_I + Rsp_Data_E for Snp_E is received from the processor (S45). If it is determined not to be received, step S45 is executed again. If it is determined that the data has been received, the response / snoop control unit 131 replaces the data part of Rsp_Data_Cnflt with the data of Rsp_Data_E (S46). That is, the data is updated. Subsequently, the response / snoop control unit 131 resets the bit corresponding to the processor 101 connected to the own response / snoop management unit in the EBR conflict detection flag of Rsp_Data_Cnflt to 0 (S47).

  Subsequently, proceeding to FIG. 20, the response / snoop control unit 131 determines whether or not all the EBR conflict detection flags are 0 (S51). Here, the response / snoop control unit 131 immediately after updating the EBR conflict detection flag from 0x25 to 0x24 in step S47. Therefore, since all are not 0, it is determined in step S51 that all of the EBR conflict detection flags are not 0. At this time, the response / snoop control unit 131 determines the processor corresponding to the smallest bit among the bits whose EBR conflict detection flag is 1 as the next reply target processor (S56). Here, since the EBR conflict detection flag is 0x24, the processor 103 is determined as the next reply target processor.

  Thereafter, the response / snoop control unit 131 sets the ID indicating the determined next reply target processor in the destination ID field of Rsp_Data_Cnflt (S57). Specifically, the response / snoop control unit 131 sets the ID corresponding to the processor 103 determined as the next reply target processor in the destination ID field of Rsp_Data_Cnflt.

  Further, the response / snoop control unit 131 sets the determined request ID of the next reply target processor in the original request ID field of Rsp_Data_Cnflt (S58). Specifically, the response / snoop control unit 131 reads the EBR request ID issued by the processor 103 from the request ID_2 of Rsp_Data_Cnflt, and sets it in the original request ID field.

  Further, the response / snoop control unit 131 issues Rsp_Data_Cnflt and transmits it to the response / snoop control unit 133 to which the processor 103 which is the next reply target processor is connected (S59). Specifically, the response / snoop control unit 131 transmits Rsp_Data_Cnflt to the crossbar 141, and the response / snoop control unit 131 transmits the Rsp_Data_Cnflt to the response / snoop control unit 133. Thereafter, the response / snoop control unit 133 routes appropriately according to the destination ID field information of Rsp_Data_Cnflt, and transmits it to the processor 103.

  Thereafter, similarly to the response / snoop control unit 131, the processing according to FIGS. 19 and 20 is also performed in the response / snoop control units 133 and 136 connected to the processors 103 and 106 which are EBR request sources.

  However, the response / snoop control unit 136 connected to the last EBR source processor 106 is the same as the response / snoop control units 131 and 133 until step S47, but in step S51, the EBR conflict detection flag is set. All are determined to be 0. Therefore, when it is determined that the EBR conflict detection flag is all 0, the response / snoop control unit 136 determines whether the SBR conflict detection flag is all 0 (S52).

  Here, since the SBR conflict detection flag of Rsp_Data_Cnflt is 0x48, the response / snoop control unit 136 determines that all of the SBR conflict detection flags are not zero. Thereafter, the response / snoop control unit 136 determines the processor 104 that is the processor corresponding to the smallest bit among the bits whose SBR conflict detection flag is 1 as the next reply target processor (S55).

  Thereafter, the response / snoop control unit 136 sets the ID meaning the processor 104 as the destination ID of Rsp_Data_Cnflt (S57), extracts the value of the request ID_3 of Rsp_Data_Cnflt, and sets it as the original request ID (S58). Then, the response / snoop control unit 136 issues Rsp_Data_Cnflt and transmits it to the response / snoop control unit 134 to which the processor 104 that is the next return target processor is connected (S59).

  Here, the response / snoop control unit 134 performs processing according to FIGS. 19 and 20. First, the response / snoop control unit 134 receives Rsp_Data_Cnflt (S41), and determines whether or not the bit corresponding to the processor 104 of the EBR conflict detection flag is 1 (S42). Here, since all the EBR conflict detection flags are 0, it is not determined that the bit corresponding to the processor to which the own response / snoop control unit is connected is 1. Therefore, the response / snoop control unit 134 returns Rsp_Data_S to the processor to which the own response / snoop control unit is connected (S48). That is, it can be said that the response / snoop control unit 134 converts the received Rsp_Data_Cnflt into Rsp_Data_S that can be processed by the processor 104.

  Subsequently, the response / snoop control unit 134 resets the bit corresponding to the processor connected to the own response / snoop management unit in the SBR conflict detection flag of Rsp_Data_Cnflt to 0 (S49). Specifically, the response / snoop control unit 134 resets the bit corresponding to the processor 104 in the SBR conflict detection flag of Rsp_Data_Cnflt to zero. Here, the SBR competition detection flag transitions from 0x48 to 0x40.

  Subsequently, proceeding to FIG. 20, the response / snoop control unit 134 determines whether or not all the EBR conflict detection flags are 0 (S51). Here, it is determined that the EBR conflict detection flags are all 0, and the response / snoop control unit 134 determines whether the SBR conflict detection flags are all 0 (S52). Here, since the SBR conflict detection flag is 0x40, it is determined that all of the SBR conflict detection flags are not zero. Then, since the EBR conflict detection flag is 0x24, the response / snoop control unit 134 determines the processor 107 as the next reply target processor (S55).

  Subsequently, the response / snoop control unit 134 sets the ID representing the processor 107 as the destination ID of Rsp_Data_Cnflt (S57), extracts the value of the request ID_6 of Rsp_Data_Cnflt, and sets it as the original request ID (S58). Then, the response / snoop control unit 134 issues Rsp_Data_Cnflt and transmits it to the response / snoop control unit 137 to which the processor 107 that is the next reply target processor is connected (S59).

  Similar to the response / snoop control unit 134, the response / snoop control unit 137 performs processing according to FIGS. However, since the SBR conflict detection flag corresponding to the processor 107 transitions from 0x40 to 0x00 in step S49, it is determined in step S52 that all the SBR conflict detection flags are 0, and the process proceeds to step S53.

  If it is determined in step S52 that all SBR conflict detection flags are 0, the response / snoop control unit 137 generates Cmp_I and WB and returns them to the coherency control unit (S53). Specifically, the response / snoop control unit 137 generates Cmp_I and WB, and issues them to the coherency control unit 143, similarly to 920 in FIG.

  Thereafter, the coherency control unit 143 resets the Valid bit of the conflict information stored in the address conflict control unit 147 to 0. Further, the coherency control unit 143 generates MEM_RQ_W by WB, issues it to the main storage management system 151 via the memory interface 183, and issues Cmp (S54). Thereby, all the processes are completed.

  As described above, in the second embodiment of the present invention, as shown in the problem, the snoop request and its completion do not reciprocate between the target processor and the cache coherency control unit every time one processor request is processed. In addition, by enabling processing of the next processor request without completion, the round-trip latency is eliminated, and it is possible to control the address conflict data to move directly between processors while guaranteeing cache coherency as a system. This reduces the processing time for all requests when an address conflict occurs.

<Other embodiments of the invention>
Furthermore, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present invention described above.

11 processor 12 processor 13 cache memory 14 cache memory 15 cache memory control system 16 transmission / reception control unit 17 coherency control unit 18 main memory 100 multiprocessor system 101 processor 102 processor 103 processor 104 processor 105 processor 106 processor 107 processor 108 processor 111 cache memory 112 Cache memory 113 Cache memory 114 Cache memory 115 Cache memory 116 Cache memory 117 Cache memory 118 Cache memory 121 Node controller 122 Node controller 131 Response / snoop control unit 132 Response / snoop control unit 133 Response / snoop Control unit 134 response / snoop control unit 135 response / snoop control unit 136 response / snoop control unit 137 response / snoop control unit 138 response / snoop control unit 141 crossbar 142 crossbar 143 coherency control unit 144 coherency control unit 145 cache status management Function 146 Cache status management function 147 Address conflict control unit 148 Address conflict control unit 151 Main memory management system 152 Main memory management system 153 Main memory 154 Main memory 155 Main memory controller 156 Main memory controller 161 System interface 162 System interface 163 System interface 164 System interface 165 System interface 166 System Interface 167 system interface 168 system interface 171 interface 172 interface 173 interface 174 interface 175 interface 176 interface 177 interface 178 interface 181 interface 182 interface 183 memory interface 184 memory interface 185 node interface 301 cache status 302 caching agent information 701 valid bit 702 EBR conflict detection Flag 703 EBR conflict detection flag 704 Request ID

Claims (16)

A transmission / reception control unit connected to a plurality of processors each having a cache memory;
A coherency controller that accesses main memory and maintains consistency among cache memories of the plurality of processors,
The coherency control unit, when a target address in a plurality of access requests including at least exclusive data read from the plurality of processors to the main memory competes, contention information that is information on contention of the plurality of access requests Sending the included response instruction to the transmission / reception control unit,
The transmission / reception control unit sends data corresponding to the access request to a reply target processor determined from among the processors having the exclusive data read as an access request based on contention information included in the response instruction. A cache memory control system characterized by sending a reply and subsequently transmitting a snoop request for requesting acquisition of data in the cache memory of the processor to be sent back.   The transmission / reception control unit determines a processor that is a reply target next to the reply target processor based on contention information included in the response instruction, and receives a response to the snoop request from the reply target processor. 2. The cache memory control system according to claim 1, wherein data corresponding to the access request is returned to the processor to be returned next.   The coherency control unit determines a first reply target processor based on the contention information, and transmits the first reply target processor to the transmission / reception control unit as a response instruction to the determined reply target processor. The cache memory control system described in 1.   The coherency control unit associates the processor that has made the plurality of access requests with the type of the access request and includes the same as the contention information in the response instruction. The cache memory control system according to item. Competing information storage means for storing the competing information,
The coherency control unit refers to the contention information storage unit, determines whether or not the target address in the plurality of access requests conflicts, and determines that the target address conflicts, the response instruction is transmitted to the transmission / reception control 5. The cache memory control system according to claim 1, wherein the cache memory control system transmits the data to a storage unit.   When the plurality of access requests are received, the coherency control unit associates the processor that has made the plurality of access requests with the type of the access request and stores them in the contention information storage unit as the contention information 6. The cache memory control system according to claim 5, wherein:   The cache memory control system according to claim 1, wherein the return target processor is determined based on a predetermined order in the plurality of processors.   8. The cache memory according to claim 1, wherein the contention information includes a contention presence / absence flag, an access request type, and identification information of the access request in an address unit of the main memory. Control system. A transmission / reception control unit connected to a plurality of processors each having a cache memory;
A cache memory control method in a multiprocessor system, comprising: a coherency control unit that accesses a main memory and maintains consistency among cache memories of the plurality of processors;
In the transmission / reception control unit, a plurality of access requests including at least exclusive data read from the plurality of processors to the main memory are received,
In the coherency control unit, when target addresses in the plurality of access requests compete, a response instruction including contention information that is information related to the competition of the plurality of access requests is transmitted to the transmission / reception control unit,
In the transmission / reception control unit, based on contention information included in the response instruction, data corresponding to the access request is sent to the reply target processor determined from among the processors that have made the exclusive data read access request. Reply,
Subsequently, the transmission / reception control unit transmits a snoop request for requesting acquisition of data in the cache memory of the processor to be returned.   In the transmission / reception control unit, after determining a processor to be returned next to the processor to be returned based on contention information included in the response instruction, and after receiving a response to the snoop request from the processor to be returned The control method according to claim 9, wherein data corresponding to the access request is returned to the processor to be returned next.   The coherency control unit determines a first reply target processor based on the contention information, and transmits to the transmission / reception control unit as a response instruction to the determined reply target processor. The control method described in 1.   12. The coherency control unit according to any one of claims 9 to 11, wherein a processor that has made the plurality of access requests and the type of the access request are associated with each other and included in the response instruction as the contention information. The control method according to item. The multiprocessor system includes contention information storage means for storing the contention information,
The coherency control unit refers to the contention information storage unit to determine whether or not the target address in the plurality of access requests conflicts, and when it is determined that the target address conflicts, the response instruction is transmitted to the transmission / reception control The control method according to claim 9, wherein the control method is transmitted to a unit.   In the coherency control unit, when the plurality of access requests are received, the processor that has made the plurality of access requests and the type of the access request are associated with each other and stored in the contention information storage unit as the contention information. The control method according to claim 13.   The control method according to claim 9, wherein the return target processor is determined based on a predetermined order in the plurality of processors.   16. The control method according to claim 9, wherein the contention information includes a contention presence / absence flag, an access request type, and identification information of the access request in an address unit of the main memory. .

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