JP5375795B2 - Liquid crystal display device, driving device and driving method for liquid crystal display element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display device which has high luminance and can be reduced in size by eliminating the need of making a data transfer period in which luminance is reduced into a blanking state. <P>SOLUTION: The driving device of the liquid crystal display device is driven by a sub-frame driving system. A sub-frame data creating unit 26 creates sub-frame data which is a step bit pulse. A data transfer unit 30 transfers the sub-frame data of a predetermined number to a liquid crystal display element line-sequentially for a fixed data transfer period and continuously transfers the sub-frame data of the next number line-sequentially. A pixel circuit unit 7 includes a sample/hold section holding the sub-frame data and a voltage selection section selecting one of a blanking voltage and a driving voltage by the held sub-frame data and supplying it to a pixel electrode of the liquid crystal display element. A voltage control unit 17 repeats the polarity reverse of the pixel of the liquid crystal display element asynchronously with the start time of the data transfer period of the data transfer unit. <P>COPYRIGHT: (C)2012,JPO&amp;INPIT

Description

  The present invention relates to a liquid crystal display device, a liquid crystal display element driving device, and a driving method thereof, and more particularly, a liquid crystal display device that displays an image by dividing one frame into a plurality of subframes using a digitized video signal as an input signal. The present invention relates to a driving device for a liquid crystal display element and a driving method thereof.

  The driving method of the liquid crystal display element used in the liquid crystal display device is an analog method in which the voltage value applied to the pixel is a continuous analog value, and the voltage applied to the pixel is binary, and the luminance of the image There is a digital method for controlling an effective voltage value applied to a pixel of a liquid crystal by changing a time width of an applied voltage corresponding to (gradation). In the case of the digital method, since only information of 0 or 1 is applied to the pixel, it is difficult to be influenced by external factors such as noise.

  In the digital method, it is common to use a subfield method in order to obtain a halftone. In the subfield method, a predetermined number of subfields with different relative ratios of drive (light emission) periods are prepared in one field period of the video signal, and the subfield is appropriately selected according to the gradation of the video signal to be displayed. Display, and halftone display is performed using the visual integration effect of the viewer.

  In the subfield method, 0 or 1 data for all the pixels is transferred to the sample hold unit during the data transfer period (WC period), and the liquid crystal of the pixels is transferred during the subsequent drive period (DC period). It is driven according to. The data transfer period is constant in all subframes. The driving period is different for each subframe. For example, in the case where one frame is composed of 12 subframes (SF) 1 to SF12, the ratio of the drive periods of each subframe is SF1 = 1, SF2 = 2, SF3 = 4, SF4 = 8. SF5 = 16 is set, and the ratio of drive periods is set to 32 for all of SF6 to SF12. Among these subframes, SF1 to SF5 are called binary pulses, and SF6 to SF12 are called step pulses.

Accordingly, a data transfer period of a predetermined period is required for all the subframes, and during that period, the pixels are in a blanking state and do not contribute to video display.
Patent Document 1 proposes a liquid crystal display element in which two sample and hold units are provided in one pixel and do not need to be in a blanking state during a data transfer period.

JP-T-2001-523847

By the way, in the method of preparing two sample hold units in a pixel, it is possible to achieve high luminance, but since the pixel becomes large, there are problems in increasing the resolution and miniaturization of the liquid crystal display element. Was.
Accordingly, the present invention provides a liquid crystal display device, a liquid crystal display element driving device, and a driving method that can achieve high brightness and a reduction in size without the need to set the data transfer period during which the luminance decreases to a blanking state. With the goal.

  In order to solve the above-described problems of the prior art, the present invention provides a subframe data generation unit that generates subframe data in which all subframes of one frame are composed of step bit pulses based on input image data. (26) and a predetermined number of sub-frame data are transferred in a predetermined data transfer period to the liquid crystal display element (6) in which a plurality of pixels are arranged in a plurality of rows and columns. A data transfer unit (30) for sequentially transferring subframe data of the next number after the number, a sample hold unit (16) for holding the input 0 or 1 subframe data, and the sample hold unit One of blanking voltage and driving voltage is selected based on 0 or 1 sub-frame data held in the liquid crystal display A pixel circuit unit (7) having a voltage selection unit (17) to be supplied to the child pixel electrode (8) and a start time of the data transfer period of the data transfer unit asynchronously with the pixel of the liquid crystal display element And a voltage control unit (32) that repeats polarity inversion, and a drive device for a liquid crystal display element.

  Further, when N, M, F, and D are integers, a look-up table unit that converts input video signal data of bit number N into (M + F + D) bit data larger than N by performing inverse gamma correction and linear interpolation. (21), (M + F + D) -bit data processed in the lookup table unit by error diffusion processing (M + F) -bit data converted into (M + F) -bit data, and processed by the error diffusion unit A frame rate control unit (24) for converting (M + F) -bit data into M-bit data by frame rate control, and M-bit data processed by the frame rate control unit are used. When the frame is configured and the driving gradation is 1, the first sub-frame is in the driving state, and the drive A sub-frame data is generated by a driving gradation table (27) that increases toward the back of a sub-frame that is already in a driving state, one sub-frame every time the gradation is increased by one. A predetermined number of subframe data is transferred in a predetermined data transfer period to the frame data creation unit (26) and the liquid crystal display element (6) in which a plurality of pixels are arranged in a plurality of rows and columns. Subsequently, a data transfer unit (30) that sequentially transfers the subframe data of the next number after the number, a sample hold unit (16) that holds the inputted 0 or 1 subframe data, The liquid crystal is selected by selecting one of a blanking voltage or a driving voltage based on the 0 or 1 subframe data held in the sample hold unit. A voltage that repeats polarity inversion of the pixels of the liquid crystal display element asynchronously with a start time of the data transfer period of the data transfer unit and a pixel circuit unit having a voltage selection unit (17) to be supplied to the pixel electrode of the display element And a controller (32). A driving device for a liquid crystal display element is provided.

  In each of the above configurations, the period for transferring the subframe data may be an integral multiple of the polarity inversion period.

  Further, any one of the liquid crystal display element driving devices described above, a liquid crystal display element (6) driven by the driving device, an illumination optical system (1) for making illumination light incident on the liquid crystal display elements, There is provided a liquid crystal display device comprising a projection lens (11) for projecting modulated light emitted from a liquid crystal display element.

  Furthermore, based on the input image data, a subframe data in which all subframes of one frame are composed of step bit pulses is created, and a liquid crystal display element in which a plurality of pixels are arranged in a plurality of rows and columns ( 6), the subframe data of a predetermined number is transferred in a row in a predetermined data transfer period, and the subframe data of the number next to the number is subsequently transferred in a row sequence. The sub-frame data is held, and one of blanking voltage or driving voltage is selected and supplied to the pixel electrode (8) of the liquid crystal display element based on the held 0 or 1 sub-frame data. A liquid crystal display element comprising: repeating polarity inversion of pixels of the liquid crystal display element asynchronously with a start time of the data transfer period To provide a driving method.

  Also, when N, M, F, and D are integers, the input video signal data of bit number N is converted into (M + F + D) bit data larger than N by performing inverse gamma correction and linear interpolation, and the (M + F + D) The bit data is converted to (M + F) bit data by error diffusion processing, the (M + F) bit data is converted to M bit data by frame rate control, the M bit data is used, and the step bit All subframes are composed of pulses, and when the driving gradation is 1, the first subframe is in the driving state, and every time the driving gradation is increased, one subframe that is in the driving state is already in the driving state. Sub-frame data is created using a driving gradation table that increases toward the back of the sub-frame. The subframe data of a predetermined number is transferred to the liquid crystal display elements (6) arranged in a row in a row in a predetermined data transfer period, and subsequently the subframe data of the number next to the number is transferred. Transfer sequentially, hold the inputted 0 or 1 subframe data, select one of blanking voltage or driving voltage by the held 0 or 1 subframe data, and the liquid crystal There is provided a driving method of a liquid crystal display element, characterized in that the liquid crystal display element is supplied to a pixel electrode of the display element, and the polarity inversion of the pixel of the liquid crystal display element is repeated asynchronously with a start time of the data transfer period.

  In each of the above methods, the period for transferring the subframe data may be an integral multiple of the polarity inversion period.

  According to the present invention, there is provided a liquid crystal display device, a liquid crystal display element driving device, and a driving method capable of achieving high brightness and downsizing without requiring a data transfer period that causes a reduction in luminance to be in a blanking state. can do.

1 is a schematic configuration diagram illustrating a liquid crystal display device according to a first embodiment of the present invention. FIG. 2 is a diagram illustrating a drive circuit configuration of each pixel in the digitally driven reflective liquid crystal display element according to the first embodiment of the present invention. It is a figure which shows the relationship between the input voltage of the reflection type liquid crystal display element in 1st Embodiment, and the intensity | strength of output light. 1 is a block diagram showing a drive circuit (drive device) according to a first embodiment. It is a figure for demonstrating the gradation expression in 1st Embodiment. It is a figure which shows the drive pattern in 1st Embodiment. It is a figure which shows the drive gradation table in 1st Embodiment. It is a figure which shows the error diffusion figure in 1st Embodiment. It is a figure which shows the error diffusion flow in 1st Embodiment. It is a figure which shows the frame rate control flow in 1st Embodiment. It is a figure which shows the frame rate control table in 1st Embodiment. It is a figure which shows the signal processing in 1st Embodiment. It is a figure which shows the polarity inversion drive of the reflection type liquid crystal display element in 1st Embodiment. It is a figure explaining the generation | occurrence | production mechanism of the horizontal electric field in a reflection type liquid crystal element. It is a figure explaining that a horizontal electric field is disperse | distributed equally by frame rate control.

  Hereinafter, a liquid crystal display device and a driving method thereof according to the present invention will be described with reference to the accompanying drawings. In the following, a projection type display device provided with an active matrix type reflective liquid crystal display element as a display panel will be described as an example.

<First Embodiment>
FIG. 1 is a schematic configuration diagram showing a liquid crystal display device according to a first embodiment of the present invention. The liquid crystal display device generally includes a reflective liquid crystal display element 6, a polarization beam splitter 5 (hereinafter referred to as PBS), and a projection lens 13. The reflective liquid crystal display element 6 has a structure in which a liquid crystal 9 is sealed between a counter electrode (also referred to as a transparent electrode) 10 and a pixel electrode 8.

  Light 2 including S-polarized light 3 and P-polarized light 4 emitted from the illumination optical system 1 enters the PBS 5. Polarized light is separated by PBS5. The S-polarized light 3 is reflected by the polarization separation surface of the PBS 5 and proceeds to the reflective liquid crystal display element 6 side. P-polarized light is transmitted through the polarization separation surface of PBS. The liquid crystal 9 of the reflective liquid crystal display element 6 modulates incident S-polarized light according to the voltage applied between the pixel electrode 8 and the counter electrode 10 by the pixel circuit 7. The S-polarized light incident on the counter electrode 10 is modulated in the process from being reflected by the pixel electrode 8 and being emitted from the counter electrode 10, and is emitted from the counter electrode 10 as light composed of P-polarized light and S-polarized light. In the light emitted from the counter electrode 10, only the P-polarized component, which is modulated light, passes through the PBS 5, and the S-polarized component is reflected by the PBS 5. The P-polarized light that has passed through the PBS 5 is emitted by the projection lens 11, and the emitted light 12 is projected on the screen 13 to display an image. The intensity of the output light described later refers to the illuminance of the output light measured on the screen 13.

  FIG. 2 is a diagram showing a drive circuit configuration of each pixel in the digitally driven reflective liquid crystal display element 6 according to the first embodiment of the present invention. Each pixel of the reflective liquid crystal display element 6 has a structure in which a liquid crystal 9 is sandwiched between a pixel electrode 8 and a counter electrode 10. A pixel circuit 7 indicated by a broken line includes a sample hold unit 16 and a voltage selection circuit 17 which is a voltage selection unit. The sample hold unit 16 is composed of an SRAM structure flip-flop. The sample hold unit 16 is connected to the column data line D and the row selection line W. The output of the sample hold unit 16 is connected to the voltage selection circuit 17. The voltage selection circuit 17 is connected to the blanking voltage line V0 and the drive voltage line V1. The voltage selection circuit 17 is connected to the pixel electrode 8 and applies a predetermined voltage from the blanking voltage or the drive voltage to the pixel electrode 8. The value of the voltage of the counter electrode 10 is called a common voltage Vcom.

  FIG. 3 is a diagram showing the relationship between the input voltage of the reflective liquid crystal display element 6 and the intensity of output light in this embodiment. In FIG. 3, the horizontal axis represents the input voltage, and shows the potential difference between the pixel electrode 8 and the counter electrode 10, that is, the driving voltage of the liquid crystal 9. The vertical axis indicates the intensity of output light emitted from the liquid crystal 9. The voltage at which the intensity of the output light emitted from the liquid crystal 9 starts to increase is the dark value voltage Vth. When the voltage is 0 (for example, both the pixel electrode 8 and the counter electrode are GND), the intensity of the output light is small and the state is black (blanking voltage), and the voltage at which the output light begins to saturate is the saturation voltage Vw (white). Level.)

  FIG. 4 is a block diagram showing a drive circuit (drive device) according to the first embodiment of the present invention. FIG. 5 is a diagram for explaining gradation expression in the first embodiment. FIG. 5 shows an example of gradation expression in each process unit when the number of bits of input video signal data is 8 bits. FIG. 6 is a diagram showing a drive pattern in the first embodiment. FIG. 7 is a diagram showing a drive gradation table in the first embodiment. FIG. 8 is a diagram showing an error diffusion flow in the first embodiment. FIG. 9 is a diagram showing an error diffusion diagram in the first embodiment. FIG. 10 is a diagram showing a frame rate control flow in the first embodiment. FIG. 11 is a diagram showing a frame rate control table in the first embodiment.

  In FIG. 4, video signal data with N bits input is converted into (M + F + D) bit data larger than N by the look-up table unit 21. Here, M is the number of bits when the number of subframes is expressed in binary, D is the number of bits to be interpolated by the error diffusion processing unit 23, and F is the number of bits to be interpolated by the frame rate control unit 24. . N, M, F, and D are integers.

  In the example of FIG. 5, the number of bits of the input video signal data is 8 bits (N = 8), the number of bits to be interpolated by the error diffusion processing unit 23 is 4 bits (D = 4), and the frame rate control unit 24 The number of bits to be interpolated is set to 2 bits (F = 2). When the number of subframes is expressed in binary, the number of bits is 4 bits (M = 4), and the drive gradation is 12 (not including black).

  Here, the operation of the lookup table unit 21 will be described. Generally, video signals are subjected to gamma correction. On the image display device side, it is necessary to perform inverse gamma correction processing on the video signal that has been subjected to gamma correction to restore the linear gradation. Inverse gamma correction is correction in which the output is X raised to the power of 2.2 with respect to the input X. In this case, the output characteristic is expressed as “gamma 2.2” below. The look-up table unit 21 has a function of realizing a liquid crystal display device having an output characteristic of gamma 2.2 by converting input / output characteristics of the reflective liquid crystal display element 6. The look-up table is adjusted in advance so that the 10-bit output has an arbitrary output characteristic (for example, gamma 2.2). For example, in the first embodiment, images by driving each of the twelve driving gradations (not including black) shown in FIG. 7 are projected by the liquid crystal display device shown in FIG. Measure each of the above. By linearly interpolating the illuminance between the respective drive gradations with 6 bits (M + D = 6) (64 gradations), illuminance data for each gradation of 0 to 768 is predicted. It is assumed that 256 pieces of data having arbitrary output characteristics (for example, gamma 2.2) are selected from those illuminance data and are stored as a lookup table in advance.

  The lookup table unit 21 has a lookup table of 256 × 10 bits (that is, “2 to the 8th power” gradation x (4 + 2 + 4) bits). Here, the “2 to the 8th power” gradation x (4 + 2 + 4) bit means that N = 8, M = 4, F = 2, and D = 4 with respect to the “2 to the Nth power” gradation x (M + F + D) bit. Is equivalent to the value of. The look-up table unit 21 converts the input 8-bit image data into 10-bit data and outputs it.

  Returning to FIG. 4, the video signal data converted into (M + F + D) bits by the look-up table unit 21 is (M + F) bit data by diffusing the lower D bits of information to surrounding pixels by the error diffusion unit 23. Is converted to In the example of FIG. 5, the converted 10-bit data is output by the error diffusion unit 23 by diffusing the lower 4 bits of information to surrounding pixels, quantizing the data into upper 6 bits.

  The error diffusion method is a method of compensating for the lack of gradation by diffusing an error (display error) between a video signal to be displayed and an actual display value to surrounding pixels. In the first embodiment, the lower 4 bits of the video signal to be displayed are set as display errors, and as shown in FIG. 8, 7/16 of the display error is displayed on the right adjacent pixel and 3/16 of the display error is displayed on the lower left pixel. , 5/16 of the display error is added to the pixel immediately below, and 1/16 of the display error is added to the pixel on the lower right.

  The operation of the error diffusion unit 23 will be described in more detail with reference to FIG. A video signal at a certain coordinate diffuses an error as described above, and an error obtained by diffusing the previous video is added. In the input 10-bit data, first, an error in which the previous image is diffused is added by the error buffer. The input video signal data is divided into upper 6 bits and lower 4 bits after the error buffer value is added.

The divided lower 4 bits are shown below. The value on the right is a display error.
Lower 4 bits Display error 0000 0
0001 +1
0010 +2
0011 +3
0100 +4
0101 +5
0110 +6
0111 +7
1000-7
1001-6
1010-5
1011 -4
1100-3
1101 -2
1110 -1
1111 0

  The display error corresponding to the divided lower 4-bit value is added to the error buffer and held as shown in FIG. Also, a threshold comparison is performed on the divided lower 4-bit value, and if the value is larger than 1000 (the row after the row where the value on the left is 1000), 1 is added to the upper 6-bit value. Is added. Then, the upper 6-bit data is output from the error diffusion unit.

  Returning to FIG. 4, the video signal data converted into (M + F) bits by the error diffusion unit 23 is input to the frame rate control unit 24. The frame rate control unit 24 includes a frame rate control table. The frame rate control unit 24 specifies the position in the frame rate control table from the lower F bit value, the pixel position information, and the frame count information, and the value (1 or 0, hereinafter 0/1) Are added to the upper M bits and converted to M bit data. Here, the frame rate control method refers to an m (m: m ≧ 2, natural number) frame as one period for display of one pixel of the display element, and n (n: n> 0, m> n) of the period. In this method, pseudo gradation is displayed by performing on display in the (natural number) frame and performing off display in the remaining (mn) frames.

  In the example of FIG. 5, the 6-bit data output from the error diffusion unit 23 is input to the frame rate control unit 24. The frame rate control unit 24 derives a value of 0/1 from the frame rate control table from the lower 2 bits information, the position information in the display area, and the frame counter information, and the upper 4 bits separated from the input 6 bits. Add to the value of the bit.

  The operation of the frame rate control unit 24 will be specifically described with reference to FIG. The input 6-bit data is divided into upper 4 bits and lower 2 bits. The lower 2 bits of the input 6-bit data, the position information in the pixel display area (that is, the lower bits of the X coordinate and the lower 2 bits of the Y coordinate, which are coordinate data), and the lower 2 bits of the frame counter A value of “0” or “1” shown in the frame rate control table of FIG. 11 is specified using a total of 8 bits. The specified value “0” or “1” is added to the upper 4 bits of data and output as 4 bits of data.

  Returning to FIG. 5, the 4-bit data output from the frame rate control unit 24 is limited to 12 which is the maximum value of the drive gradation by the limiter unit 25 shown in FIG. At 26, the data is converted into 12-bit data to be transferred to the reflective liquid crystal display element 6. The drive gradation table 27 is used for conversion to 12-bit data.

  Returning to FIG. 4, the 12-bit data output from the subframe data creation unit 26 is stored in the frame buffer 29 divided for each subframe by the memory control unit 28. The frame buffer 29 has a double buffer structure. While data is being stored in the frame buffer 0, the data in the frame buffer 1 is transferred to the reflective liquid crystal display element 6 via the data transfer unit. In the next frame, the data in the frame buffer 0 stored during the previous frame period is transferred to the liquid crystal display element 6 via the data transfer unit 30, and the subframe data of the video signal data input to the frame buffer 1. Output data from the creation unit 26 is stored.

  The drive control unit 31 controls processing timing for each subframe, and performs a transfer instruction to the data transfer unit 30 and control of the gate driver 34. The data transfer unit 30 instructs the memory control unit 28 in accordance with an instruction from the drive control unit 31, receives the designated subframe data from the memory control unit 28, and transfers the data to the source driver 33. The data transfer unit 30 transfers subframe data at regular intervals.

  Each time the source driver 33 receives data for one line from the data transfer unit 30, it simultaneously transfers the data to the corresponding pixel circuit 7 of the reflective liquid crystal display element 6 using the column data lines D0-Dn. At this time, the gate driver 34 activates the row selection line Wy of the row designated by the vertical start signal (VST) / vertical shift clock signal (VCK) from the drive control unit 31, and all the designated rows y are activated. Data is transferred to the pixels in the column.

  The voltage control unit 32 performs polarity inversion processing of V0 / V1 / Vcom which is a voltage applied to the liquid crystal. V0 is a blanking voltage, V1 is a driving voltage, and Vcom (common voltage) is a voltage of the counter electrode 10 of the liquid crystal. The polarity inversion process is a process in which the voltage value V0 / V1 / Vcom is alternately set to GND and Vw at equal intervals. V0 and Vcom are applied in the same phase, and V1 is applied in a phase shifted by 1/2 period from V0 / Vcom. The polarity inversion period is independent of the processing in the data transfer unit 30, and the polarity inversion processing is performed asynchronously.

  The drive pattern in the first embodiment will be described with reference to FIG. FIG. 6 shows a case where the video signal is 60 frames per second and the number of subframes is 12. The WC period represents a data transfer period (WC period) in which data for each subframe is transferred to all pixels in the liquid crystal display element. Data of subframe 1 is transferred during the WC period from T0 to T1, which is the head of the frame period. As soon as all the data of subframe 1 is transferred at T1, the data of subframe 2 is transferred during the WC period from T1 to T2. Thus, the upper horizontal line starting from T0 in FIG. 6 corresponds to TOP (0 row) in the display area, and the lower horizontal line in FIG. 6 corresponds to the bottom (m line) in the display area. Yes.

  Since the data for every 12 subframes are sequentially transferred to the liquid crystal display element in this way, all the subframe periods of each pixel are the same as the WC period, which is the data transfer period. Within one frame period, the WC period and the DC period are alternately repeated 12 times, and 0 or 1 data for each subframe assigned in the order of SF1, SF2,..., SF11, SF12 from the beginning. Is transferred in the WC period, and when the data sampled and held in the pixel is 0, the pixel is in a blanking state, and in the case of 1, it is in a driving state.

  Next, the drive gradation table in the first embodiment shown in FIG. 7 will be described. As in FIG. 6, the video signal is 60 frames per second, the number of subframes is 12, the data transfer period (WC period) is 1388 [μs], and the drive period (DC period) is 1388 [μs]. FIG. 7 shows the state of the DC period for each subframe with respect to the drive gradation. The gradation in the vertical column in FIG. 7 is 4-bit data obtained by the frame rate control unit 24 and is limited by the limiter unit 25 by 12 which is the maximum value of the drive gradation. SF1-SF12 represents the order of subframes within one frame. When the DC period column is 1, it indicates a driving state. A zero in the DC period column indicates a blank state.

  When the gradation shown in the vertical column of FIG. 7 is 1, only the first subfield SF1 is in the drive state. When the gradation is 2, only SF1 and SF2 are driven. Hereinafter, as the number of gradations increases, the number of subframes in the driving state increases, and in the case of 12 which is the highest gradation, all subframes are in the driving state. In other words, as the number of gradations increases, the number of subframes that are in the drive state increases backward in time.

  FIG. 12 is a diagram illustrating signal processing in the first embodiment. FIG. 13 is a diagram showing polarity inversion driving of the reflective liquid crystal display element 6 in the first embodiment.

  Hereinafter, the signal processing will be described with reference to FIG. 12, with reference to FIG. 2, FIG. 4, and FIG. FIG. 12 shows signal processing in the first embodiment. At time T0, the vertical synchronization signal Vsync becomes active, the frame period starts, and the data of subframe 1 is transferred in the WC period (T0-T2). At T1, a row selection line W (y) of a certain y row is selected, and data D (x, y) “1” of a certain x column is applied to the column data line. As a result, the value of the sample hold unit (sample hold data (x, y)) in the pixel of a certain x column y row becomes “1”. When the value of the sample hold unit is “1”, the value of the voltage line V1 is applied to the pixel electrode. When the voltage line V1 is selected, an electric field of the driving voltage Vw is applied to the liquid crystal, and the liquid crystal is displayed as white. At T7, since the value of the sample hold unit is “0”, the value of the voltage line V0 is applied to the pixel electrode. When the voltage line V0 is selected, the liquid crystal is in a blanking state in which no blanking voltage, that is, no electric field is applied, and black is displayed.

  In FIG. 12, V0 is a blanking voltage, V1 is a driving voltage, and Vcom (common voltage) is a voltage of the counter electrode 10 of the liquid crystal. V0 / V1 / Vcom is polarity-inverted and driven asynchronously with the above signal processing. The voltage value of V0 / V1 / Vcom is alternately set to GND and Vw at equal intervals. In the polarity inversion drive, the GND period and the Vw period are the same, V0 / Vcom performs the same operation, and V1 performs the operation opposite to V0 / Vcom. That is, when V0 / Vcom is GND, it is controlled to be Vw, and when V0 / Vcom is Vw, it is controlled to be GND. Also, the polarity inversion period needs to be an integral number of a data transfer period (WC period). By doing so, the integrated voltage of all the pixels becomes 0 [v], which prevents burn-in. That is, by applying the same voltage and a different voltage (+ Vw / −Vw) to the liquid crystal for the same period, the voltage applied to the liquid crystal on an average for a long time is set to + Vw + (− Vw) = 0 [v]. Preventing burn-in. In FIG. 13, a state where V1 is Vw and V0 / Vcom is GND is represented as DC balance +. A state where V1 is GND and V0 / Vcom is Vw is represented as DC balance.

  As described above, in accordance with the instruction from the drive control unit 31, the data transfer unit 30 is the first of the reflective liquid crystal display elements 6 in which a plurality of pixels are arranged in a plurality of rows and columns as shown in FIG. The subframe data having a predetermined number is transferred in a predetermined data transfer period (WC period) sequentially from the 0th line to the last m line, and subsequently the next number of the subframe. The sub-frame data is transferred line-sequentially. On the other hand, the voltage control unit 32 repeats the polarity inversion operation asynchronously with the start time of the data transfer period (WC period). That is, as shown in FIG. 6, the start time of the data transfer period (WC period) sequentially varies from the first row of the reflective liquid crystal display element 6 to the last row m, In addition to the above signal processing as shown in FIG. 6, the voltage control unit 32 performs the V0 / V1 / Vcom polarity inversion processing at the same time regardless of the pixel row. The subframe data transfer period is an integral multiple of the polarity inversion period. As is apparent from FIG. 12, in the first embodiment, the period for transferring the subframe data is three times the polarity inversion period.

  By doing so, the problem that the pixel state is in the blanking state during the data transfer period and the display luminance is lowered is solved. Further, the liquid crystal display driving that does not need to be in the blanking state during the data transfer period is realized with one sample hold unit in the pixel. Since only one sample hold unit is required in the pixel, high luminance can be realized, and since the pixel is small, the liquid crystal display element can be downsized. By downsizing the pixel, it becomes possible to form many pixel circuits with the same size element, and even when the same optical system is used, higher resolution can be achieved, which is very advantageous in terms of cost. . In addition, since the display element can be reduced in size, a smaller display device can be provided with the same resolution.

  By the way, in the first embodiment, a projection type display device provided with an active matrix type reflective liquid crystal display element 6 as a display element is described as an example. Here, characteristics when the liquid crystal is driven by the gradation drive table of FIG. 7 will be described. In FIG. 7, it is assumed that the gradation is K. Then, SF1 to SFK becomes 1 (driving state). Since 1 from SF1 to SFK is regarded as a substantially continuous ON state, the relationship between K (the number of gradations) and output light is approximately the input voltage of the reflective liquid crystal display element 6 shown in FIG. Draw a curve close to the relationship. This has an advantageous effect on the operation of the lookup table unit 21. That is, since the relationship between the input voltage of the reflective liquid crystal display element 6 and the intensity of the output light is relatively close to the gamma 2.2 curve targeted by the lookup table unit 21, the lookup table unit 21 uses the gamma 2 The burden of converting to a curve of .2 is reduced. The above characteristics are the same in the transmissive liquid crystal element.

  The first embodiment is also characterized in that step bit pulses having the same width are used without using binary bit pulses that cause a moving image pseudo contour, as shown in FIGS. The binary bit pulse performs so-called “binary weighting” in which a weight is expressed by 2n (n = 0, 1, 2, 3,...) For each subfield. On the other hand, when there are 1, 2, 4, 8, 16 binary bit pulses, step bit pulses are pulses having the same weight, such as 32, 32, 32, 32, 32, 32, 32. Compared with the case where all binary bit pulses are used, the combined use of step bit pulses has an effect of relatively reducing the moving image pseudo contour.

  Video pseudo-contour means that in a similar gradation of adjacent pixels, most of the binary bit pulses in one pixel are in the driving state, and many of the binary bit pulses in the other pixel are in the blanking state In this case, when the line of sight is moved or when the face is moved up, unintended luminance is perceived by the eyes. In the present embodiment, step bit pulses having the same width are used without using binary bit pulses that cause moving image pseudo contours. Therefore, even when the line-of-sight direction is moved, the luminance does not change remarkably, so that the moving image pseudo contour is hardly perceived.

  Next, an effect obtained by providing a frame rate control unit in a driving circuit of a liquid crystal display device using a reflective liquid crystal display element will be described. FIG. 14 is a diagram for explaining the generation mechanism of the transverse electric field in the reflective liquid crystal element. As shown in FIG. 14, the pixel electrodes 8 </ b> A and 8 </ b> B of the reflective liquid crystal element are formed on the silicon substrate 43.

  In the case of digital drive, the drive state (drive / blanking) frequently differs between adjacent pixels. For example, it is assumed that the gradation of adjacent pixels in a certain frame is “5” (pixel PA) and “6” (pixel PB), respectively. Further, consider the case where the counter electrode 10 is V0 with DC balance +. That is, since DC balance is + in FIG. 15, V0 = Vcom = 0 (V) and V1 = Vw. At the time of subframe 6, the driving state of adjacent pixels is different. As can be seen from FIG. 7, since the pixel PA is in the blanking state, a voltage of V0 is applied to the pixel electrode 8A, and since the pixel PB is in the driving state, a voltage of V1 is applied to the pixel electrode 8B.

  FIG. 16 shows the state of the electric field 41 of the liquid crystal layer when the voltage V0 is applied to the pixel electrode 8A and the voltage V1 is applied to the pixel electrode 8B. A potential difference is generated between the pixel electrode 8B (potential: Vw) and the counter electrode 10 (potential: 0 (V)) of the pixel PB, and the liquid crystal is rotated by a predetermined amount. At this time, a potential difference also occurs between the pixel electrode 8A (potential: 0 (V)) of the pixel PA and the pixel electrode 8B (potential: Vw) of the pixel PB, and an electric field is generated in the horizontal direction. Such a lateral electric field 42 causes unintentional disruption in the movement of the liquid crystal between the pixels. The above phenomenon contributed to image quality deterioration.

  By using the frame rate control, the above problem can be solved. FIG. 15 is a diagram for explaining that the horizontal electric field is evenly distributed by the frame rate control.

  FIG. 15 illustrates a case where the value of the lower F bits of the input data ((M + F) bits) to the frame rate control unit is “01”. Four tables (frames 0 to 3) are used for each frame. In each frame, when the driving state (driving or blanking) is different between adjacent pixels, the driving state is “0” (blanking state) from the pixel whose driving state is “1” (driving state). A horizontal electric field is generated in the direction of the pixel. The direction of the horizontal electric field between the pixels is represented by an arrow in FIG. In the rightmost state, the horizontal electric field states of the four frames are superimposed. That is, on the average of four frames, the horizontal electric field between all the pixels cancels out. As described above, by using the frame rate control, it is possible to cancel a lateral electric field that is a cause of image quality degradation.

  In the first embodiment, the number of bits of the input video signal data is N, the number of bits when the display device can be driven is expressed in binary, and the number of bits is diffused as an error by error diffusion processing. The case has been described where N = 8, M = 4, D = 4, and F = 2, where D is the number of bits and F is the number of bits expressed as a pseudo gradation by the frame rate control. However, the values of N, M, D, and F are not limited to the above values, and various values can be used. Among them, it is more preferable that N = 8 to 12, M = 4 to 6, D = 4 to 8, and F = 2 to 3.

1 illumination optical system, 2 light, 3 S polarized light, 4 P polarized light,
5 Polarizing beam splitter (PBS), 6 Reflective liquid crystal display element
7 pixel circuit, 8 pixel electrode, 9 liquid crystal, 10 counter electrode (transparent electrode),
11 projection lens, 12 emission light, 13 screen,
15 sample hold unit, 17 voltage selection circuit (voltage selection unit),
21 lookup table section, 22 signal conversion section,
23 error diffusion unit, 24 frame rate control unit,
25 limiter section, 26 subframe data creation section,
27 drive gradation table, 28 memory control unit, 29 frame buffer,
30 data transfer unit, 31 drive control unit, 32 voltage control unit,
33 Source driver, 34 Gate driver 41 Electric field, 42 Lateral electric field, 43 Silicon substrate

Claims (7)

A subframe data creation unit that creates subframe data in which all subframes of one frame are configured by step bit pulses based on input image data;
Subframe data of a predetermined number is transferred in a row to a liquid crystal display element in which a plurality of pixels are arranged in a plurality of rows and columns in a predetermined data transfer period. A data transfer unit for transferring the frame data in a line-sequential manner;
Either a blanking voltage or a driving voltage is selected according to the sample hold unit that holds the input 0 or 1 subframe data and the 0 or 1 subframe data held in the sample hold unit. A pixel circuit unit having a voltage selection unit to be supplied to the pixel electrode of the liquid crystal display element;
A voltage controller that repeats polarity inversion of pixels of the liquid crystal display element asynchronously with a start time of the data transfer period of the data transfer unit;
A drive device for a liquid crystal display element, comprising: A lookup table unit for converting input video signal data of bit number N into (M + F + D) bit data larger than N by performing inverse gamma correction and linear interpolation when N, M, F, and D are integers;
An error diffusion unit that converts (M + F + D) bit data processed by the lookup table unit into (M + F) bit data by error diffusion processing;
A frame rate control unit that converts (M + F) -bit data processed by the error diffusion unit into M-bit data by frame rate control;
The M bit data processed by the frame rate control unit is used, and all subframes are configured by step bit pulses. When the driving gradation is 1, the first subframe is in the driving state, and the driving gradation is 1 A subframe data creation unit that creates subframe data by a driving gradation table that increases toward the rear of a subframe that is already in a driving state, one by one, every time the subframe is in a driving state;
Subframe data of a predetermined number is transferred in a row to a liquid crystal display element in which a plurality of pixels are arranged in a plurality of rows and columns in a predetermined data transfer period. A data transfer unit for transferring the frame data in a line-sequential manner;
Either a blanking voltage or a driving voltage is selected according to the sample hold unit that holds the input 0 or 1 subframe data and the 0 or 1 subframe data held in the sample hold unit. A pixel circuit unit having a voltage selection unit to be supplied to the pixel electrode of the liquid crystal display element;
A voltage controller that repeats polarity inversion of pixels of the liquid crystal display element asynchronously with a start time of the data transfer period of the data transfer unit;
A drive device for a liquid crystal display element, comprising: In liquid crystal display devices,
3. The liquid crystal display element driving device according to claim 1, wherein a period during which the subframe data is transferred is an integral multiple of the polarity inversion period. A driving device for a liquid crystal display element according to any one of claims 1 to 3,
A liquid crystal display element driven by the driving device;
An illumination optical system for making illumination light incident on the liquid crystal display element;
A projection lens that projects the modulated light emitted from the liquid crystal display element;
A liquid crystal display device comprising: Based on the input image data, create subframe data in which all subframes of one frame are composed of step bit pulses,
Subframe data of a predetermined number is transferred in a row to a liquid crystal display element in which a plurality of pixels are arranged in a plurality of rows and columns in a predetermined data transfer period. Transfer frame data line by line,
Holds the input 0 or 1 subframe data,
According to the held 0 or 1 subframe data, one of blanking voltage or driving voltage is selected and supplied to the pixel electrode of the liquid crystal display element,
The polarity inversion of the pixels of the liquid crystal display element is repeated asynchronously with the start time of the data transfer period,
A method for driving a liquid crystal display element. When N, M, F, and D are integers, N-bit input video signal data is converted into (M + F + D) bit data larger than N by performing inverse gamma correction and linear interpolation,
The (M + F + D) bit data is converted into (M + F) bit data by error diffusion processing,
The (M + F) bit data is converted into M bit data by frame rate control,
Using the M-bit data, all sub-frames are configured by step bit pulses. When the driving gradation is 1, the first sub-frame is in the driving state, and every time the driving gradation is increased, the driving state is brought about. Subframe data is created by a driving gradation table that increases toward the back of subframes that are already driven one by one,
Subframe data of a predetermined number is transferred in a row to a liquid crystal display element in which a plurality of pixels are arranged in a plurality of rows and columns in a predetermined data transfer period. Transfer frame data line by line,
Holds the input 0 or 1 subframe data,
According to the held 0 or 1 subframe data, one of blanking voltage or driving voltage is selected and supplied to the pixel electrode of the liquid crystal display element,
The polarity inversion of the pixels of the liquid crystal display element is repeated asynchronously with the start time of the data transfer period,
A method for driving a liquid crystal display element. 7. The method of driving a liquid crystal display element according to claim 5, wherein a period for transferring the subframe data is an integral multiple of a polarity inversion period.

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