JP5350829B2 - 補強材付き配線基板の製造方法、補強材付き配線基板用の配線基板 - Google Patents
補強材付き配線基板の製造方法、補強材付き配線基板用の配線基板 Download PDFInfo
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- JP5350829B2 JP5350829B2 JP2009033313A JP2009033313A JP5350829B2 JP 5350829 B2 JP5350829 B2 JP 5350829B2 JP 2009033313 A JP2009033313 A JP 2009033313A JP 2009033313 A JP2009033313 A JP 2009033313A JP 5350829 B2 JP5350829 B2 JP 5350829B2
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Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
Description
21…半導体集積回路チップとしてのICチップ
31…補強材としてのスティフナ
35…開口部
40…配線基板
41…基板主面
42…基板裏面
43〜46…樹脂絶縁層
48…無機材料としてのガラスクロス
51…導体層
52…主面側接続端子としての端子パッド
57…ビア導体
Claims (7)
- 基板主面及び基板裏面を有し、コア基板を含まずに複数の樹脂絶縁層及び複数の導体層を積層してなる構造を有し、半導体集積回路チップを接続可能な複数の主面側接続端子が前記基板主面上に配設された配線基板と、
前記基板主面側にのみ接合され、前記複数の主面側接続端子を露出させる開口部が貫通形成された補強材と
を備える補強材付き配線基板の製造方法であって、
前記複数の樹脂絶縁層のうち層数が最も多いものの熱膨張係数が前記補強材の熱膨張係数よりも大きい場合には前記基板主面側が凹となる反りを有する配線基板を作製し、前記複数の樹脂絶縁層のうち層数が最も多いものの熱膨張係数が前記補強材の熱膨張係数よりも小さい場合には前記基板裏面側が凹となる反りを有する配線基板を作製する配線基板作製工程と、
反りを有する前記配線基板の前記基板主面に前記補強材を接着する接着工程と
を含むことを特徴とする補強材付き配線基板の製造方法。 - 前記接合工程前における前記配線基板の前記反りの大きさが100μm以上500μm以下であり、前記接合工程後における前記配線基板の前記反りの大きさが0μm以上50μm以下であることを特徴とする請求項1に記載の補強材付き配線基板の製造方法。
- 前記複数の樹脂絶縁層には複数のビア導体が形成され、前記複数のビア導体は前記複数の樹脂絶縁層の各層において同一方向に拡径していることを特徴とする請求項1または2に記載の補強材付き配線基板の製造方法。
- 前記配線基板作製工程において、前記複数の樹脂絶縁層のうち他のものと比べて相対的に熱膨張係数の小さい材料からなる少なくとも1つの樹脂絶縁層を前記基板裏面となる側に配置して積層を行うことで、前記基板主面側が凹となる反りを有する配線基板を作製することを特徴とする請求項1乃至3のいずれか1項に記載の補強材付き配線基板の製造方法。
- 前記配線基板作製工程において、前記複数の樹脂絶縁層のうち他のものと比べて相対的に熱膨張係数の小さい材料からなる少なくとも1つの樹脂絶縁層を前記基板主面となる側に配置して積層を行うことで、前記基板裏面側が凹となる反りを有する配線基板を作製することを特徴とする請求項1乃至3のいずれか1項に記載の補強材付き配線基板の製造方法。
- 前記複数の樹脂絶縁層のうち他のものと比べて相対的に熱膨張係数の小さい材料からなる少なくとも1つの樹脂絶縁層は、樹脂材料中に無機材料を含有させた複合材料からなることを特徴とする請求項4または5に記載の補強材付き配線基板の製造方法。
- 基板主面及び基板裏面を有し、コア基板を含まずに複数の樹脂絶縁層及び複数の導体層を積層してなる構造を有し、半導体集積回路チップを接続可能な複数の主面側接続端子が前記基板主面上に配設され、前記複数の主面側接続端子を露出させる開口部が貫通形成された補強材が接合されるべき配線基板であって、100μm以上500μm以下の大きさの反りを有し、前記複数の樹脂絶縁層には複数のビア導体が形成され、前記複数のビア導体は前記複数の樹脂絶縁層の各層において同一方向に拡径しており、前記複数の樹脂絶縁層のうち他のものと比べて相対的に熱膨張係数の小さい材料からなる樹脂絶縁層を少なくとも1つ有することを特徴とする補強材付き配線基板用の配線基板。
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JP2012069739A (ja) * | 2010-09-24 | 2012-04-05 | Shinko Electric Ind Co Ltd | 配線基板の製造方法 |
KR102380304B1 (ko) * | 2015-01-23 | 2022-03-30 | 삼성전기주식회사 | 전자부품 내장 기판 및 그 제조방법 |
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JP2003258153A (ja) * | 2002-03-05 | 2003-09-12 | Nec Corp | 半導体パッケージの実装構造 |
JP2005340355A (ja) * | 2004-05-25 | 2005-12-08 | Ngk Spark Plug Co Ltd | 配線基板 |
JP5211570B2 (ja) * | 2007-04-24 | 2013-06-12 | 日立化成株式会社 | 半導体装置用ビルドアップ配線板 |
JP5018251B2 (ja) * | 2007-06-04 | 2012-09-05 | 株式会社デンソー | 回路基板の製造方法および回路基板の製造装置 |
JP2009252916A (ja) * | 2008-04-04 | 2009-10-29 | Nec Electronics Corp | 多層配線基板、半導体パッケージ、および半導体パッケージの製造方法 |
JP5120304B2 (ja) * | 2008-09-30 | 2013-01-16 | 凸版印刷株式会社 | スティフナー付きプリント配線板および放熱板付き半導体パッケージの製造方法 |
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