JP5292839B2 - Active matrix liquid crystal display device. - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an active matrix type liquid crystal display device capable of performing display on which crosstalk in a direction along a data line is hard to view even in frame-reversal drive while reducing loads for operation. <P>SOLUTION: A scanning period St for performing the scanning of gate lines and a non-scanning period Nt for stopping the scanning of the gate lines are set for each frame, and an amplitude shape of a series of display signal voltages supplied to data lines in the non-scanning period Nt is set to shape reversed to an amplitude shape of a series of display signal voltages supplied to the data lines in the scanning period St. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

  The present invention relates to an active matrix liquid crystal display device.

  As a dot matrix type display panel used in a liquid crystal display device, a simple matrix type display panel and an active matrix type display panel are known. Among them, an active matrix display panel is arranged on a display panel so that a plurality of gate lines and a plurality of data lines are orthogonal to each other, and a thin film transistor (Thin Film) is provided in the vicinity of the intersection of the gate lines and the data lines. A pixel electrode is disposed through a transistor (hereinafter referred to as TFT). In addition, a common electrode is disposed so as to face the pixel electrode, and a liquid crystal is filled between the pixel electrode and the common electrode to constitute a display pixel. Then, the display signal voltage is applied from the data line to the display pixel selected by the scanning signal voltage input through the gate line. A common signal voltage is applied to the common electrode. At this time, a voltage corresponding to the difference between the display signal voltage and the common signal voltage is applied to the liquid crystal composing the display pixel, thereby changing the alignment state of the liquid crystal for display.

  Here, AC driving is essential for driving the liquid crystal for reasons such as extending the life. As this AC drive method, for example, a frame inversion drive is known in which the polarity of the voltage Vlcd applied to the liquid crystal is inverted for each frame as shown in FIG.

  In the active matrix display panel, even when the gate line corresponding to the display pixel is not selected, the display signal voltage on the data line corresponding to the display pixel is required for the display pixel corresponding to the other gate line. It fluctuates according to the display signal voltage. In the case of frame inversion drive, when the display signal voltage fluctuates in this way, the potential change of the display pixel due to the influence of capacitive coupling (Cds) generated between the pixel electrode of the display pixel and the corresponding data line. However, there is a problem that the display quality deteriorates because it appears on the display as crosstalk in the direction along the data line.

  For example, in the normally black mode in which white is displayed when voltage is applied and black is displayed when no voltage is applied, scanning of the gate line in the frame starts from the top of the screen (from scanning at the bottom of the screen to the top of the screen). In the case of sequentially selecting gate lines from the gate line at the top of the screen toward the gate line at the bottom of the screen, as shown in FIG. When the black window 201 is to be displayed on the background area 200 of gray display (display at an intermediate gradation level), as shown in FIG. 20B, the gate line corresponding to the black window 201 is being scanned. In addition, in the background area 200 a on the upper side of the black window 201, vertical crosstalk that is closer to black than the original intermediate gradation occurs, and the black window 201. In the lower part of the background region 200a, vertical crosstalk occurs which becomes white closer than the original halftone. For this reason, as shown in FIG. 21A, when information is displayed at the top of the screen, black vertical stripes are visually recognized on the entire screen, and as shown in FIG. When information is displayed at the bottom of the screen, white vertical stripes are visually recognized on the entire screen.

  Therefore, in Patent Document 1, the occurrence of crosstalk is reduced by correcting the image data in the frame based on the image data between the frames. That is, the value of the image data of the Lth row is subtracted from the image data of each row driven with the same polarity as the Lth row until the Lth row is selected after the selection of the Lth row. After that, the sum (A) of the image data of each row driven with the same polarity as the Lth row is obtained. Further, the value of the image data of the Lth row is subtracted from the image data of each row driven with a polarity different from that of the Lth row until the Lth row is selected after the selection of the Lth row. Then, the sum (B) of the image data of each row driven with a polarity different from that of the Lth row is obtained. Then, the image data of the Lth row is corrected using A and B and displayed.

JP-A-2005-77508

  However, in the conventional technology as described above, the calculation formula for correcting the image data is different for each row, so that the calculation for correcting the image data becomes complicated and the calculation amount becomes enormous, and the calculation in the control unit The problem was that the load for the project would increase.

  The present invention has been made in view of the above circumstances, and can reduce the load for computation and can perform display in which crosstalk in the direction along the data line is difficult to be visually recognized in frame inversion driving. An object is to provide a matrix type liquid crystal display device.

In order to achieve the above object, an active matrix type liquid crystal display device according to claim 1 is provided with a plurality of gate lines arranged in one direction and in other directions intersecting with the gate lines. and set data lines, a display screen having a plurality of display pixels arranged at intersections near to the respective gate lines and the data lines, as well as scanning the gate lines, the data in normally black type active matrix liquid crystal display device for supplying a display signal voltage to each of the display pixels corresponding to the respective gate lines through the line, each pixel is connected to the data line through a switching element And a common electrode opposite to the pixel electrode, and each frame has a first subframe in the second half having a time of equal length. The frame is divided into a frame period and a first subframe period of the first half, and scanning of each gate line is performed from the top to the bottom of the display screen in the first subframe period, and the second subframe a gate line driving means said stop scanning of the gate lines in a period, and a data line driving means for performing the frame inversion driving by supplying the display signal voltage to the data lines in the first sub-frame period, the data first complementary voltage line driving means comprises an amplitude shape obtained by reversing the amplitude shape of a series of the display signal voltage supplied to said first sub-frame period, or the data line drive means the second pair a second complementary voltage having an amplitude shape to match the amplitude shape of a series of the display signal voltage supplied to the sub-frame periods to the data lines And complementary voltage value deriving means for deriving by, generates a common signal voltage signal level changes alternately every frame period and a common voltage generating means for supplying to said common electrode, said complementary voltage value deriving means Displays information between the upper part of the display screen and the area corresponding to the first gate line, and the area scanned by the gate line driving means after the first gate line is set to a certain intermediate gradation. The first complementary voltage value is derived, the data line driving unit supplies the first complementary voltage value to the data line during the second subframe period, and the complementary voltage value deriving unit includes: Information is displayed from the lower part of the display screen to the area corresponding to the second gate line, and the area scanned by the gate line driving means before the second gate line is set to a certain intermediate floor. When the derives the second complementary voltage value, the data line driving means and supplying to said data lines said second complementary voltage value to the sub-frame period of the two.

The active matrix liquid crystal display device according to claim 2 is the active matrix liquid crystal display device according to claim 1, wherein the complementary voltage value deriving means is supplied during the second subframe period. wherein as a value obtained by adding the first complementary voltage value to the display signal voltage is a voltage value corresponding to the maximum gray level of the display signal voltage that, and characterized in that deriving the first complementary voltage value To do.

Further, the active matrix type liquid crystal display device according to claim 3 , wherein a plurality of gate lines arranged in one direction, a data line arranged in another direction intersecting each gate line, wherein a display screen having a plurality of display pixels arranged at intersections near the respective gate lines and the data lines, wherein while scanning each of the gate lines, wherein via the data line gate lines wherein the normally black type active matrix liquid crystal display device for supplying a display signal voltage to each display pixel, wherein each pixel includes a pixel electrode connected to the data line through a switching element, the pixel corresponding to A first sub-frame period in the first half and a second second in the second half , each of which has an equal length of time. The gate lines are divided into sub-frame periods, the gate lines are scanned from the top to the bottom of the display screen in the first sub-frame period, and the gate lines are scanned in the second sub-frame period. a gate line driving means to stop, and the data line driving means for performing the frame inversion driving by supplying the said display signal voltage to the data lines in the first sub-frame period, the data line drive means the first the amplitude shape of a series of the display signal voltage supplied to the sub-frame period, the first complementary voltage value having inverted amplitude shape, or a series and supplies the data line drive means to said first sub-frame period It said complementary display voltage value deriving hand a second complementary voltage value derived in correspondence to the data line having the corresponding amplitude shape and transition of the signal voltage When a common voltage generating means for supplying to said common electrode and generates a common signal voltage switched signal level for each timing of the first subframe period and the second sub-frame period is changed alternately The complementary voltage value deriving unit displays information from the upper part of the display screen to a region corresponding to the first gate line, and is scanned by the gate line driving unit after the first gate line. when the area to be in constant intermediate tone, and derives the second complementary voltage value, the data line driving means the supply to the data line the second complementary voltage value to the second sub-frame period The complementary voltage value deriving means displays information between a lower area of the display screen and a region corresponding to the second gate line, and the gate line driver is connected before the second gate line. The first complementary voltage value is derived when the scanned area is set to a certain intermediate gray level, and the data line driving means supplies the first complementary voltage value to the data line in the second subframe period. It is characterized by supplying .

The active matrix liquid crystal display device according to claim 4 is the active matrix liquid crystal display device according to claim 3 , wherein the complementary voltage value deriving means supplies the data line to the data line during the first subframe period. so that the value obtained by adding the first supplemental voltage to the display signal voltage to be supplied a voltage value corresponding to the maximum gray level of the display signal voltage, deriving the first supplemental voltage It is characterized by.

  According to the present invention, it is possible to perform display in which crosstalk in the direction along the data line is difficult to be visually recognized in frame inversion driving while reducing the load for calculation.

(First embodiment)
Hereinafter, a first embodiment in which the active matrix liquid crystal display device of the present invention is applied to a digital camera will be described. As shown in FIGS. 1A and 1B, the external configuration of the digital camera 1 includes a photographing lens 2, a self-timer lamp 3, an optical viewfinder window 4, a microphone section on the front surface of a substantially rectangular thin plate-like body. 5, a strobe light emitting unit 6, a rubber grip 7, and the like are disposed, and a power key 8 for power on / off operation, a shutter key 9 for determining shooting timing, and the like are disposed on the upper surface. .

  On the back of the digital camera 1, a mode switch (SW) 10, a speaker unit 11, a menu key 12, a cross key 13, a set key 14, an optical finder 15, a strobe charge lamp 16, and a display unit 17 are arranged. Yes. The mode switch 10 is constituted by a slide key switch, for example, and switches between a recording mode “R” and a reproduction mode “P” which are basic modes. The menu key 12 is operated when selecting various menu items. The cross key 13 is integrally formed with keys for moving the cursor in the up, down, left, and right directions, and is operated when moving menu items and the like displayed on the display unit 17. The set key 14 is disposed at the center position of the cross key 13 and is operated to set the contents of the menu item selected at that time. The strobe charge lamp 16 is an LED lamp disposed in the vicinity of the optical viewfinder 15, which is either when the user of the digital camera 1 is looking into the optical viewfinder 15 or looking at the display unit 17. However, it is possible for the user to visually recognize the charge state of the strobe.

  The display unit 17 is composed of an active matrix type liquid crystal display device, and displays a through image on the monitor as an electronic viewfinder in the recording mode, and reproduces and displays the selected image and the like in the reproduction mode. Further, the display unit 17 does not perform any key operation when a predetermined menu is selected by operating the menu key 12, the cross key 13, the set key 14, or the like, or for a predetermined time or more. In the case of shifting to the standby mode, for example, a predetermined information display screen as shown in FIGS. 2A and 2B is displayed. That is, a raster screen on which the remaining recording capacity of the recording medium, the remaining battery capacity, and the like are displayed on a part of the screen is displayed. Here, the gradation level of the display pixel corresponding to the information is the maximum gradation level (the voltage applied to the liquid crystal is the maximum voltage), and the gradation level of the display pixel corresponding to the background is the intermediate gradation level. It shall be. Further, the information display location 250 such as the remaining capacity of the recording medium is configured so that the display can be changed to the upper part of the screen or the lower part of the screen by selecting a menu separately.

  Hereinafter, an active matrix liquid crystal display device as the display unit 17 will be described in detail. As shown in FIG. 3, the display unit 17 includes a display panel 110 on which an image is manifested and displayed, a scanning driver 120 for scanning a gate line of the display panel 110, and a display signal on a data line of the display panel 110. A signal driver 130 for supplying a voltage, a common voltage generating circuit 140 for applying a predetermined voltage to the common electrode of the display panel 110, a scanning driver 120 or the like so that a desired image is displayed on the display panel 110. The signal driver 130 includes a control unit 150 that controls the drive of the voltage generation circuit 140, and a power supply adjustment circuit 160 that adjusts the supplied power to a voltage necessary for driving and supplies the voltage to each unit. Then, an area corresponding to the general display panel 110 is mounted on the digital camera 1 so as to be visible from the outside of the digital camera 1, and an image is displayed on the display panel 110.

  The display panel 110 has a configuration in which liquid crystal is sandwiched between two substrates 116 and 117 which are arranged opposite to each other and bonded by a sealant 115. A plurality of gate lines (for example, n gate lines) extended in the row direction and a plurality of data lines (for example, m data lines) extended in the column direction on one substrate 116. The display pixel shown in FIG. 4 is provided in the vicinity of each intersection of the gate line and the data line. Here, FIG. 4 is a diagram showing an equivalent circuit corresponding to one display pixel among a plurality of display pixels provided in the display panel 110.

  A gate electrode of the thin film transistor (TFT) 111 is connected to the gate line G (j) shown in FIG. 4, and a source electrode of the TFT 111 is connected to the data line S (i). Further, a pixel electrode is connected to the drain electrode of the TFT 111. A common electrode 118 is disposed on the other substrate 117 so as to face the pixel electrode, and liquid crystal is filled between the pixel electrode and the common electrode 118. Further, a storage capacitor Ccs is connected in parallel with the liquid crystal capacitor Clcd configured as described above. In such a configuration, when a voltage is applied between the pixel electrode and the common electrode, the alignment state of the liquid crystal filled between the pixel electrode and the common electrode changes according to the voltage, and the liquid crystal layer The transmittance of light at is changed. As a result, the transmission state of light from a light source (backlight) (not shown) arranged on the back surface of the display pixel shown in FIG. 4 is changed to display an image. FIG. 4 also shows the parasitic capacitance Cds generated between the pixel electrode and the data line. Here, i = 1, 2, 3,..., M. j = 1, 2, 3,..., n.

  The gate line G (j) of FIG. 4 is connected to the scan driver 120, and scanning of the gate line G (j) in each frame is started based on the vertical control signal Vs output from the control unit 150, and the control is performed. Each gate line G (j) is individually selected based on the horizontal control signal Hs output from the unit 150.

  Hereinafter, in order to simplify the description, the number n of gate lines is specifically described as eight, but the number is not limited to this number. As shown in FIG. 5 or FIG. 6, when the vertical control signal Vs output from the control unit 150 is input, the scan driver 120 starts scanning the gate line G (j) in the frame. Note that at this time, the scanning driver 120 sets the gate line G (j) in the frame on the condition that the scanning allowable signal As output from the control unit 150 is high and the scanning prohibition signal Ps is low. Start scanning. That is, when the vertical control signal Vs is input, when the scanning allowance signal As is different from the high level, or when the scanning inhibition signal Ps is different from the low level, the scanning allowance signal As is at the high level. The scanning of the gate line G (j) in the frame is started after waiting for the scanning inhibition signal Ps to become low level (for example, timing T2a with respect to timing T1a and timing T4a with respect to timing T3a).

  While the scanning allowance signal As is at the high level and the scanning inhibition signal Ps is at the low level, the selection of the gate line such that the scanning signal is switched from the low level to the high level for a predetermined period of time is horizontally controlled. In synchronization with the signal Hs, the operation is sequentially performed for each gate line G (j) from the preceding gate line G (1) to the succeeding gate line G (8). As a result, the TFTs 111 corresponding to the respective gate lines G (j) are sequentially turned on for a predetermined period, and at this time, the display signal voltage supplied to the data lines S (i) corresponding to the respective display pixels is displayed on the display pixels. To the pixel electrode. Note that the gate line G (1) side corresponds to the upper side of the display screen, and the gate line G (8) side corresponds to the lower side of the display screen.

  The data line S (i) in FIG. 4 is connected to the signal driver 130, and R (red), G (green), B (blue), and the like are based on the horizontal control signal Hs output from the control unit 150. The input gradation signal Ksh of each color component is captured in display pixel units (gate line units) for one row, the display signal voltage Ds corresponding to the captured input gradation signal Ksh is generated, and each corresponding data line S ( i). Further, the signal level of the display signal voltage Ds is inverted around a predetermined center voltage in accordance with the polarity inversion control signal Pol input from the control unit 150 at the start of the frame.

  The common voltage generation circuit 140 selects either one of the common signal voltages VcomH and VcomL adjusted by the power supply adjustment circuit 160 according to the polarity inversion control signal Pol input from the control unit 150, and the common voltage generation circuit 140 uses the common signal as a rectangular wave. The signal Vc is supplied to the common electrode of the display pixel. That is, the common voltage generation circuit 140 switches the voltage value of the common signal Vc at the start timing of the frame.

  When the video signal VD including the gradation signal Kso is input, the control unit 150 generates various control signals as described above so that an image based on the gradation signal Kso is displayed on the display panel. The signal generation unit 151 that generates various control signals as described above, and the video memory 152 that can store the input gradation signal Kso corresponding to at least one screen of display pixels. And a calculation unit 153 that calculates and derives a predetermined complementary voltage value based on the gradation signal Kso for one screen stored in the video memory 152.

  As shown in FIG. 5 or FIG. 7, the signal generation unit 151 defines a frame that is a period for the scan driver 120, the signal driver 130, and the common voltage generation circuit 140 to display an image for one screen in synchronization. At the same time, a vertical synchronizing signal Vs and a polarity inversion control signal Pol for starting the frame are generated and output. In addition, the signal generation unit 151 includes a horizontal synchronization signal Hs for writing the display signal voltage Ds for each display pixel corresponding to each gate line G (j) in synchronization with the scanning driver 120 and the signal driver 130, and a scanning allowable signal As. The scan inhibition signal Ps is also generated and output.

  Note that the signal generation unit 151 performs scanning of each gate line G (j) in each frame and outputs the display signal voltage Ds to each display pixel in response to the output of the scanning allowance signal As and the scanning prohibition signal Ps. And a non-scanning period Nt as a second subframe in which scanning of each gate line G (j) is prohibited and the display signal voltage Ds is prohibited from being written to each display pixel. The scanning driver 120 and the signal driver 130 are controlled so that the time division is performed and the scanning period St and the non-scanning period Nt are equal in length. At this time, in each frame, the output timing of each control signal is set so that the non-scanning period Nt is obtained prior to the scanning period St.

  That is, for example, when one frame in the input video signal VD is 16 ms, the scanning is allowed so that the first 8 ms of the frame is the non-scanning period Nt and the next 8 ms is the scanning period St. The signal As and the scan inhibition signal Ps are generated and output.

  Further, the signal generation unit 151 generates and outputs a horizontal control signal Hs so that the display signal voltage Ds can be written to the display pixels for one screen during the 8 ms. That is, if the number n of gate lines is 8, the horizontal control signal Hs is generated so that the on period and the off period of the TFT corresponding to each gate line G (j) are sequentially shifted by 1 ms. Output. The horizontal control signal Hs is continuously output regardless of the scanning period St and the non-scanning period Nt.

  Here, in the scanning period St, the control unit 150 synchronizes with the horizontal control signal Hs, and uses the gradation signal Kso corresponding to the display pixels for one screen stored in the video memory 152 as the display gradation signal Ksh. The grayscale signals corresponding to the preceding gate line G (j) are output to the signal driver 130 in units of display pixels (gate line units) for one row in order. On the other hand, in the non-scanning period Nt set prior to the scanning period St in the frame, the calculation unit 53 performs the calculation based on the gradation signal Kso corresponding to the display pixels for one screen stored in the video memory 152. As will be described in detail later, an input gradation signal Ksh corresponding to a complementary voltage value derived as described later is output to the signal driver 130 in units of display pixels (gate lines) for one row in synchronization with the horizontal control signal Hs. Then, the input gradation signal Ksh output from the control unit 150 is taken in by the signal driver 130, converted into the display signal voltage Ds corresponding to the input gradation signal Ksh, and the corresponding data line S (i). Supplied.

The calculation unit 153 derives a complementary voltage value Ds (i, j, Nt) as a display signal voltage supplied to each data line S (i) by the signal driver 130 in the non-scanning period Nt. When displaying information on the raster screen as shown in 2 ( b ) above the center of the screen, the signal driver 130 supplies the data line S (i) in the scanning period St. The amplitude shape of the transition of the display signal voltage Ds (i, j, St) and the series of display signal voltages Ds (i, j) that the signal driver 130 supplies to the data line S (i) during the non-scanning period Nt. , Nt), the display signal voltage Ds (i, j, Nt) as a complementary voltage value is derived so as to match the amplitude shape of the transition. Further, for example, FIG. 2 in such than the center of the screen on the raster screen as shown in (a) displaying the information at the bottom, and supplies the signal driver 130 to the data line S (i) in the scanning period St A series of display signals that the signal driver 130 supplies to the data line S (i) in the non-scan period Nt with respect to the amplitude shape of the transition of the series of display signal voltages Ds (i, j, St). The display signal voltage Ds (i, j, Nt) as a complementary voltage value is derived so that the amplitude shape of the transition of the voltage Ds (i, j, Nt) is reversed.

  Hereinafter, first, the derivation of the complementary voltage value in the case where information is displayed below the center of the screen on the raster screen as shown in FIG. 2B will be described in detail. Next, FIG. The derivation of the complementary voltage value in the case where information is displayed above the center of the screen on the raster screen as shown will be described in detail.

  It should be noted that determination of display contents performed prior to the derivation of the complementary voltage value by the calculation unit 153, that is, whether information is displayed above the center of the screen on a raster screen as shown in FIG. 2A, for example. Alternatively, for example, on the raster screen as shown in FIG. 2B, whether the information is displayed below the center of the screen is determined by analyzing the video signal using the various image analysis techniques. A display video determination unit that directly determines the display content may be provided, and the display video determination unit may implement the menu content of the digital camera 1 selected by the user or set by the digital camera. In the case where the display content is set in advance corresponding to the function, a display video determination unit that determines the display content based on the set menu content or function is provided, May be configured to the display image determination unit is performed.

  Further, here, the display signal voltage corresponding to the maximum gradation level is set in advance to −x [V] corresponding to the common signal voltage VcomH, and x [V] corresponding to the common signal voltage VcomL in advance. It is assumed that it is set to.

  Hereinafter, a case where information is displayed below the center of the screen on the raster screen as shown in FIG. 2B will be described based on the following specific example. That is, a series of display signal voltages DS (i, j, St) to be supplied to the data line S (i) in the scanning period St in the frame is changed to a common signal voltage VcomL as shown in FIG. Correspondingly, x [V] is set during the high level period in the scanning signals of the gate lines G (7) and G (8), and the gate lines G (1), G (2), G (3), G (4 ), G (5), G (6), x / 2 [V] during the high level period of the scanning signal, and gate lines G (7), G (8) corresponding to the common signal voltage VcomH. -X [V] during the high level period of the scanning signal of, and scanning signals of the gate lines G (1), G (2), G (3), G (4), G (5), G (6) In the high level period in FIG.

  In this case, the arithmetic unit 153, as shown in FIGS. 5, 6A, and 6B, displays the display signal voltage Ds (i, i) supplied to the data line S (i) in the non-scanning period Nt. j, Nt) corresponds to the common signal voltage VcomL, and when the start timing T1a of the non-scanning period Nt is temporarily matched with the start timing T2a of the scanning period St, the gate lines G (7), G (8) The gate lines G (1), G (2), G (3), G (4), G (5), and G (6) are set to x [V] during the high level period of the scanning signal. The complementary voltage value is derived so as to be x / 2 [V] during the high level period of the scanning signal, and the start timing T3a of the non-scanning period Nt is set to the start timing of the scanning period St in correspondence with the common signal voltage VcomH. Temporarily matched with T4a In addition, the gate lines G (1), G (2), G (3), G (3), G (7), G (8) are set to −x [V] during the high level period in the scanning signals of the gate lines G (7), G (8). The complementary voltage value is derived so as to be −x / 2 [V] during the high level period in the scanning signals of G (4), G (5), and G (6).

  That is, the arithmetic unit 153 derives a complementary voltage value as the display signal voltage Ds (i, j, Nt) supplied to the data line S (i) in the non-scanning period Nt based on (Equation 1). Thus, the complementary voltage value is set so that the transition of the display signal voltage Ds (i, j, St) in the scanning period St matches the transition of the display signal voltage Ds (i, j, Nt) in the non-scanning period Nt. To derive.

(Equation 1)
Ds (i, j, Nt) = Ds (i, j, St)

  Note that the relationship between the gradation signal Kso or the input gradation signal Ksh as the gradation level and the display signal voltage is such that, for example, a lookup table as shown in FIG. 9A and FIG. It is assumed that it is stored in advance and can be appropriately converted by the control unit 150.

  Next, the case where information is displayed above the center of the screen on the raster screen as shown in FIG. 2A will be described based on the following specific example. In other words, a series of display signal voltages to be supplied to the data line S (i) in the scanning period St in the frame corresponds to the common signal voltage VcomL as shown in FIG. 1) and x (V) during the high level period of the scanning signal of G (2), and the gate lines G (3), G (4), G (5), G (6), G (7), G During the high level period of the scanning signal of (8), x / 2 [V] is set, and in correspondence with the common signal voltage VcomH, during the high level period of the scanning signal of the gate lines G (1) and G (2). In this case, −x [V] is set, and −x during the high level period of the scanning signals of the gate lines G (3), G (4), G (5), G (6), G (7), G (8). This will be described as / 2 [V].

  In this case, as shown in FIGS. 7, 8A, and 8B, the arithmetic unit 153 determines that the display signal voltage supplied to the data line S (i) in the non-scanning period Nt is a common signal. Corresponding to the voltage VcomL, when the start timing T1b of the non-scan period Nt is temporarily matched with the start timing T2b of the scan period St, during the high level period in the scan signals of the gate lines G (1) and G (2) In the high level period of the scanning signals of the gate lines G (3), G (4), G (5), G (6), G (7), G (8) so as to be 0 [V]. When the complementary voltage value is derived so as to be x / 2 [V] and the start timing T3b of the non-scanning period Nt is temporarily matched with the start timing T4b of the scanning period St in correspondence with the common signal voltage VcomH. The gate line The gate lines G (3), G (4), G (5), G (6), G () are set so as to be 0 [V] during the high level period of the scanning signals (1) and G (2). 7) The complementary voltage value is derived so as to be −x / 2 [V] during the high level period in the scanning signal of G (8).

  That is, the arithmetic unit 153 derives a complementary voltage value as the display signal voltage Ds (i, j, Nt) supplied to the data line S (i) in the non-scanning period Nt based on (Equation 2). Thus, the start timings of the transition of the display signal voltage Ds (i, j, St) in the scanning period St and the transition of the display signal voltage Ds (i, j, Nt) in the non-scanning period Nt preceding thereto coincide with each other. When each of them is added, a complementary voltage value that is leveled with the display signal voltage x [V] or −x [V] corresponding to the maximum gradation level is derived.

(Equation 2)
Pol: Low level Ds (i, j, Nt) = x−Ds (i, j, St)
Pol: at high level Ds (i, j, Nt) = − x + Ds (i, j, St)

  As described above, when the complementary voltage value based on the video signal to be displayed is derived by the calculation unit 153, the control unit 150 horizontally outputs each input gradation signal Ksh corresponding to the derived complementary voltage value. In synchronization with the control signal Hs, the signal is output to the signal driver 130 in display pixel units (gate line units) for one row in the non-scanning period Nt.

  The signal driver 130 can supply the display signal voltage Ds as shown in FIGS. 5 and 7 to the data line S (i) by the control of the control unit 150 as described above.

  That is, in the first embodiment, for each frame, a scanning period St for executing scanning of each gate line G (j) and a non-scanning period Nt for stopping scanning of each gate line G (j) are set. . When information is displayed below the center of the screen on the raster screen as shown in FIG. 2B, a series of display signal voltages supplied to the data line S (i) during the scanning period St. Display on the data line S (i) in the non-scanning period Nt so that the amplitude shape of a series of display signal voltages supplied to the data line S (i) in the non-scanning period Nt is equal to the amplitude shape of The signal voltage is supplied. Further, when information is displayed on the raster screen as shown in FIG. 2A above the center of the screen, a series of display signal voltages supplied to the data line S (i) in the scanning period St. To the data line S (i) in the non-scanning period Nt so that the amplitude shape of a series of display signal voltages supplied to the data line S (i) in the non-scanning period Nt is inverted. The display signal voltage is supplied.

  10 and 11 show time-series changes in the voltage Vlcd applied to the liquid crystal layer corresponding to each display pixel when the display unit 17 is driven and controlled as described above. In order to simplify the description, the fluctuation of Vlcd accompanying the polarity inversion of the voltage supplied to the data line S (i), and between the gate line G (j) and the pixel electrode P (i, j). The fluctuation of Vlcd due to the parasitic capacitance generated in FIG. Also, Vlcd is normalized based on the potential of the counter electrode.

10 corresponds to the case where information is displayed below the center of the screen on the raster screen as shown in FIG. 2B, as shown in FIG. 5, the display signal voltage Ds ( i, j, St) when the display signal voltage is supplied to the data line S (i) so that the transition of the display signal voltage Ds (i, j, Nt) in the non-scanning period Nt that precedes the transition It is a time series change of Vlcd. Here, the time series change of Vlcd corresponding to the pixel electrode P (i, 1) connected to the second-stage gate line G (2) from the previous stage side is shown as an example, but each gate line G (1 ), G (3), G (4), G (5), G (6) respectively connected to the pixel electrodes P (i, 1), P (i, 3), P (i, 4), The same applies to Vlcd corresponding to P (i, 5) and P (i, 6).

  As shown in FIG. 10, in each frame, the fluctuation of Vlcd that occurs as the voltage supplied to the data line S (i) fluctuates from the voltage written in the display pixel is expressed as a non-scanning period Nt. It is possible to cancel out with the scanning period St. That is, the fluctuation “+ ΔV” of Vlcd that occurs in the scanning period St can be offset by the fluctuation “−ΔV” of Vlcd that occurs in the non-scanning period Nt. Therefore, for example, in a normally black mode in which white is displayed when a voltage is applied and black is displayed when no voltage is applied, a relatively black vertical streak displayed on the entire screen as shown in FIG. And the relatively white vertical streak displayed on the entire screen as shown in FIG. 12B in the non-scanning period Nt preceding it, the display luminance is temporally averaged, and the vertical streak is less visible. Is possible. That is, crosstalk in the direction along the data line S (i) as a vertical stripe can be made difficult to be visually recognized.

  On the other hand, FIG. 11 shows the display signal voltage in the scanning period St as shown in FIG. 6 in correspondence with the case where information is displayed above the center of the screen on the raster screen as shown in FIG. When the transition of Ds (i, j, St) and the transition of the display signal voltage Ds (i, j, Nt) in the non-scanning period Nt preceding the transition are added so that their start timings coincide with each other, This is a time-series change in Vlcd when the display signal voltage is supplied to the data line S (i) so as to be leveled at the display signal voltage x [V] or −x [V] corresponding to the maximum gradation level. Here, the time series change of Vlcd corresponding to the pixel electrode P (i, 7) connected to the gate line G (7) of the second stage from the rear stage side (the seventh stage from the front stage side) is shown as an example. Are pixel electrodes P (i, 3), P (i, 4) connected to the gate lines G (3), G (4), G (5), G (6), G (8), respectively. , P (i, 5), P (i, 6), and Vlcd corresponding to P (i, 8) are the same.

  As shown in FIG. 11, even in this case, in each frame, the fluctuation of Vlcd that occurs as the voltage supplied to the data line S (i) fluctuates from the voltage written to the display pixel. It is possible to cancel out between the non-scanning period Nt and the scanning period St. That is, the fluctuation “−ΔV” of Vlcd occurring in the scanning period St is canceled by the fluctuation “+ ΔV” of Vlcd occurring in the non-scanning period Nt. Therefore, for example, in a normally black mode in which white is displayed when a voltage is applied and black is displayed when no voltage is applied, a relatively white vertical streak displayed on the entire screen as shown in FIG. 13A in the scanning period St. And the relatively black vertical streaks displayed on the entire screen as shown in FIG. 13B in the non-scanning period Nt preceding that, the display luminance is temporally averaged and the vertical streaks are not easily seen. Is possible. That is, crosstalk in the direction along the data line S (i) as a vertical stripe can be made difficult to be visually recognized.

  Since the display signal voltage to be added may be derived by a simple arithmetic expression as shown in (Equation 1) or (Equation 2), data is reduced in the frame inversion drive while reducing the load for the operation. A display in which crosstalk in the direction along the line is difficult to be visually recognized can be performed.

(Second embodiment)
In the first embodiment described above, the case where the non-scan period Nt corresponding to the frame is set prior to the scan period St of the frame has been described. However, the non-scan corresponding to the scan period St of the frame will be described below. A second embodiment in which the period Nt is set after the scanning period St of the frame will be described. In addition, the same code | symbol as 1st embodiment is attached | subjected to the component same as 1st embodiment, and the description is abbreviate | omitted.

  In the second embodiment, as shown in FIGS. 14, 15, and 16, the control unit 150 causes the signal generation unit 151 to precede the polarity inversion signal Pol by ½ frame (one subframe). A polarity inversion signal Pola is generated, and this polarity inversion signal Pola is output to the common voltage generation circuit 140 instead of the polarity inversion signal Pol. Then, the common voltage generation circuit 140 selects one of the common signal voltages VcomH and VcomL adjusted by the power supply adjustment circuit 160 according to the polarity inversion signal Pola, and uses the common signal Vc as a rectangular wave for the display pixels in common. Supply to electrode.

  Further, the control unit 150 sets the output timing of each control signal so that the non-scanning period Nt is obtained after the scanning period St in each frame. That is, for example, when one frame in the input video signal VD is 16 ms, signal generation is performed so that the first 8 ms of the frame is the scanning period St and the next 8 ms is the non-scanning period Nt. The unit 151 generates and outputs a scanning allowance signal As and a scanning inhibition signal Ps.

  For example, when the information unit 153 displays information on the raster screen as shown in FIG. 2A above the center of the screen, the signal driver 130 causes the data line S ( The signal driver 130 supplies the data line S (i) during the non-scan period Nt with respect to the amplitude shape of the transition of the series of display signal voltages Ds (i, j, St) to be supplied to i). The display signal voltage Ds (i, j, Nt) as a complementary voltage value is derived so that the amplitude shape of the transition of the series of display signal voltages Ds (i, j, Nt) becomes inverted. For example, when displaying information below the center of the screen on the raster screen as shown in FIG. 2B, the signal driver 130 supplies the data line S (i) during the scanning period St. The amplitude shape of the transition of the series of display signal voltages Ds (i, j, St) to be changed and the series of display signal voltages Ds to be supplied to the data line S (i) by the signal driver 130 during the non-scanning period Nt. The display signal voltage Ds (i, j, Nt) as a complementary voltage value is derived so that the amplitude shape of the transition of (i, j, Nt) matches.

  That is, in the second embodiment, for each frame, a scanning period St for executing scanning of each gate line G (j) and a non-scanning period Nt for stopping scanning of each gate line G (j) are set. . When information is displayed below the center of the screen on the raster screen as shown in FIG. 2B, a series of display signal voltages supplied to the data line S (i) during the scanning period St. To the data line S (i) in the non-scanning period Nt so that the amplitude shape of a series of display signal voltages supplied to the data line S (i) in the non-scanning period Nt is inverted. The display signal voltage is supplied. Further, when information is displayed on the raster screen as shown in FIG. 2A above the center of the screen, a series of display signal voltages supplied to the data line S (i) in the scanning period St. Display on the data line S (i) in the non-scanning period Nt so that the amplitude shape of a series of display signal voltages supplied to the data line S (i) in the non-scanning period Nt is equal to the amplitude shape of The signal voltage is supplied.

  17 and 18 show time-series changes in the voltage Vlcd applied to the liquid crystal layer corresponding to each display pixel when the display unit 17 is driven and controlled as described above. In the second embodiment, in order to simplify the description, the fluctuation of Vlcd accompanying the polarity inversion of the voltage supplied to the data line S (i), the gate line G (j), and the pixel electrode P Variation of Vlcd due to the parasitic capacitance generated between (i, j) is omitted. Also, Vlcd is normalized based on the potential of the counter electrode.

  17 corresponds to the case where information is displayed below the center of the screen on the raster screen as shown in FIG. 2B, and as shown in FIG. 15, the display signal voltage Ds ( When the transition of i, j, St) and the transition of the display signal voltage Ds (i, j, Nt) in the subsequent non-scanning period Nt are added so that their start timings coincide with each other, the maximum This is a time-series change in Vlcd when the display signal voltage is supplied to the data line S (i) so as to be leveled at the display signal voltage x [V] or -x [V] corresponding to the gradation level. Here, the time series change of Vlcd corresponding to the pixel electrode P (i, 1) connected to the second-stage gate line G (2) from the previous stage side is shown as an example, but each gate line G (1 ), G (3), G (4), G (5), G (6) respectively connected to the pixel electrodes P (i, 1), P (i, 3), P (i, 4), The same applies to Vlcd corresponding to P (i, 5) and P (i, 6).

  As shown in FIG. 17, in each frame, the fluctuation of Vlcd that occurs as the voltage supplied to the data line S (i) fluctuates from the voltage written in the display pixel is expressed as the non-scanning period Nt. It is possible to cancel out with the scanning period St. That is, the fluctuation “+ ΔV” of Vlcd occurring in the scanning period St is canceled by the fluctuation “−ΔV” of Vlcd occurring in the non-scanning period Nt. Therefore, for example, in a normally black mode in which white is displayed when a voltage is applied and black is displayed when no voltage is applied, a relatively black vertical streak displayed on the entire screen as shown in FIG. And the relatively white vertical streak displayed on the entire screen as shown in FIG. 12B in the subsequent non-scanning period Nt, the display luminance is temporally averaged, and the vertical streak is less visible. Is possible. That is, crosstalk in the direction along the data line S (i) as a vertical stripe can be made difficult to be visually recognized.

  On the other hand, FIG. 18 shows the display signal voltage in the scanning period St as shown in FIG. 16, corresponding to the case where information is displayed above the center of the screen on the raster screen as shown in FIG. The display signal voltage is supplied to the data line S (i) so that the transition of Ds (i, j, St) and the transition of the display signal voltage Ds (i, j, Nt) in the subsequent non-scanning period Nt coincide with each other. Is the time series change of Vlcd. Here, the time series change of Vlcd corresponding to the pixel electrode P (i, 7) connected to the gate line G (7) of the second stage from the rear stage side (the seventh stage from the front stage side) is shown as an example. Are pixel electrodes P (i, 3), P (i, 4) connected to the gate lines G (3), G (4), G (5), G (6), G (8), respectively. , P (i, 5), P (i, 6), and Vlcd corresponding to P (i, 8) are the same.

  As shown in FIG. 18, in each frame, the fluctuation of Vlcd that occurs as the voltage supplied to the data line S (i) fluctuates from the voltage written in the display pixel is expressed as a non-scanning period Nt. It is possible to cancel out with the scanning period St. That is, the fluctuation “−ΔV” of Vlcd that occurs in the scanning period St can be canceled by the fluctuation “+ ΔV” of Vlcd that occurs in the non-scanning period Nt. Therefore, for example, in a normally black mode in which white is displayed when a voltage is applied and black is displayed when no voltage is applied, a relatively white vertical streak displayed on the entire screen as shown in FIG. 13A in the scanning period St. And the relatively black vertical streaks displayed on the entire screen as shown in FIG. 13B in the subsequent non-scanning period Nt, the display luminance is temporally averaged so that the vertical streaks are less visible. Is possible. That is, crosstalk in the direction along the data line S (i) as a vertical stripe can be made difficult to be visually recognized.

  Also in the second embodiment, similarly to the first embodiment, the display signal voltage to be added may be derived by a simple arithmetic expression as shown in (Equation 1) or (Equation 2). Therefore, it is possible to perform a display in which crosstalk in the direction along the data line is difficult to be visually recognized in the frame inversion driving while reducing the calculation load.

  In each of the above-described embodiments, the amplitude shape of a series of display signal voltages supplied to the data line S (i) in the non-scanning period Nt is supplied to the data line S (i) in the scanning period St. The configuration for selecting whether the amplitude shape of the series of display signal voltages is inverted or equal to the amplitude shape has been described according to the video to be displayed, but regardless of the video to be displayed. Alternatively, only one of them may be selected.

  In each of the above-described embodiments, the case where the active matrix liquid crystal display device of the present invention is applied to a digital camera has been described. However, the present invention is not limited to this, and other portable terminal devices such as a cellular phone, The present invention can be applied to various electronic devices that require a display unit.

Explanatory drawing of the external appearance structure of a digital camera. It is explanatory drawing of an information display screen, (a) is the example which displayed information on the upper part of the screen, (b) is the example which displayed information on the lower part of the screen. Explanatory drawing of active matrix type liquid crystal display device Illustration of equivalent circuit of display pixel Control signal timing chart when displaying information at the bottom of the screen Illustration of derivation of complementary voltage value Control signal timing chart when displaying information at the top of the screen Illustration of derivation of complementary voltage value It is a relationship diagram between a gradation level and a display signal voltage, (a) when applying a positive voltage to the liquid crystal, (b) when applying a negative voltage to the liquid crystal. Timing chart of the voltage applied to the liquid crystal of the display pixel above the display pixel where information is displayed when displaying information at the bottom of the screen Timing chart of the voltage applied to the liquid crystal of the display pixel below the display pixel where information is displayed when displaying information at the top of the screen It is a display example for every sub-frame in the case of displaying information on the lower part of a screen, (a) is a display example in a scanning period, (b) is a display example in a non-scanning period. It is a display example for every sub-frame in the case of displaying information on the upper part of a screen, (a) is a display example in a scanning period, (b) is a display example in a non-scanning period. Explanatory drawing of active matrix type liquid crystal display device Control signal timing chart when displaying information at the bottom of the screen Control signal timing chart when displaying information at the top of the screen Timing chart of the voltage applied to the liquid crystal of the display pixel above the display pixel where information is displayed when displaying information at the bottom of the screen Timing chart of the voltage applied to the liquid crystal of the display pixel below the display pixel where information is displayed when displaying information at the top of the screen Illustration of frame inversion drive It is explanatory drawing of crosstalk, (a) is the image | video which should be displayed, (b) is the relationship between the image | video which should be displayed, and the generated crosstalk. It is explanatory drawing of more concrete crosstalk, (a) is the crosstalk when information is displayed at the top of the screen, (b) is the crosstalk when information is displayed at the bottom of the screen

Explanation of symbols

1: Digital camera 17: Display unit (active matrix liquid crystal display device)
110: display panel 120: scan driver 130: signal driver 140: common voltage generation circuit 150: control unit 151: signal generation unit 152: video memory 153: calculation unit St: scanning period Nt: non-scanning period

Claims (4)

A plurality of gate lines arranged in one direction, a data line arranged in another direction intersecting each gate line, and each intersection of the gate line and the data line. includes a plurality of display pixels, the display screen having been said with scans each gate line, and supplies a display signal voltage to each of the display pixels where the corresponding to the gate lines through the data lines normally In the black type active matrix liquid crystal display device,
Each pixel has a pixel electrode connected to the data line via a switching element, and a common electrode facing the pixel electrode,
Divided into a second sub-frame period of the first half and the first sub-frame period of the second half having a same length of time each frame, the display scanning of the gate lines in the first sub frame period Gate line driving means for executing from the top to the bottom of the screen and stopping scanning of each gate line during the second subframe period;
A data line driving means for performing the frame inversion driving by supplying the display signal voltage to the data lines in the first sub-frame period,
First complementary voltage having an amplitude shape the data line driving means is reversed with respect to the amplitude shape of a series of the display signal voltage supplied to said first sub-frame period, or the data line drive means the second Complementary voltage value deriving means for deriving a second complementary voltage value having an amplitude shape matching the amplitude shape of a series of the display signal voltages supplied in two subframe periods in correspondence with the data line;
A common voltage generating means for generating a common signal voltage whose signal level alternately changes every frame period and supplying the common signal voltage to the common electrode ; and
The complementary voltage value deriving unit displays information from the upper part of the display screen to a region corresponding to the first gate line, and the region scanned by the gate line driving unit after the first gate line is displayed. When the intermediate gray level is set, the first complementary voltage value is derived, and the data line driving means supplies the first complementary voltage value to the data line during the second subframe period .
The complementary voltage value deriving unit displays information between a region corresponding to the second gate line from the lower part of the display screen, and is a region scanned by the gate line driving unit before the second gate line The second complementary voltage value is derived, and the data line driving means supplies the second complementary voltage value to the data line during the second subframe period. An active matrix liquid crystal display device. The complementary voltage value deriving means, a voltage value in which the value obtained by adding the first complementary voltage value to the display signal voltage supplied to the second sub-frame period corresponding to the maximum gray level of the display signal voltage The active matrix liquid crystal display device according to claim 1 , wherein the first complementary voltage value is derived so that A plurality of gate lines arranged in one direction, a data line arranged in another direction intersecting each gate line, and each intersection of the gate line and the data line. a display screen having a plurality of display pixels, wherein while scanning each of the gate lines, normally black supplies a display signal voltage to each of the display pixels corresponding to the respective gate lines through the data line Type active matrix liquid crystal display device,
Each pixel has a pixel electrode connected to the data line via a switching element, and a common electrode facing the pixel electrode,
Divided into a first sub-frame period and the second sub-frame period of the second half of the first half having a same length of time each frame, the display scanning of the gate lines in the first sub frame period Gate line driving means for executing from the top to the bottom of the screen and stopping scanning of each gate line during the second subframe period;
A data line driving means for performing the frame inversion driving by supplying the display signal voltage to the data lines in the first sub-frame period,
Wherein the amplitude shape of the data line drive means a series of the display signal voltage supplied to said first sub-frame period, the first complementary voltage value having inverted amplitude shape, or, the data line driving means the Complementary voltage value deriving means for deriving a second complementary voltage value having an amplitude shape corresponding to a transition of the series of display signal voltages supplied in the first subframe period in correspondence with the data line;
Common voltage generating means for generating a common signal voltage whose signal level alternately changes at each switching timing between the first subframe period and the second subframe period and supplying the common signal voltage to the common electrode; Prepared,
The complementary voltage value deriving unit displays information from the upper part of the display screen to a region corresponding to the first gate line, and the region scanned by the gate line driving unit after the first gate line is displayed. The second complementary voltage value is derived when the intermediate gray level is set, and the data line driving means supplies the second complementary voltage value to the data line during the second subframe period ,
The complementary voltage value deriving unit displays information between a region corresponding to the second gate line from the lower part of the display screen, and is a region scanned by the gate line driving unit before the second gate line The first complementary voltage value is derived when the intermediate gray level is set to a certain intermediate gradation, and the data line driving means supplies the first complementary voltage value to the data line during the second subframe period. An active matrix liquid crystal display device. The complementary voltage value deriving means, the maximum gray level of the first sub-frame period wherein the display signal voltage to the first value obtained by adding the complementary voltage value the display signal voltage supplied to the data line 4. The active matrix liquid crystal display device according to claim 3 , wherein the first complementary voltage value is derived so as to have a corresponding voltage value .