JP5262581B2 - Differential output circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a differential output circuit capable of satisfying a DC specification of an output common mode even when the DC specification of an output common mode voltage is extremely eccentric from near a center voltage between a power supply voltage that a first power supply line supplies and a power supply voltage that a second power supply line supplies, to a side of the power supply voltage that the second power supply line supplies or of the power supply voltage that the first power supply line supplies. <P>SOLUTION: When a VC setting unit (output common mode voltage setting unit) 82 is provided at a upstream side of a signal transmission unit 71 on a current path from a VDD power supply line 68 to a VSS power supply line 69, a constant current source 88 is connected between the VDD power supply line 68 and a source of a PMOS transistor 87 of the VC setting unit 82 and even when a DC specification of an output common mode voltage is extremely eccentric from near VDD/2 to a VSS side, a source/drain voltage VSD of a PMOS transistor 89 constituting the constant current source 88 is sufficiently ensured. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

  The present invention relates to a differential output circuit suitable for mounting on an LSI (large scale integrated circuit) chip or the like that performs high-speed serial data communication.

  In recent years, high speed is required for data transfer between LSI chips. For this reason, in data transfer between LSI chips, for example, a differential output circuit is used to convert a transmission signal into a small amplitude differential signal such as LVDS (low voltage differential signaling) to increase power supply noise. In some cases, a technique that enables high-speed data transfer is used.

  FIG. 26 is a circuit diagram showing an example of a conventional differential output circuit. In FIG. 26, 1 is an LSI on the transmission side, 2 is an example of a conventional differential output circuit provided in LSI 1, 3, 4 is an external output terminal of LSI 1, 5, 6 are signal wirings, 7 is a terminating resistor (for example, 100Ω) The receiving side LSI is not shown.

  In the differential output circuit 2, 8 is a VDD power supply line that supplies a positive power supply voltage VDD, 9 is a VSS power supply line that supplies a power supply voltage VSS that is 0 V or a negative voltage, and 10 is an input signal to the differential output circuit 2. An internal signal terminal to which SA is provided, 11 is a signal transmission unit, 12 is an output buffer for inputting an input signal SA and outputting an in-phase output signal SP, and 13 is an output signal having a reverse phase by inputting the input signal SA. This is an output buffer for outputting SN.

  In the output buffer 12, 14 and 15 are inverters, 16 is a PMOS transistor, and 17 is an NMOS transistor. In the output buffer 13, 18 is a buffer formed by cascading two inverters, 19 is an inverter, 20 is a PMOS transistor, and 21 is an NMOS transistor.

  Reference numeral 22 denotes a VC setting unit for setting the output common mode voltage VC. Reference numerals 23 and 24 denote resistors constituting a VCM detection circuit for detecting the average voltage VCM of the output signal SP and the output signal SN. Reference numeral 25 denotes the common mode voltage VOS. Is a common mode voltage setting terminal, 26 is an operational amplifier, and 27 is a PMOS transistor. The resistors 23 and 24 have sufficiently larger resistance values than the termination resistor 7. Reference numeral 28 denotes a constant current source, 29 denotes an NMOS transistor, and VBN denotes a gate bias voltage of the NMOS transistor 29 generated by a bias circuit (not shown).

  In the differential output circuit 2, the output differential voltage VD that is the difference voltage between the output signals SP and SN is determined by the constant current IA from the constant current source 28 and the resistance value of the termination resistor 7. Since the VC setting unit 22 forms a negative feedback loop, the on-resistance value of the PMOS transistor 27 is controlled by the output voltage of the operational amplifier 26 so that the output common mode voltage VC = the common mode voltage VOS. The

  FIG. 27 is a diagram showing a current path for determining the output voltage of the external output terminals 3 and 4. FIG. 27A shows a case where the input signal SA is logic 1 (H level), and FIG. This is the case of (L level).

  Here, for example, when VDD = 1.2V and VSS = 0V, the DC specifications of the differential output circuit 2 are the output differential voltage VD = 0.2 Vp-p, the output common mode voltage VC = VDD / 2 = Assuming 0.6V, when the input signal SA is logic 1 (H level), as shown in (A), between the VDD power supply line 8 and the external output terminal 3 and between the external output terminal 4 and the VSS power supply line. A voltage of 0.5 V is applied to the voltage 9. When the input signal SA is logic 0 (L level), as shown in (B), between the VDD power supply line 8 and the external output terminal 4 and between the external output terminal 3 and the VSS power supply line 9. 0.5V is applied.

  FIG. 28 is a circuit diagram showing another example of a conventional differential output circuit. In FIG. 28, 31 is an LSI on the transmission side, 32 is another example of a conventional differential output circuit provided in the LSI 31, 33 and 34 are external output terminals of the LSI 31, 35 and 36 are signal wirings, and 37 is a termination resistor (for example, , 100Ω), and the LSI on the receiving side is not shown.

  In the differential output circuit 32, 38 is a VDD power supply line, 39 is a VSS power supply line, 40 is an internal signal terminal to which an input signal SA to the differential output circuit 32 is given, 41 is a signal transmission unit, and 42 is an input signal. An output buffer 43 that inputs SA and outputs an in-phase output signal SP, and 43 is an output buffer that inputs an input signal SA and outputs an output signal SN having a reverse phase.

  In the output buffer 42, 44 and 45 are inverters, 46 is a PMOS transistor, and 47 is an NMOS transistor. In the output buffer 43, 48 is a buffer formed by connecting two inverters in cascade, 49 is an inverter, 50 is a PMOS transistor, and 51 is an NMOS transistor.

  Reference numeral 52 denotes a VC setting unit for setting the output common mode voltage VC. Reference numerals 53 and 54 denote resistors constituting a VCM detection circuit for detecting the average voltage VCM of the output signal SP and the output signal SN. Reference numeral 55 denotes the common mode voltage VOS. Is a common mode voltage setting terminal, 56 is an operational amplifier, and 57 is an NMOS transistor. Note that the resistors 53 and 54 have sufficiently larger resistance values than the termination resistor 37. 58 is a constant current source, 59 is a PMOS transistor, and VBP is a gate bias voltage of the PMOS transistor 59 generated by a bias circuit (not shown).

  In the differential output circuit 32, the output differential voltage VD is determined by the constant current IB from the constant current source 58 and the resistance value of the termination resistor 37. Since the VC setting unit 52 forms a negative feedback loop, the on-resistance value of the NMOS transistor 57 is controlled by the operational amplifier 56 so that the output common mode voltage VC = the common mode voltage VOS.

  FIG. 29 is a diagram showing a current path for determining the output voltage of the external output terminals 33 and 34. FIG. 29A shows a case where the input signal SA is logic 1 (H level), and FIG. This is the case of (L level).

Here, for example, when VDD = 1.2V and VSS = 0V, the DC specifications of the differential output circuit 32 are the output differential voltage VD = 0.2 Vp-p, the output common mode voltage VC = VDD / 2 = Assuming 0.6V, when the input signal SA is logic 1 (H level), as shown in (A), between the VDD power supply line 38 and the external output terminal 33 and between the external output terminal 34 and the VSS power supply line. The voltage of 0.5 V is applied to the voltage 39. When the input signal SA is logic 0 (L level), as shown in (B), between the VDD power supply line 38 and the external output terminal 34 and between the external output terminal 33 and the VSS power supply line 39. 0.5V is applied.
JP 2005-123773 A JP 2004-112453 A JP 2006-60416 A Japanese Patent Laid-Open No. 11-4158 JP 2006-340266 A JP 2007-134940 A US Patent Gazette (Patent No. 6,590,422) US Patent Gazette (Patent No. 7,183,804) US Patent Gazette (Patent No. 7,336,780) JP-A-11-150469

  In recent years, with the diversification of high-speed data transfer, LSI chips used with different power supply voltages may be connected, and a signal voltage range may be used for detection of an operation mode, operation confirmation, and the like. In such a case, the DC specification of the output common mode voltage VC is extremely biased toward the VSS side or the VDD side, not near VDD / 2.

  FIG. 30 is a diagram for explaining a problem that occurs in the differential output circuit 2 when the DC specification of the output common mode voltage VC is extremely biased to the VSS side. FIG. In the case of (H level), (B) is the case where the input signal SA is logic 0 (L level).

  Here, for example, when VDD = 1.2V and VSS = 0V, the DC specifications of the differential output circuit 2 are the output differential voltage VD = 0.2 Vp-p and the output common mode voltage VC = 0.2 V. Then, when the input signal SA is logic 1 (H level), 0.9 V is applied between the VDD power supply line 8 and the external output terminal 3 as shown in FIG. 0.1V is applied between the power supply line 9 and the VSS power supply line 9. When the input signal SA is logic 0 (L level), as shown in (B), 0.9 V is applied between the VDD power supply line 8 and the external output terminal 4, and the external output terminal 3 and VSS are connected. A voltage of 0.1 V is applied to the power supply line 9.

  That is, when the input signal SA is logic 1 (H level), only 0.1 V is secured as the sum of the drain-source voltages of the NMOS transistors 21 and 29 connected in series as shown in FIG. When the input signal SA is logic 0 (L level), only 0.1 V is secured as the sum of the drain-source voltages of the NMOS transistors 17 and 29 connected in series as shown in FIG. Can not do.

  As in this example, in the differential output circuit 2, when the drain-source voltage VDS of the NMOS transistor 29 becomes less than 0.1 V, the NMOS transistor 29 operates in the non-saturated region. Due to variations in PTV (process / temperature / voltage) conditions, the constant current IA varies, and the DC specification of the output common mode voltage VC cannot be satisfied.

  FIG. 31 is a diagram for explaining a problem that occurs in the differential output circuit 32 when the DC specification of the output common mode voltage VC is extremely biased toward the VDD side. FIG. In the case of (H level), (B) is the case where the input signal SA is logic 0 (L level).

  Here, for example, when VDD = 1.2V and VSS = 0V, the DC specifications of the differential output circuit 32 are as follows: the output differential voltage VD = 0.2 Vp-p, and the output common mode voltage VC = 1.0 V. Then, when the input signal SA is logic 1 (H level), 0.1 V is applied between the VDD power supply line 38 and the external output terminal 33 as shown in FIG. 0.9 V is applied between the power supply line 39 and the VSS power supply line 39. When the input signal SA is logic 0 (L level), 0.1 V is applied between the VDD power line 38 and the external output terminal 34 as shown in FIG. A voltage of 0.9 V is applied to the power supply line 39.

  As in this example, in the differential output circuit 32, when the source-drain voltage VSD of the PMOS transistor 59 is less than 0.1 V, the PMOS transistor 59 operates in the non-saturated region. Due to variations in PTV (process / temperature / voltage) conditions, the constant current IB varies, resulting in a problem that the DC specification of the output common mode voltage VC cannot be satisfied.

  In view of this point, the present invention is such that the DC specification of the output common mode voltage VC is determined from the vicinity of the center voltage between the power supply voltage supplied by the first power supply line and the power supply voltage supplied by the second power supply line. Even when the power supply voltage supplied by the line or the power supply voltage supplied by the first power supply line is extremely biased, the DC specification of the output common mode voltage VC can be satisfied and the yield can be improved. It is an object of the present invention to provide a differential output circuit that can be used.

  A first differential output circuit disclosed in the present application includes a first power supply line, a constant current source having a current input terminal connected to the first power supply line, a variable resistance element, and the variable resistance element. An output common mode voltage setting unit having one end connected to the current output terminal of the constant current source, a first power supply terminal connected to the other end of the variable resistance element, and a second power supply terminal connected to the first power supply. And a signal transmission unit connected to a second power supply line that supplies a lower voltage than the line.

  A second differential output circuit disclosed in the present application includes a first power supply line and a variable resistance element, and an output common mode voltage setting unit in which one end of the variable resistance element is connected to the first power supply line. A constant current source having a current input terminal connected to the other end of the variable resistance element, a first power supply terminal connected to a current output terminal of the constant current source, and a second power supply terminal connected to the first power supply And a signal transmission unit connected to a second power supply line that supplies a lower voltage than the line.

  A third differential output circuit disclosed in the present application includes a first power supply line, a signal transmission unit in which a first power supply terminal is connected to the first power supply line, and a variable resistance element. An output common mode voltage setting unit in which one end of the resistance element is connected to the second power supply terminal of the signal transmission unit, a current input terminal is connected to the other end of the variable resistance element, and a current output terminal is connected to the first power supply. And a constant current source connected to a second power supply line that supplies a lower voltage than the line.

  A fourth differential output circuit disclosed in the present application includes a first power supply line, a signal transmission unit in which a first power supply terminal is connected to the first power supply line, and a current input terminal of the signal transmission unit. A constant current source connected to a second power supply terminal; and a variable resistance element; one end of the variable resistance element is connected to a current output terminal of the constant current source; the other end of the variable resistance element is the first And an output common mode voltage setting unit connected to a second power supply line for supplying a lower voltage than the power supply line.

  A fifth differential output circuit disclosed in the present application includes a first power supply line, a constant current source having a current input terminal connected to the first power supply line, a variable resistance element, and the variable resistance element. An output common mode voltage setting unit in which one end of the variable resistance element is connected to a second power supply line that supplies a voltage lower than that of the first power supply line. And a signal transmission unit in which a first power supply terminal is connected to a current output terminal of the constant current source, and a second power supply terminal is connected to the second power supply line.

  A sixth differential output circuit disclosed in the present application includes a first power supply line and a variable resistance element, and an output common mode voltage setting unit in which one end of the variable resistance element is connected to the first power supply line. A constant current source having a current input terminal connected to the other end of the variable resistance element and a current output terminal connected to a second power supply line for supplying a lower voltage than the first power supply line; and a first power supply And a signal transmission unit having a terminal connected to the other end of the variable resistance element and a second power supply terminal connected to the second power supply line.

  A seventh differential output circuit disclosed in the present application includes a first power supply line, a signal transmission unit in which a first power supply terminal is connected to the first power supply line, and a current input terminal of the signal transmission unit. A constant current source connected to a second power supply terminal and having a current output terminal connected to a second power supply line for supplying a lower voltage than the first power supply line; and a variable resistance element, the variable resistance element And an output common mode voltage setting unit in which the other end of the variable resistance element is connected to the current input terminal of the constant current source.

  An eighth differential output circuit disclosed in the present application includes a first power supply line, a signal transmission unit in which a first power supply terminal is connected to the first power supply line, a variable resistance element, and the variable output circuit. An output common in which one end of the resistance element is connected to a second power supply terminal of the signal transmission unit, and the other end of the variable resistance terminal is connected to a second power supply line that supplies a lower voltage than the first power supply line. A mode voltage setting unit; and a constant current source having a current input terminal connected to the first power supply line and a current output terminal connected to one end of the variable resistance element.

  According to the disclosed first differential output circuit, when the output common mode voltage setting unit is provided upstream of the signal transmission unit on the current path from the first power supply line to the second power supply line. Since the constant current source is connected between the first power supply line and the output common mode voltage setting unit, the DC specification of the output common mode voltage VC is the same as the power supply voltage supplied by the first power supply line The source / drain of the field effect transistor that constitutes the constant current source even when the power supply voltage supplied by the second power supply line is extremely biased from the vicinity of the center voltage to the power supply voltage supplied by the second power supply line A sufficient voltage can be secured as the inter-voltage.

  Therefore, the DC specification of the output common mode voltage VC is changed from the vicinity of the center voltage between the power supply voltage supplied by the first power supply line and the power supply voltage supplied by the second power supply line to the power supply voltage supplied by the second power supply line. Even if it is extremely biased, the DC specification of the output common mode voltage VC can be satisfied, and the yield can be improved.

  According to the disclosed second differential output circuit, when the output common mode voltage setting unit is provided upstream of the signal transmission unit on the current path from the first power supply line to the second power supply line. Since the constant current source is connected between the output common mode voltage setting section and the signal transmission section, the DC specification of the output common mode voltage VC is the same as the power supply voltage supplied by the first power supply line and the second power supply voltage. The voltage between the source and drain of the field-effect transistor that constitutes the constant current source, even when the power supply voltage supplied by the power supply line is extremely biased from the vicinity of the center voltage to the power supply voltage supplied by the second power supply line A sufficient voltage can be secured.

  Therefore, the DC specification of the output common mode voltage VC is changed from the vicinity of the center voltage between the power supply voltage supplied by the first power supply line and the power supply voltage supplied by the second power supply line to the power supply voltage supplied by the second power supply line. Even if it is extremely biased, the DC specification of the output common mode voltage VC can be satisfied, and the yield can be improved.

  According to the disclosed third differential output circuit, when the output common mode voltage setting unit is provided downstream of the signal transmission unit on the current path from the first power supply line to the second power supply line. Since the constant current source is connected between the output common mode voltage setting unit and the second power supply line, the DC specifications of the output common mode voltage VC are the same as the power supply voltage supplied by the first power supply line and the second power supply line. The drain / source of the field effect transistor that constitutes the constant current source even when the power supply voltage supplied by the second power supply line is extremely biased from the vicinity of the center voltage to the power supply voltage supplied by the first power supply line A sufficient voltage can be secured as the inter-voltage.

  Therefore, the DC specification of the output common mode voltage VC is changed from the vicinity of the center voltage between the power supply voltage supplied by the first power supply line and the power supply voltage supplied by the second power supply line to the power supply voltage supplied by the first power supply line. Even if it is extremely biased, the DC specification of the output common mode voltage VC can be satisfied, and the yield can be improved.

  According to the disclosed fourth differential output circuit, when the output common mode voltage setting unit is provided downstream of the signal transmission unit on the current path from the first power supply line to the second power supply line. Since the constant current source is connected between the signal transmission unit and the output common mode voltage setting unit, the DC specification of the output common mode voltage VC is equal to the power supply voltage supplied by the first power supply line and the second The drain-source voltage of the field-effect transistor that constitutes the constant current source even when it is extremely deviated from the vicinity of the center voltage to the power supply voltage supplied by the power supply line to the power supply voltage supplied by the first power supply line A sufficient voltage can be secured.

  Therefore, the DC specification of the output common mode voltage VC is changed from the vicinity of the center voltage between the power supply voltage supplied by the first power supply line and the power supply voltage supplied by the second power supply line to the power supply voltage supplied by the first power supply line. Even if it is extremely biased, the DC specification of the output common mode voltage VC can be satisfied, and the yield can be improved.

  According to the disclosed fifth differential output circuit, when the constant current source is provided upstream of the signal transmission unit on the current path from the first power supply line to the second power supply line, the output common Since the mode voltage setting unit is connected between the constant current source and the second power supply line, the DC specification of the output common mode voltage VC is the power supply voltage supplied by the first power supply line and the second power supply. As a voltage between the source and drain of the field effect transistor constituting the constant current source, even if it is extremely biased from the vicinity of the center voltage to the power supply voltage supplied by the line to the power supply voltage supplied by the second power supply line A sufficient voltage can be secured.

  Therefore, the DC specification of the output common mode voltage VC is changed from the vicinity of the center voltage between the power supply voltage supplied by the first power supply line and the power supply voltage supplied by the second power supply line to the power supply voltage supplied by the second power supply line. Even if it is extremely biased, the DC specification of the output common mode voltage VC can be satisfied, and the yield can be improved.

  According to the disclosed sixth differential output circuit, when the output common mode voltage setting unit is provided upstream of the signal transmission unit on the current path from the first power supply line to the second power supply line. Since the constant current source is connected between the output common mode voltage setting unit and the second power supply line, the DC specifications of the output common mode voltage VC are the same as the power supply voltage supplied by the first power supply line and the second power supply line. The drain / source of the field effect transistor that constitutes the constant current source even if it is extremely biased from the vicinity of the center voltage to the power supply voltage supplied by the second power supply line to the power supply voltage supplied by the second power supply line A sufficient voltage can be secured as the inter-voltage.

  Therefore, the DC specification of the output common mode voltage VC is changed from the vicinity of the center voltage between the power supply voltage supplied by the first power supply line and the power supply voltage supplied by the second power supply line to the power supply voltage supplied by the second power supply line. Even if it is extremely biased, the DC specification of the output common mode voltage VC can be satisfied, and the yield can be improved.

  According to the disclosed seventh differential output circuit, when the constant current source is provided on the current path from the first power supply line to the second power supply line and downstream of the signal transmission unit, the output common Since the mode voltage setting unit is connected between the first power supply line and the constant current source, the DC specification of the output common mode voltage VC is the power supply voltage supplied by the first power supply line and the second power supply. As a voltage between the drain and source of the field effect transistor constituting the constant current source, even when the power supply voltage supplied by the line is extremely biased from the vicinity of the center voltage to the power supply voltage supplied by the first power supply line A sufficient voltage can be secured.

  Therefore, the DC specification of the output common mode voltage VC is changed from the vicinity of the center voltage between the power supply voltage supplied by the first power supply line and the power supply voltage supplied by the second power supply line to the power supply voltage supplied by the first power supply line. Even if it is extremely biased, the DC specification of the output common mode voltage VC can be satisfied, and the yield can be improved.

  According to the disclosed eighth differential output circuit, when the output common mode voltage setting unit is provided downstream of the signal transmission unit on the current path from the first power supply line to the second power supply line. Since the constant current source is connected between the first power supply line and the output common mode voltage setting unit, the DC specification of the output common mode voltage VC is the same as the power supply voltage supplied by the first power supply line The source / drain of the field effect transistor that constitutes the constant current source even when the power supply voltage supplied by the second power supply line is extremely biased from the vicinity of the center voltage to the power supply voltage supplied by the first power supply line A sufficient voltage can be secured as the inter-voltage.

  Therefore, the DC specification of the output common mode voltage VC is changed from the vicinity of the center voltage between the power supply voltage supplied by the first power supply line and the power supply voltage supplied by the second power supply line to the power supply voltage supplied by the first power supply line. Even if it is extremely biased, the DC specification of the output common mode voltage VC can be satisfied, and the yield can be improved.

(First embodiment)
FIG. 1 is a circuit diagram showing a first embodiment of the present invention. In FIG. 1, 61 is a transmission-side LSI, 62 is a first embodiment of the present invention provided in the LSI 61, 63 and 64 are external output terminals (second and third signal terminals) of the LSI 61, and 65 is an external output terminal 63. , Signal wiring connected to the external output terminal 64, 67 a termination resistor (for example, 100Ω) connected between the signal wirings 65 and 66, and the LSI on the receiving side is not shown. doing.

  The first embodiment 62 of the present invention is a differential output circuit suitable for application when the DC specification of the output common mode voltage VC is extremely biased from VDD / 2 to the VSS side. In the first embodiment 62 of the present invention, 68 is a VDD power supply line (first power supply line), 69 is a VSS power supply line (second power supply line), 70 is an internal circuit (not shown), and the first embodiment of the present invention. 62 is an internal signal terminal (first signal terminal) to which an input signal SA to 62 is applied.

  71 is a signal transmission unit, 72 is an output buffer (first output buffer) that inputs an input signal SA and outputs an in-phase output signal SP, and 73 is an input signal SA that is input and outputs an anti-phase output signal SN. Is an output buffer (second output buffer).

  In the output buffer 72, 74 is a buffer formed by cascading two inverters, 75 is an inverter, and 76 and 77 are NMOS transistors constituting an output circuit composed of a totem pole circuit. In the output buffer 73, 78 is an inverter, 79 is a buffer formed by cascading two inverters, and 80 and 81 are NMOS transistors constituting an output circuit comprising a totem pole circuit.

  The buffer 74 has an input terminal connected to the internal signal terminal 70 and an output terminal connected to the gate of the NMOS transistor 76. The inverter 75 has an input terminal connected to the internal signal terminal 70 and an output terminal connected to the gate of the NMOS transistor 77.

  The NMOS transistor 76 has a drain connected to the first power supply terminal 71 A of the signal transmission unit 71, a source connected to the drain of the NMOS transistor 77, and the NMOS transistor 77 has a source connected to the second power supply terminal of the signal transmission unit 71. It is connected to 71B. The connection point between the source of the NMOS transistor 76 and the drain of the NMOS transistor 77 is connected to the external output terminal 63.

  The inverter 78 has an input terminal connected to the internal signal terminal 70 and an output terminal connected to the gate of the NMOS transistor 80. The buffer 79 has an input terminal connected to the internal signal terminal 70 and an output terminal connected to the gate of the NMOS transistor 81.

  The NMOS transistor 80 has a drain connected to the first power supply terminal 71A of the signal transmission unit 71, a source connected to the drain of the NMOS transistor 81, and the NMOS transistor 81 has a source connected to the second power supply terminal of the signal transmission unit 71. It is connected to 71B. The connection point between the source of the NMOS transistor 80 and the drain of the NMOS transistor 81 is connected to the external output terminal 64. The second power supply terminal 71B of the signal transmission unit 71 is connected to the VSS power supply line 69.

  In the first embodiment 62 of the present invention, the output circuit in the output buffer 72 is constituted by a totem pole circuit comprising NMOS transistors 76 and 77, and the output circuit in the output buffer 73 is constituted by a totem pole comprising NMOS transistors 80 and 81. The circuit is configured in order to reduce the influence of the substrate bias effect.

  Reference numeral 82 denotes a VC setting unit (output common mode voltage setting unit) for setting the output common mode voltage VC. Reference numerals 83 and 84 denote VCM detection circuits (differential differential signals) for detecting the average voltage VCM of the output signal SP and the output signal SN. The resistor constituting the output signal average voltage detection circuit), 85 is a common mode voltage setting terminal to which the common mode voltage VOS is applied, 86 is an operational amplifier, and 87 is a power supply voltage applied to the first power supply terminal 71A of the signal transmission unit 71. This is a PMOS transistor forming a variable resistance element. The resistors 83 and 84 have sufficiently larger resistance values than the termination resistor 67.

  The resistors 83 and 84 are connected in series between the external output terminals 63 and 64, and the connection point of the resistors 83 and 84 is connected to the non-inverting input terminal of the operational amplifier 86. The common mode voltage setting terminal 85 is connected to the inverting input terminal of the operational amplifier 86, the output terminal of the operational amplifier 86 is connected to the gate of the PMOS transistor 87, and the PMOS transistor 87 has a drain connected to the first power supply of the signal transmission unit 71. It is connected to the terminal 71A.

  Reference numeral 88 denotes a constant current source, 89 is a PMOS transistor, and VBP is a gate bias voltage of the PMOS transistor 89. The PMOS transistor 89 has a source connected to the VDD power supply line 68 via the current input terminal 88A of the constant current source 88, and a drain connected to the source of the PMOS transistor 87 via the current output terminal 88B of the constant current source 88. Yes.

  FIG. 2 is a circuit diagram showing a configuration example of a bias circuit that generates the gate bias voltage VBP. In FIG. 2, 91 is a bias circuit, 92 is a PMOS transistor, and 93 is a resistor. The PMOS transistor 92 has a source connected to the VDD power supply line 68, a gate connected to the drain, a drain connected to the VSS power supply line 69 via the resistor 93, and a gate bias voltage VBP obtained at the drain. Yes. The drain of the PMOS transistor 92 is connected to the gate of the PMOS transistor 89, and the PMOS transistor 92 and the PMOS transistor 89 constitute a current mirror circuit.

  3A and 3B are diagrams showing current paths for determining the output voltages of the external output terminals 63 and 64. FIG. 3A shows a case where the input signal SA is logic 1 (H level), and FIG. This is the case of (L level).

  Here, for example, when VDD = 1.2V and VSS = 0V, the DC specifications of the first embodiment 62 of the present invention are the output differential voltage VD = 0.2 Vp-p, the output common mode voltage VC = 0. Assuming that the input signal SA is logic 1 (H level), 0.9 V is applied between the VDD power supply line 68 and the external output terminal 63 as shown in FIG. 0.1 V is applied between the output terminal 64 and the VSS power supply line 69. When the input signal SA is logic 0 (L level), 0.9V is applied between the VDD power supply line 68 and the external output terminal 64 as shown in FIG. A voltage of 0.1 V is applied to the power supply line 69. Therefore, whether the input signal SA is logic 1 (H level) or logic 0 (L level), a sufficient voltage is secured as the source-drain voltage VSD of the PMOS transistor 89 constituting the constant current source 88. be able to.

  FIG. 4 is a diagram showing input / output waveforms of the first embodiment 62 of the present invention. As shown in FIG. 3, when VDD = 1.2V and VSS = 0V, The circuit simulation waveforms when the DC specification is the output differential voltage VD = 0.2 Vp-p and the output common mode voltage VC = 0.2 V are shown, and the DC specification of the output common mode voltage VC is satisfied. It is shown that.

  For example, when VDD = 1.2V and VSS = 0V, the DC specifications of the first embodiment 62 of the present invention are the output differential voltage VD = 0.2 Vp-p, the output common mode voltage VC = VDD / Assuming 2 = 0.6 V, when the input signal SA is logic 1 (H level), between the VDD power supply line 68 and the external output terminal 63 and between the external output terminal 64 and the VSS power supply line 69. 0.5V is applied. When the input signal SA is logic 0 (L level), 0.5 V is applied between the VDD power supply line 68 and the external output terminal 64 and between the external output terminal 63 and the VSS power supply line 69. Also in this case, a sufficient voltage can be secured as the source-drain voltage VSD of the PMOS transistor 89 constituting the constant current source 88.

  As described above, according to the first embodiment 62 of the present invention, when the VC setting unit 82 is provided upstream of the signal transmission unit 71 on the current path from the VDD power supply line 68 to the VSS power supply line 69, the constant current Since the source 88 is connected between the VDD power supply line 68 and the source of the PMOS transistor 87 of the VC setting unit 82, the DC specification of the output common mode voltage VC is extremely biased from the vicinity of VDD / 2 to the VSS side. Even in this case, the source-drain voltage VSD of the PMOS transistor 89 constituting the constant current source 88 can be sufficiently secured.

  Therefore, even when the DC specification of the output common mode voltage VC is extremely biased from the vicinity of VDD / 2 to the VSS side, the DC specification of the output common mode voltage VC can be satisfied and the yield can be improved. Can do.

(Second Embodiment)
FIG. 5 is a circuit diagram showing a second embodiment of the present invention. In the second embodiment 95 of the present invention, the source of the PMOS transistor 87 of the VC setting unit 82 is connected to the VDD power supply line 68, and the constant current source 88 is connected to the drain of the PMOS transistor 87 of the VC setting unit 82 and the signal transmission unit 71. It connects between the 1st power supply terminal 71A, and others are comprised similarly to 1st Embodiment 62 of this invention.

  FIG. 6 is a circuit diagram showing a first configuration example of the bias circuit for the PMOS transistor 89 used in the second embodiment 95 of the present invention. In FIG. 6, 137 is a bias circuit, 138 is a PMOS transistor, and 139 and 140 are resistors. The PMOS transistor 138 has a source connected to the VDD power supply line 68 via the resistor 139, a gate connected to the drain, a drain connected to the VSS power supply line 69 via the resistor 140, and a gate bias voltage VBP applied to the drain. Have been to get. The drain of the PMOS transistor 138 is connected to the gate of the PMOS transistor 89, and the PMOS transistor 138 and the PMOS transistor 89 constitute a current mirror circuit.

  The bias circuit 137 is provided with a resistor 139 as a linear element between the VDD power line 68 and the source of the PMOS transistor 138 as a replica element of the PMOS transistor 87, and a gate-source voltage | VGS | By increasing the channel conductance, the channel conductance | gm | is adjusted to suppress variations in the output differential voltage VD.

  FIG. 7 is a circuit diagram showing a second configuration example of the bias circuit for the PMOS transistor 89 used in the second embodiment 95 of the present invention. In FIG. 7, reference numeral 141 denotes a bias circuit. The bias circuit 141 is provided with a PMOS transistor 142 instead of the resistor 139 provided in the bias circuit 137 shown in FIG. It is. In the bias circuit 141, the same effect as that of the bias circuit 137 can be obtained by setting the gate voltage VGP in a range in which the operation region of the PMOS transistor 142 is a linear region.

  Also in the second embodiment 95 of the present invention, for example, when VDD = 1.2V and VSS = 0V, the DC specifications are the output differential voltage VD = 0.2 Vp-p, the output common mode voltage VC = 0. Assuming 2 V, when the input signal SA is logic 1 (H level), 0.9 V is applied between the VDD power line 68 and the external output terminal 63, and the external output terminal 64 and the VSS power line 69 In between, 0.1V is applied. When the input signal SA is logic 0 (L level), 0.9 V is applied between the VDD power supply line 68 and the external output terminal 64, and between the external output terminal 63 and the VSS power supply line 69. 0.1V is applied. Therefore, whether the input signal SA is logic 1 (H level) or logic 0 (L level), a sufficient voltage is secured as the source-drain voltage VSD of the PMOS transistor 89 constituting the constant current source 88. be able to.

  For example, when VDD = 1.2V and VSS = 0V, the DC specifications of the second embodiment 95 of the present invention are as follows: output differential voltage VD = 0.2 Vp-p, output common mode voltage VC = VDD / Assuming 2 = 0.6 V, when the input signal SA is logic 1 (H level), between the VDD power supply line 68 and the external output terminal 63 and between the external output terminal 64 and the VSS power supply line 69. 0.5V is applied. When the input signal SA is logic 0 (L level), 0.5 V is applied between the VDD power supply line 68 and the external output terminal 64 and between the external output terminal 63 and the VSS power supply line 69. Also in this case, a sufficient voltage can be secured as the source-drain voltage VSD of the PMOS transistor 89 constituting the constant current source 88.

  As described above, according to the second embodiment 95 of the present invention, when the VC setting unit 82 is provided upstream of the signal transmission unit 71 on the current path from the VDD power supply line 68 to the VSS power supply line 69, the constant current Since the source 88 is connected between the drain of the PMOS transistor 87 of the VC setting unit 82 and the first power supply terminal 71A of the signal transmission unit 71, the DC specification of the output common mode voltage VC is near VDD / 2. Even when it is extremely biased from the VSS to the VSS side, the source-drain voltage VSD of the PMOS transistor 89 constituting the constant current source 88 can be sufficiently secured. Therefore, even when the DC specification of the output common mode voltage VC is extremely biased from the vicinity of VDD / 2 to the VSS side, the DC specification of the output common mode voltage VC can be satisfied and the yield can be improved. Can do.

(Third embodiment)
FIG. 8 is a circuit diagram showing a third embodiment of the present invention. In FIG. 8, 101 is a transmission-side LSI, 102 is a third embodiment of the present invention provided in the LSI 101, 103 and 104 are external output terminals (second and third signal terminals) of the LSI 101, and 105 is an external output terminal 103. , A signal wiring connected to the external output terminal 104, a termination resistor (for example, 100Ω) connected between the signal wirings 105 and 106, and a receiving-side LSI not shown doing.

  The third embodiment 102 of the present invention is a differential output circuit suitable for application when the DC specification of the output common mode voltage VC is extremely biased from VDD / 2 to the VDD side. In the third embodiment 102 of the present invention, reference numeral 108 denotes a VDD power supply line (first power supply line), 109 denotes a VSS power supply line (second power supply line), and 110 denotes an internal circuit (not shown). An internal signal terminal (first signal terminal) to which an input signal SA to 102 is applied.

  111 is a signal transmission unit, 112 is an output buffer (first output buffer) that inputs an input signal SA and outputs an in-phase output signal SP, and 113 is an input signal SA that is input and receives an anti-phase output signal SN. Is an output buffer (second output buffer).

  In the output buffer 112, 114 is an inverter, 115 is a buffer formed by cascading two inverters, and 116 and 117 are PMOS transistors constituting an output circuit composed of a totem pole circuit. In the output buffer 113, 118 is a buffer formed by cascading two inverters, 119 is an inverter, and 120 and 121 are PMOS transistors constituting an output circuit composed of a totem pole circuit.

  The inverter 114 has an input terminal connected to the internal input terminal 110 and an output terminal connected to the gate of the PMOS transistor 116. The buffer 115 has an input terminal connected to the internal signal terminal 110 and an output terminal connected to the gate of the PMOS transistor 117.

  The PMOS transistor 116 has a source connected to the first power supply terminal 111 A of the signal transmission unit 111, a drain connected to the source of the PMOS transistor 117, and the PMOS transistor 117 has a drain connected to the second power supply terminal of the signal transmission unit 111. 111B. The connection point between the drain of the PMOS transistor 116 and the source of the PMOS transistor 117 is connected to the external output terminal 103.

  The buffer 118 has an input terminal connected to the internal signal terminal 110 and an output terminal connected to the gate of the PMOS transistor 120. The inverter 119 has an input terminal connected to the internal signal terminal 110 and an output terminal connected to the gate of the PMOS transistor 121.

  The PMOS transistor 120 has a source connected to the first power supply terminal 111 A of the signal transmission unit 111, a drain connected to the source of the PMOS transistor 121, and the PMOS transistor 121 has a drain connected to the second power supply terminal of the signal transmission unit 111. 111B. A connection point between the drain of the PMOS transistor 120 and the source of the PMOS transistor 121 is connected to the external output terminal 104. The first power supply terminal 111A of the signal transmission unit 111 is connected to the VDD power supply line 108.

  In the third embodiment 102 of the present invention, the output circuit in the output buffer 112 is constituted by a totem pole circuit composed of PMOS transistors 116 and 117, and the output circuit in the output buffer 113 is a totem pole circuit composed of PMOS transistors 120 and 121. This is to reduce the influence of the substrate bias effect.

  Reference numeral 122 denotes a VC setting unit (output common mode voltage setting unit) for setting the output common mode voltage VC, and 123 and 124 denote VCM detection circuits (differential differential signals) for detecting the average voltage VCM of the output signal SP and the output signal SN. The resistor constituting the output signal average voltage detection circuit), 125 is a common mode voltage setting terminal to which the common mode voltage VOS is applied, 126 is an operational amplifier, and 127 is a power supply voltage applied to the second power supply terminal 111B of the signal transmission unit 111. This is an NMOS transistor forming a variable resistance element. The resistors 123 and 124 have sufficiently larger resistance values than the termination resistor 107.

  The resistors 123 and 124 are connected in series between the external output terminals 103 and 104, and the connection point of the resistors 123 and 124 is connected to the non-inverting input terminal of the operational amplifier 126. The common mode voltage setting terminal 125 is connected to the inverting input terminal of the operational amplifier 126. The output terminal of the operational amplifier 126 is connected to the gate of the NMOS transistor 127, and the drain of the NMOS transistor 127 is connected to the second power supply terminal 111 B of the signal transmission unit 111.

  Also, 128 is a constant current source, 129 is an NMOS transistor, and VBN is a gate bias voltage of the NMOS transistor 129. The NMOS transistor 129 has a drain connected to the source of the NMOS transistor 127 via the current input terminal 128A of the constant current source 128, and a source connected to the VSS power supply line 109 via the current output terminal 128B of the constant current source 128. Yes.

  FIG. 9 is a circuit diagram showing a configuration example of a bias circuit for generating the gate bias voltage VBN. In FIG. 9, 131 is a bias circuit, 132 is an NMOS transistor, and 133 is a resistor. The NMOS transistor 132 has a source connected to the VSS power supply line 109, a gate connected to the drain, a drain connected to the VDD power supply line 108 via the resistor 133, and a gate bias voltage VBN obtained at the drain. Yes. The drain of the NMOS transistor 132 is connected to the gate of the NMOS transistor 129, and the NMOS transistor 132 and the NMOS transistor 129 constitute a current mirror circuit.

  10A and 10B are diagrams showing current paths for determining the output voltages of the external output terminals 103 and 104. FIG. 10A shows a case where the input signal SA is logic 1 (H level), and FIG. This is the case of (L level).

  Here, for example, when VDD = 1.2V and VSS = 0V, the DC specifications of the third embodiment 102 of the present invention are the output differential voltage VD = 0.2 Vp-p, the output common mode voltage VC = 1. Assuming that the input signal SA is logic 1 (H level), 0.1 V is applied between the VDD power supply line 108 and the external output terminal 103 as shown in FIG. 0.9 V is applied between the output terminal 104 and the VSS power supply line 109. When the input signal SA is logic 0 (L level), as shown in (B), 0.1 V is applied between the VDD power supply line 108 and the external output terminal 104, and the external output terminal 103 and VSS are connected. A voltage of 0.9 V is applied to the power supply line 109. Therefore, whether the input signal SA is logic 1 (H level) or logic 0 (L level), a sufficient voltage is secured as the drain-source voltage VDS of the NMOS transistor 129 constituting the constant current source 128. be able to.

  For example, when VDD = 1.2V and VSS = 0V, the DC specifications of the third embodiment 102 of the present invention are the output differential voltage VD = 0.2 Vp-p, the output common mode voltage VC = 0. Assuming 6V, when the input signal SA is logic 1 (H level), 0.5V is applied between the VDD power supply line 108 and the external output terminal 103 and between the external output terminal 104 and the VSS power supply line 109. Applied. When the input signal SA is logic 0 (L level), 0.5 V is applied between the VDD power supply line 108 and the external output terminal 104 and between the external output terminal 103 and the VSS power supply line 109. Also in this case, a sufficient voltage can be secured as the drain-source voltage VDS of the NMOS transistor 129 constituting the constant current source 128.

  As described above, according to the third embodiment 102 of the present invention, when the VC setting unit 122 is provided downstream of the signal transmission unit 111 on the current path from the VDD power supply line 108 to the VSS power supply line 109, the constant current Since the source 128 is connected between the source of the NMOS transistor 127 of the VC setting unit 122 and the VSS power supply line 109, the DC specification of the output common mode voltage VC is extremely biased from the vicinity of VDD / 2 to the VDD side. Even in this case, the drain-source voltage VDS of the NMOS transistor 129 constituting the constant current source 128 can be sufficiently secured. Therefore, even when the DC specification of the output common mode voltage VC is extremely biased from the vicinity of VDD / 2 to the VDD side, the DC specification of the output common mode voltage VC can be satisfied and the yield can be improved. Can do.

(Fourth embodiment)
FIG. 11 is a circuit diagram showing a fourth embodiment of the present invention. In the fourth embodiment 135 of the present invention, the source of the NMOS transistor 127 of the VC setting unit 122 is connected to the VSS power supply line 109, and the constant current source 128 is connected to the second power supply terminal 111B of the signal transmission unit 111 and the VC setting unit 122. The other transistors are connected in the same manner as the third embodiment 102 of the present invention.

  FIG. 12 is a circuit diagram showing a first configuration example of the bias circuit for the NMOS transistor 129 used in the fourth embodiment 135 of the present invention. In FIG. 12, 144 is a bias circuit, 145 is an NMOS transistor, and 146 and 147 are resistors. The NMOS transistor 145 has a drain connected to the VDD power supply line 108 via the resistor 146, a gate connected to the drain, a source connected to the VSS power supply line 109 via the resistor 147, and a gate bias voltage VBN applied to the drain. Have been to get. The drain of the NMOS transistor 145 is connected to the gate of the NMOS transistor 129, and the NMOS transistor 145 and the NMOS transistor 129 constitute a current mirror circuit.

  The bias circuit 144 is provided with a resistor 147 as a linear element between the source of the NMOS transistor 145 and the VSS power supply line 109 as a replica element of the NMOS transistor 127, and a gate-source voltage | VGS | By increasing the channel conductance, the channel conductance | gm | is adjusted to suppress variations in the output differential voltage VD.

  FIG. 13 is a circuit diagram showing a second configuration example of the bias circuit for the NMOS transistor 129 used in the fourth embodiment 135 of the present invention. In FIG. 13, reference numeral 148 denotes a bias circuit, and the bias circuit 148 is provided with an NMOS transistor 149 instead of the resistor 147 included in the bias circuit 144 shown in FIG. It is. In the bias circuit 148, the same effect as that of the bias circuit 144 can be obtained by setting the gate voltage VGN within a range in which the operation region of the NMOS transistor 149 is a linear region.

  Also in the fourth embodiment 135 of the present invention, when VDD = 1.2V and VSS = 0V, the DC specifications are the output differential voltage VD = 0.2Vp-p, the output common mode voltage VC = 1.0V. Then, when the input signal SA is logic 1 (H level), 0.1 V is applied between the VDD power supply line 108 and the external output terminal 103, and between the external output terminal 104 and the VSS power supply line 109. Is applied with 0.9V. When the input signal SA is logic 0 (L level), 0.1 V is applied between the VDD power supply line 108 and the external output terminal 104, and between the external output terminal 103 and the VSS power supply line 109. 0.9V is applied. Therefore, whether the input signal SA is logic 1 (H level) or logic 0 (L level), a sufficient voltage is secured as the drain-source voltage VDS of the NMOS transistor 129 constituting the constant current source 128. be able to.

  For example, when VDD = 1.2V and VSS = 0V, the DC specifications of the fourth embodiment 135 of the present invention are the output differential voltage VD = 0.2 Vp-p and the output common mode voltage VC = 0. Assuming 6V, when the input signal SA is logic 1 (H level), 0.5V is applied between the VDD power supply line 108 and the external output terminal 103 and between the external output terminal 104 and the VSS power supply line 109. Applied. When the input signal SA is logic 0 (L level), 0.5 V is applied between the VDD power supply line 108 and the external output terminal 104 and between the external output terminal 103 and the VSS power supply line 109. Also in this case, a sufficient voltage can be secured as the drain-source voltage VDS of the NMOS transistor 129 constituting the constant current source 128.

  As described above, according to the fourth embodiment 135 of the present invention, when the VC setting unit 122 is provided downstream of the signal transmission unit 111 on the current path from the VDD power supply line 108 to the VSS power supply line 109, the constant current Since the source 128 is connected between the second power supply terminal 111B of the signal transmission unit 111 and the drain of the NMOS transistor 127 of the VC setting unit 122, the DC specification of the output common mode voltage VC is near VDD / 2. Even when it is extremely biased from the VDD to the VDD side, the drain-source voltage VDS of the NMOS transistor 129 constituting the constant current source 128 can be sufficiently secured. Therefore, even when the DC specification of the output common mode voltage VC is extremely biased from the vicinity of VDD / 2 to the VDD side, the DC specification of the output common mode voltage VC can be satisfied and the yield can be improved. Can do.

(Fifth embodiment)
FIG. 14 is a circuit diagram showing a fifth embodiment of the present invention. The fifth embodiment 152 of the present invention is an improvement of the first embodiment 62 of the present invention shown in FIG. 1, and is different in VC setting from the VC setting unit 82 provided in the first embodiment 62 of the present invention. The unit 153 is provided, the current output terminal 88B of the constant current source 88 is connected to the first power supply terminal 71A of the signal transmission unit 71, and the others are configured similarly to the first embodiment 62 of the present invention. .

  The VC setting unit 153 includes an NMOS transistor 154 as a variable resistance element instead of the PMOS transistor 87 provided in the VC setting unit 82 shown in FIG. The output terminal of the operational amplifier 86 is connected to the gate of the NMOS transistor 154. The drain of the NMOS transistor 154 is connected to the current output terminal 88 B of the constant current source 88, and the source of the NMOS transistor 154 is connected to the VSS power supply line 69. Others are configured in the same manner as the VC setting unit 82.

  15A and 15B are diagrams showing current paths for determining the output voltages of the external output terminals 63 and 64. FIG. 15A shows a case where the input signal SA is logic 1 (H level), and FIG. This is the case of (L level).

  Here, for example, when VDD = 1.2V and VSS = 0V, the DC specifications of the fifth embodiment 152 of the present invention are the output differential voltage VD = 0.2 Vp-p and the output common mode voltage VC = 0. Assuming that the input signal SA is logic 1 (H level), 0.9 V is applied between the VDD power supply line 68 and the external output terminal 63 as shown in FIG. 0.1 V is applied between the output terminal 64 and the VSS power supply line 69. When the input signal SA is logic 0 (L level), 0.9V is applied between the VDD power supply line 68 and the external output terminal 64 as shown in FIG. A voltage of 0.1 V is applied to the power supply line 69. Therefore, whether the input signal SA is logic 1 (H level) or logic 0 (L level), a sufficient voltage is secured as the source-drain voltage VSD of the PMOS transistor 89 constituting the constant current source 88. be able to.

  For example, when VDD = 1.2V and VSS = 0V, the DC specifications of the fifth embodiment 152 of the present invention are as follows: output differential voltage VD = 0.2 Vp-p, output common mode voltage VC = VDD / Assuming 2 = 0.6 V, when the input signal SA is logic 1 (H level), between the VDD power supply line 68 and the external output terminal 63 and between the external output terminal 64 and the VSS power supply line 69. 0.5V is applied. When the input signal SA is logic 0 (L level), 0.5 V is applied between the VDD power supply line 68 and the external output terminal 64 and between the external output terminal 63 and the VSS power supply line 69. Also in this case, a sufficient voltage can be secured as the source-drain voltage VSD of the PMOS transistor 89 constituting the constant current source 88.

  The fifth embodiment 152 of the present invention can be used as, for example, a differential interface circuit for transferring image data in a mobile phone. It has become common for the required specifications of such a differential interface circuit for image data transfer to include the reflection characteristic indicated by the S parameter. The fifth embodiment 152 of the present invention can sufficiently satisfy such required specifications. Hereinafter, this point will be described.

  In the fifth embodiment 152 of the present invention, when the input signal SA = logic 1 (H level), as shown in FIG. 15A, the VDD power line 68 (fixed end) and the VSS power supply from the external output terminal 63 In the path to the line 69A (fixed end), there is a series circuit of an NMOS transistor 76 and a PMOS transistor 89 and an NMOS transistor 154 that can be seen as being connected in parallel. In addition, an NMOS transistor 81 exists in the path from the external output terminal 64 to the VSS power supply line 69B (fixed end).

  When the input signal SA = logic 0 (L level), as shown in FIG. 15B, an NMOS transistor 80 and a path from the external output terminal 64 to the VDD power supply line 68 and the VSS power supply line 69A, There is a series circuit with PMOS transistor 89 and NMOS transistor 154 that can be seen as being connected in parallel. Further, an NMOS transistor 77 exists in the path from the external output terminal 63 to the VSS power supply line 69B.

  Here, when the input signal SA = logic 1 (H level), the DC resistance value between the external output terminal 63 and the VDD power supply line 68 and the VSS power supply line 69A is 50Ω, and the external output terminal 64 and the VSS power supply line 69B If the parasitic resistance due to the LSI package or the like is ignored, the output impedance on the fifth embodiment 152 side of the present invention viewed from the external output terminal 63 and the external output terminal 64 can be considered. In addition, the output impedance on the side of the fifth embodiment 152 of the present invention can be matched with the characteristic impedance (usually about 50Ω) of the transmission line connected to the external output terminal.

  When the input signal SA = logic 0 (L level), the DC resistance value between the external output terminal 64 and the VDD power supply line 68 and the VSS power supply line 69A is 50Ω, and the external output terminal 63 and the VSS power supply line 69B If the DC resistance value between them can be 50Ω, the output impedance on the fifth embodiment 152 side of the present invention viewed from the external output terminal 63 and the fifth embodiment 152 side of the present invention viewed from the external output terminal 64 The output impedance can be matched with the characteristic impedance (50Ω).

  Thus, the output impedance on the fifth embodiment 152 side of the present invention viewed from the external output terminal 63 and the output impedance on the fifth embodiment 152 side of the present invention viewed from the external output terminal 64 are both characteristic impedance (50Ω). , The reflection coefficients at the external output terminals 63 and 64 can be set to 0, and the values of the S parameters Sdd11, Scc11, and Scd11 can be improved.

  For example, if the DC resistance value of the PMOS transistor 89 is 120Ω, the DC resistance value of the NMOS transistor 154 is 60Ω, the DC resistance value of the NMOS transistors 76 and 80 is 10Ω, and the DC resistance value of the NMOS transistors 77 and 81 is 50Ω, The DC resistance value on the fifth embodiment 152 side of the present invention viewed from the output terminal 63 and the DC resistance value on the fifth embodiment 152 side of the present invention viewed from the external output terminal 64 are both 50Ω, and from the external output terminal 63 The output impedance on the fifth embodiment 152 side of the present invention as viewed and the output impedance on the fifth embodiment 152 side of the present invention viewed from the external output terminal 64 can both coincide with the characteristic impedance (50Ω).

  FIG. 16 is a circuit diagram showing a reflection measurement model of the fifth embodiment 152 of the present invention. In FIG. 16, Rp is a DC resistance component between the external output terminal 63 and the VDD power supply line 68 and the VSS power supply line 69A, Rn is a DC resistance component between the external output terminal 64 and the VSS power supply line 69B, and Cp is parasitic. Capacitance (usually about 1 to 2 pF), Rs is a terminating resistor, and Sip and Sin are signal sources.

  Here, the S parameters Sdd11, Scc11, and Scd11 are defined as shown in Equation 1.

  Where Γdd11 is a reflection coefficient indicating the relationship between the differential input and the differential output, Γcc11 is a reflection coefficient indicating the relationship between the in-phase input and the in-phase output, and Γcd11 is a reflection coefficient indicating the relationship between the differential input and the in-phase output. is there. Vid is a differential input, Vic is an in-phase input, Vrd is a differential reflection, and Vrc is an in-phase reflection, which are defined as shown in Equation (2).

  Where vip is an input voltage to the external output terminal 63, vin is an input voltage to the external output terminal 64, vrp is a reflected voltage from the external output terminal 63, and vrn is a reflected voltage from the external output terminal 64.

  When Rp = 50Ω, Rn = 50Ω, Rs = 50Ω, and Cp = 0pF, the reflection coefficient Γp at the external output terminal 63 and the reflection coefficient Γn at the external output terminal 64 are as shown in Equation 3.

  Therefore, theoretically, the S parameters Sdd11, Scc11, and Scd11 are as shown in Equation 4.

  FIG. 17 is a diagram showing the frequency characteristics of the S parameter Sdd11 obtained by executing circuit simulation on the reflection measurement model shown in FIG. In FIG. 17, the horizontal axis represents the signal frequency [GHz], the vertical axis represents the value of Sdd11 [dB], Sdd11 = 0 [dB], total reflection, and Sdd11 = −∞ [dB], no reflection. Means.

  According to the circuit simulation result shown in FIG. 17, when the frequency of the signal≈0 [Hz], Sdd11≈−16 [dB]. For example, the reflection specification of the differential interface circuit for transferring image data used in a cellular phone may require a frequency range of 1 GHz or less and a maximum value of Sdd11 = −14 [dB]. The fifth embodiment 152 satisfies this specification.

  FIG. 18 is a diagram showing the frequency characteristics of the S parameter Scd11 obtained by executing circuit simulation on the reflection measurement model shown in FIG. In FIG. 18, the horizontal axis represents the signal frequency [GHz] and the vertical axis represents the value of Scd11 [dB]. When Scd11 = 0 [dB], total reflection, and when Scd11 = −∞ [dB], there is no reflection. Means.

  According to the circuit simulation result shown in FIG. 18, when the signal frequency is approximately 0 [Hz], Scd11 is approximately −44 [dB]. For example, the maximum value of Scd11 = −26 [dB] may be required as the reflection specification of the differential interface circuit for transferring image data used in a mobile phone. The fifth embodiment 152 of the present invention is This specification is satisfied.

  As described above, according to the fifth embodiment 152 of the present invention, when the constant current source 88 is provided upstream of the signal transmission unit 71 on the current path from the VDD power supply line 68 to the VSS power supply line 69, VC setting is performed. Since the NMOS transistor 154 forming the variable resistance element of the unit 153 is connected between the current output terminal 88B of the constant current source 88 and the VSS power supply line 69, the DC specification of the output common mode voltage VC is from around VDD / 2. Even when it is extremely biased to the VSS side, the source-drain voltage VSD of the PMOS transistor 89 constituting the constant current source 88 can be sufficiently secured. Therefore, even when the DC specification of the output common mode voltage VC is extremely biased from the vicinity of VDD / 2 to the VSS side, the DC specification of the output common mode voltage VC can be satisfied and the yield can be improved. Can do.

  In addition, since the NMOS transistor 154 forming the variable resistance element of the VC setting unit 153 is connected between the current output terminal 88B of the constant current source 88 and the VSS power supply line 69, the PMOS transistor 89 and the NMOS transistors 76, 77, By adjusting the DC resistance values of 80, 81 and 154, the output impedance on the fifth embodiment 152 side of the present invention viewed from the external output terminal 63 and the fifth embodiment 152 of the present invention viewed from the external output terminal 64 are shown. The output impedance on the side can be matched with the characteristic impedance. Therefore, the reflection characteristics can be improved.

  In addition, since the number of transistors between the VDD power supply line 68 and the signal transmission unit 71 is one stage of the PMOS transistor 89 of the constant current source 88, the power supply voltage VDD is lowered to reduce the power consumption. Can do.

(Sixth embodiment)
FIG. 19 is a circuit diagram showing a sixth embodiment of the present invention. The sixth embodiment 165 of the present invention is an improvement of the second embodiment 95 of the present invention shown in FIG. 5, and is a constant current having a circuit configuration different from that of the constant current source 88 provided in the second embodiment 82 of the present invention. The source 166 is provided, the drain of the PMOS transistor 87 of the VC setting unit 82 is connected to the first power supply terminal 71A of the signal transmission unit 71, and the others are configured similarly to the second embodiment 95 of the present invention. is there.

  The constant current source 166 includes an NMOS transistor 167 instead of the PMOS transistor 89 provided in the constant current source 88 shown in FIG. The drain of the NMOS transistor 167 is connected to the drain of the PMOS transistor 87 of the VC setting unit 82 via the current input terminal 166A of the constant current source 166. The source of the NMOS transistor 167 is connected to the VSS power supply line 69 via the current output terminal 166B of the constant current source 166. A gate bias voltage VBN is applied to the gate of the NMOS transistor 167.

  20A and 20B are diagrams showing current paths for determining the output voltages of the external output terminals 63 and 64. FIG. 20A shows a case where the input signal SA is logic 1 (H level), and FIG. This is the case of (L level).

  Here, for example, when VDD = 1.2V and VSS = 0V, the DC specifications of the sixth embodiment 165 of the present invention are the output differential voltage VD = 0.2 Vp-p, the output common mode voltage VC = 0. Assuming that the input signal SA is logic 1 (H level), 0.9 V is applied between the VDD power supply line 68 and the external output terminal 63 as shown in FIG. 0.1 V is applied between the output terminal 64 and the VSS power supply line 69. When the input signal SA is logic 0 (L level), 0.9V is applied between the VDD power supply line 68 and the external output terminal 64 as shown in FIG. A voltage of 0.1 V is applied to the power supply line 69.

  In addition, whether the input signal SA is logic 1 (H level) or logic 0 (L level), 1.2 V is applied between the source of the PMOS transistor 87 and the source of the NMOS transistor 167. . Therefore, whether the input signal SA is logic 1 (H level) or logic 0 (L level), a sufficient voltage is secured as the drain-source voltage VDS of the NMOS transistor 167 constituting the constant current source 166. be able to.

  For example, when VDD = 1.2V and VSS = 0V, the DC specifications of the second embodiment 95 of the present invention are as follows: output differential voltage VD = 0.2 Vp-p, output common mode voltage VC = VDD / Assuming 2 = 0.6 V, when the input signal SA is logic 1 (H level), between the VDD power supply line 68 and the external output terminal 63 and between the external output terminal 64 and the VSS power supply line 69. 0.5V is applied. When the input signal SA is logic 0 (L level), 0.5 V is applied between the VDD power supply line 68 and the external output terminal 64 and between the external output terminal 63 and the VSS power supply line 69.

  In addition, whether the input signal SA is logic 1 (H level) or logic 0 (L level), 1.2 V is applied between the source of the PMOS transistor 87 and the source of the NMOS transistor 167. . Also in this case, a sufficient voltage can be secured as the drain-source voltage VDS of the NMOS transistor 167 constituting the constant current source 166.

  In the sixth embodiment 165 of the present invention, when the input signal SA = logic 1 (H level), as shown in FIG. 20A, the VDD power supply line 68 and the VSS power supply line 69A are connected from the external output terminal 63. In the path up to, there is a series circuit of an NMOS transistor 76 and a PMOS transistor 87 and an NMOS transistor 167 that can be regarded as being connected in parallel. In addition, an NMOS transistor 81 exists in the path from the external output terminal 64 to the VSS power supply line 69B.

  When the input signal SA = logic 0 (L level), as shown in FIG. 20B, an NMOS transistor 80 and a path from the external output terminal 64 to the VDD power supply line 68 and the VSS power supply line 69A are provided. There is a series circuit of PMOS transistor 87 and NMOS transistor 167 that can be seen as being connected in parallel. Further, an NMOS transistor 77 exists in the path from the external output terminal 63 to the VSS power supply line 69B.

  Here, when the input signal SA = logic 1 (H level), the DC resistance value between the external output terminal 63 and the VDD power supply line 68 and the VSS power supply line 69A is 50Ω, and the external output terminal 64 and the VSS power supply line 69B If the DC resistance value between them can be 50Ω, the output impedance on the sixth embodiment 165 side of the present invention viewed from the external output terminal 63 and the sixth embodiment 165 side of the present invention viewed from the external output terminal 64 Can be made to match the characteristic impedance (50Ω).

  When the input signal SA = logic 0 (L level), the DC resistance value between the external output terminal 64 and the VDD power supply line 68 and the VSS power supply line 69A is 50Ω, and the external output terminal 63 and the VSS power supply line 69B If the DC resistance value between them can be 50Ω, the output impedance on the sixth embodiment 165 side of the present invention viewed from the external output terminal 63 and the sixth embodiment 165 side of the present invention viewed from the external output terminal 64 The output impedance can be matched with the characteristic impedance (50Ω).

  Thus, the output impedance on the sixth embodiment 165 side of the present invention viewed from the external output terminal 63 and the output impedance on the sixth embodiment 165 side of the present invention viewed from the external output terminal 64 are both characteristic impedance (50Ω). , The reflection coefficients at the external output terminals 63 and 64 can be set to 0, and the values of the S parameters Sdd11, Scc11, and Scd11 can be improved.

  For example, when the DC resistance value of the PMOS transistor 87 is 120Ω, the DC resistance value of the NMOS transistor 167 is 60Ω, the DC resistance value of the NMOS transistors 76 and 80 is 10Ω, and the DC resistance value of the NMOS transistors 77 and 81 is 50Ω, The DC resistance value on the sixth embodiment 165 side of the present invention viewed from the output terminal 63 and the DC resistance value on the sixth embodiment 165 side of the present invention viewed from the external output terminal 64 are both 50Ω, and from the external output terminal 63 The output impedance on the sixth embodiment 165 side of the present invention as viewed and the output impedance on the sixth embodiment 165 side of the present invention viewed from the external output terminal 64 can both coincide with the characteristic impedance (50Ω).

  As described above, according to the sixth embodiment 165 of the present invention, when the VC setting unit 82 is provided upstream of the signal transmission unit 71 on the current path from the VDD power supply line 68 to the VSS power supply line 69, the constant current Since the source 166 is connected between the source of the PMOS transistor 87 forming the variable resistance element of the VC setting unit 82 and the VSS power supply line 69, the DC specification of the output common mode voltage VC is changed from the vicinity of VDD / 2 to the VSS side. Even in an extremely biased case, the drain-source voltage VDS of the NMOS transistor 167 constituting the constant current source 166 can be sufficiently secured. Therefore, even when the DC specification of the output common mode voltage VC is extremely biased from the vicinity of VDD / 2 to the VSS side, the DC specification of the output common mode voltage VC can be satisfied and the yield can be improved. Can do.

  Further, since the constant current source 166 is connected between the drain of the PMOS transistor 87 of the VC setting unit 82 and the VSS power supply line 69, the DC resistance of the PMOS transistor 87 and the NMOS transistors 76, 77, 80, 81, 167. By adjusting the value, the output impedance of the sixth embodiment 165 side of the present invention viewed from the external output terminal 63 and the output impedance of the sixth embodiment 165 side of the present invention viewed from the external output terminal 64 are both characteristic impedances. Can be matched. Therefore, the reflection characteristics can be improved.

  Since the number of transistors between the VDD power supply line 68 and the signal transmission unit 71 is one stage of the PMOS transistor 87 that forms the variable resistance element of the VC setting unit 82, the power supply voltage VDD is reduced to reduce the power consumption. Reduction can be achieved.

(Seventh embodiment)
FIG. 21 is a circuit diagram showing a seventh embodiment of the present invention. The seventh embodiment 172 of the present invention is an improvement of the third embodiment 102 of the present invention shown in FIG. 8, and VC setting having a circuit configuration different from that of the VC setting unit 122 provided in the third embodiment 102 of the present invention. The second power supply terminal 111B of the signal transmission unit 111 is connected to the current input terminal 128A of the constant current source 128, and the others are configured similarly to the third embodiment 102 of the present invention. .

  The VC setting unit 173 includes a PMOS transistor 174 as a variable resistance element instead of the NMOS transistor 127 provided in the VC setting unit 122 shown in FIG. The output terminal of the operational amplifier 126 is connected to the gate of the PMOS transistor 174. The source of the PMOS transistor 174 is connected to the VDD power supply line 108, and the drain of the PMOS transistor 174 is connected to the current input terminal 128 A of the constant current source 128. About others, it is comprised similarly to the VC setting part 122. FIG.

  22A and 22B are diagrams showing current paths for determining the output voltages of the external output terminals 103 and 104. FIG. 22A shows a case where the input signal SA is logic 1 (H level), and FIG. This is the case of (L level).

  Here, for example, when VDD = 1.2V and VSS = 0V, the DC specifications of the seventh embodiment 172 of the present invention are the output differential voltage VD = 0.2 Vp-p, the output common mode voltage VC = 1. Assuming that the input signal SA is logic 1 (H level), 0.1 V is applied between the VDD power supply line 108 and the external output terminal 103 as shown in FIG. 0.9 V is applied between the output terminal 104 and the VSS power supply line 109. When the input signal SA is logic 0 (L level), as shown in (B), 0.1 V is applied between the VDD power supply line 108 and the external output terminal 104, and the external output terminal 103 and VSS are connected. A voltage of 0.9 V is applied to the power supply line 109. Therefore, whether the input signal SA is logic 1 (H level) or logic 0 (L level), a sufficient voltage is secured as the drain-source voltage VDS of the NMOS transistor 129 constituting the constant current source 128. be able to.

  For example, when VDD = 1.2V and VSS = 0V, the DC specifications of the seventh embodiment 172 of the present invention are the output differential voltage VD = 0.2 Vp-p and the output common mode voltage VC = 0. Assuming 6V, when the input signal SA is logic 1 (H level), 0.5V is applied between the VDD power supply line 108 and the external output terminal 103 and between the external output terminal 104 and the VSS power supply line 109. Applied. When the input signal SA is logic 0 (L level), 0.5 V is applied between the VDD power supply line 108 and the external output terminal 104 and between the external output terminal 103 and the VSS power supply line 109. Also in this case, a sufficient voltage can be secured as the drain-source voltage VDS of the NMOS transistor 129 constituting the constant current source 128.

  In the seventh embodiment 172 of the present invention, when the input signal SA = logic 1 (H level), as shown in FIG. 22A, from the external output terminal 103 to the VDD power supply line 108A (fixed end). The PMOS transistor 116 exists in the path of. In addition, the PMOS transistor 121 and the NMOS transistor 174 that can be regarded as being connected in parallel are connected to the path from the external output terminal 104 to the VDD power supply line 108B (fixed end) and the VSS power supply line 109 (fixed end). A series circuit with transistor 129 exists.

  When the input signal SA = logic 0 (L level), as shown in FIG. 22B, the PMOS transistor 120 exists in the path from the external output terminal 104 to the VDD power supply line 108A. Further, a path from the external output terminal 103 to the VDD power supply line 108B and the VSS power supply line 109 includes a PMOS transistor 117 and a series circuit of a PMOS transistor 174 and an NMOS transistor 129 that can be regarded as being connected in parallel. To do.

  Here, when the input signal SA = logic 1 (H level), the DC resistance value between the external output terminal 103 and the VDD power supply line 108A is 50Ω, the external output terminal 104, the VDD power supply line 108B, and the VSS power supply line 109 Can be 50Ω, the output impedance on the seventh embodiment 172 side of the present invention viewed from the external output terminal 103 and the seventh embodiment 172 side of the present invention viewed from the external output terminal 104 Both output impedances can be made to match the characteristic impedance (50Ω).

  When the input signal SA = logic 0 (L level), the DC resistance value between the external output terminal 104 and the VDD power supply line 108A is 50Ω, the external output terminal 103, the VDD power supply line 108B, and the VSS power supply line 109. 7 can be set to 50Ω, the output impedance on the seventh embodiment 172 side of the present invention viewed from the external output terminal 103 and the seventh embodiment 172 of the present invention viewed from the external output terminal 104. Both output impedances can be made to coincide with the characteristic impedance (50Ω).

  Thus, the output impedance on the seventh embodiment 172 side of the present invention viewed from the external output terminal 103 and the output impedance on the seventh embodiment 172 side of the present invention viewed from the external output terminal 104 are both characteristic impedance (50Ω). , The reflection coefficients at the external output terminals 103 and 104 can be set to 0, and the values of the S parameters Sdd11, Scc11, and Scd11 can be improved.

  For example, if the DC resistance value of the NMOS transistor 129 is 120Ω, the DC resistance value of the PMOS transistor 174 is 60Ω, the DC resistance value of the PMOS transistors 117 and 121 is 10Ω, and the DC resistance value of the PMOS transistors 116 and 120 is 50Ω, Both the output impedance on the seventh embodiment 172 side of the present invention viewed from the output terminal 103 and the output impedance on the seventh embodiment 172 side of the present invention viewed from the external output terminal 104 are both 50Ω, and match the characteristic impedance (50Ω). Can be made.

  As described above, according to the seventh embodiment 172 of the present invention, when the constant current source 128 is provided downstream of the signal transmission unit 111 on the current path from the VDD power supply line 108 to the VSS power supply line 109, the VC setting is performed. Since the PMOS transistor 174 forming the variable resistance element of the unit 173 is connected between the VDD power line 108 and the current input terminal 128A of the constant current source 128, the DC specification of the output common mode voltage VC is from around VDD / 2. Even when it is extremely biased toward the VDD side, the drain-source voltage VDS of the NMOS transistor 129 constituting the constant current source 128 can be sufficiently secured. Therefore, even when the DC specification of the output common mode voltage VC is extremely biased from the vicinity of VDD / 2 to the VDD side, the DC specification of the output common mode voltage VC can be satisfied and the yield can be improved. Can do.

  Further, since the PMOS transistor 174 forming the variable resistance element of the VC setting unit 173 is connected between the VDD power supply line 108 and the current input terminal 128A of the constant current source 128, the PMOS transistors 116, 117, 120, 121, The seventh embodiment 172 of the present invention viewed from the external output terminal 104 and the output impedance on the seventh embodiment 172 side of the present invention viewed from the external output terminal 103 by adjusting the DC resistance value of 174 and the NMOS transistor 129. The output impedance on the side can be matched with the characteristic impedance. Therefore, the reflection characteristics can be improved.

  Since the number of transistors between the signal transmission unit 111 and the VSS power supply line 109 is one stage of the NMOS transistor 129 of the constant current source 128, the power supply voltage VDD is lowered to reduce power consumption. Can do.

(Eighth embodiment)
FIG. 23 is a circuit diagram showing an eighth embodiment of the present invention. The eighth embodiment 185 of the present invention is an improvement of the fourth embodiment 135 of the present invention shown in FIG. 11, and is a constant current having a circuit configuration different from that of the constant current source 128 provided by the fourth embodiment 135 of the present invention. The source 186 is provided, the second power supply terminal 111B of the signal transmission unit 111 is connected to the drain of the NMOS transistor 127 of the VC setting unit 122, and the others are configured similarly to the fourth embodiment 135 of the present invention. is there.

  The constant current source 186 includes a PMOS transistor 187 instead of the NMOS transistor 129 provided by the constant current source 128 shown in FIG. The source of the PMOS transistor 187 is connected to the VDD power supply line 108 via the current input terminal 186A of the constant current source 186. The drain of the PMOS transistor 187 is connected to the drain of the NMOS transistor 127 of the VC setting unit 122 via the current output terminal 186B of the constant current source 186. A gate bias voltage VBP is applied to the gate of the PMOS transistor 187.

  24A and 24B are diagrams showing current paths for determining the output voltages of the external output terminals 103 and 104. FIG. 24A shows a case where the input signal SA is logic 1 (H level), and FIG. This is the case of (L level).

  Here, for example, when VDD = 1.2V and VSS = 0V, the DC specifications of the eighth embodiment 185 of the present invention are the output differential voltage VD = 0.2 Vp-p, the output common mode voltage VC = 1. Assuming that the input signal SA is logic 1 (H level), 0.1 V is applied between the VDD power supply line 108 and the external output terminal 103 as shown in FIG. 0.9 V is applied between the output terminal 104 and the VSS power supply line 109. When the input signal SA is logic 0 (L level), as shown in (B), 0.1 V is applied between the VDD power supply line 108 and the external output terminal 104, and the external output terminal 103 and VSS are connected. A voltage of 0.9 V is applied to the power supply line 109.

  In addition, regardless of whether the input signal SA is logic 1 (H level) or logic 0 (L level), 1.2 V is applied between the source of the PMOS transistor 187 and the source of the NMOS transistor 127. Therefore, whether the input signal SA is logic 1 (H level) or logic 0 (L level), a sufficient voltage is secured as the source-drain voltage VSD of the PMOS transistor 187 constituting the constant current source 186. be able to.

  Further, for example, when VDD = 1.2V and VSS = 0V, the DC specifications of the eighth embodiment 185 of the present invention are the output differential voltage VD = 0.2 Vp-p, the output common mode voltage VC = 0. Assuming 6V, when the input signal SA is logic 1 (H level), 0.5V is applied between the VDD power supply line 108 and the external output terminal 103 and between the external output terminal 104 and the VSS power supply line 109. Applied. When the input signal SA is logic 0 (L level), 0.5 V is applied between the VDD power supply line 108 and the external output terminal 104 and between the external output terminal 103 and the VSS power supply line 109. Also in this case, a sufficient voltage can be secured as the drain-source voltage VDS of the PMOS transistor 187 constituting the constant current source 186.

  In the eighth embodiment 185 of the present invention, when the input signal SA = logic 1 (H level), as shown in FIG. 24A, the path from the external output terminal 103 to the VDD power supply line 108A is not present. , A PMOS transistor 116 is present. A path from the external output terminal 104 to the VDD power supply line 108B and the VSS power supply line 109 includes a PMOS transistor 121 and a series circuit of a PMOS transistor 187 and an NMOS transistor 127 that can be regarded as being connected in parallel. To do.

  When the input signal SA = logic 0 (L level), as shown in FIG. 24B, the PMOS transistor 120 exists in the path from the external output terminal 104 to the VDD power supply line 108A. A path from the external output terminal 103 to the VDD power supply line 108B and the VSS power supply line 109 includes a PMOS transistor 117 and a series circuit of a PMOS transistor 187 and an NMOS transistor 127 that can be considered to be connected in parallel. To do.

  Here, when the input signal SA = logic 1 (H level), the DC resistance value between the external output terminal 103 and the VDD power supply line 108A is 50Ω, the external output terminal 104, the VDD power supply line 108B, and the VSS power supply line 109 If the DC resistance value between them can be 50Ω, the output impedance on the eighth embodiment 185 side of the present invention viewed from the external output terminal 103 and the eighth embodiment 185 side of the present invention viewed from the external output terminal 104 Both output impedances can be made to match the characteristic impedance (50Ω).

  When the input signal SA is logic 0 (L level), the DC resistance value between the external output terminal 104 and the VDD power supply line 108A is 50Ω, and the external output terminal 103, the VDD power supply line 108B, and the VSS power supply line 109 If the DC resistance value between them can be 50Ω, the output impedance on the eighth embodiment 185 side of the present invention viewed from the external output terminal 103 and the eighth embodiment 185 side of the present invention viewed from the external output terminal 104 Both output impedances can be matched to the characteristic impedance (50Ω).

  Thus, the output impedance on the eighth embodiment 185 side of the present invention viewed from the external output terminal 103 and the output impedance on the eighth embodiment 185 side of the present invention viewed from the external output terminal 104 are both characteristic impedance (50Ω). , The reflection coefficients at the external output terminals 103 and 104 can be set to 0, and the values of the S parameters Sdd11, Scc11, and Scd11 can be improved.

  For example, if the DC resistance value of the NMOS transistor 127 is 120Ω, the DC resistance value of the PMOS transistor 187 is 60Ω, the DC resistance value of the PMOS transistors 117 and 121 is 10Ω, and the DC resistance value of the PMOS transistors 116 and 120 is 50Ω, The output impedance on the side of the eighth embodiment 185 of the present invention viewed from the output terminal 103 and the output impedance on the side of the eighth embodiment 185 of the present invention viewed from the external output terminal 104 are both 50Ω, and match the characteristic impedance (50Ω). Can be made.

  As described above, according to the eighth embodiment 185 of the present invention, when the VC setting unit 122 is provided downstream of the signal transmission unit 111 on the current path from the VDD power supply line 108 to the VSS power supply line 109, the constant current Since the source 186 is connected between the VDD power supply line 108 and the drain of the NMOS transistor 127 of the VC setting unit 122, the DC specification of the output common mode voltage VC is extremely biased from the vicinity of VDD / 2 to the VDD side. Even so, the source-drain voltage VSD of the PMOS transistor 187 constituting the constant current source 186 can be sufficiently secured. Therefore, even when the DC specification of the output common mode voltage VC is extremely biased from the vicinity of VDD / 2 to the VDD side, the DC specification of the output common mode voltage VC can be satisfied and the yield can be improved. Can do.

  Further, since the constant current source 186 is connected between the VDD power supply line 108 and the drain of the NMOS transistor 127 of the VC setting unit 122, the DC resistance of the PMOS transistors 116, 117, 120, 121, and 187 and the NMOS transistor 127 By adjusting the value, the output impedance of the eighth embodiment 185 side of the present invention viewed from the external output terminal 103 and the output impedance of the eighth embodiment 185 side of the present invention viewed from the external output terminal 104 are both characteristic impedances. Can be matched. Therefore, the reflection characteristics can be improved.

  Further, since the number of transistors between the signal transmission unit 111 and the VSS power supply line 109 is one stage of the NMOS transistor 127 that constitutes the variable resistance element of the VC setting unit 122, the power supply voltage VDD is lowered and the power consumption is reduced. Reduction can be achieved.

(Usage example of the embodiment of the present invention)
FIG. 25 is a block circuit diagram showing an example of a system using the embodiment of the present invention, and simply shows the configuration of a synchronous interface for image data and clock transfer provided in a mobile phone. In FIG. 25, reference numeral 190 denotes a camera module, 191 denotes a processor unit, and 192 denotes a display unit. The camera module 190, the processor unit 191 and the display unit 192 are configured by separate LSI chips. . These LSI chips are connected by a high-speed data transfer technique to transmit and receive image data and a clock.

  The camera module 190 A / D converts an analog image signal obtained by a CCD sensor or the like, converts it into serial data, and transfers it to the processor unit 191. Reference numeral 193 denotes a transmission unit, 194-1 and 194-n are multiplexers, 195-1 is a differential output circuit that complements and outputs image data output from the multiplexer 194-1, and 195-n is a multiplexer 194-n. It is a differential output circuit that complements and outputs image data to be output. The multiplexers 194-2 to 194- (n-1) and the differential output circuits 195-2 to 195- (n-1) are not shown. Reference numeral 196 denotes a differential output circuit that complements and outputs the clock CLK. As the differential output circuits 195-1 to 195-n and 196, the first to eighth embodiments of the present invention can be used.

  The processor unit 191 receives the image data DATA1a, / DATA1a to DATAna, / DATAna and the clocks CLK, / CLK transmitted by the transmission unit 193 of the camera module 190, and processes the image signal. Reference numeral 197 denotes a receiving unit, 198-1 is a differential input circuit for inputting image data DATA1a and / DATA1a, 198-n is a differential input circuit for inputting image data DATAna and / DATAna, and 199-1 is a differential input circuit. A demultiplexer 199-n demultiplexes the image data received by the circuit 198-1. The demultiplexer 199-n demultiplexes the image data received by the differential input circuit 198-n. The differential input circuits 198-2 to 198- (n-1) and demultiplexers 199-2 to 199- (n-1) are not shown. Reference numeral 200 denotes a differential input circuit for inputting clocks CLK and / CLK.

  Reference numeral 201 denotes a transmission unit, 202-1 and 202-n are multiplexers, 203-1 is a differential output circuit that complements and outputs image data output from the multiplexer 202-1, and 203-n is a multiplexer 202-. This is a differential output circuit that complements and outputs the image data output by n. The multiplexers 202-2 to 202- (n-1) and the differential output circuits 203-2 to 203- (n-1) are not shown. Reference numeral 204 denotes a differential output circuit that complements and outputs the clock CLK. As the differential output circuits 203-1 to 203-n and 204, the first to eighth embodiments of the present invention can be used.

  The display unit 192 inputs the image data DATA1b, / DATA1b to DATAnb, / DATAnb and clocks CLK, / CLK transmitted by the transmission unit 201 of the processor unit 191, and performs data display on a liquid crystal display panel or the like via a driver. . 205 is a receiving unit, 206-1 is a differential input circuit for inputting image data DATA1b and / DATA1b, 206-n is a differential input circuit for inputting image data DATAnb and / DATAnb, and 207-1 is a differential input. A demultiplexer that demultiplexes the image data received by the circuit 206-1, and 207-n is a demultiplexer that demultiplexes the image data received by the differential input circuit 206-n. The differential input circuits 206-2 to 206- (n-1) and the demultiplexers 207-2 to 207- (n-1) are not shown. Reference numeral 208 denotes a differential input circuit for inputting clocks CLK and / CLK.

  Transfer of image data DATA1a, / DATA1a to DATAna, / DATAna from the transmission unit 193 of the camera module 190 to the reception unit 197 of the processor unit 191, and the reception unit of the display unit 192 from the transmission unit 201 of the processor unit 191 The transfer of the image data DATA1b, / DATA1b to DATAnb, / DATAnb to 205 is synchronized by a clock CLK multiplied by a PLL (phase-locked loop). By using such a system, signal quality in high-speed data transfer between LSI chips can be guaranteed.

1 is a circuit diagram showing a first embodiment of the present invention. FIG. 3 is a circuit diagram showing a configuration example of a bias circuit that generates a gate bias voltage of a PMOS transistor that constitutes the constant current source included in the first embodiment of the present invention. It is a figure which shows the electric current path which determines the output voltage of the external output terminal in 1st Embodiment of this invention. It is a wave form diagram which shows the input-output waveform of 1st Embodiment of this invention. It is a circuit diagram which shows 2nd Embodiment of this invention. It is a circuit diagram which shows the 1st structural example of the bias circuit for PMOS transistors which comprises the constant current source used in 2nd Embodiment of this invention. It is a circuit diagram which shows the 2nd structural example of the bias circuit for PMOS transistors which comprises the constant current source used by 2nd Embodiment of this invention. It is a circuit diagram which shows 3rd Embodiment of this invention. It is a circuit diagram which shows the structural example of the bias circuit which produces | generates the gate bias voltage of the NMOS transistor which comprises the constant current source with which 3rd Embodiment of this invention is provided. It is a figure which shows the electric current path which determines the output voltage of the external output terminal in 3rd Embodiment of this invention. It is a circuit diagram which shows 4th Embodiment of this invention. It is a circuit diagram which shows the 1st structural example of the bias circuit for NMOS transistors which comprises the constant current source used in 4th Embodiment of this invention. It is a circuit diagram which shows the 2nd structural example of the bias circuit for NMOS transistors which comprises the constant current source used in 4th Embodiment of this invention. It is a circuit diagram which shows 5th Embodiment of this invention. It is a figure which shows the electric current path which determines the output voltage of the external output terminal in 5th Embodiment of this invention. It is a circuit diagram which shows the reflection measurement model of 5th Embodiment of this invention. It is a figure which shows the frequency characteristic of S parameter Sdd11 obtained by performing circuit simulation about the reflection measurement model shown in FIG. It is a figure which shows the frequency characteristic of S parameter Scd11 obtained by performing circuit simulation about the reflection measurement model shown in FIG. It is a circuit diagram which shows 6th Embodiment of this invention. It is a figure which shows the electric current path which determines the output voltage of the external output terminal in 6th Embodiment of this invention. It is a circuit diagram which shows 7th Embodiment of this invention. It is a figure which shows the current pathway which determines the output voltage of the external output terminal in 7th Embodiment of this invention. It is a circuit diagram which shows 8th Embodiment of this invention. It is a figure which shows the electric current path which determines the output voltage of the external output terminal in 8th Embodiment of this invention. It is a block circuit diagram showing an example of a system using an embodiment of the present invention. It is a circuit diagram which shows an example of the conventional differential output circuit. FIG. 27 is a diagram showing a current path for determining an output voltage of an external output terminal in the conventional differential output circuit shown in FIG. 26. It is a circuit diagram which shows the other example of the conventional differential output circuit. FIG. 29 is a diagram showing a current path for determining an output voltage of an external output terminal in the conventional differential output circuit shown in FIG. 28. It is a figure for demonstrating the problem which generate | occur | produces in the conventional differential output circuit shown in FIG. 26 when the DC specification of an output common mode voltage is extremely biased to the VSS side. It is a figure for demonstrating the problem which generate | occur | produces in the conventional differential output circuit shown in FIG. 28 when DC specification of an output common mode voltage is extremely biased to VDD side.

Explanation of symbols

1 ... LSI
DESCRIPTION OF SYMBOLS 2 ... Example of a conventional differential output circuit 3, 4 ... External output terminal 5, 6 ... Signal wiring 7 ... Termination resistor 8 ... VDD power supply line 9 ... VSS power supply line 10 ... Internal signal terminal 11 ... Signal transmission part 12, 13 ... Output buffer 14, 15 ... Inverter 16 ... PMOS transistor 17 ... NMOS transistor 18 ... Buffer 19 ... Inverter 20 ... PMOS transistor 21 ... NMOS transistor 22 ... VC setting unit (output common mode voltage setting unit)
DESCRIPTION OF SYMBOLS 23, 24 ... Resistance 25 ... Common mode voltage setting terminal 26 ... Operational amplifier 27 ... PMOS transistor 28 ... Constant current source 29 ... NMOS transistor 31 ... LSI
32 ... Other examples of conventional differential output circuit 33, 34 ... External output terminal 35, 36 ... Signal wiring 37 ... Termination resistor 38 ... VDD power supply line 39 ... VSS power supply line 40 ... Internal signal terminal 41 ... Signal transmission unit 42 43 ... Output buffer 44, 45 ... Inverter 46 ... PMOS transistor 47 ... NMOS transistor 48 ... Buffer 49 ... Inverter 50 ... PMOS transistor 51 ... NMOS transistor 52 ... VC setting unit (output common mode voltage setting unit)
53, 54 ... Resistance 55 ... Common mode voltage setting terminal 56 ... Operational amplifier 57 ... NMOS transistor 58 ... Constant current source 59 ... PMOS transistor 61 ... LSI
62 ... First embodiment of the present invention 63, 64 ... External output terminals 65, 66 ... Signal wiring 67 ... Termination resistor 68 ... VDD power supply line 69 ... VSS power supply line 70 ... Internal signal terminal 71 ... Signal transmission unit 72, 73 ... Output buffer 74 ... Buffer 75 ... Inverter 76, 77 ... NMOS transistor 78 ... Inverter 79 ... Buffer 80, 81 ... NMOS transistor 82 ... VC setting section (output common mode voltage setting section)
83, 84 ... Resistance 85 ... Common mode voltage setting terminal 86 ... Operational amplifier 87 ... PMOS transistor 88 ... Constant current source 89 ... PMOS transistor 91 ... Bias circuit 92 ... PMOS transistor 93 ... Resistance 95 ... Second embodiment of the present invention 101 ... LSI
102 ... Third embodiment of the present invention 103, 104 ... External output terminal 105, 106 ... Signal wiring 107 ... Terminating resistor 108 ... VDD power supply line 109 ... VSS power supply line 110 ... Internal signal terminal 111 ... Signal transmission unit 112, 113 ... Output buffer 114 ... Inverter 115 ... Buffer 116, 117 ... PMOS transistor 118 ... Buffer 119 ... Inverter 120, 121 ... PMOS transistor 122 ... VC setting unit (output common mode voltage setting unit)
123, 124 ... resistors 125 ... common mode voltage setting terminal 126 ... operational amplifier 127 ... NMOS transistor 128 ... constant current source 129 ... NMOS transistor 131 ... bias circuit 132 ... NMOS transistor 133 ... resistor 135 ... fourth embodiment of the present invention 137 ... Bias circuit 138... PMOS transistor 139, 140... Resistor 141... Bias circuit 142... PMOS transistor 144... Bias circuit 145... NMOS transistor 146 and 147. ... VC setting unit 154 ... NMOS transistor 165 ... Sixth embodiment of the present invention 166 ... Constant current source 167 ... NMOS transistor 172 ... Seventh embodiment of the present invention 173 ... VC Fixed unit 174 ... PMOS transistor 185 ... Eighth embodiment of the present invention 186 ... Constant current source 187 ... PMOS transistor 190 ... Camera module 191 ... Processor unit 192 ... Display unit 193 ... Transmitter 194-1, 194-n ... Multiplexers 195-1, 195-n, 196... Differential output circuit 197... Receivers 198-1, 198-n... Differential input circuit 199-1, 199-n. Units 202-1, 202-n: multiplexers 203-1, 203-n, 204 ... differential output circuit 205 ... receiving units 206-1, 206-n ... differential input circuits 207-1, 207-n ... demultiplexers 208: Differential input circuit

Claims (12)

A first power line;
A constant current source having a current input terminal connected to the first power line;
An output common mode voltage setting unit having a variable resistance element, wherein one end of the variable resistance element is connected to a current output terminal of the constant current source;
A first power supply terminal is connected to the other end of the variable resistance element, and a second power supply terminal is connected to a second power supply line that supplies a lower voltage than the first power supply line, and according to an input signal A signal transmission unit having a signal output terminal for outputting an output signal ,
The constant current source, the first on a current path from the power supply line to the second power supply line, the differential output circuit according to claim Rukoto disposed upstream as viewed from the signal output terminal. A first power line;
An output common mode voltage setting unit having a variable resistance element and having one end of the variable resistance element connected to the first power supply line;
A constant current source having a current input terminal connected to the other end of the variable resistance element;
A first power supply terminal is connected to a current output terminal of the constant current source, a second power supply terminal is connected to a second power supply line that supplies a lower voltage than the first power supply line, and an input signal is applied. A signal transmission unit having a signal output terminal for outputting the output signal ,
The constant current source, the first on a current path from the power supply line to the second power supply line, the differential output circuit according to claim Rukoto disposed upstream as viewed from the signal output terminal. The signal transmission unit is
A first output buffer connected between a first signal terminal and a second signal terminal and outputting a first output signal in phase with an input signal applied to the first signal terminal;
A second output buffer connected between the first signal terminal and the third signal terminal and outputting a second output signal having a phase opposite to that of the input signal;
The first output buffer comprises:
A first buffer having an input terminal connected to the first signal terminal;
A first N-channel field effect transistor having a gate connected to the output terminal of the first buffer, a drain connected to the first power supply terminal, and a source connected to the second signal terminal;
A first inverter having an input terminal connected to the first signal terminal;
A second N-channel field effect transistor having a gate connected to the output terminal of the first inverter, a drain connected to the second signal terminal, and a source connected to the second power supply terminal;
The second output buffer comprises:
A second inverter having an input terminal connected to the first signal terminal;
A third N-channel field effect transistor having a gate connected to the output terminal of the second inverter, a drain connected to the first power supply terminal, and a source connected to the third signal terminal;
A second buffer having an input terminal connected to the first signal terminal;
A fourth N-channel field effect transistor having a gate connected to the output terminal of the second buffer, a drain connected to the third signal terminal, and a source connected to the second power supply terminal. The differential output circuit according to claim 1, wherein the differential output circuit is a differential output circuit. A first power line;
A signal transmission unit having a signal output terminal for connecting a first power supply terminal to the first power supply line and outputting an output signal corresponding to the input signal ;
An output common mode voltage setting unit having a variable resistance element, wherein one end of the variable resistance element is connected to a second power supply terminal of the signal transmission unit;
A constant current source having a current input terminal connected to the other end of the variable resistance element and a current output terminal connected to a second power supply line for supplying a lower voltage than the first power supply line ;
The constant current source, the first on a current path from the power supply line to the second power supply line, the differential output circuit according to claim Rukoto disposed downstream as viewed from the signal output terminal. A first power line;
A signal transmission unit having a signal output terminal for connecting a first power supply terminal to the first power supply line and outputting an output signal corresponding to the input signal ;
A constant current source having a current input terminal connected to a second power supply terminal of the signal transmission unit;
A variable resistance element; one end of the variable resistance element is connected to a current output terminal of the constant current source; and the other end of the variable resistance element is supplied with a lower voltage than the first power supply line. An output common mode voltage setting unit connected to the power line ,
The constant current source, the first on a current path from the power supply line to the second power supply line, the differential output circuit according to claim Rukoto disposed downstream as viewed from the signal output terminal. The signal transmission unit is
A first output buffer connected between a first signal terminal and a second signal terminal and outputting a first output signal in phase with an input signal applied to the first signal terminal;
A second output buffer connected between the first signal terminal and the third signal terminal and outputting a second output signal having a phase opposite to that of the input signal;
The first output buffer comprises:
A first inverter having an input terminal connected to the first signal terminal;
A first P-channel field effect transistor having a gate connected to the output terminal of the first inverter, a source connected to the first power supply terminal, and a drain connected to the second signal terminal;
A first buffer having an input terminal connected to the first signal terminal;
A second P-channel field effect transistor having a gate connected to the output terminal of the first buffer, a source connected to the second signal terminal, and a drain connected to the second power supply terminal;
The second output buffer comprises:
A second buffer having an input terminal connected to the first signal terminal;
A third P-channel field effect transistor having a gate connected to the output terminal of the first buffer, a source connected to the first power supply terminal, and a drain connected to the third signal terminal;
A second inverter having an input terminal connected to the first signal terminal;
A fourth P-channel field effect transistor having a gate connected to the output terminal of the second inverter, a source connected to the third signal terminal, and a drain connected to the second power supply terminal. The differential output circuit according to claim 4 or 5, characterized in that: A first power line;
A constant current source having a current input terminal connected to the first power line;
A variable resistance element; one end of the variable resistance element is connected to a current output terminal of the constant current source; and the other end of the variable resistance element is supplied with a lower voltage than the first power supply line. An output common mode voltage setting unit connected to the power line;
A differential output circuit comprising: a signal transmission unit having a first power supply terminal connected to a current output terminal of the constant current source and a second power supply terminal connected to the second power supply line. A first power line;
An output common mode voltage setting unit having a variable resistance element and having one end of the variable resistance element connected to the first power supply line;
A constant current source having a current input terminal connected to the other end of the variable resistance element, and a current output terminal connected to a second power supply line that supplies a lower voltage than the first power supply line;
A differential output circuit comprising: a signal transmission unit having a first power supply terminal connected to the other end of the variable resistance element and a second power supply terminal connected to the second power supply line. A first power line;
A signal transmission unit having a first power supply terminal connected to the first power supply line;
A constant current source having a current input terminal connected to a second power supply terminal of the signal transmission unit, and a current output terminal connected to a second power supply line supplying a lower voltage than the first power supply line;
An output common mode voltage setting unit having a variable resistance element, one end of the variable resistance element connected to the first power supply line, and the other end of the variable resistance element connected to a current input terminal of the constant current source; A differential output circuit comprising: A first power line;
A signal transmission unit having a first power supply terminal connected to the first power supply line;
A variable resistance element; one end of the variable resistance element is connected to a second power supply terminal of the signal transmission unit; and the other end of the variable resistance terminal is supplied with a voltage lower than that of the first power supply line. An output common mode voltage setting unit connected to two power lines;
A differential output circuit comprising: a constant current source having a current input terminal connected to the first power supply line and a current output terminal connected to one end of the variable resistance element. A first power line;
A second power supply line for supplying a lower voltage than the first power supply line;
A signal transmission unit provided between the first power supply line and the second power supply line and having a signal output terminal for outputting an output signal corresponding to an input signal;
An output common mode voltage setting unit having a variable resistance element provided between the first power supply line and the signal transmission unit, the resistance value of which varies according to the voltage of the output signal;
A constant current source that is provided between the first power supply line and the signal transmission unit and supplies a constant current to the signal output terminal;
With
The constant current source is provided on the upstream side of the signal output terminal on the current path from the first power supply line to the second power supply line.
A differential output circuit characterized by. A first power line;
A second power supply line for supplying a lower voltage than the first power supply line;
A signal transmission unit provided between the first power supply line and the second power supply line and having a signal output terminal for outputting an output signal corresponding to an input signal;
An output common mode voltage setting unit having a variable resistance element provided between the signal transmission unit and the second power supply line and having a resistance value that varies according to the voltage of the output signal;
A constant current source provided between the signal transmission unit and the second power supply line and drawing a constant current from the signal output terminal;
With
The constant current source is provided on the downstream side of the signal output terminal on the current path from the first power supply line to the second power supply line.
A differential output circuit characterized by.

Images