JP3916502B2 - Output circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an output circuit, and more particularly to an output circuit mounted in a signal transmission system, a semiconductor memory device, or the like.
[0002]
In recent years, it has become necessary to transfer signals between circuits (Large Scale Integration Circuits) constituting an information processing apparatus or between circuits having different power supply voltages even in signals within LSIs. However, in the transmission of signals between circuits having different power supply voltages, it is difficult for the output circuit to output a signal having an optimum common level at the receiving end. Has a problem of high frequency component loss and signal reflection. Therefore, it is desired to provide an output circuit that can output a signal having an optimum common level on the receiving circuit side and that can transmit a signal with a small amplitude that prevents loss of high-frequency components and signal reflection. .
[0003]
[Prior art]
FIG. 1 is a circuit diagram showing an example of a conventional output circuit, and shows an example of an output circuit of LVDS (Low Voltage Differential Signaling) which is a small amplitude interface.
[0004]
As shown in FIG. 1, examples of a conventional LVDS output circuit include current sources 301 and 302, p-channel MOS transistors (pMOS transistors) 303 and 304, n-channel MOS transistors (nOS transistors) 305 and 306, Also, resistors 307 and 308 are provided.
[0005]
Between the current source 301 connected to the high potential power supply line (V1) and the current source 302 connected to the low potential power supply line (V0), inverters (transistors 304) to which the input signals DATA and DATAX are respectively supplied. , 306 and 303, 305). Here, the input signals DATA and DATAX are differential (complementary) signals, the output signal OUT is taken out from the output of the inverter (transistors 303 and 305) supplied with the input signal DATAX, and the input signal DATA is supplied. The output signal OUTX is extracted from the output of the inverter (transistors 304 and 306). The differential outputs OUT and OUTX are provided with resistors 307 and 308 connected in series. A common voltage VCM is applied to the connection node of the resistors 307 and 308.
[0006]
In the conventional output circuit shown in FIG. 1, the amplitude (output amplitude) of the output signals OUT and OUTX can be adjusted by the current values of the current sources 301 and 302 and the resistance values of the resistors 307 and 308. The common bell of the signals OUT and OUTX can be adjusted by the common voltage VCM applied to the connection node of the resistors 307 and 308.
[0007]
[Problems to be solved by the invention]
By the way, for a circuit capable of high-speed operation that satisfies the demand for high-speed transmission in recent years, for example, an element (transistor) that has been processed such as thinning the gate oxide film can be used to drive with a low power supply voltage. Many. In other words, a circuit capable of high-speed operation is often composed of a transistor that can operate at high speed but has a low withstand voltage. For example, when connected to a circuit having different power supply voltage, signal amplitude, common level, etc. It is also conceivable that the circuit is destroyed by applying a voltage exceeding the breakdown voltage of the transistor.
[0008]
Therefore, conventionally, in order to cut off the difference in the DC level (average voltage, common level) of the signal, it is necessary to take measures not to exceed the breakdown voltage by capacitive coupling or the like. Specifically, when the signal of the output circuit that outputs a signal varies between 4V and 5V, and the input (withstand voltage) of the receiving circuit that receives the output signal is 0.5V to 1.5V, the output of the output circuit Capacitance is provided between the (OUT OUT, OUTX in FIG. 1) and the receiving circuit to block the difference in the DC level of the signal.
[0009]
However, for example, in the output circuit of FIG. 1, when the common voltage VCM is applied to adjust the common level of the output signals (OUT, OUTX), a current flows from the power supply of the output circuit to the common voltage terminal (VCM) side. As a result, the current consumption increases. Furthermore, when the current flowing from the power source to the common voltage terminal side is large, the common voltage VCM must be connected to a signal pin having a large current capacity in order to set the potential of the common voltage terminal to a desired voltage.
[0010]
An object of the present invention is to provide an output circuit capable of outputting a signal having an optimum amplitude and common level on the receiving circuit side in view of the problems of the above-described conventional output circuit. Another object of the present invention is to provide a low power consumption output circuit capable of transmitting a signal with a small amplitude to prevent loss of high frequency components and signal reflection.
[0011]
[Means for Solving the Problems]
According to the present invention, a data control circuit including an element capable of operating at high speed and controlling data of an output signal according to an input signal is connected in series with the data control circuit between a first power supply line and a second power supply line. A variable resistance circuit provided in the circuit, a common level detection circuit for detecting a common level of the output signal, and a high withstand voltage element, and the resistance value of the variable resistance circuit is adjusted according to the output of the common level detection circuit comprising an adjusting circuit for the, as well as adjusting the common level of the output signal to an arbitrary voltage level, the output circuit, wherein provided that the amplitude of the output signal is adjustable.
[0012]
According to the output circuit of the present invention, the data control circuit for controlling the data of the output signal according to the input signal and the variable resistance circuit are provided in series between the first power supply line and the second power supply line, and the adjustment circuit is The resistance value of the variable resistance circuit is adjusted according to the output of the common level detection circuit that detects the common level of the output signal. As a result, the common level of the output signal can be adjusted to an arbitrary voltage level, and the amplitude of the output signal can be adjusted.
[0013]
Here, the adjustment circuit includes a transistor with a high breakdown voltage, and the data control circuit includes a transistor capable of high-speed operation. Furthermore, the variable resistance circuit includes a transistor with a high breakdown voltage. That is, the output circuit of the present invention secures a withstand voltage by arranging a high withstand voltage element in an output stage directly connected to another circuit, and uses a high-speed element for a switch portion that determines the speed of the circuit. Realizes high-speed operation.
[0014]
The common level of the output signal can be adjusted to the potential divided by resistance in the current path from the high potential power supply voltage V1 to the low potential power supply voltage V0 by adjusting the resistance value of the variable resistor. Further, by setting the high potential power supply voltage V1 high, the common level can be set to a voltage higher than the withstand voltage of the switch, and a signal can be output in a wide voltage range. In addition, since the amplitude of the output signal can be adjusted to a small amplitude, when transmitting at high speed, the effect of loss of high frequency components and signal reflection prevention can be obtained, and bit errors in signal transmission can be reduced.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of an output circuit according to the present invention will be described in detail with reference to the accompanying drawings.
[0016]
FIG. 2 is a circuit diagram showing a first embodiment of an output circuit according to the present invention, and shows an example of a single-ended output circuit. In FIG. 2, reference numeral 1 indicates the output of the low speed / high withstand voltage portion, and 2 indicates the high speed / low withstand voltage portion.
[0017]
The low speed / high withstand voltage unit 1 includes a variable resistor (variable resistor circuit) 11, a current source 12, a comparator (adjustment circuit) 13, and an average voltage detector (common level detection circuit) 14. 2 includes a switch 21 and a leak path 22. Here, the high speed / low withstand voltage unit 2 functions as a data control circuit for controlling the data of the output signal OUT in accordance with the input signal DATAX.
[0018]
As a transistor constituting the low speed / high withstand voltage section 1 (variable resistor 11, current source 12, comparator 13 and average voltage detector 14), for example, a gate oxide film is thick and the operation speed is slow, but a high withstand voltage is used. As the transistors that are used and constitute the high-speed / low-voltage section 2 (the switch 21 and the leak path 22), for example, a transistor that has a thin gate oxide film and low withstand voltage but can operate at high speed is used. That is, it is possible to output the output signal OUT in a wide voltage range by using a high-breakdown-voltage element (transistor) for a circuit that defines the amplitude and common level of the output signal OUT.
[0019]
A variable resistor 11, a current source 12 and a switch 21 are connected in series between the high potential power supply line (V1) and the low potential power supply line (V0), and a leak path 22 is connected in parallel to the switch 21. ing. That is, the current source 12 is inserted into the high-speed switch 21 so that a high voltage is not directly applied to one end (node Va) thereof.
[0020]
The variable resistor 11 is controlled by the output of the comparator 13, and the comparator 13 compares the reference voltage Vref applied to its positive input with the output voltage Vx of the average voltage detector 14 supplied to its negative input. The resistance value R1 of the variable resistor 11 is controlled so that the voltage Vx becomes equal to the reference voltage Vref.
[0021]
The output circuit of the first embodiment outputs a low level “L” or high level “H” output signal OUT when the switch 21 is turned on or off. Here, the comparator 13 compares the average voltage of the output signal OUT obtained from the average voltage detector 14 with a reference voltage (arbitrary voltage) Vref, and the resistance value (R1) of the variable resistor 11 according to the comparison result. ). That is, if the resistance value R1 of the variable resistor 11 is increased in accordance with the reference voltage Vref, the common level (average voltage) of the output signal OUT is lowered. Conversely, if the resistance value R1 is decreased, the common level is increased. Furthermore, by controlling the amount of current flowing through the leak path 22, the high level when the switch 21 is off and the amplitude of the output signal OUT can be adjusted.
[0022]
3 is a diagram for explaining the operation of the output circuit of FIG. 2. FIG. 3A is an equivalent circuit diagram when the switch 21 is turned off, and FIG. 3B is a diagram when the switch 21 is turned on. FIG. 3C is a diagram for explaining the amplitude and common level of the output signal OUT.
[0023]
First, as shown in FIGS. 3A and 3C, when the switch 21 is turned off, the high potential power supply line (V1) and the low potential power supply line (V0) are equivalently variable. The resistor 11 (R1) and the leak path 22 (R2) are connected in series, and the high level voltage Vmax of the output signal OUT is Vmax = {R2 / (R1 + R2)} × V1].
[0024]
On the other hand, as shown in FIGS. 3 (b) and 3 (c), when the switch 21 is turned on, the high potential power supply line (V1) and the low potential power supply line (V0) are equivalently variable. The resistor 11 (R1) and the current source 12 are connected in series, and the output low level voltage Vmin is Vmin = V1−R1 × I.
[0025]
Further, the average voltage (common level) Vx of the output signal OUT is detected by the average voltage detector 14, and the output (Vx) of the average voltage detector 14 and the reference voltage Vref are compared by the comparator 13, and the variable resistor 11. Since the resistance value R1 is feedback-controlled, the common level Vx of the output signal OUT is adjusted to a level corresponding to the reference voltage Vref.
[0026]
FIG. 4 is a circuit diagram showing a second embodiment of the output circuit according to the present invention.
[0027]
As apparent from the comparison between FIG. 4 and FIG. 2, the output circuit of the second embodiment is the same as the output circuit of the first embodiment except that the variable resistor 11 is composed of a pMOS transistor, the current source 12, the switch 21 and Each of the leak paths 22 is configured by an nMOS transistor. Here, the bias voltage Vcn is applied to the gate of the current source transistor 12, and the input signal (inverted level signal) DATAX is supplied to the gate of the switch transistor 21.
[0028]
In the output circuit of the second embodiment, the drain (node Va) of the switching transistor 21 is connected to the source of the transistor 12 for current source, and the maximum voltage Va (max) at the node Va is the transistor 12. This is a voltage obtained by subtracting the threshold voltage Vth of the transistor 12 from the bias voltage Vcn applied to the gate (Va (max) = Vcn−Vth).
[0029]
Therefore, by controlling the potential of the bias voltage Vcn, the maximum voltage Va (max) of the node Va can be adjusted so that a voltage lower than the breakdown voltage of the high-speed element is applied to the switching transistor 21. .
[0030]
The leak path transistor 22 having the gate and drain connected is for adjusting the voltage of the node Va until the potential of the bias voltage Vcn at standby or when the power is turned on is stabilized. Further, the leak path transistor 22 also has a function of determining the potential of the output signal OUT (high level “H” potential) when the switch transistor 21 is off.
[0031]
FIG. 5 is a circuit diagram showing a third embodiment of the output circuit according to the present invention, wherein the single-ended output circuit of the first embodiment shown in FIG. 2 is configured as a differential. In FIG. 5, reference numerals 201 and 202 denote high-speed / low withstand voltage parts, and the other parts constitute low-speed / high withstand voltage parts. That is, the switches 211 and 212 and the leak paths 221 and 222 are constituted by, for example, transistors that have a thin gate oxide film and a low withstand voltage but can operate at high speed. The variable resistors 111 and 112, current sources 121 and 122, and comparators 13 and the common voltage detector 14 are composed of, for example, high breakdown voltage transistors with a thick gate oxide film and a low operation speed.
[0032]
In the output circuit of the third embodiment, the switch 211 and the switch 212 are alternately turned on / off, and conflicting signals are output to the differential outputs (OUT, OUTX). The common voltage detector 14 detects the common voltage (common level) of the differential output signals OUT and OUTX, and the detected common voltage Vx is supplied to the comparator 13. The comparator 13 compares the common voltage Vx applied to the negative input with the reference voltage Vref applied to the positive input, and adjusts the resistance values of the variable resistors 111 and 112 according to the comparison result. That is, if the resistance values of the variable resistors 111 and 112 are increased in accordance with the reference voltage Vref, the common voltage of the output signal OUT is decreased. Conversely, if the resistance values of the variable resistors 111 and 112 are decreased, the common voltage is increased. . Further, if the current flowing through the leak paths 221 and 222 is increased, the signal amplitude is increased, and if the current flowing through the leak paths 221 and 222 is decreased, the signal amplitude is decreased.
[0033]
As described above, the circuit that defines the signal amplitude and the common level uses a high-breakdown-voltage element even at a low speed, thereby enabling the output signals OUT and OUTX to be output in a wide voltage range. Note that current sources 121 and 122 are inserted into the high-speed switches 211 and 212 so that a high voltage is not directly applied to the nodes Va1 and Va2.
[0034]
FIG. 6 is a circuit diagram showing a fourth embodiment of the output circuit according to the present invention.
[0035]
As is apparent from the comparison between FIG. 6 and FIG. 5, the output circuit of the fourth embodiment is the same as the output circuit of the third embodiment, in which the variable resistors 111 and 112 are configured by pMOS transistors, and the current sources 121 and 122 The switches 211 and 212 and the leak paths 221 and 222 are configured by nMOS transistors, respectively. Here, the bias voltage Vcn is applied to the gates of the current source transistors 121 and 122, and the input signal (inverted logic signal) DATAX is supplied to the gate of the switch transistor 211. An input signal (positive logic signal) DATA is supplied to the gate. Further, the common voltage detector 14 includes resistors 141 and 142, and an output (Vx) is extracted from a connection node of these resistors.
[0036]
FIG. 7 is a circuit diagram showing a fifth embodiment of the output circuit according to the present invention.
[0037]
As is apparent from the comparison between FIG. 7 and FIG. 6, the output circuit of the fifth embodiment has substantially the same configuration as that of the fourth embodiment described above. The comparator 13 is configured as a general differential amplifier having load pMOS transistors 131 and 132, differential pair nMOS transistors 133 and 134, and an nMOS transistor 135 functioning as a current source. The reference voltage Vref is applied to the gate of the transistor 133, and the common voltage Vx detected by the common voltage detector 14 is applied to the gate of the other transistor 134 of the differential pair. The output taken out from the connection node of the transistors 131 and 133 of the comparator 13 is supplied to the gates of the pMOS transistors 111 and 112 functioning as variable resistors, and the resistance values of these variable resistors are controlled. .
[0038]
Here, also in the output circuit of the fifth embodiment, the switches (nMOS transistors) 211 and 212 and the leak paths (nMOS transistors) 221 and 222 (high-speed / low withstand voltage portions 201 and 202) have, for example, thin gate oxide films. It is composed of a transistor having a low withstand voltage but capable of high-speed operation, and other parts, that is, variable resistors (pMOS transistors) 111 and 112, current sources (nMOS transistors) 121 and 122, and a comparator 13 (pMOS transistors 131 and 132 and The nMOS transistors 133 to 135) are constituted by, for example, high breakdown voltage transistors with a thick gate oxide film and a low operation speed. The common voltage detector 14 includes resistors 141 and 142. When these resistors are formed using transistors, for example, the gate oxide film is thick and the operation speed is low, but the high withstand voltage is high. A transistor is used.
[0039]
As described above, the output circuit of the present invention can be applied to single-ended and differential output circuits, and the transistor conductivity type (p and n channel type) also changes depending on the polarity of the power supply voltage to which the transistor is applied. Of course you get. Furthermore, the devices constituting the output circuit are not limited to the above-described MOS transistors, and various comparators and common voltage detectors can be applied.
[0040]
(Appendix 1) A data control circuit that controls data of an output signal according to an input signal;
A variable resistance circuit provided in series with the data control circuit between the first power supply line and the second power supply line;
A common level detection circuit for detecting a common level of the output signal;
And an adjustment circuit that adjusts the resistance value of the variable resistance circuit in accordance with the output of the common level detection circuit. The common level of the output signal can be adjusted to an arbitrary voltage level and the amplitude of the output signal can be adjusted. An output circuit characterized by that.
[0041]
(Additional remark 2) The output circuit of Additional remark 1 WHEREIN: The said adjustment circuit is provided with an element with a high proof pressure, and the said data control circuit is provided with the element which can be operated at high speed, The output circuit characterized by the above-mentioned.
[0042]
(Additional remark 3) The output circuit of Additional remark 2 WHEREIN: Furthermore, the said variable resistance circuit is provided with an element with a high proof pressure, The output circuit characterized by the above-mentioned.
[0043]
(Additional remark 4) The output circuit of Additional remark 2 WHEREIN: Furthermore, the said common level detection circuit is provided with an element with a high proof pressure, The output circuit characterized by the above-mentioned.
[0044]
(Supplementary Note 5) In the output circuit according to Supplementary Note 2, the data control circuit includes a switch element in which the input signal is supplied to a control electrode, and the switch element operates at high speed even if the withstand voltage is low. An output circuit that is possible.
[0045]
(Supplementary Note 6) In the output circuit according to Supplementary Note 5, the data control circuit includes a diode-connected leakage path transistor, and the leakage path transistor is a transistor capable of high-speed operation even if the breakdown voltage is low. An output circuit characterized by.
[0046]
(Supplementary note 7) The output circuit according to any one of supplementary notes 1 to 6, further comprising a current source provided between the variable resistance circuit and the data control circuit.
[0047]
(Additional remark 8) The output circuit of Additional remark 7 WHEREIN: The said current source is a transistor by which the bias voltage was applied to the control electrode, The output circuit characterized by the above-mentioned.
[0048]
(Supplementary note 9) In the output circuit according to any one of supplementary notes 1 to 8, the adjustment circuit is a differential amplifier, and differentially amplifies a reference voltage and an output of the common level detection circuit. Output circuit.
[0049]
(Supplementary Note 10) In the output circuit according to any one of Supplementary notes 1 to 9, the first power supply line is a high potential power supply line, and the second power supply line is a low potential power supply line. Output circuit.
[0050]
(Supplementary note 11) In the output circuit according to supplementary note 10, the variable resistance circuit is a p-channel MOS transistor, and an output of the adjustment circuit is supplied to a gate of the p-channel MOS transistor. Output circuit.
[0051]
(Supplementary note 12) In the output circuit according to supplementary note 10, the data control circuit includes a switching nMOS transistor whose gate is supplied with the input signal, and a diode-connected leak path nMOS transistor. Output circuit.
[0052]
(Supplementary note 13) In the output circuit according to any one of Supplementary notes 1 to 12, the input signal and the output signal are single-ended signals, and the output circuit is a single-ended output circuit. Output circuit.
[0053]
(Supplementary note 14) The output circuit according to any one of supplementary notes 1 to 12, wherein the input signal and the output signal are differential signals, and the output circuit is a differential output circuit. Output circuit.
[0054]
(Supplementary Note 15) In the output circuit according to Supplementary Note 14, the common level detection circuit and the adjustment circuit are provided in common for differential signals, and other configurations are provided separately for differential signals. An output circuit characterized by that.
[0055]
(Supplementary note 16) In the output circuit according to supplementary note 15, the common level detection circuit includes first and second resistors connected in series for receiving a differential output signal, and a resistance by the first and second resistors. An output circuit for detecting a common level of the output signal by dividing.
[0056]
【The invention's effect】
As described above in detail, according to the present invention, the amplitude and common level of the output signal can be arbitrarily adjusted, so that a signal having the optimum amplitude and common level can be output on the receiving circuit side. A simple output circuit can be provided. Furthermore, according to the present invention, since it is possible to transmit a signal with a small amplitude that prevents loss of high-frequency components and signal reflection, an output circuit with low power consumption can be provided.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing an example of a conventional output circuit.
FIG. 2 is a circuit diagram showing a first embodiment of an output circuit according to the present invention.
FIG. 3 is a diagram for explaining the operation of the output circuit of FIG. 2;
FIG. 4 is a circuit diagram showing a second embodiment of the output circuit according to the present invention.
FIG. 5 is a circuit diagram showing a third embodiment of the output circuit according to the present invention.
FIG. 6 is a circuit diagram showing a fourth embodiment of the output circuit according to the present invention.
FIG. 7 is a circuit diagram showing a fifth embodiment of the output circuit according to the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Low speed and high voltage | pressure-resistant part 2; 201,202 ... High speed and low voltage | pressure-resistant part 11; 111,112 ... Variable resistance 12; 121,122 ... Current source 13 ... Comparator 14 ... Average voltage detector (common voltage detector)
21; 211, 212 ... switch (transistor for switch)
22; 221, 222 ... leak path (transistor for leak path)
DATA, DATAX ... input signal OUT, OUTX ... output signal V0 ... low potential power supply voltage (low potential power supply line)
V1 ... high potential power supply voltage (high potential power supply line)
Vref ... reference voltage Vx ... output voltage of average voltage detector (common voltage detector)

Claims (9)

A data control circuit including an element capable of high-speed operation and controlling data of an output signal according to an input signal;
A variable resistance circuit provided in series with the data control circuit between the first power supply line and the second power supply line;
A common level detection circuit for detecting a common level of the output signal;
Together with a high withstand voltage element, and an adjusting circuit for adjusting the resistance value of the variable resistance circuit in accordance with an output of the common level detection circuit, for adjusting the common level of the output signal to an arbitrary voltage level, An output circuit characterized in that the amplitude of the output signal can be adjusted. 2. The output circuit according to claim 1 , wherein the variable resistance circuit further includes an element having a high breakdown voltage . 2. The output circuit according to claim 1 , wherein the data control circuit includes a switching element in which the input signal is supplied to a control electrode, and the switching element can operate at a high speed even if the withstand voltage is low. An output circuit characterized by that. 4. The output circuit according to claim 3 , wherein the data control circuit includes a diode-connected leakage path transistor, and the leakage path transistor is a transistor capable of high-speed operation even with a low breakdown voltage. Output circuit. The output circuit according to claim 1, further output circuit, characterized in that it comprises a current source provided between said variable resistance circuit and the data control circuit. 6. The output circuit according to claim 1, wherein the input signal and the output signal are single-ended signals, and the output circuit is a single-ended output circuit. . The output circuit according to any one of claims 1 to 5, wherein the input signal and the output signal is a signal of the differential, the output circuit output circuit, characterized in that an output circuit of the differential . 8. The output circuit according to claim 7 , wherein the common level detection circuit and the adjustment circuit are provided in common for the differential signal, and other configurations are provided separately for the differential signal. An output circuit characterized by. 9. The output circuit according to claim 8, wherein the common level detection circuit includes first and second resistors connected in series for receiving a differential output signal, and the resistance is divided by the first and second resistors. An output circuit characterized by detecting a common level of an output signal.

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