JP5226591B2 - Solid-state imaging device and camera system - Google Patents

Description

  The present invention relates to a solid-state imaging device and a camera system that can operate in a thinning readout mode for reading out signals corresponding to the charges of some pixels included in a predetermined column among a plurality of pixels.

  First, the basic configuration and driving method of a conventional MOS type solid-state imaging device will be described with reference to FIG. 5, FIG. 6, FIG. 7, and FIG.

  FIG. 5 shows a configuration of a pixel used in the MOS type solid-state imaging device. The MOS solid-state imaging device has a structure in which a plurality of unit pixels 100 shown in FIG. 5 are arranged in a two-dimensional matrix, and acquires image information from the unit pixels 100.

  In FIG. 5, a photodiode 101 is a photoelectric conversion element that accumulates charges according to incident light. The amplification transistor 104 is a transistor for converting the photogenerated charge generated in the photodiode 101 into a voltage by a PN junction capacitance, a gate capacitance, etc., amplifying and reading the voltage. The transfer transistor 102 is a transistor for transferring photogenerated charges generated in the photodiode 101 to the gate terminal of the amplification transistor 104.

  The reset transistor 103 is a transistor for resetting the gate terminal of the amplification transistor 104 and the photodiode 101. The selection transistor 105 is a transistor for selecting a pixel and transmitting the output of the amplification transistor 104 to the vertical signal line 110. Here, light is shielded except for the photodiode 101.

  The pixel power supply line 106 is a wiring that supplies power (pixel power supply VDD) in common to all the pixels, and is electrically connected to the drain terminal of the amplification transistor 104 and the drain terminal of the reset transistor 103. The row reset line 107 is a wiring for resetting pixels for one row, and is electrically connected to the gate terminal of the reset transistor 103 of the pixels for one row.

  The row transfer line 108 is a wiring for transferring the photogenerated charges of the pixels for one row to the gate terminal of the amplification transistor 104 of each pixel, and is electrically connected to the gate terminals of the transfer transistors 102 for one row, respectively. It is connected. The row selection line 109 is a wiring for selecting pixels for one row, and is electrically connected to the gate terminals of the selection transistors 105 for one row. With such a pixel configuration, a photoelectric conversion function, a reset function, a memory function, an amplification readout function, and a selection function are realized.

  FIG. 6 schematically shows a basic configuration of the MOS type solid-state imaging device. The pixel unit 200 is configured by arranging a plurality of unit pixels 100 in a two-dimensional matrix. Each of the pixels P11 to P34 corresponds to the unit pixel 100. Here, in order to simplify the description, a configuration in which unit pixels 100 are arranged in three rows and four columns is shown.

  The vertical scanning circuit 202 is a circuit that sequentially outputs a vertical scanning signal φVSR (i) (i = 1, 2, 3) for performing row selection. In response to the vertical scanning signal φVSR (i), the vertical selection unit 203 applies a row selection signal φSE (i) (i =) to the row selection line 109, the row reset line 107, and the row transfer line 108 of each pixel P11 to P34. 1, 2, 3), a row reset signal φRS (i) (i = 1, 2, 3), and a row transfer signal φTR (i) (i = 1, 2, 3). The vertical selection unit 203 includes vertical selection circuits (MV1, MV2, MV3) corresponding to the respective rows. In FIG. 6, one line for transmitting the row selection signal φSE, the row reset signal φRS, and the row transfer signal φTR to the vertical selection circuit of each row is shown, and the output of the vertical selection circuit is shown by one row. But in reality, each is independent.

  In FIG. 6, the current source unit 201 includes current sources ML1, ML2, ML3, and ML4 provided for each column. The current sources ML1 to ML4 pass a constant bias current. One terminal of each of the current sources ML1 to ML4 is connected to the vertical signal line 110, and the other terminal is connected to the GND line 111. The current sources ML1 to ML4 and the vertical signal lines 110 in each column are electrically connected to each other, whereby a source follower circuit including the amplification transistor 104 and the current sources ML1 to ML4 is configured for each column.

  The column processing circuit unit 204 performs correlated double sampling (CDS) on the pixel signals output from the source follower circuit by the column processing circuits CDS1, CDS2, CDS3, and CDS4 provided for each column. This circuit stores signal processing results after performing signal processing such as offset variation removal and signal amplification such as pixel fixed pattern noise.

  The horizontal scanning circuit 205 is a circuit for selecting a column, and sequentially outputs horizontal scanning signals φHSR (j) (j = 1, 2, 3, 4). The horizontal selection switch unit 206 transmits the signal processing result stored in the column processing circuit unit 204 to the horizontal signal line 207 in accordance with the horizontal scanning signal φHSR (j) (j = 1, 2, 3, 4). . The output amplifier unit 208 amplifies the signal processing result transmitted from the column processing circuit unit 204 transmitted to the horizontal signal line 207 and outputs the result to the outside.

  Next, the drive timing at the time of moving image shooting of the MOS type imaging device will be described with reference to FIG. When the vertical scanning signal φVSR (1) in the first row is output from the vertical scanning circuit 202, the pixels in the first row can be driven.

  More specifically, the row selection signal φSE is applied to the pixels in the first row via the vertical selection circuit MV1 and the row selection line 109 as the selection signal φSE (1) of the first row. The signal is transmitted to the gate terminal of the pixel selection transistor 105. Further, for the pixels in the first row, the row reset signal φRS is reset as the reset signal φRS (1) in the first row via the vertical selection circuit MV1 and the row reset line 107. The signal is transmitted to the gate terminal of the transistor 103. Further, the row transfer signal φTR is transferred to the pixels in the first row via the vertical selection circuit MV1 and the row transfer line 108 as the transfer signal φTR (1) in the first row. The signal is transmitted to the gate terminal of the transistor 102.

  The selection signal φSE (1), the reset signal φRS (1), and the transfer signal φTR (1) in the first row are transmitted to the pixels in the first row in the period Tv. An operation in this period Tv will be described. When the vertical scanning signal φVSR (1) becomes “H” level and then the row selection signal φSE (1) becomes “H” level, the output of the amplification transistor 104 is transmitted to the vertical signal line 110. That is, a period for performing signal reading and signal processing is started. Next, when the row reset signal φRS (1) becomes “H” level, the gate terminal of the amplification transistor 104 is reset to the level of the pixel power supply VDD. Next, when the row reset signal φRS (1) becomes “L” level, the reset level output output from the amplification transistor 104 at this time is sampled by the column processing circuit unit 204.

  Next, when the row transfer signal φTR (1) becomes “H” level, the photogenerated charges accumulated in the photodiode 101 are transferred to the gate terminal of the amplification transistor 104. When the row transfer signal φTR (1) becomes the “L” level, the signal level output output at this time is sampled again by the column processing circuit unit 204.

  Thereafter, the column processing circuit unit 204 performs difference processing between the sampled signal level output and the reset level output, and stores the signals after the difference processing in the column processing circuits CDS1, CDS2, CDS3, and CDS4, respectively. Then, when the row selection signal φSE (1) becomes “L” level, the period for performing signal reading and signal processing ends. When the operation of transferring the photogenerated charge accumulated in the photodiode 101 to the gate terminal of the amplification transistor 104 is completed, the photodiode 101 is reset, and the photodiode 101 starts accumulating the photogenerated charge.

  Next, the operation in the period Th after the period Tv will be described. When the horizontal scanning signal φHSR (j) (j = 1, 2, 3, 4) is sequentially output from the horizontal scanning circuit 205, it is stored in the column processing circuits CDS1, CDS2, CDS3, CDS4 of the column processing circuit unit 204. The signals after the difference processing are sequentially read out to the horizontal signal line 207 via the horizontal selection switches MH1, MH2, MH3, and MH4 of the horizontal selection switch unit 206, respectively. The signal read to the horizontal signal line 207 is amplified by the output amplifier unit 208 and output to the outside. In FIG. 7, a signal output to the outside is indicated by Vout. At this time, an appropriate bias current is supplied to the output amplifier unit 208 according to the signal band.

  With the above operation, the pixel signals for one row are read out. By sequentially performing this operation from the first row to the third row, signals of all the pixels of the pixel portion 200 can be read (all pixel reading mode). That is, the pixel signals of the pixels P11 to P34 of the pixel unit 200 are sequentially output from the output amplifier unit 208 as Vout. The above period is one frame period Tf, which is a period for accumulating photogenerated charges of the photodiode 101 in this description.

  Next, a description will be given of a case where still image shooting is performed using the solid-state imaging device shown in FIG. In still image shooting, an exposure time is determined using a mechanical shutter. The operation during still image shooting is as follows. All pixels are reset (initial reset) in a state where the mechanical shutter is closed and shielded from light, and then the front curtain of the mechanical shutter is opened to start exposure. Thereafter, after a desired time has elapsed, the rear curtain of the mechanical shutter is closed to shield the light, and the exposure ends. After the exposure is completed, a reading operation is performed.

  In a digital camera or the like, not only pixel information of all pixels is read out independently, but an operation mode in which only a part of pixel information is used by reducing the amount of pixel information actually used may be provided. For example, there are a so-called thinning-out reading mode in which pixel signals are read for each row or column at a predetermined interval, and a cut-out mode in which pixel signals are read out by dividing a certain area. These operation modes are used, for example, when a subject is monitored with a liquid crystal monitor. This is because it is only necessary to read out information for the number of pixels of the monitor from the pixel signal.

  Further, in image transmission in a portable device such as a digital camera, the transmission data rate is limited. Therefore, in order to obtain a high-definition image for a still image, pixel information of all the pixels is transmitted, and for a moving image, the information amount is reduced by thinning out the pixel information.

  A solid-state imaging device having such a function has been proposed which has a function of switching a current source connected to the vertical signal line 110 by a switch in the thinning readout mode. An example is shown in FIG. In the configuration shown in FIG. 8, a switch 120 is provided between the current sources ML1, ML2, ML3, ML4 and the GND line 111, and a control unit 209 that controls ON / OFF of the switch 120 is provided. The configuration is the same as that shown in FIG. In this solid-state imaging device, in the thinning readout mode, the current source connected to the column from which the pixel signal is read is turned on by the switch 120, and the current source connected to the column from which the pixel signal is not read is turned off by the switch 120. Therefore, low power consumption is achieved in the thinning readout mode (see Patent Document 1). In the thinning readout mode, the horizontal scanning circuit 205 turns on only the horizontal selection switch of the column from which the pixel signal is read by the horizontal scanning signal φHSR (j), so that the pixel signal for each column spaced by a predetermined interval is turned on. Is read out.

JP 2007-142738 A

  However, in the above-described solid-state imaging device, since the current value flowing through the GND line 111 is different between the thinning readout mode and the all pixel readout mode, the reference of the current sources ML1 to ML4 is caused by the voltage drop due to the wiring resistance of the GND line 111. The GND level becomes fluctuating. For this reason, even if the output level in the pixel is the same, the signal level in the vertical signal line 110 differs between the thinning readout mode and the all pixel readout mode. Therefore, the input level to the signal processing circuit at the subsequent stage differs between the thinning readout mode and the all-pixel readout mode, and the signal range to be handled changes. For this reason, there has been a problem that even if optimum signal processing is performed in one of the operation modes, a good image cannot be obtained in the other operation mode.

  The present invention has been made in view of the above-described problems, and an object thereof is to provide a solid-state imaging device and a camera system capable of obtaining a good image while reducing power consumption in the thinning readout mode. To do.

  The present invention has been made to solve the above-described problem, and has a structure in which a plurality of pixels each having a photoelectric conversion element for accumulating electric charges are two-dimensionally arranged. A solid-state imaging device operable in a thinning readout mode for reading out signals corresponding to charges of only some of the pixels included in a column, wherein the solid-state imaging device includes pixels from which signals are read out in the thinning readout mode. A first pixel column, a second pixel column composed of pixels from which the signal is not read out in the thinning readout mode among the plurality of pixels, and one terminal for flowing in or out a predetermined amount of current, A plurality of first current sources connected to a first signal line extending from each pixel of the first pixel column and one terminal for flowing in or out a predetermined amount of current are connected to the second pixel column. Picture A plurality of second current sources connected to a second signal line extending from each, a first position to which a first voltage is applied, and the other terminal of each of the plurality of first current sources are electrically connected A second wiring for electrically connecting a second position to which a second voltage is applied and the other terminal of each of the plurality of second current sources, and the second readout in the thinning readout mode. And a switch that electrically disconnects the current source from the second signal line.

  In the solid-state imaging device of the present invention, the level of the second voltage is a power supply voltage level or a GND level.

  In the solid-state imaging device of the present invention, the power supply voltage is applied to the first power supply line that electrically connects the third position to which the power supply voltage is applied and the power supply voltage input terminal of each pixel of the first pixel column. And a second power supply line for electrically connecting the fourth position to the power supply voltage input terminal of each pixel of the second pixel column.

  Moreover, this invention is a camera system which has said solid-state imaging device.

  According to the present invention, the power consumption can be reduced by electrically disconnecting the second current source connected to the second pixel column from which no signal is read out from the second signal line in the thinning readout mode. it can. In addition, since the variation between the current flowing through the first wiring and the current flowing through the second wiring is reduced regardless of the operation mode, the variation in the signal output from the pixel is reduced, which is favorable. An image can be obtained.

1 is a block diagram illustrating a configuration of a solid-state imaging device according to a first embodiment of the present invention. It is a block diagram which shows the structure of the electric current source part periphery which the solid-state imaging device by the 1st Embodiment of this invention has. 1 is a block diagram illustrating a configuration of a digital camera according to a first embodiment of the present invention. It is a block diagram which shows the structure of the solid-state imaging device by the 2nd Embodiment of this invention. It is a circuit diagram which shows the structure of a pixel. It is a block diagram which shows the structure of the conventional solid-state imaging device. It is a timing chart which shows operation | movement of the conventional solid-state imaging device. It is a block diagram which shows the structure around the current source part which the conventional solid-state imaging device has.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
First, a first embodiment of the present invention will be described. FIG. 1 shows the overall configuration of the solid-state imaging device according to the present embodiment. The configuration shown in FIG. 1 is a control unit 209 that controls ON / OFF of the GND lines 111a and 111b connected to the current sources (ML1, ML2, ML3, and ML4) and the current sources (ML1, ML2, ML3, and ML4). The configuration is the same as that shown in FIG. In addition, the configuration of the unit pixels 100 (pixels P11 to P34) configuring the pixel unit 200 is the same as the configuration illustrated in FIG.

  The pixels P11, P21, and P31 constitute the first pixel column, the pixels P12, P22, and P32 constitute the second pixel column, and the pixels P13, P23, and P33 constitute the third pixel column. Pixels P14, P24, and P34 constitute a fourth pixel column. The solid-state imaging device according to the present embodiment can operate in each of the all-pixel readout mode and the thinning readout mode. In the all pixel readout mode, signals are read from all the pixel columns, but in the thinning readout mode, signals are read from the first pixel column and the third pixel column, and the second pixel column and the fourth column. No signal is read from the pixel column.

  FIG. 2 shows a configuration around the current source unit 201 connected to the vertical signal line 110. One terminal of the current sources ML 1, ML 2, ML 3, ML 4 constituting the current source unit 201 is connected to vertical signal lines 110-1 to 110-4 extending from the pixel unit 200. A predetermined amount of current flows from one of the vertical signal lines 110-1 to 110-4 to one terminal of each of the current sources ML1, ML2, ML3, and ML4, or one terminal of each of the current sources ML1, ML2, ML3, and ML4. Current of a predetermined magnitude flows out from the vertical signal lines 110-1 to 110-4. The other terminals of the current sources ML1, ML2, ML3, and ML4 are connected to the GND lines 111a and 111b via the switch 120.

  The switch 120 has a function of switching the current source ON and OFF. One terminal of the switch 120 is connected to the other terminals of the current sources ML1, ML2, ML3, and ML4, and the other terminal of the switch 120 is connected to the GND lines 111a and 111b. The GND line 111a is connected to the other terminals of the current sources ML1 and ML3 connected to the vertical signal lines 110-1 and 110-3 of the first pixel column and the third pixel column for reading signals in the thinning readout mode. Are connected via a switch 120. The GND line 111b is the other terminal of the current sources ML2 and ML4 connected to the vertical signal lines 110-2 and 110-4 of the second and fourth pixel columns from which signals are not read out in the thinning readout mode. Are connected through a switch 120. The GND level is applied to the GND lines 111a and 111b.

  Next, the configuration of a digital camera when the above-described solid-state imaging device is applied to a digital camera (camera system) will be described with reference to FIG. In FIG. 3, the lens 1 forms a subject image on the solid-state imaging device 5. The lens control device 2 drives and controls the zoom, focus, aperture, and the like of the lens 1. The shutter 3 is a light shielding member, and is a focal plane type shutter mechanism used in a so-called single-lens reflex camera. The shutter driving device 4 controls the driving of the shutter 3.

  The solid-state imaging device 5 has the configuration shown in FIG. 1, and takes in the subject image formed by the lens 1 as an image signal. The A / D converter 6 converts the signal output from the output terminal of the solid-state imaging device 5 into a digital signal. The imaging signal processing circuit 9 performs amplification of the image signal, various corrections of the image data, compression of the image data, and the like on the signal output from the A / D conversion unit 6.

  The drive circuit 7 drives and controls the solid-state imaging device 5. The control device 11 controls the entire digital camera. The memory 8 temporarily stores image data. The recording device 10 is a recording medium such as a detachable semiconductor memory, and can record or read image data.

  When the solid-state imaging device having the above configuration operates in the all-pixel readout mode, the switches 120 connected to all the current sources ML1, ML2, ML3, and ML4 are turned on. On the other hand, when the solid-state imaging device operates in the thinning readout mode, the current sources ML2 connected to the vertical signal lines 110-2 and 110-4 of the second and fourth pixel columns from which signals are not read out. Only the switch 120 connected to ML4 is turned OFF. As a result, low power consumption can be achieved in the thinning readout mode.

  Further, since the GND line is divided into the GND line 111a and the GND line 111b, the voltage drop due to the wiring resistance of the GND line is equal between the thinning readout mode and the all-pixel readout mode. That is, the reference level does not change in the thinning readout mode and the all-pixel readout mode, and the current flowing through the GND line does not change. For this reason, if the output level in the pixel is the same in the thinning readout mode and the all-pixel readout mode, the signal level on the vertical signal line 110 is the same, and the pixel output signal of the same level is used in the signal processing circuit in the subsequent stage. Can be obtained. Therefore, optimal signal processing can be performed in both modes, and a good image can be obtained.

  In the present embodiment, the pixel column from which a signal is read out in the thinning readout mode and the pixel column from which no signal is read out are separated from each other.

(Second Embodiment)
Next, a second embodiment of the present invention will be described. In the present embodiment, a configuration for reducing the fluctuation of the GND level will be described. FIG. 4 shows the overall configuration of the solid-state imaging device according to the present embodiment. The configuration shown in FIG. 4 is the same as the configuration shown in FIG. 1 except for the pixel power supply lines 106a and 106b.

  Pixel power supply lines 106a and 106b are connected to the pixels P11 to P34. The pixel power supply line 106a is connected to the pixels P11, P21, and P31 in the first pixel column and the pixels P13, P23, and P33 in the third pixel column for reading out signals in the thinning-out reading mode, and is in the all-pixel reading mode. The pixel power supply VDD is supplied to each pixel in the time and thinning readout mode. The pixel power line 106b is connected to the pixels P12, P22, and P32 of the second pixel column and the pixels P14, P24, and P34 of the fourth pixel column that do not read signals in the thinning readout mode, and all pixel readout is performed. The pixel power supply VDD is supplied to each pixel only in the mode. The points other than the above are the same as in the first embodiment.

  In the solid-state imaging device having such a configuration, as in the first embodiment, it is possible to turn off the current source of the pixel column that does not read out signals in the thinning readout mode, thereby realizing low power consumption. be able to. As in the first embodiment, the reference level does not change in the thinning readout mode and the all-pixel readout mode, and the current flowing through the GND line does not change. Furthermore, since the power supply level does not change during the thinning readout mode and the all-pixel readout mode, the change in the reference level is further suppressed. Therefore, if the output level in the pixel is the same in the all-pixel reading mode and the thinning-out reading mode, the pixel output signal of the same level can be obtained in the signal processing circuit in the subsequent stage. Therefore, optimal signal processing can be performed in both modes, and a good image can be obtained.

  In the present embodiment, the pixel column from which a signal is read out in the thinning readout mode and the pixel column from which no signal is read out are separated from each other.

  As described above, the embodiments of the present invention have been described in detail with reference to the drawings. However, the specific configuration is not limited to the above-described embodiments, and includes design changes and the like without departing from the gist of the present invention. . For example, the GND lines 111a and 111b in FIG. 1 or 4 may be connected to a voltage source that outputs a predetermined voltage.

  DESCRIPTION OF SYMBOLS 100 ... Unit pixel, 101 ... Photodiode, 102 ... Transfer transistor, 103 ... Reset transistor, 104 ... Amplification transistor, 105 ... Selection transistor, 200 ... Pixel part, 201 ... Current source unit, 202 ... Vertical scanning circuit, 203 ... Vertical selection unit, 204 ... Column processing circuit unit, 205 ... Horizontal scanning circuit, 206 ... Horizontal selection switch unit, 208 ... Output amplifier unit, 209 ... Control unit

Claims (4)

It has a structure in which a plurality of pixels each having a photoelectric conversion element for accumulating charges are two-dimensionally arranged, and reads out a signal corresponding to the charge of only some of the pixels included in a predetermined column among the plurality of pixels. A solid-state imaging device operable in a thinning readout mode,
A first pixel column composed of pixels from which signals are read out in the thinning readout mode among the plurality of pixels;
A second pixel column composed of pixels from which signals are not read out in the thinning readout mode among the plurality of pixels;
A plurality of first current sources connected to a first signal line extending from each of the pixels of the first pixel column, wherein one terminal for flowing in or out a predetermined amount of current;
A plurality of second current sources connected to second signal lines extending from the respective pixels of the second pixel column, wherein one terminal for flowing in or out a predetermined amount of current;
A first wiring electrically connecting a first position to which a first voltage is applied and the other terminal of each of the plurality of first current sources;
A second wiring electrically connecting a second position to which a second voltage is applied and the other terminal of each of the plurality of second current sources;
A switch for electrically disconnecting the second current source from the second signal line during the thinning readout mode;
A solid-state imaging device.   The solid-state imaging device according to claim 1, wherein the level of the second voltage is a level of a power supply voltage or a GND level. A first power supply line electrically connecting a third position to which a power supply voltage is applied and a power supply voltage input terminal of each pixel of the first pixel column;
A second power supply line for electrically connecting a fourth position to which a power supply voltage is applied and a power supply voltage input terminal of each pixel of the second pixel column;
The solid-state imaging device according to claim 1, further comprising:   The camera system which has a solid-state imaging device in any one of Claims 1-3.

Images