JP2013162421A - Solid-state imaging apparatus and digital camera employing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the quality of an image to be obtained by reducing influences of a dark current depending on heat generated from circuits provided around a pixel part.SOLUTION: A solid-state imaging apparatus 4 comprises a plurality of pixels PX which are disposed in a two-dimensional manner, and control means 23 which controls the plurality of pixels PX to read out signals from pixels PX of rows at one side in a column direction of the plurality of pixels PX and pixels PX of rows at another side, among the plurality of pixels, before reading out signals from pixels PX of rows near the center in the column direction among the plurality of pixels PX.

Description

  The present invention relates to a solid-state imaging device and a digital camera using the same.

  In an electronic camera such as a digital camera, an XY address type solid-state imaging device such as a CMOS image sensor (for example, Patent Document 1 below) is generally used.

  Conventionally, readout of signals from the XY address type solid-state imaging device has been performed in order from the horizontal line at one end of the imaging device in the vertical direction to the horizontal line at the other end in the vertical direction for each horizontal line.

JP-A-11-122532

  However, in the conventional electronic camera, the influence of the dark current depending on the heat generated from the circuit provided around the pixel portion is increased, and the image quality of the obtained image is deteriorated. This point will be described in detail later in the description of the comparative example compared with the present invention.

  The present invention has been made in view of such circumstances, and can reduce the influence of dark current depending on heat generated from a circuit provided in the periphery of the pixel portion, thereby improving the image quality of the obtained image. It is an object of the present invention to provide a solid-state imaging device that can be used, and an electronic camera using the same.

  The following aspects are presented as means for solving the problems. The solid-state imaging device according to the first aspect is ahead of reading out signals from a plurality of pixels arranged in a two-dimensional manner and pixels in a row near the center of the plurality of pixels in the column direction. And control means for controlling the plurality of pixels so as to read signals from pixels in one row in the column direction and pixels in the other row of the plurality of pixels. .

  A solid-state imaging device according to a second aspect is the solid-state imaging device according to the first aspect, wherein circuit portions that generate heat during operation are respectively disposed on both sides in the column direction with respect to the pixel portion where the plurality of pixels are disposed. .

  In the solid-state imaging device according to a third aspect, in the first or second aspect, the control means has the same readout timing of signals from pixels in the same row among the plurality of pixels, and the plurality The plurality of pixels are controlled so that readout timings of signals from pixels in different rows of the pixels are different.

  The solid-state imaging device according to a fourth aspect is the solid state imaging device according to the third aspect, wherein the one side and the other side in the column direction are k (k is an integer greater than or equal to 1) rows in the column direction. The plurality of pixels are controlled so that signals are sequentially read out from pixels in each of the k rows sequentially selected from the extreme end of the selected side while being alternately selected one by one. .

  In the solid-state imaging device according to the fifth aspect, in the fourth aspect, k is 1, and the control unit generates a first shift pulse for selecting the row on the one side in the column direction. A first shift register; and a second shift register that generates a second shift pulse for selecting the other row in the column direction. The first and second shift registers include: The generation cycle of the first shift pulse and the generation cycle of the second shift pulse are the same, and the generation timing of the first shift pulse and the generation timing of the second shift pulse are the generation cycle. It is driven so as to be shifted by a half cycle.

  The solid-state imaging device according to a sixth aspect is the solid-state imaging device according to any one of the first to fifth aspects, wherein the control unit is arranged in the vicinity of the center in the column direction of the plurality of pixels in the global shutter operation. Prior to reading out signals from the pixels in the row, the plurality of pixels are controlled so as to read out signals from the pixels in one row in the column direction and the pixels in the other row of the plurality of pixels. Is.

  The solid-state imaging device according to a seventh aspect is the solid-state imaging device according to any one of the first to sixth aspects, wherein the control means is arranged in a rolling shutter operation near the center in the column direction of the plurality of pixels. Prior to resetting the pixels in the row, the pixels in one row in the column direction and the pixels in the other row in the plurality of pixels are reset, and the pixels in the plurality of pixels are reset. Before reading out signals from the pixels in the row near the center of the plurality of pixels in the column direction, the signals are read out from the pixels in one row in the column direction and the pixels in the other row of the plurality of pixels. Thus, the plurality of pixels are controlled.

  An electronic camera according to an eighth aspect includes the solid-state imaging device according to any one of the first to seventh aspects.

  According to the present invention, it is possible to reduce the influence of dark current depending on heat generated from a circuit provided in the periphery of a pixel unit, and to improve the image quality of an obtained image, and to this An electronic camera using can be provided.

1 is a schematic block diagram schematically showing an electronic camera according to an embodiment of the present invention. It is a circuit diagram which shows schematic structure of the solid-state imaging device in FIG. FIG. 3 is a circuit diagram showing a pixel in FIG. 2. FIG. 3 is a schematic plan view schematically showing the solid-state imaging device shown in FIG. 2. 3 is a timing chart illustrating an example of a global shutter operation of the solid-state imaging device illustrated in FIG. 2. It is a circuit diagram which shows schematic structure of the solid-state imaging device by a comparative example. 7 is a timing chart showing a global shutter operation of the solid-state imaging device shown in FIG. 6. 7 is a diagram illustrating signal levels of pixels in each row obtained during a global shutter operation of a solid-state imaging device similar to the solid-state imaging device illustrated in FIG. 2 and a solid-state imaging device similar to the solid-state imaging device illustrated in FIG. 3 is a timing chart illustrating an example of a rolling shutter operation of the solid-state imaging device illustrated in FIG. 2. 7 is a timing chart illustrating a rolling shutter operation of the solid-state imaging device illustrated in FIG. 6. FIG. 7 is a diagram schematically illustrating a state of a subject and an image obtained during a rolling shutter operation of the solid-state imaging device illustrated in FIG. 2 and the solid-state imaging device illustrated in FIG. 6.

  Hereinafter, a solid-state imaging device and an electronic camera according to the present invention will be described with reference to the drawings.

  FIG. 1 is a schematic block diagram schematically showing an electronic camera 1 according to an embodiment of the present invention.

  The electronic camera 1 according to the present embodiment is configured as, for example, a single-lens reflex digital camera. However, the electronic camera according to the present invention is not limited to this, and is mounted on another electronic camera such as a compact camera or a mobile phone. It can also be applied to electronic cameras.

  A photographing lens 2 is attached to the electronic camera 1. The photographing lens 2 is driven by a lens control unit 3 for focus and diaphragm. In the image space of the photographing lens 2, the imaging surface of the solid-state imaging device 4 is arranged.

  The solid-state imaging device 4 is driven by a command from the imaging control unit 5 and outputs a digital image signal. In the present embodiment, the imaging control unit 5 controls the solid-state imaging device 4 so as to perform a rolling shutter operation, which will be described later, in the electronic viewfinder mode or in moving image shooting. In the present embodiment, the imaging control unit 5 controls the solid-state imaging device 4 so as to perform a global shutter operation to be described later at the time of normal main shooting (at the time of still image shooting). Any image signal is processed by the digital signal processing unit 6 and then temporarily stored in the memory 7. The digital signal processing unit 6 performs image processing such as digital amplification, color interpolation processing, and white balance processing on the digital image signal output from the solid-state imaging device 4. The memory 7 is connected to the bus 8. The bus 8 is also connected with a lens control unit 3, an imaging control unit 5, a CPU 9, a display unit 10 such as a liquid crystal display panel, a recording unit 11, an image compression unit 12 and an image processing unit 13. An operation unit 14 such as a release button is connected to the CPU 9. A recording medium 11a is detachably attached to the recording unit 11.

  When the electronic viewfinder mode or moving image shooting is instructed by the operation of the operation unit 14, the CPU 9 in the electronic camera 1 drives the imaging control unit 5 accordingly. The imaging control unit 5 controls the solid-state imaging device 4 so as to perform a rolling shutter operation described later. At this time, the lens controller 3 appropriately adjusts the focus and the aperture. Digital image signals obtained from the solid-state imaging device 4 are stored in the memory 7. The CPU 9 displays an image signal on the display unit 10 in the electronic viewfinder mode, and records the image signal on the recording medium 11a during moving image shooting. In the case of normal main shooting (still image shooting) or the like, the CPU 9 stores the image signal in the memory 7 and then, based on a command from the operation unit 14, the image processing unit 13 or the image compression unit as necessary. 12, the desired processing is performed, and the processed signal is output to the recording unit 11 and recorded on the recording medium 11a.

  FIG. 2 is a circuit diagram showing a schematic configuration of the solid-state imaging device 4 in FIG. In the present embodiment, the solid-state imaging device 4 is configured as a CMOS type solid-state imaging device, but may be configured as another XY address type solid-state imaging device.

  As shown in FIG. 2, the solid-state imaging device 4 includes a pixel unit 21 including pixels PX arranged in a two-dimensional matrix in n rows and m columns, a timing generation circuit 22, a vertical scanning circuit 23, and pixels PX. Control lines 24 to 26 provided for each row, a plurality of (m) vertical signal lines 27 that receive signals from the pixels PX in the corresponding columns provided for each column of the pixels PX, and the vertical signal lines 27 A constant current source 28, a CDS circuit (correlated double sampling circuit) 29 and an A / D converter 30 provided corresponding to each vertical signal line 27, and a horizontal readout circuit 31. Yes.

  FIG. 3 is a circuit diagram showing one pixel PX in FIG. Each pixel PX, like a general CMOS image sensor, has a photodiode PD as a photoelectric conversion unit that generates and accumulates charge according to incident light, and a charge voltage that receives the charge and converts the charge into a voltage. A floating diffusion FD as a conversion unit, an amplification transistor AMP as an amplification unit that outputs a signal corresponding to the potential of the floating diffusion FD, a transfer transistor TX that transfers charges from the photodiode PD to the floating diffusion FD, and a floating diffusion FD 3 has a reset transistor RES for resetting the potential and a selection transistor SEL for selecting a readout row, which are connected as shown in FIG. In FIG. 3, VDD is a power supply potential. In the present embodiment, the transistors AMP, TX, RES, and SEL of the pixel PX are all nMOS transistors.

  The gate of the transfer transistor TX is commonly connected to the control line 25 for each row, and a control signal φTX for controlling the transfer transistor TX is supplied from the vertical scanning circuit 23 thereto. The gate of the reset transistor RES is commonly connected to the control line 24 for each row, and a control signal φRES for controlling the reset transistor RES is supplied from the vertical scanning circuit 23 to the reset line. The gates of the selection transistors SEL are commonly connected to the control line 26 for each row, and a control signal φSEL for controlling the selection transistors SEL is supplied from the vertical scanning circuit 23 thereto. When each control signal φTX is distinguished for each row, the control signal φTX in the j-th row is indicated by a symbol φTX (j). This also applies to the control signals φRES and φSEL.

  The photodiode PD of each pixel PX generates a signal charge according to the amount of incident light (subject light). The transfer transistor TX is turned on during the high level period of the control signal φTX, and transfers the charge of the photodiode PD to the floating diffusion FD. The reset transistor RES is turned on during the high level period (period of the power supply potential VDD) of the control signal φRES, and resets the floating diffusion FD.

  The amplification transistor AMP has its drain connected to the power supply potential VDD, its gate connected to the floating diffusion FD, its source connected to the drain of the selection transistor SEL, and a constant current source 28 (not shown in FIG. 3). 2) is configured as a load. The amplification transistor AMP outputs a read signal to the vertical signal line 27 via the selection transistor SEL according to the voltage value of the floating diffusion FD. The selection transistor SEL is turned on during the high level period of the control signal φSEL, and connects the source of the amplification transistor AMP to the vertical signal line 27.

  The vertical scanning circuit 23 is based on signals such as a clock and a pulse generated by the timing generation circuit 22 under the control of the imaging control unit 5 in FIG. 2 so as to realize a global shutter operation and a rolling shutter operation to be described later. Control signals φSEL, φRES, and φTX are output for each row of the pixels PX to control the pixels PX of the pixel unit 21. By this control, a signal (analog signal) of the pixel PX in the corresponding column is supplied to each vertical signal line 27.

  In the present embodiment, the vertical scanning circuit 23 includes an upper vertical shift register (first shift register) 32, a lower vertical shift register (second shift register) 33, and a vertical drive circuit 34. Yes. The upper vertical shift register 32 includes first shift pulses φV (1) to φV (n / n) for sequentially selecting each row of the upper half pixels PX in the order from the first row to the n / 2th row. 2) is generated. That is, the shift direction of the upper vertical shift register 32 is the lower direction in FIG. At this time, the upper vertical shift register 32 generates all of the shift pulses φV (1) to φV (n / 2) in response to the signal from the timing generation circuit 22 in the all-row read mode. In the thinning-out reading mode, the shift pulse of the row to be thinned out of the shift pulses φV (1) to φV (n / 2) is not generated through and the shift pulse of the row not to be thinned out (row to be read out). Only to generate. The lower vertical shift register 33 is a second shift for sequentially selecting each row of the lower half pixels PX from the (n / 2) + 1-th row to the n-th row in the reverse order. Pulses φV ((n / 2) +1) to φV (n) are generated. That is, the shift direction of the lower vertical shift register 33 is the upward direction in FIG. At this time, the lower vertical shift register 33 applies all of the shift pulses φV ((n / 2) +1) to φV (n) according to the signal from the timing generation circuit 22 in the all-row read mode. On the other hand, in the thinning-out reading mode, the shift pulse of the thinned-out row among the shift pulses φV ((n / 2) +1) to φV (n) is not generated and the row that is not thinned out (the row to be read out) ) Shift pulse only.

  The vertical shift registers 32 and 33 are driven by a signal from the timing generation circuit 22 so that the shift pulse generation period of the upper vertical shift register 32 and the lower vertical shift are both in the all-row reading mode and the thinning-out reading mode. The shift pulse generation period of the register 33 is also set to two horizontal periods, the timing of the start pulse from the timing generation circuit 22 for the upper vertical shift register 32 and the timing of the start pulse from the timing generation circuit 22 for the lower vertical shift register 33. Are shifted by one horizontal period so that the shift pulse generation timing of the upper vertical shift register 32 and the shift pulse generation timing of the lower vertical shift register 33 are shifted by a half period (one horizontal period) of the shift pulse generation period. Na To have.

  In the present embodiment, this allows the timing generation circuit 22 and the vertical scanning circuit 23 to read out rows from the pixels PX of the pixel unit 21 (all rows in the all-pixel reading mode, and thinning in the thinning-out reading mode). With respect to a non-drawing row), k (k is an integer of 1 or more) in one side (upper side in FIG. 2) and the other side (lower side in FIG. 2) in the column direction (vertical direction, vertical direction in FIG. 2). The pixels PX of the pixel unit 21 are controlled so that signals are sequentially read out from the pixels in each row of k rows sequentially selected from the extreme end of the selected side while alternately selecting rows. It is like that. However, in this embodiment, k = 1, and the row to be read out of the pixel PX of the pixel unit 21 is selected by alternately selecting the upper side in FIG. 2 and the lower side in FIG. On the selected side, the pixels PX of the pixel unit 21 are controlled so as to sequentially read out signals from one row of pixels sequentially selected from the extreme end of the selected side. Therefore, in this embodiment, in the all-row reading mode, the first row, the nth row, the second row, the n−1th row, the third row, the n-2th row,. The pixels PX in the (n / 2) -th row and the (n / 2) + 1-th row are sequentially read in that order.

  For example, a decoder circuit may be used instead of the shift registers 32 and 33. In this case, not only k may be set to 1, but k may be set to 2 or more. Further, in the present invention, with respect to the row to be read out of the pixel PX of the pixel unit 21, on the side selected while alternately selecting one side and the other side in the column direction by k (k is an integer of 1 or more) rows. It is provided in the periphery of the pixel unit 21 that the pixel PX of the pixel unit 21 is controlled so that signals are sequentially read from the pixels in each of the k rows sequentially selected from the extreme end on the selected side. Although it is preferable in order to further reduce the influence of dark current depending on heat generated from the circuit unit 41 (see FIG. 4 described later), the present invention is not limited to this. In the present invention, before reading a signal from the pixel PX in the column near the center in the column direction among the pixels PX in the pixel unit 21, the pixel in one row in the column direction among the pixels PX in the pixel unit 21. It is only necessary to control the pixel PX of the pixel unit 21 so that signals are read from PX and the pixel PX on the other side. In that case, the influence of the dark current can be reduced.

  The vertical drive circuit 34 is described later for each row of the pixels PX based on the shift pulses φV (1) to φV (n) from the vertical shift registers 32 and 33 and signals such as clocks and pulses from the timing generation circuit 22. Control signals φSEL, φRES, and φTX for outputting a global shutter operation and a rolling shutter operation described later are output.

  Note that the configuration of the pixel PX is not limited to the configuration illustrated in FIG. 3 described above. For example, for every two or more pixels PX adjacent in the column direction, the two or more pixels PX may share a set of floating diffusion FD, amplification transistor AMP, reset transistor RES, and selection transistor SEL.

  A signal read from the pixel PX to the vertical signal line 27 is subjected to a predetermined noise removal process by the CDS circuit 29 for each column, and then converted to a digital signal by the A / D converter 30. The digital signal is held in the A / D converter 30. A digital image signal held in each A / D converter 30 is horizontally scanned by a horizontal readout circuit 31 based on a signal such as a clock or a pulse from the timing generation circuit 22 and, if necessary, has a predetermined signal format. And output to the outside (digital signal processing unit 6 in FIG. 1).

  Under the control of the imaging control unit 5, the timing generation circuit 22 provides necessary clocks and clocks to other units (CDS circuit 29, A / D converter 30, horizontal readout circuit 31, etc.) in addition to the vertical scanning circuit 23. A signal such as a pulse is supplied to realize the above-described operation.

  FIG. 4 is a schematic plan view schematically showing the solid-state imaging device 4 shown in FIG. In the present embodiment, the circuit unit 41 including elements other than the pixel unit 21 in FIG. 2 is distributed on the upper side (one side in the row direction) and the lower side (the other side in the row direction) of the pixel unit 21. Are arranged. It is preferable to arrange the circuit units 41 symmetrically above and below the pixel unit 21 so that the heat generation state (the state of heat generated by the operation) of the upper part and the lower part of the circuit unit 41 are substantially the same. For example, in FIG. 2, the CDS circuit 29 and the A / D converter 30 are described as if they are arranged only below the pixel unit 21. It is preferable that the converters 30 are arranged in half on the upper side and the lower side of the pixel unit 21, respectively. In the present embodiment, the circuit unit 41 is disposed only on the upper side and the lower side of the pixel unit 21, but the circuit unit 41 is disposed not only on the upper side and the lower side of the pixel unit 21 but also on the left side and / or the right side. For example, the vertical scanning circuit 23 may be arranged on the left side of the pixel unit 21.

  FIG. 5 is a timing chart showing an example of the global shutter operation of the solid-state imaging device 4 shown in FIG. In the operation example shown in FIG. 5, the read operation is performed in the all row read mode in which all rows are read target rows. The transistors TX, RES, and SEL of the pixel PX are turned on in response to a high level (high) control signal. Note that the global shutter operation shown in FIG. 5 is performed at the time of still image shooting or the like.

  First, in a period T11, φTX of all rows is set to high (H), and the transfer transistors TX of all the pixels PX are turned on. At this time, φRES of all rows is set to high (H) and the reset transistors RES of all the pixels PX are turned on, so that the photodiode PD and the floating diffusion FD of all the pixels PX are reset in the period T11. The period T11 is a so-called global reset period. ΦTX of all rows is set to low (L) after the period T11, and the transfer transistor TX of the pixel PX is turned off.

  In a period T12 after the period T11, a mechanical shutter (not shown) is opened. This period T12 is an exposure period.

  Next, in a period T13, φSEL in the first row is set high (H). As a result, the selection transistor SEL in the first row is turned on, row selection in the first row is started, and source follower reading by the amplification transistor AMP in the first row is started.

  The period T21 is started after a predetermined period has elapsed since the start of the period T13. In the period T21, φRES in the first row is set to low (L), the reset transistor RES in the first row is turned off, and the reset of the floating diffusion FD in the first row is completed. Between the start time of the period T21 and the start time of the period T22, the dark level of the first row (a signal output from the amplification transistor AMP of the first row corresponding to the reset state of the floating diffusion FD) is the amplification transistor. The signal is clamped (saved) from the AMP to the CDS circuit 29 via the vertical signal line 27.

  In the period T22, φTX in the first row is set high (H), and the transfer transistor TX in the first row is turned on. Thereby, the signal charges accumulated in the photodiode PD of the pixel PX in the first row are transferred to the floating diffusion FD of the pixel PX. At the end of the period T22, φTX in the first row is set to low (L), and the transfer transistor TX in the first row is turned off. Between the end point of the period T22 and the end point of the period T21 (end point of the period T13), the potential fluctuation due to the charge transferred to the floating diffusion FD in the first row occurs from the amplification transistor AMP via the vertical signal line 27. Clamped to the CDS circuit 29. That is, the signal reading of the photodiode PD is performed. Then, the CDS circuit 29 acquires a difference signal between this signal and the previous dark level.

  Thereafter, at the end of the period T13 (end of the period T21), φRES in the first row is set to high (H), the reset transistor RES in the first row is turned on, and the floating diffusion FD in the first row is reset. Is started, φSEL in the first row is set to low (L), the selection transistor SEL in the first row is turned off, and the row selection in the first row is completed.

  Next, the operation moves to the period T14 of the selection operation of the nth row through the horizontal blanking period. A period from the start time of the selection operation period T13 of the first row to the start time of the selection operation period T14 of the n-th row is one horizontal period. Thereafter, after a horizontal blanking period, a selection operation period T15 for the second row, a selection operation period T16 for the (n-1) th row, a selection operation period for the third row, and a selection operation for the (n-2) th row, respectively. Period,..., (N / 2) row selection operation period, (n / 2) +1 row selection operation period sequentially, and then a horizontal blanking period. Since the operation similar to that of the first row is performed for each row other than the first row, the description thereof is omitted here. The start point of the ON period of the transfer transistor TX in the selection period of each row is delayed by a time ΔT (= 1 horizontal period length ta). In this way, when signals are read from all rows, reading of one frame of image signal is terminated. In each horizontal blanking period, the difference signal acquired by each CDS circuit 29 is converted to a digital signal by an A / D converter 30 and externally (digital signal processing in FIG. Part 6).

  As can be seen from the above description, in the operation example shown in FIG. 5, the signal readout timings for the pixels PX in the same row are the same, and the signal readout timings for the pixels PX in the different rows are different.

  As can be seen from the above description, in the operation example shown in FIG. 5, the photodiode PD of the pixel PX in the j-th row generates a signal charge proportional to the amount of light received during the exposure period T12. The photodiode PD of the pixel PX on the j-th row has a period from the end of the global reset period T11 to the start point of the on-period of the transfer transistor TX in the selection period on the j-th row (rising point of φ (j)). , Noise charges due to dark current can be accumulated. For example, the photodiode PD of the pixel PX in the second row has a noise charge caused by dark current during the period from the end of the global reset period T11 to the rise of φ (2) in the selection period of the second row. Can be accumulated.

  However, in the operation example shown in FIG. 5, the first line, the nth line, the second line, the n−1 line, the third line, the n−2 line,..., The (n / 2) line, (N / 2) +1 rows are read in order, and the rows close to the upper and lower circuit portions 41 of the pixel portion 21 are preferentially read, and the rows closer to the upper and lower circuit portions 41 to the inner rows (circuit portions). 41). Therefore, it can be read from the row before the heat propagated from the upper and lower circuit portions 41 to each row of the pixel portion 21 arrives, or is propagated from the upper and lower circuit portions 41 to each row of the pixel portion 21. The time from reading to reading can be shortened. For this reason, it is possible to prevent or reduce the dark current noise caused by the heat propagated from the upper and lower circuit portions 41 from being superimposed on the exposure charge. As a result, it is possible to reduce the influence of dark current depending on the heat generated from the circuit unit 41 provided around the pixel unit 21, and to improve the image quality of the obtained image.

  FIG. 6 is a circuit diagram showing a schematic configuration of a solid-state imaging device 54 according to a comparative example, and corresponds to FIG. 6, elements that are the same as or correspond to those in FIG. 2 are given the same reference numerals, and redundant descriptions thereof are omitted.

  The solid-state imaging device 54 shown in FIG. 6 is different from the solid-state imaging device 4 shown in FIG. 2 only in that a vertical shift register 35 is provided instead of the upper vertical shift register 32 and the lower vertical shift register 33. is there. The vertical shift register 35 generates shift pulses φV (1) to φV (n) for sequentially selecting all the rows from the first row to the n-th row in that order. That is, the shift direction of the vertical shift register 35 is the downward direction in FIG. At this time, the vertical shift register 35 generates all the shift pulses φV (1) to φV (n) in the all-row read mode in accordance with the signal from the timing generation circuit 22, while the thinned-out read is performed. In the case of the mode, the shift pulse of the thinned-out row among the shift pulses φV (1) to φV (n) is not generated through, and only the shift pulse of the row not to be thinned (row to be read) is generated. It has become. When the vertical shift register 35 is driven by a signal from the timing generation circuit 22, the shift pulse generation period of the vertical shift register 35 is set to one horizontal period in both the all-row reading mode and the thinning-out reading mode.

  Thus, in the solid-state imaging device 54 according to this comparative example, with respect to the row from which the pixel PX of the pixel unit 21 is to be read (all rows in the all-pixel read mode and rows that are not thinned in the thin-out read mode), 1 Signals are sequentially read from the pixels in each row in the direction from the row to the n-th row. Therefore, in this comparative example, in the all-row reading mode, the pixels PX in the first row, the second row, the third row, the fourth row,. Data are sequentially read in that order.

  FIG. 7 is a timing chart showing the global shutter operation of the solid-state imaging device 54 shown in FIG. 6, and corresponds to FIG. 7, elements that are the same as or correspond to those in FIG. 5 are given the same reference numerals, and redundant descriptions thereof are omitted. In the operation shown in FIG. 7 as well, as in the operation example shown in FIG.

  The global shutter operation of the solid-state imaging device 54 according to the comparative example shown in FIG. 7 is different from the global shutter operation of the solid-state imaging device 4 shown in FIG. 5 in the operation example shown in FIG. The rows, n−1, 3, n-2,..., (N / 2), (n / 2) +1 are read in this order, whereas FIG. In the operation shown, only the points read in the order of the first row, the second row, the third row, the fourth row,.

  Similarly to the operation illustrated in FIG. 5, the operation illustrated in FIG. 7 includes, in the photodiode PD of the pixel PX in the j-th row, the ON period of the transfer transistor TX in the selection period of the j-th row from the end of the global reset period T11. In the period up to the start time (rising time of φ (j)), noise charges due to dark current can be accumulated.

  In the operation shown in FIG. 7, the first row, the second row, the third row, the fourth row,..., The n−1th row, and the nth row are read in this order, so that it is close to the lower circuit portion 41. For the lower row, the period during which the noise charge due to the dark current can be accumulated becomes longer. Therefore, for the lower row close to the lower circuit portion 41, the time from when heat is propagated from the lower circuit portion 41 to the row becomes longer. For this reason, in the lower row of the pixel portions 21, a large amount of dark current noise caused by the heat propagated from the lower circuit portion 41 is superimposed on the exposure charge. As a result, the influence of the dark current depending on the heat generated from the circuit unit 41 provided on the lower side of the pixel unit 21 is increased, and so-called whitening occurs on the lower side of the obtained image. The image quality will deteriorate. In particular, when the number of pixels PX is large and the number of rows is large, or when the amount of heat generated by the circuit unit 41 is large due to an increase in speed or the like, the deterioration in image quality becomes large.

  On the other hand, in the operation shown in FIG. 5, the 1st row, the nth row, the 2nd row, the n−1th row, the 3rd row, the n−2th row,..., The (n / 2) th row. , (N / 2) +1 rows are read out in order, so that, as described above, before the heat propagated from the upper and lower circuit portions 41 to each row of the pixel portions 21 can be read from the rows, Alternatively, the time from propagation from the upper and lower circuit portions 41 to each row of the pixel portion 21 to reading can be shortened. For this reason, according to the present embodiment, it is possible to reduce the influence of the dark current depending on the heat generated from the circuit unit 41 provided around the pixel unit 21, and the whitening as in the comparative example can be reduced. It can be prevented or reduced, and the image quality of the obtained image can be improved.

  8A is actually obtained by causing the solid-state imaging device similar to the solid-state imaging device 54 shown in FIG. 6 to perform an operation similar to the global shutter operation shown in FIG. 7 while blocking incident light. The level of the image signal in each row is shown. FIG. 8B is actually obtained by causing the solid-state imaging device similar to the solid-state imaging device 4 shown in FIG. 2 to perform the same operation as the global shutter operation shown in FIG. 5 while blocking incident light. The level of the image signal in each row is shown.

  In FIG. 8A according to the comparative example, the pixel signal level increases and whitening occurs on the lower side (n-row side) of the obtained image, whereas FIG. 8 according to the present embodiment. In (b), the level of the pixel signal does not increase in the entire image including the lower side (n-row side) of the obtained image, and whitening does not occur.

  In addition, it is possible to improve the image quality by adopting a method of correcting an image in which whitening has occurred in the comparative example by image processing, but in that case, an image processing circuit or the like for the correction is provided. Cost. In this embodiment, as compared with the comparative example, only the reading order of each row is changed, so that such an image processing circuit or the like is not required. For this reason, in this Embodiment, since the circuit scale of the whole system of the electronic camera 1 can be made small, it also contributes to cost reduction and can also suppress the heat_generation | fever of the whole system. However, in the present embodiment, it is possible to further improve the image quality by using the image processing circuit for the correction together.

  FIG. 9 is a timing chart showing an example of the rolling shutter operation of the solid-state imaging device 4 shown in FIG. During the rolling shutter operation, a mechanical shutter (not shown) is kept open. In the operation example shown in FIG. 9, the reading operation is performed in the all-row reading mode in which all the rows are the reading target rows. However, in the rolling shutter operation, for example, in the electronic viewfinder mode or the moving image shooting, for example. Depending on the moving picture standard (Full HD, HD, etc.) to be realized and the frame rate (30 fps, 60 fps, etc.), a thinning-out reading mode in which only selected rows are read may be set. Note that a rolling shutter operation in the all-row reading mode as shown in FIG. 9 may be performed during still image shooting.

  In the rolling shutter operation shown in FIG. 9, the 1st row, the nth row, the 2nd row, the n−1th row, the 3rd row, the n-2th row,..., The (n / 2) th row, ( n / 2) The same operation is sequentially performed for each row in the order of the + 1st row. Therefore, only the operation in the first row will be described here. FIG. 9 shows operations for the first row, the nth row, the second row, and the n−1th row.

  First, while φRES in the first row is high (H), φTX in the first row is set to high (H) and low (L), thereby resetting the photodiode PD and the floating diffusion FD. After a predetermined time has elapsed, φSEL in the first row is set to high (H), and the selection transistor SEL in the first row is turned on. The first row φRES is set high (H) for a certain period from the start of φSEL high (H) in the first row, the level of the floating diffusion FD is reset to the reference level, and then the first row φRES is set low. (L). Next, a level (dark level) corresponding to the reference level of the floating diffusion FD is clamped to the CDS circuit 29 from the amplification transistor AMP in the first row via the vertical signal line 27.

  Next, φTX in the first row is again set to high (H) and low (L). As a result, the charges accumulated in the photodiodes PD in the first row are transferred to the floating diffusion FD. After that, a signal having a level corresponding to a signal in which the reference level and the signal due to the electric charge are superimposed is clamped from the amplification transistor AMP in the first row to the CDS circuit 29 via the vertical signal line 27. Then, the CDS circuit 29 acquires a difference signal between the signal clamped here and the previous dark level. Then, the difference signal acquired by each CDS circuit 29 is converted into a digital signal by the A / D converter 30 and output to the outside (digital signal processing unit 6 in FIG. 1) by the horizontal readout circuit 31.

  From the time when φTX of the first row is changed from high (H) to low (L) while φRES of the first row is high (H), φTX of the first row is then changed to high (H). The period up to the point of time is the exposure period for the first row. The exposure period of each row has the same length, but the first row, the nth row, the second row, the n−1th row, the third row, the n-2th row,..., (N / 2) The line shifts in the order of (n / 2) +1 line.

  As can be seen from the above description, the first line, the nth line, the second line, the n−1 line, the third line, the n−2 line,..., The (n / 2) line, (n / 2) The photodiode PD of the pixel PX is reset in the order of the + 1st row, and the 1st row, the nth row, the 2nd row, the n−1th row, the 3rd row, the n−2th row,. A signal is read from the pixel PX in the order of the (n / 2) th row and the (n / 2) + 1th row.

  FIG. 10 is a timing chart showing the rolling shutter operation of the solid-state imaging device 54 shown in FIG. 6, and corresponds to FIG. 10, elements that are the same as or correspond to those in FIG. 9 are given the same reference numerals, and redundant descriptions thereof are omitted. Also in the operation illustrated in FIG. 10, as in the operation example illustrated in FIG. 9, the read operation is performed in the all-row read mode in which all the rows are read target rows.

  The rolling shutter operation of the solid-state imaging device 54 according to the comparative example shown in FIG. 10 is different from the rolling shutter operation of the solid-state imaging device 4 shown in FIG. 9 in the example of operation shown in FIG. On the other hand, the same operation is performed in the order of the line, the (n−1) th line, the third line, the (n−2) th line,..., The (n / 2) line, and the (n / 2) +1 line. The operation shown in FIG. 10 is only that the same operation is performed in the order of the first row, the second row, the third row, the fourth row,..., The n−1th row, and the nth row.

  In both the operation example shown in FIG. 9 and the operation shown in FIG. 10, the length of the period from the time when the photodiode PD is reset to the start time of the on-period of the transfer transistor TX is the same for any row. Therefore, it is difficult to be affected by dark current. However, when these operations are performed in still image shooting or the like, the operation shown in FIG. 10 according to the comparative example has a relatively large influence of dark current due to heat propagated from the upper and lower circuit portions 41, and the image quality is increased. In contrast, in the operation example shown in FIG. 9 according to the present embodiment, the influence of the dark current caused by the heat propagated from the upper and lower circuit portions 41 is relatively small, and the image quality can be improved. .

  In the operation example shown in FIG. 9 according to the present embodiment, an advantage that rolling distortion is less noticeable than the operation shown in FIG. 10 according to the comparative example is also obtained. For example, as shown in FIG. 11 (a), when a rectangular subject moving in the right direction in the drawing is imaged by the operation shown in FIG. 10 according to the comparative example, the subject image is shown in FIG. 11 (b). It becomes a parallelogram shape that is slanted as a whole, and rolling distortion is relatively conspicuous. On the other hand, as shown in FIG. 11 (a), when a rectangular object traveling in the right direction in the drawing is imaged in the operation example shown in FIG. 9 according to the present embodiment, it is shown in FIG. 11 (c). Thus, the subject image has a shape in which the vicinity of the center is shifted to the right as compared with the upper side and the lower side, and the rolling distortion is relatively inconspicuous.

  It is preferable to reduce the voltage supplied to the circuit unit 41 because the amount of heat generated from the circuit unit 41 is reduced and the influence of dark current due to heat propagated from the upper and lower circuit units 41 is further reduced. In particular, in the case of moving image shooting, the amount of heat generated from the circuit unit 41 increases, so it is preferable to reduce the voltage supplied to the circuit unit 41.

  As mentioned above, although embodiment of this invention and its modification were demonstrated, this invention is not limited to these.

  For example, in the above embodiment, the row readout order of the present invention is applied to both the global shutter operation and the rolling shutter operation. However, in the present invention, the present invention is applied to only one of the global shutter operation and the rolling shutter operation. The other row reading order may be applied, and the other operation may adopt the relatively same row reading order.

  The present invention is not limited to the all-row readout mode or the thinning-out readout mode, and is also applied to a solid-state imaging device configured to be able to perform an addition or mixed readout mode that reads out signals of pixels in a plurality of rows by addition or mixing. Can be applied.

DESCRIPTION OF SYMBOLS 1 Electronic camera 4 Solid-state imaging device 21 Pixel part 22 Timing generation circuit 23 Vertical scanning circuit 32 Upper vertical shift register 33 Lower vertical shift register 41 Circuit part

Claims (8)

A plurality of pixels arranged two-dimensionally;
Prior to reading a signal from a pixel in a row near the center in the column direction of the plurality of pixels of the plurality of pixels, a pixel in one row in the column direction and the other side of the plurality of pixels Control means for controlling the plurality of pixels so as to read out signals from the pixels in the row;
A solid-state imaging device comprising:   The solid-state imaging device according to claim 1, wherein circuit portions that generate heat during operation are arranged on both sides in the column direction with respect to the pixel portion where the plurality of pixels are arranged.   The control means is such that the readout timing of signals from the pixels in the same row among the plurality of pixels is the same, and the readout timing of signals from the pixels in different rows of the plurality of pixels is different. The solid-state imaging device according to claim 1, wherein the plurality of pixels are controlled.   With respect to the row to be read out of the plurality of pixels, the one side and the other side in the column direction are alternately selected by k (k is an integer of 1 or more) rows and the selected side is selected. 4. The solid-state imaging device according to claim 3, wherein the plurality of pixels are controlled so as to sequentially read out signals from pixels in each row of k rows sequentially selected from the end. 5. k is 1,
The control unit includes: a first shift register that generates a first shift pulse for selecting the one row in the column direction; and a second shift register for selecting the other row in the column direction. A second shift register for generating a shift pulse of
The first and second shift registers have the same generation period of the first shift pulse and the generation period of the second shift pulse, and the generation timing of the first shift pulse and the second shift register. Is driven such that the generation timing of the shift pulse is shifted by a half period of the generation period,
The solid-state imaging device according to claim 4.   In the global shutter operation, the control unit may read the signals in the column direction among the plurality of pixels before reading out signals from the pixels in the row in the vicinity of the center in the column direction of the plurality of pixels. 6. The solid-state imaging device according to claim 1, wherein the plurality of pixels are controlled so as to read signals from pixels on one side row and pixels on the other side row.   In the rolling shutter operation, the control means is configured to reset one of the plurality of pixels in the column direction before resetting a pixel in the vicinity of the center in the column direction of the plurality of pixels. Before resetting the pixels in the side row and the pixels in the other side row, and reading out signals from the pixels in the row near the center of the plurality of pixels in the column direction, The plurality of pixels are controlled so that signals are read out from pixels in one row in the column direction and pixels in the other row of the plurality of pixels. The solid-state imaging device described in 1.   An electronic camera comprising the solid-state imaging device according to claim 1.