JP5203719B2 - Method for manufacturing dual gate semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a dual gate semiconductor device and a structure thereof, and more particularly to a method for manufacturing a CMOSFET semiconductor device and a structure thereof.

In recent years, in a dual gate semiconductor device such as a CMOSFET, a metal gate electrode is used to prevent the formation of a depletion layer as the semiconductor device is miniaturized. In the formation process of the metal gate electrode, it is difficult to form the metal gate electrodes made of different materials by etching, like the p-type FET and the n-type FET. For this reason, a manufacturing method is used in which both gate electrodes are formed of the first metal material and embedded in the interlayer insulating layer, and then one of the gate electrodes is selectively removed and the second metal material is embedded instead. (For example, refer to Patent Document 1).
JP 2002-289700 A

However, in a dual gate semiconductor device such as a CMOSFET, it is necessary to connect a gate wiring made of the first metal material and a gate wiring made of the second metal material. However, there is a problem that disconnection is likely to occur, and the manufacturing yield decreases.
In addition, when the gate wiring is composed of a metal gate electrode film and a low-resistance metal gate wiring film formed thereon, the connection of the gate wiring sandwiches the metal gate electrode film, so that the connection portion has a high resistance, and the semiconductor There was also a problem that the characteristics of the device deteriorated.

  Accordingly, an object of the present invention is to provide a method for manufacturing a dual gate semiconductor device and a structure thereof in which the connection between two gate wirings can be easily performed with low resistance in a dual gate semiconductor device.

  The present invention is a method of manufacturing a dual gate semiconductor device including a first conductivity type FET and a second conductivity type FET, the step of preparing a semiconductor substrate, and a gate insulating film and a first on the semiconductor substrate, respectively. Forming a first and second electrode including a gate metal film; forming an interlayer insulating layer so as to embed the first and second electrodes; and an upper portion of the first and second electrodes On the interlayer insulating layer so as to cover the first and second electrodes, a step of exposing the first insulating film from the interlayer insulating layer, a selective removing step of selectively removing the first gate metal film of the second electrode. A deposition step of depositing a two-gate metal film and a gate wiring film; and patterning the second gate metal film and the gate wiring film to form a first gate metal film, a second gate metal film, and a gate wiring film on the gate insulating film The first game Forming a second gate electrode in which a second gate metal film and a gate wiring film are sequentially stacked on the gate insulating film, and connecting the first gate electrode and the second gate electrode with the gate wiring film; A method of manufacturing a dual gate semiconductor device.

  The present invention also provides a dual gate semiconductor device including two FETs having different conductivity types, a semiconductor substrate, and a first gate metal film sequentially stacked on the gate insulating film provided on the semiconductor substrate, The first gate electrode of the first conductivity type FET including the second gate metal film and the gate wiring film, and the second conductivity type FET including the second gate metal film and the gate wiring film sequentially stacked on the gate insulating film. A dual gate semiconductor device having a second gate electrode, wherein the first gate electrode and the second gate electrode are electrically connected by a gate wiring film common to these electrodes.

  With the method for manufacturing a semiconductor device according to the present invention, it is possible to provide a dual gate semiconductor device having a good manufacturing yield and good characteristics.

Embodiment 1 FIG.
FIG. 1 is a cross-sectional view of the manufacturing process of the CMOSFET semiconductor device according to the first embodiment, the whole being represented by 100. This manufacturing process includes the following processes 1 to 9.

Step 1: A silicon substrate 1 is prepared as shown in FIG. A silicon layer 2 is formed on the silicon substrate 1. In the silicon layer 2, an n-FET region and a p-FET region electrically isolated by an element isolation region 3 such as silicon oxide are formed. These regions include, for example, a gate insulating film 4 made of a High-k (high dielectric) material such as HfSiON, a first gate metal film 5 made of TaSiN, a metal gate wiring film 13 made of W, and a hard made of SiN. A mask 6 is formed. For the first gate metal film 5, not only TaSiN but also a metal film such as TaC, TaN, TiSiN, TiN may be used. These can be simultaneously formed by RIE or the like using the hard mask 6. Subsequently, a sidewall 7 made of, for example, SiO ₂ is formed. Further, ion implantation using the hard mask 6 or the like as a mask and activation of implanted ions by heat treatment are performed to form the source / drain regions 8.

  Step 2: As shown in FIG. 1B, a PMD (Pre-Metal Dielectric) layer 10 is formed by, for example, a CVD method.

  Step 3: As shown in FIG. 1C, the PMD layer 10 is planarized using, for example, a CMP method. In this process, the hard mask 6 embedded in the PMD layer 10 is exposed.

  Step 4: As shown in FIG. 1D, the hard mask 6 is selectively removed using RIE or wet etching. Subsequently, the metal gate wiring film 13 is selectively removed. The removal of the metal gate wiring film 13 is performed, for example, by wet etching using hydrogen peroxide water at 60 ° C.

  Step 5: As shown in FIG. 1E, after the amorphous silicon layer 14 is formed on the entire surface, the amorphous silicon layer 14 is left only in the n-FET region by etching.

  Step 6: As shown in FIG. 1F, the first gate metal film 5 in the p-FET region is selectively removed using the amorphous silicon layer 14 as a mask. The removal of the first gate metal film 5 is performed, for example, by wet etching using ammonia hydrogen peroxide mixed water (APM) at about 60 to 80 ° C.

  Step 7: As shown in FIG. 1G, the amorphous silicon layer 14 in the n-FET region is removed by wet etching using hydrogen peroxide. Subsequently, for example, a second gate metal film 5 made of TiN and a metal gate wiring film 25 made of W are formed on the entire surface. In this process, the first gate metal film 5 in the n-FET region and the second gate metal film 20 in the p-FET region are connected.

The second gate metal film 5 includes TiN, TiAlN, TaN, TaAlN, Ru, Ir, Pt, Ni, Co, W, WN, Mo, MoN, NiSi (preferably Ni _x Si x is 1 or more), It is preferable to select a material mainly composed of a material selected from the group consisting of PtSi (preferably _x of Pt _x Si is 1 or more). The same applies to the following second and third embodiments.

  Moreover, it is preferable that the temperature of the silicon substrate 1 is 500 degrees C or less after the following processes 8.

  Step 8: As shown in FIG. 1H, the second gate metal film 20 and the metal gate wiring film 25 are etched using an etching mask (not shown). In this step, the electrode may be patterned by planarizing the PMD layer 10 using a CMP process.

Step 9: As shown in FIG. 1I, an interlayer insulating layer 30 made of, for example, SiO ₂ is formed, and lead wires 35 are formed from the source / drain regions, thereby completing the CMOSFET semiconductor device 100.

  2A and 2B are schematic views of the CMOSFET semiconductor device 100, where FIG. 2A is a top view and FIG. 2B is a cross-sectional view when viewed in the II-II direction of FIG. 2, the same reference numerals as those in FIG. 1 denote the same or corresponding parts.

As described above, in step 7 (FIG. 1G), the gate electrode in the n-FET region and the gate electrode in the p-FET region are connected by the metal gate wiring film 25 made of W. For this reason, it is not necessary to connect the gate wiring layer in the n-FET region and the gate wiring layer in the p-FET region as in the prior art, and it is possible to prevent a decrease in yield due to poor connection.
Further, since the first gate metal film 5 and the second gate metal film 20 are connected by the low-resistance metal gate wiring film 25 without sandwiching them, it is possible to prevent the performance from being deteriorated due to the high resistance of the connection portion.

Embodiment 2. FIG.
FIG. 3 is a cross-sectional view of the manufacturing process of the CMOSFET semiconductor device according to the second embodiment, the whole being represented by 200. 3, the same reference numerals as those in FIG. 1 denote the same or corresponding parts. This manufacturing process includes the following processes 1 to 9.

Step 1: As shown in FIG. 3A, a gate made of a High-k material such as HfSiON, for example, in the n-FET region and the p-FET region in substantially the same step as in Step 1 of the first embodiment. An insulating film 4, a first gate metal film 5 made of TaSiN, an amorphous silicon (mask silicon) film 15, and a hard mask 6 made of SiN are formed. For the first gate metal film 5, not only TaSiN but also a metal film such as TaC, TaN, TiSiN, TiN may be used. Subsequently, a sidewall 7 made of, for example, SiO ₂ is formed, and then a source / drain region 8 is formed by ion implantation.
Here, the structure is the same as that of FIG. 1A except that an amorphous silicon film 15 is formed instead of the metal gate wiring film 13 made of W. In place of the amorphous silicon film 15, a polysilicon film may be used.

  Step 2: As shown in FIG. 3B, the PMD layer 10 is formed by, for example, a CVD method.

  Step 3: As shown in FIG. 3C, the PMD layer 10 is planarized using, for example, a CMP method, and the hard mask 6 is exposed. Steps 2 and 3 are the same as steps 2 and 3 in the first embodiment.

  Step 4: As shown in FIG. 3D, the hard mask 10 in the n-FET region and the p-FET region is selectively removed by using RIE or wet etching. Subsequently, the n-FET region is covered with, for example, a resist mask (not shown), and the amorphous silicon film 15 in the p-FET region is selectively removed by, for example, RIE.

  Step 5: As shown in FIG. 3E, the first gate metal film 5 in the p-FET region is selectively etched by, for example, wet etching using an ammonia / hydrogen peroxide mixed water at 60 to 80 ° C. Remove.

  Step 6: As shown in FIG. 3F, the amorphous silicon film 15 in the n-FET region is removed by wet etching using, for example, an ammonium hydroxide solution at 60 ° C.

  Step 7: As shown in FIG. 3G, for example, a second gate metal film 5 made of TiN and a metal gate wiring film 25 made of W are formed on the entire surface. In this process, the first gate metal film 5 in the n-FET region and the second gate metal film 20 in the p-FET region are connected.

  Step 8: As shown in FIG. 3H, the second gate metal film 20 and the metal gate wiring film 25 are etched using an etching mask (not shown). In this step, the electrode may be patterned by planarizing the PMD layer 10 using a CMP process.

Step 9: As shown in FIG. 3I, an interlayer insulating layer 30 made of, for example, SiO ₂ is formed, and lead-out wirings 35 are formed from the source / drain regions, thereby completing the CMOSFET semiconductor device 200.

  In the manufacturing method according to the second embodiment, the amorphous silicon film 15 formed on the first gate metal film 5 functions as an etching mask in steps 4 and 5. Therefore, a step of separately forming an etching mask for the polysilicon layer 15 as in step 5 (FIG. 1E) of the first embodiment can be omitted.

Embodiment 3 FIG.
FIG. 4 is a cross-sectional view of the manufacturing process of the CMOSFET semiconductor device according to the third embodiment, the whole being represented by 300. 4, the same reference numerals as those in FIG. 1 denote the same or corresponding parts. This manufacturing process includes the following processes 1 to 9.

Step 1: As shown in FIG. 4A, a gate made of a High-k material such as HfSiON, for example, in the n-FET region and the p-FET region in substantially the same step as the step 1 of the second embodiment. An insulating film 4, a first gate metal film 5 made of TaSiN, an amorphous silicon film 15, and a hard mask 6 made of SiN are formed. For the first gate metal film 5, not only TaSiN but also a metal film such as TaC, TaN, TiSiN, TiN may be used. Subsequently, a sidewall 7 made of, for example, SiO ₂ is formed, and then a source / drain region 8 is formed by ion implantation. Instead of the amorphous silicon film 15, a polysilicon film may be used.

  Process 2: As shown in FIG.4 (b), the PMD layer 10 is formed by CVD method, for example.

  Step 3: As shown in FIG. 4C, the PMD layer 10 is planarized using, for example, a CMP method, and the hard mask 6 is exposed. Steps 2 and 3 are the same as steps 2 and 3 in the first embodiment.

  Step 4: As shown in FIG. 4D, the hard mask 10 in the n-FET region and the p-FET region is selectively removed by using RIE or wet etching. Subsequently, the n-FET region is covered with, for example, a resist mask (not shown), and the amorphous silicon film 15 in the p-FET region is selectively removed by, for example, RIE.

  Step 5: As shown in FIG. 4E, the first gate metal film 5 in the p-FET region is selectively etched by wet etching using, for example, an ammonia / hydrogen peroxide mixed water at 60 to 80 ° C. Remove.

  Step 6: As shown in FIG. 4F, the amorphous silicon film 15 in the n-FET region is removed by wet etching using, for example, an ammonium hydroxide solution at 60 ° C.

  Step 7: As shown in FIG. 4G, after a polysilicon film is formed on the entire surface, a polysilicon film 40 to be a gate electrode later is formed by patterning using RIE or the like. The patterning of the polysilicon film may be performed in step 9.

  Step 8: As shown in FIG. 4H, a nickel layer 45 is formed on the entire surface by, eg, vapor deposition. The thickness of the nickel layer 45 is thicker than the thickness of the polysilicon film 40, and preferably about twice.

Step 9: As shown in FIG. 4 (i), the polysilicon film 40 is heated to about 400 ° C. to react with nickel in the nickel layer 45, and nickel silicide (Ni _x Si: x is preferably 1 or more) The film 41 (FUSI electrode) is used. Subsequently, the nickel layer 45 is patterned using an etching mask (not shown).

Step 10: As shown in FIG. 4J, the interlayer insulating layer 30 made of, for example, SiO ₂ is formed, and the source / drain electrodes 35 are formed, whereby the CMOSFET semiconductor device 300 is completed.

  In this manufacturing method, the conventional FUSI gate manufacturing process can be applied to the processes after the process 7, and the process conditions and the like can be easily set.

Further, in the CMOSFET semiconductor device 300, the threshold value of the FET can be changed by the nickel content of the nickel silicide (Ni _x Si) film 41, and the threshold value decreases as the nickel content increases. For example, by setting the Ni / Si composition ratio to about 2-3, the effective work function of the nickel silicide film 4 is about 4.8 eV, and the threshold value can be −0.4V.

  In the first to third embodiments, the MOSFET is described as an example, but the present invention can also be applied to a MISFET in which the gate insulating film is made of an insulating film other than an oxide film. Further, the present invention can also be applied to semiconductor materials other than silicon, such as gallium arsenide and silicon carbide.

  Further, a structure used for a general CMOSFET, such as nickel silicide on the surface of the source / drain region 8 or an extension region in the source / drain region 8, may be applied as appropriate.

It is sectional drawing of the manufacturing process of the CMOSFET semiconductor device concerning Embodiment 1 of this invention. It is the schematic of the gate electrode part of the CMOSFET semiconductor device concerning Embodiment 1 of this invention. It is sectional drawing of the manufacturing process of the CMOSFET semiconductor device concerning Embodiment 2 of this invention. It is sectional drawing of the manufacturing process of the CMOSFET semiconductor device concerning Embodiment 3 of this invention.

Explanation of symbols

  1 silicon substrate, 2 silicon layer, 3 element isolation region, 4 gate insulating film, 5 first gate metal film, 6 hard mask, 7 side wall, 8 source / drain region, 10 PMD layer, 14 amorphous silicon layer, 20 first 2 gate metal film, 25 metal gate wiring film, 30 interlayer insulating layer, 100 CMOSFET semiconductor device.

Claims (7)

A method of manufacturing a dual gate semiconductor device including an N-type FET having a first gate electrode and a P-type FET having a second gate electrode ,
(A) preparing a semiconductor substrate;
(B) forming a gate insulating film of the N-type FET and a gate insulating film of the P-type FET on the semiconductor substrate;
(C) forming a first gate metal film on each of the gate insulating films of the N-type FET and the P-type FET;
(D) forming a hard mask on each of the first gate metal films of the N-type FET and the P-type FET;
(E) forming an interlayer insulating layer on the hard mask so as to fill the space between the gate insulating film, the first gate metal film and the hard mask of the N-type FET and the P-type FET;
(F) exposing an upper portion of the hard mask from the interlayer insulating layer;
(G) After the step (f), removing the hard mask of the N-type FET and the P-type FET;
(H) a selective removal step of selectively removing the first gate metal film of the P-type FET while leaving the first gate metal film of the N-type FET after the step (g);
(I) Deposition for depositing a second gate metal film on the first gate metal film of the N-type FET, on the gate insulating film of the P-type FET and on the interlayer insulating layer after the step (h) Process,
(J) after the step (i), forming a gate wiring film on the second gate metal film;
(K) after the step (j), selectively removing the second gate metal film and the gate wiring film formed on the interlayer insulating layer,
The first gate electrode of the N-type FET has the first metal film, the second metal film, and the gate wiring film,
The second gate electrode of the P-type FET has the second metal film and the gate wiring film,
The first gate electrode of the N-type FET and the second gate electrode of the P-type FET are connected by the gate wiring film,
The first gate metal film is made of TaSiN, TaC, TaN, TiSiN or TiN,
The second gate metal film is made of a material different from that of the first gate metal film, and TiN, TiAlN, TaN, TaAlN, Ru, Ir, Pt, Ni, Co, W, WN, Mo, MoN, NiSi. And a method of manufacturing a dual gate semiconductor device, characterized in that a material selected from the group consisting of PtSi is a main component . 2. The method of manufacturing a dual gate semiconductor device according to claim 1, wherein the step (k) is performed using a CMP process. 2. The method of manufacturing a dual gate semiconductor device according to claim 1, wherein the step (k) is performed by patterning the second metal film and the gate wiring film using an etching mask. The method of manufacturing a dual gate semiconductor device according to claim 1, wherein the step (k) and subsequent steps are steps performed at a temperature of the semiconductor substrate of 500 ° C. or less. A method of manufacturing a dual gate semiconductor device including an N-type FET having a first gate electrode and a P-type FET having a second gate electrode ,
(A) preparing a semiconductor substrate;
(B) forming a gate insulating film of the N-type FET and a gate insulating film of the P-type FET on the semiconductor substrate;
(C) forming a first gate metal film on each of the gate insulating films of the N-type FET and the P-type FET;
(D) forming a hard mask on each of the first gate metal films of the N-type FET and the P-type FET;
(E) forming an interlayer insulating layer on the hard mask so as to fill the space between the gate insulating film, the first gate metal film and the hard mask of the N-type FET and the P-type FET;
(F) exposing an upper portion of the hard mask from the interlayer insulating layer;
(G) After the step (f), removing the hard mask of the N-type FET and the P-type FET;
(H) a selective removal step of selectively removing the first gate metal film of the P-type FET while leaving the first gate metal film of the N-type FET after the step (g);
(I) after the step (h), a deposition step of depositing a silicon film on the first gate metal film of the N-type FET, on the gate insulating film of the P-type FET and on the interlayer insulating layer;
(J) after the step (i), forming a nickel layer so as to cover the silicon film;
(K) after the step (j), a step of reacting the silicon film and a part of the nickel layer by heat treatment to form a nickel silicide film;
(L) after the step (k), selectively removing the nickel silicide film and the nickel layer formed on the interlayer insulating layer,
The first gate electrode of the N-type FET has the first metal film, the nickel silicide film, and the nickel layer,
The second gate electrode of the P-type FET has the nickel silicide film and the nickel layer,
The first gate electrode of the N-type FET and the second gate electrode of the P-type FET are connected by the nickel layer,
The method of manufacturing a dual gate semiconductor device, wherein the first gate metal film is made of TaSiN, TaC, TaN, TiSiN, or TiN . 6. The method of manufacturing a dual gate semiconductor device according to claim 5, wherein the step (l) is performed by patterning the nickel silicide film and the nickel layer using an etching mask. 7. The method of manufacturing a dual gate semiconductor device according to claim 1, wherein the gate insulating film is made of HfSiON.

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