CN117423736A - Semiconductor device, method of manufacturing the same, and method of forming continuous metal cap - Google Patents

Abstract

The semiconductor device includes: a gate structure above the semiconductor substrate, having a high dielectric coefficient dielectric layer, a P-type work function layer, an N-type work function layer, a dielectric anti-reaction layer and a glue layer; and a continuous metal cap over the gate structure, formed by: a metal material is deposited over the gate structure, portions of the anti-reaction layer are selectively removed, and additional metal material is deposited over the gate structure. The manufacturing method comprises the following steps: receiving a gate structure; planarizing the top layer of the gate structure; pre-cleaning and pre-treating the surface of the grid structure; depositing a metal material over the gate structure to form a discontinuous metal cap; selectively removing a portion of the anti-reaction layer; depositing additional metal material over the gate structure to create a continuous metal cap; inhibit the growth of the metal cap. The present disclosure also relates to a method of forming a continuous metal cap over a metal gate structure.

Description

Semiconductor device, method of manufacturing same, and method of forming continuous metal cover

Technical field

Embodiments of the present disclosure relate to a semiconductor device and a manufacturing method thereof.

Background technique

Semiconductor devices are used in a variety of electronic applications such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate, and patterning the various material layers using photolithography to form circuit components and components thereon .

The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously shrinking the minimum component size, which allows more components to be integrated into a given area. However, as minimum component sizes shrink, other issues arise that should be addressed.

Contents of the invention

One embodiment of the present disclosure is a semiconductor device. The semiconductor device includes a gate structure located above the semiconductor substrate and a continuous metal cover located above the gate structure. The gate structure includes: a high dielectric coefficient dielectric layer; a P-type work function layer; an N-type work function layer; an anti-reaction layer, including dielectric materials; and a glue layer. The continuous metal cap is formed by depositing a metal material over the gate structure during a plurality of first deposition operations, the metal material forming a discontinuous metal cap; and selectively placing the resist during a plurality of first wet chemical operations. A portion of the reactive layer is removed; additional metal material is deposited over the gate structure during a plurality of second deposition operations to create a continuous metal cap; and the continuous metal cap is suppressed during a plurality of second wet chemical operations grow.

Another embodiment of the present disclosure is a method of forming a continuous metal cover above a metal gate structure, including: receiving a gate structure having a high-k dielectric layer, a P-type work function layer, N-type work function layer, anti-reaction layer including dielectric material and glue layer. The method also includes pretreating the surface of the gate structure using an oxidation or nitriding process; using a plurality of first deposition operations to deposit a metal material over the gate structure that forms a discontinuous metal cap; using a plurality of first deposition operations Wet chemical operations selectively remove a portion of the anti-reaction layer; use multiple second deposition operations to deposit additional metal material over the gate structure to create a continuous metal cap; and use multiple second wet chemical operations Inhibits continuous metal cap growth.

Yet another embodiment of the present disclosure is a method of manufacturing a semiconductor device, including: receiving a gate structure, the gate structure having a high-k dielectric layer, a P-type work function layer, an N-type work function layer, a dielectric reactance Reactive layer and adhesive layer. The method of manufacturing a semiconductor device further includes: using oxygen (O ₂ ) or hydrogen/nitrogen (H ₂ /N ₂ ) plasma treatment to pretreat the surface of the gate structure; using multiple first atomic layer deposition (ALD) operations Depositing a first metal material including tungsten (W) material or molybdenum (Mo) material over the gate structure to form a discontinuous metal cover; using dilute hydrofluoric acid to selectively remove a portion of the anti-reaction layer ;Using multiple second atomic layer deposition operations to deposit a second metal material containing tungsten or molybdenum over the gate structure to create a continuous metal cap; by removing the unwanted metal material through a wet etching operation using an ozone solution Removing from the plurality of side spacers to inhibit growth of the metal cap; and forming a via gate (VG) over the metal cap. Forming the via gate over the metal cap includes using multiple etching operations to form openings through interlayer dielectric (ILD) material to contact the metal cap and using multiple deposition operations to deposit metallic material in the openings.

Description of the drawings

Complete disclosure is made based on the following detailed description and accompanying drawings. It should be noted that, consistent with common practice in the industry, the various components are not necessarily drawn to scale. In fact, the dimensions of the various components may be arbitrarily enlarged or reduced for clarity of illustration.

1 is a flowchart illustrating an exemplary method of semiconductor fabrication including fabricating a multi-gate device, in accordance with some embodiments.

2A, 3A, 4A, 5A, 6A, 7A, 8A, 9A, and 10A are isometric views illustrating exemplary semiconductor devices in accordance with some embodiments.

2B, 3B, 4B, 5B, 6B, 7B, 8B, 9B, and 10B illustrate an exemplary semiconductor device along a first slit XX' according to some embodiments. Cross-sectional side view corresponding to each embodiment.

11 is a flowchart depicting an exemplary manufacturing method for fabricating a continuous metal cap over a metal gate for use with subsequently fabricated via gate (VG) conductors, in accordance with some embodiments.

12A-12H are diagrams depicting enlarged views of exemplary semiconductor gate structures at various stages of fabricating a continuous metal cap over a metal gate, in accordance with some embodiments.

13 is a process flow diagram depicting an exemplary method of further semiconductor fabrication including metal drain fabrication and via gate fabrication, in accordance with some embodiments.

14A-14E are diagrams depicting enlarged views of exemplary regions at various stages of semiconductor fabrication including metal drain fabrication and via gate fabrication, in accordance with some embodiments.

FIG. 15 is a graph illustrating the reduction in gate resistance that may result from forming a continuous metal cap over a metal gate structure in a semiconductor device.

Among them, the reference symbols are explained as follows:

100, 1100, 1300: Method

102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 1102, 1104, 1106, 1108, 1110, 1112, 1114, 1116, 1118, 1120, 1122, 1302, 1304, 1306, 1308, 1310, 1312, 1314, 1316, 1318, 1320, 1322: Block

200: Semiconductor devices

202: Substrate

204: Epitaxial stacking

206, 208 epitaxial layer

210: fin element

302: STI parts

304: Gate stack

402: Spacer material layer

602: Oxide layer

702: Source/Drain Components

802: Interlayer dielectric (ILD) layer

1002: Gate stack

1004: High-k gate dielectric layer

1006: Metal layer

1200: Gate structure

1201: Gate stack

1202: Adhesive layer

1204: Anti-reaction layer

1206: n-type work function layer

1208: p-type work function layer

1210: High dielectric coefficient interlayer dielectric material

1212: Gate spacer

1214: Plasma treatment

1215: average

1216: Discontinuous metal cover

1217: Additional metal materials

1218: concave part

1220: Continuous Metal Cover

1222: Via hole gate (VG)

1224: Interlayer dielectric (ILD)

1400: Area

1402: Substrate

1404: Source/drain area

1406: Patterned Mask

1409: Silicide Contact

X-X’: first incision

Detailed ways

The following disclosure provides many different embodiments or examples for implementing different components of the present invention. The following disclosure describes specific examples of each component and its arrangement to simplify the description. Of course, these specific examples are not limiting.

For the sake of brevity, conventional techniques related to conventional semiconductor device fabrication may not be described in detail herein. Additionally, the various tasks and processes described herein may be incorporated into more comprehensive programs or processes with additional functionality not described in detail herein. In particular, various processes in semiconductor device fabrication are well known, and therefore, for the sake of brevity, many conventional processes will only be briefly mentioned here or will be omitted entirely without providing well-known process details. As will be apparent to those skilled in the art upon reading this disclosure in its entirety, the structures disclosed herein may be used with a variety of technologies and may be incorporated into a variety of semiconductor devices and products. Additionally, it should be noted that semiconductor device structures include varying numbers of components and that a single component shown in the drawings may represent multiple components.

In addition, words related to space, such as "above", "overlying", "below", "on", "top", "under", "below", "of" "Bottom", "bottom" and similar terms are used herein to facilitate describing the relationship between one element or component and another element or component in the drawings. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be rotated 90 degrees or at other orientations and the spatially relative terms used herein interpreted accordingly. When spatially relative terms such as those listed above are used to describe a first element relative to a second element, the first element may be directly on the other element or intervening elements or layers may be present. When an element or layer is referred to as being "on" another element or layer, it is directly on and in contact with the other element or layer.

Additionally, this disclosure may repeat reference symbols and/or labels in various examples. These repetitions are for the purpose of simplicity and clarity and are not intended to limit specific relationships between the different embodiments and/or structures discussed.

It should be noted that references in the specification to "one embodiment," "an embodiment," "an exemplary embodiment," "exemplary," "example," etc., indicate that the described embodiment may include certain components. , structure or characteristics, but each embodiment does not necessarily contain specific components, structures or characteristics. Furthermore, such statements are not necessarily referring to the same embodiment. Furthermore, when a particular component, structure or characteristic is described in connection with one embodiment, whether or not explicitly described, it will be within the knowledge of one skilled in the art to affect such component, structure or characteristic in connection with other embodiments.

It is to be understood that the terms or terminology used herein are for the purpose of description and not limitation, so that one skilled in the relevant art can interpret the terms or terminology in the present specification in accordance with the teachings herein.

Various embodiments are discussed herein in the specific context of forming semiconductor structures including fin-like field-effect transistor (FinFET) devices. The semiconductor structure may be, for example, a complementary metal-oxide-semiconductor (CMOS) device, including a P-type metal-oxide-semiconductor (PMOS) FinFET device and an N-type metal-oxide-semiconductor (NMOS) FinFET device. Embodiments will now be described with respect to specific examples involving FinFET fabrication procedures. However, embodiments are not limited to the examples provided herein, and the concepts may be implemented in a wide range of embodiments. Accordingly, various embodiments may be applied to other semiconductor devices/processes, such as planar transistors and the like. Furthermore, some embodiments discussed herein are discussed in the context of devices formed using a gate-last process. In other embodiments, a gate-first process may be used.

Although the drawings illustrate various embodiments of semiconductor devices, additional components may be added to the semiconductor devices depicted in the drawings, and features described below may be replaced, modified, or removed in other embodiments of the semiconductor devices. Some parts.

Additional operations may be provided before, during and/or after the stages described in these embodiments. For different embodiments, some of the stages described may be replaced or eliminated. Additional components may be added to the semiconductor device structure. Some of the components described below may be replaced or eliminated for different embodiments. Although some embodiments are discussed with operations performed in a specific order, the operations may be performed in another logical order.

It should also be noted that the present disclosure presents embodiments in the form of multi-gate transistors. Multi-gate transistors include transistors whose gate structures are formed on at least two sides of a channel region. These multi-gate devices may include P-type metal oxide semiconductor devices or N-type metal oxide semiconductor multi-gate devices. Due to their fin-like structure, specific examples can be presented in this article and are called FinFETs. Also presented herein is an embodiment of a multi-gate transistor called a gate-all-around (GAA) device. GAA devices include any device whose gate structure or portions thereof are formed on four sides of a channel region (eg, surrounding a portion of the channel region). Devices presented herein also include embodiments having channel regions disposed in nanowire channels, strip channels, and/or other suitable channel configurations. Presented herein are embodiments of devices that can have one or more channel regions (eg, nanowires) associated with a single contiguous gate structure. However, one of ordinary skill will appreciate that this teaching may be applied to a single channel (eg, a single nanowire) or any number of channels. One of ordinary skill may recognize other examples of semiconductor devices that may benefit from aspects of this disclosure.

FIG. 1 is a flowchart illustrating an exemplary method 100 of semiconductor fabrication including fabricating a multi-gate device. As used herein, the term "multi-gate device" is used to describe a device (eg, a semiconductor transistor) having at least some gate material disposed on multiple sides of at least one channel of the device. In some examples, a multi-gate device, which may be referred to as a GAA device, has gate material disposed on at least four sides of at least one channel of the device. Channel regions may be referred to as "nanowires" as used herein, which encompass channel regions of various geometries (eg, cylinders, strips) and various sizes.

Figure 1 is combined with Figure 2A-Figure 2B, Figure 3A-Figure 3B, Figure 4A-Figure 4B, Figure 5A-Figure 5B, Figure 6A-Figure 6B, Figure 7A-Figure 7B, Figure 8A-Figure 8B, Figure 9A-Figure 9B 10A-10B, which illustrate a semiconductor device 200 or structure at various stages of fabrication according to some embodiments. Method 100 is merely an example, and is not intended to limit the disclosure beyond what is expressly stated in the patent application. Additional steps may be provided before, during, and after method 100, and some of the steps described may be moved, replaced, or eliminated for other embodiments of method 100. Additional components may be added to the semiconductor device 200 depicted in the figures, and some of the components described below may be replaced, modified, or eliminated in other embodiments.

As with other method embodiments and exemplary devices discussed herein, it should be understood that portions of semiconductor devices may be fabricated by typical semiconductor technology process flows, and therefore some processes are only briefly described herein. Additionally, exemplary semiconductor devices may include various other devices and components, such as other types of devices, such as additional transistors, bipolar junction transistors, resistors, capacitors, inductors, dials , fuses and/or other logic devices, etc., but are simplified for easier understanding of the concepts of the present disclosure. In some embodiments, an exemplary device includes a plurality of semiconductor devices (eg, transistors), including PFETs, NFETs, etc., which may be interconnected. Furthermore, it should be noted that the process steps of method 100 , including any description given with reference to the drawings, as well as the remainder of the methods and exemplary drawings provided in this disclosure, are exemplary only and are not intended to limit the disclosure. beyond what is explicitly stated in the scope of the patent application.

According to some embodiments, FIGS. 2A, 3A, 4A, 5A, 6A, 7A, 8A, 9A, and 10A are isometric views of an exemplary semiconductor device 200, and FIG. 2B , FIG. 3B, FIG. 4B, FIG. 5B, FIG. 6B, FIG. 7B, FIG. 8B, FIG. 9B, and FIG. 10B are exemplary semiconductor devices 200 along the first slit XX′ during an exemplary manufacturing process. A cross-sectional side view corresponding to an embodiment. In some drawings, some reference signs to illustrated components or features may be omitted to avoid confusing other components or features; this is for convenience in depicting the drawings.

At block 102 , the exemplary method 100 includes providing a substrate 202 . Referring to the examples of FIGS. 2A and 2B , in an embodiment of block 102 , a substrate 202 is provided. In some embodiments, substrate 202 may be a semiconductor substrate, such as a silicon substrate. Substrate 202 may include various layers, including conductive layers or insulating layers formed over a semiconductor substrate. Substrate 202 may contain various doping configurations according to design requirements known in the art. For example, different doping profiles (eg, n-wells) may be formed over substrate 202 in areas designed for different device types (eg, n-type field effect transistors (NFETs), p-type field effect transistors (PFETs) , p-well). Suitable doping may include ion implantation and/or diffusion processes of dopants. The substrate 202 typically has isolation features (eg, shallow trench isolation (STI) features) to interpose regions providing different device types. The substrate 202 may also include other semiconductors, such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, the substrate 202 may include compound semiconductors and/or alloy semiconductors. Furthermore, the substrate 202 optionally includes an epitaxial layer (epi-layer), which can be strained to improve performance, can include silicon-on-insulator (SOI) structures, and/or have other suitable reinforcing components.

Returning to FIG. 1 , the method 100 then proceeds to block 104 to grow one or more epitaxial layers on the substrate. Referring to the example of FIGS. 2A and 2B , in the embodiment of block 104 , epitaxial stack 204 is formed over substrate 202 . The epitaxial stack 204 includes a plurality of epitaxial layers 206 of a first composition interposed by a plurality of epitaxial layers 208 of a second composition. The first component and the second component can be different. In one embodiment, epitaxial layer 206 is silicon germanium and epitaxial layer 208 is silicon (Si). However, other embodiments may also include embodiments providing first and second components with different oxidation rates and/or etch selectivities. In some embodiments, where epitaxial layer 206 includes SiGe and where epitaxial layer 208 includes Si, the oxidation rate of Si of epitaxial layer 208 is less than the oxidation rate of SiGe of epitaxial layer 206 .

Epitaxial layer 208 or portions thereof may form channel regions of multi-gate device 200 . For example, the epitaxial layer 208 may be referred to as a "nanowire" used to form the channel region of a multi-gate device 200 such as a GAA device. These "nanowires" are also used to form portions of the source/drain regions of multi-gate device 200 as described below. Source/drain regions may refer to source or drain, individually or collectively, depending on context. Likewise, as the term is used herein, "nanowire" refers to cylindrical as well as other configurations of semiconductor layers, such as strips. The use of epitaxial layer 208 to define one or more channels of the device is discussed further below.

It should be noted that four (4) layers of each of epitaxial layers 206 and 208 are shown in FIGS. 2A-2B and 3A-3B for illustrative purposes only and are not intended to limit the disclosure to the claims. Except for what is clearly stated. It will be appreciated that any number of epitaxial layers may be formed in epitaxial stack 204; the number of layers depends on the number required for the channel area of device 200. In some embodiments, the number of epitaxial layers 208 is between 2 and 10.

In some embodiments, epitaxial layer 206 has a thickness in the range of approximately 2 to 6 nanometers (nm). The thickness of epitaxial layer 206 may be substantially uniform. In some embodiments, epitaxial layer 208 has a thickness in the range of approximately 6 to 12 nm. In some embodiments, the thickness of stacked epitaxial layers 208 is substantially uniform. As described in more detail below, the epitaxial layer 208 may serve as a channel region for a subsequently formed multi-gate device, and its thickness is selected based on device performance considerations. Epitaxial layer 206 may be used to define the gap distance between adjacent channel regions for subsequently formed multi-gate devices, and its thickness is selected based on device performance considerations.

For example, epitaxial growth of the layers of stack 204 may be performed by a molecular beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, and/or other suitable epitaxial growth processes. In some embodiments, epitaxially grown layers, such as layer 208 , include the same material as substrate 202 . In some embodiments, epitaxially grown layers 206, 208 comprise a different material than substrate 202. As described above, in at least some examples, epitaxial layer 206 includes an epitaxially grown silicon germanium (SiGe) layer and epitaxial layer 208 includes an epitaxially grown silicon (Si) layer. Alternatively, in some embodiments, either of epitaxial layers 206, 208 may include other materials such as germanium, compound semiconductors (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or or indium antimonide), alloy semiconductors (e.g., SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP and/or GaInAsP), or combinations thereof. As discussed, the materials of the epitaxial layers 206, 208 may be selected based on providing different oxidation and etch selectivity characteristics. In various embodiments, the epitaxial layers 206, 208 are substantially free of dopants (ie, have an extrinsic dopant concentration of about 0 cm ⁻³ to about 1 × 10 ¹⁷ cm ⁻³ ), e.g., during the epitaxial growth process There is no intentional doping.

Next, method 100 proceeds to block 106 where fin-like elements are patterned and formed. Referring to the example of FIG. 2A , in the embodiment of block 106 , a plurality of fin-like elements 210 are formed extending from the substrate 202 . In various embodiments, each fin element 210 includes a portion of the substrate formed from the substrate 202 , and the portion of each epitaxial layer of the epitaxial stack includes epitaxial layers 206 and 208 .

The fin-shaped element 210 may be fabricated using suitable processes including photolithography and etching processes. The photolithography process may include forming a photoresist layer over the substrate 202 (eg, over the epitaxial stack 204), exposing the photoresist layer to the pattern, performing a post-exposure bake process, and developing the photoresist layer to form a photoresist layer containing The mask component of the resistive layer. In some embodiments, patterning the photoresist layer to form the mask element may be performed using an electron beam (e-beam) photolithography process. Masking elements may then be used to protect areas of the substrate 202 and the layer 204 formed thereon, while the etching process forms trenches in the unprotected areas through the masking layer (eg, a hard mask), leaving much extended fins. The trenches may be etched using dry etching (eg, reactive ion etching), wet etching, and/or other suitable processes. The trenches can be filled with dielectric material, forming shallow trench isolation features such as inserted fins.

In some embodiments, the dielectric layer may include silicon dioxide (SiO ₂ ), silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low dielectric coefficient (low -κ) dielectrics, combinations thereof and/or other suitable materials known in the art. In various examples, the dielectric layer may be formed by a chemical vapor deposition (CVD) process, a sub-atmospheric chemical vapor deposition (SACVD) process, a flowable chemical vapor deposition process, or an atomic layer deposition (ALD) process. , physical vapor deposition (PVD) process and/or other suitable processes. In some embodiments, after depositing the dielectric layer, the device 200 may be annealed, for example, to improve the quality of the dielectric layer. In some embodiments, the dielectric layer (and subsequently formed shallow trench isolation (STI) feature 302) may comprise a multi-layer structure, for example, with one or more liner layers.

In some embodiments where isolation (STI) features are formed, after depositing the dielectric layer, the deposited dielectric material is thinned and planarized, such as by a chemical mechanical polishing (CMP) process. The CMP process may planarize the top surface to form the STI component 302 . The STI component 302 into which the fin element is inserted is recessed. Referring to the example of FIG. 3A , STI component 302 is recessed to provide fin-like elements 210 extending above STI component 302 . In some embodiments, the recessing process may include a dry etching process, a wet etching process, and/or a combination thereof. In some embodiments, the recess depth is controlled (eg, by controlling etch time) to produce a desired height "H" of the exposed upper portion of fin element 210 . Height "H" exposes each layer of epitaxial stack 204 .

Many other embodiments of methods of forming fins on a substrate may also be used, including, for example, defining fin areas (eg, by masking or isolating areas) and epitaxially growing the epitaxial stack 204 in the form of fins. In some embodiments, forming the fins may include a trimming process to reduce the width of the fins. The trimming process may include a wet or dry etching process.

Next, method 100 proceeds to block 108 to form sacrificial layers/features, specifically dummy gate structures. Although the present discussion is directed to a replacement gate process whereby a dummy gate structure is formed and subsequently replaced, other configurations are possible.

Referring to FIGS. 3A and 3B , a gate stack 304 is formed. In one embodiment, gate stack 304 is a dummy (sacrificial) gate stack that is subsequently removed as discussed with reference to block 108 of method 100 .

Therefore, in some embodiments using a gate-last process, gate stack 304 is a dummy gate stack and will be replaced by the final gate stack during subsequent processing stages of device 200 . In particular, gate stack 304 may be replaced by a high-k dielectric layer (HK) and a metal gate electrode (MG) in subsequent processing stages as described below. In some embodiments, gate stack 304 is formed over substrate 202 and disposed at least partially over fin elements 210 . The portion of fin element 210 below gate stack 304 may be referred to as the channel region. Gate stack 304 may also define the source/drain regions of fin element 210, such as the region of fin and epitaxial stack 204 adjacent and on opposite sides of the channel region.

In some embodiments, gate stack 304 includes a dielectric layer and a dummy electrode layer. Gate stack 304 may also include one or more hard mask layers (eg, oxide, nitride). In some embodiments, gate stack 304 is formed through various process steps, such as layer deposition, patterning, etching, and other suitable process steps. Exemplary layer deposition processes include chemical vapor deposition (including low pressure chemical vapor deposition and plasma-assisted chemical vapor deposition), physical vapor deposition, atomic layer deposition, thermal oxidation, electron beam evaporation, other suitable deposition techniques, or combinations thereof. Taking the formation of a gate stack as an example, the patterning process includes a lithography process (such as photolithography or electron beam lithography), which may further include photoresist coating (such as spin coating), soft baking, and masking. alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (such as spin drying and/or hard baking), other suitable lithography techniques, and/or combinations thereof. In some embodiments, the etching process may include dry etching (eg, RIE etching), wet etching, and/or other etching methods.

As discussed above, gate stack 304 may include additional gate dielectric layers. For example, gate stack 304 may include silicon oxide. Alternatively or additionally, the gate dielectric layer of gate stack 304 may include silicon nitride, a high-k dielectric material, or other suitable materials. In some embodiments, the electrode layer of the gate stack 304 may include polysilicon. Hard mask layers, such as SiO ₂ , Si ₃ N ₄ , silicon oxynitride, optionally contain silicon carbide and/or may also contain other suitable components.

Next, the method 100 proceeds to block 110 to deposit a layer of spacer material over the substrate. Referring to the example of FIGS. 4A and 4B , a spacer material layer 402 is disposed on the substrate 202 . The spacer material layer 402 may include a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN film, silicon oxycarbide, SiOCN film, and/or combinations thereof. In some embodiments, spacer material layer 402 includes multiple layers, such as primary spacers, liner layers, and the like. For example, the spacer material layer 402 may be formed by depositing a dielectric material over the gate stack 304 using, for example, a CVD process, a sub-atmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, or other processes. Suitable process. It should be noted that the spacer material layer 402 is shown covering the epitaxial stack 204 in FIGS. 4A and 4B.

In some embodiments, depositing the layer of spacer material is followed by (eg, anisotropically) etching back the dielectric spacer material. Referring to the examples of FIGS. 5A and 5B , after the spacer material layer 402 is formed, the spacer material layer 402 may be etched back to expose the fin element 210 adjacent to the gate stack 304 but not the gate stack 304 Covered portions (e.g., source/drain regions). A layer of spacer material may remain over the sidewalls of the gate stack 304 forming the spacer elements. In some embodiments, the etch back of the spacer material layer 402 may include a wet etching process, a dry etching process, a multi-step etching process, and/or a combination thereof. As shown in FIGS. 5A and 5B , the layer of spacer material 402 may be removed from the top surface of the exposed epitaxial stack 204 and the sides of the exposed epitaxial stack 204 .

Next, the method 100 proceeds to block 112 to perform an oxidation process. Due to the different oxidation rates of the multiple layers of the epitaxial stack 204, the oxidation process may be referred to as selective oxidation, with specific layers being oxidized. In some examples, the oxidation process may be performed by exposing device 200 to a wet oxidation process, a dry oxidation process, or a combination thereof. In at least some embodiments, the apparatus 200 is exposed to a wet oxidation process using water vapor or steam as the oxidant at a pressure of about 1 ATM and a temperature range of about 400 to 600° C. for about 0.5 to 2 hours. It should be noted that the oxidation process conditions provided herein are exemplary only and are not intended to be limiting. It should be noted that in some embodiments, this oxidation process may be extended such that the oxidized portions of the stacked epitaxial layers abut the sidewalls of the gate stack 304 .

Referring to the example of FIGS. 6A and 6B , in the embodiment of block 112 , the device 200 is exposed to an oxidation process that completely oxidizes the epitaxial layer 206 of each of the plurality of fin elements 210 . Epitaxial layer 206 transforms into oxide layer 602. Oxide layer 602 extends to gate stack 304 , including under spacer elements 402 . In some embodiments, oxide layer 602 has a thickness in the range of about 5 to about 25 nanometers (nm). In one embodiment, oxide layer 602 may include silicon germanium oxide (SiGeOx).

For example, in embodiments where epitaxial layer 206 includes SiGe and epitaxial layer 208 includes Si, a faster (i.e., compared to Si) SiGe oxidation rate ensures that epitaxial layer 206 is fully oxidized while minimizing or eliminating other epitaxial Oxidation of layer 208. It should be understood that any of the various materials discussed above may be selected for each of the first epitaxial layer and the second epitaxial layer portion to provide different suitable oxidation rates.

Next, the method 100 proceeds to block 114 to form source/drain features on the substrate. The source/drain features may be formed by performing an epitaxial growth process by providing epitaxial material over the fin elements 210 in the source/drain regions. In one embodiment, the source/drain epitaxial material is formed to cover the portion of the epitaxial layer that remains in the source/drain region of the fin. Referring to the example of FIGS. 7A and 7B , source/drain features 702 are formed on substrate 202 in/on fin elements 210 adjacent and associated with gate stack 304 . Source/drain features 702 include material formed by epitaxial growth of semiconductor material over exposed epitaxial layer 208 and/or oxide layer 602 . It should be noted that the shape of source/drain features 702 is illustrative only and not limiting; as one of ordinary skill in the art understands, any epitaxial growth will occur on the semiconductor material (eg, 208) and Instead of being over the dielectric material (eg, 602), the epitaxial growth can be grown as shown so that it merges with the dielectric layer (eg, over 602).

In various embodiments, the grown semiconductor material of source/drain features 702 may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable materials. In some embodiments, the material of source/drain features 702 may be doped in-situ during the epitaxial process. For example, in some embodiments, the epitaxially grown material may be doped with boron. In some embodiments, the epitaxially grown material may be doped with carbon to form Si:C source/drain features, with phosphorus to form Si:P source/drain features, or with carbon and phosphorus to form SiCP Source/drain components. In one embodiment, the epitaxial material of source/drain features 702 is silicon and layer 208 is also silicon. In some embodiments, layers 702 and 208 may include similar materials (eg, Si), but be doped differently. In other embodiments, the epitaxial layer for source/drain features 702 includes a first semiconductor material and the epitaxial growth material 208 includes a second semiconductor material that is different from the first semiconductor material. In some embodiments, the epitaxially grown material of source/drain features 702 is not doped in situ, but rather, for example, an implantation process is performed.

Next, the method 100 proceeds to block 116 to form an inter-layer dielectric (ILD) layer on the substrate. Referring to the examples of FIGS. 8A and 8B , in the embodiment of block 116 , an interlayer dielectric layer 802 is formed over the substrate 202 . In some embodiments, before forming the ILD layer 802, a contact etch stop layer (CESL) is formed over the substrate 202. In some examples, CESL includes a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, and/or other materials known in the art. CESL can be formed by a plasma-assisted chemical vapor deposition (PECVD) process and/or other suitable deposition or oxidation processes. In some embodiments, ILD layer 802 includes, for example, tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide (eg, borophosphosilicate glass ( borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG)) and/or other suitable dielectric materials . ILD layer 802 may be deposited by a PECVD process or other suitable deposition technique. In some embodiments, after forming the ILD layer 802, the semiconductor device 200 may be subjected to a high thermal budget process to anneal the ILD layer.

In some examples, after depositing the ILD (and/or CESL or other dielectric layer), a planarization process may be performed to expose the top surface of gate stack 304. For example, the planarization process includes a chemical mechanical planarization (CMP) process, which removes portions of the ILD layer 802 (and CESL layer, if present) covering the gate stack 304 and planarizes the semiconductor device 200 the top surface.

Next, the method 100 proceeds to block 118 to remove the dummy gate (see block 108). The gate and/or gate dielectric layer may be removed by a suitable etching process. In some embodiments, block 118 also includes selectively removing the epitaxial layer in the channel region of the device. In embodiments, selected epitaxial elements are placed in the fin elements within the trenches provided by removing the dummy electrodes (e.g., the fin regions over and above which the gate structures will be formed, or the channel regions). Layer removed. Referring to the example of FIGS. 9A and 9B , the epitaxial layer 206 is removed from the channel regions and trenches of the substrate 202 . In some embodiments, epitaxial layer 206 is removed through a selective wet etching process. In some embodiments, the selective wet etch includes HF. In one embodiment, epitaxial layer 206 is SiGe and epitaxial layer 208 is silicon, which allows for selective removal of SiGe epitaxial layer 206.

Next, the method 100 proceeds to block 120 to form a gate structure. The gate structure may be the gate of a multi-gate transistor. The final gate structure may be a high-k/metal gate stack, but other compositions are possible. In some embodiments, the gate structure forms a gate associated with multiple channels provided by a plurality of nanowires in the channel region, now with gaps therebetween. Exemplary embodiments of gate structures will be discussed in more detail.

Referring to the examples of FIGS. 10A and 10B , in one embodiment of block 120 , high-k/metal gate stack 1002 is formed in a trench of device 200 by removing the dummy gate and/or Release the nanowire provided as described above with reference to block 118. In various embodiments, high-k/metal gate stack 1002 includes an interface layer, a high-k gate dielectric layer 1004 formed over the interface layer, and/or a high-k gate dielectric layer 1004 formed over the interface layer. Metal layer 1006 above layer 1004. As used and described herein, a high-k gate dielectric layer includes a dielectric material having a high dielectric constant, for example, greater than the dielectric constant of thermal oxide silicon (~3.9). The metal layers used within the high-k/metal gate stack may include metals, metal alloys, or metal silicides. Additionally, formation of the high-k/metal gate stack may include deposition to form various gate materials, one or more liner layers, and one or more CMP processes to remove excess gate material to remove the semiconductor. The top surface of device 200 is planarized.

In some embodiments, the interface layer of gate stack 1002 may include a dielectric material such as silicon oxide (SiO ₂ ), HfSiO, or silicon oxynitride (SiON). The interface layer can be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD) and/or other suitable methods. Gate dielectric layer 1004 of gate stack 1002 may include a high-k dielectric layer, such as hafnium oxide (HfO ₂ ). Alternatively, the gate dielectric layer 1004 of the gate stack 1002 may include other high-k dielectrics, such as TiO ₂ , HfZrO, Ta ₂ O ₃ , HfSiO ₄ , ZrO ₂ , ZrSiO ₂ , LaO, AlO, ZrO, TiO, Ta ₂ O ₅ , Y ₂ O ₃ , SrTiO ₃ (STO), BaTiO ₃ (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba, Sr)TiO ₃ (BST) , Al ₂ O ₃ , Si ₃ N ₄ , oxynitride (eg, SiON), combinations thereof, or other suitable materials. The high-k gate dielectric layer 1004 may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and/or other suitable methods. The metal layers of the high-k/metal gate stack 1002 may include single-layer or multi-layer structures, such as metal layers with selected work functions to enhance device performance (work function metal layers), liner layers, wetting layers, Various combinations of adhesive layers, metal alloys or metal silicides. For example, the metal layer of gate stack 1002 may include Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Re, Ir , Co, Ni, other suitable metal materials or combinations thereof. In various embodiments, the metal layer of gate stack 1002 may be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable processes. Furthermore, metal layers of gate stack 1002 may be formed separately for N-FET and P-FET transistors that may use different metal layers. In various embodiments, a CMP process may be performed to remove excess metal from the metal layer of gate stack 1002 to provide a substantially planar top surface of the metal layer of gate stack 1002 . Metal layer 1006 of gate stack 1002 is illustrated in Figures 10A and 10B. Additionally, the metal layer can provide an N-type or P-type work function and can be used as a transistor (eg, FinFET) gate electrode, and in at least some embodiments, the metal layer of gate stack 1002 can include a polysilicon layer. Gate structure 1002 includes portions inserted into each epitaxial layer 306 , each of which forms a channel of multi-gate device 200 .

In some embodiments, an anti-reaction layer may be included in gate stack 1002 to prevent oxidation. In some embodiments, the anti-reaction layer may include a dielectric material. In some embodiments, the anti-reaction layer may include silicon-based materials. In some embodiments, the anti-reaction layer may include silicon (Si), silicon oxide (SiO _x ), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbide (SiC) , combinations thereof or multiple layers thereof or the like. However, any suitable material may be used. The anti-reaction layer can be conformally deposited using deposition processes such as ALD, CVD, PVD, and the like. The anti-reaction layer may be deposited to a thickness of about 0.3 nm to about 5 nm.

In some embodiments, a glue layer may be included in the gate stack 1002 . The glue line may contain any acceptable material to promote adhesion and prevent spreading. For example, the glue layer can be formed of metal or metal nitride, such as titanium nitride, titanium aluminum, titanium aluminum nitride, silicon-doped titanium nitride, tantalum nitride or the like, which can be formed by ALD, CVD , deposited by a process similar to PVD.

In one embodiment, the gate structure includes a high-k dielectric layer, a p-type work function layer located above the high-k dielectric layer, an n-type work function layer located above the p-type work function layer, and an n-type work function layer located above the high-k dielectric layer. an anti-reaction layer above the type work function layer and a glue layer above the anti-reaction layer. The gate structure may include different or additional layers, or the previously discussed layers may be omitted. The layers of the gate structure can also be deposited in different sequences. Additional layers may include barrier layers, diffusion layers, adhesion layers, combinations thereof, or multiple layers thereof, or the like. In some embodiments, additional layers may include chlorine (Cl) or similar materials. Additional layers may be deposited by ALD, CVD, PVD or similar processes.

The method 100 then proceeds to block 122 to perform further fabrication. The semiconductor device may undergo further processing to form various features and regions known in the art. For example, subsequent processing may form contact openings, contact metals, and various contacts/vias/lines and multi-layer interconnect features (e.g., metal layers and interlayer dielectric layers) on the substrate configured to connect Various components are used to form functional circuits that may include one or more multi-gate devices. In further examples, multi-level interconnects may include vertical interconnects (eg, vias or contacts) and horizontal interconnects (eg, metal lines). Various interconnect components may be made from a variety of conductive materials, including copper, tungsten, and/or silicide. In one example, damascene and/or dual damascene processes are used to form copper-related multi-layer interconnect structures. Additionally, additional process steps may be performed before, during, and after method 100 , and some of the foregoing process steps may be replaced or removed according to various embodiments of method 100 .

11 is a flow diagram illustrating an example method 1100 of further semiconductor fabrication after forming a metal gate structure, including fabricating a continuous metal cap for use with subsequently fabricated via gate conductors. 11 is described in conjunction with FIGS. 12A-12G, which illustrates a semiconductor device or structure in different manufacturing stages according to some embodiments. Method 1100 is merely an example and is not intended to limit the disclosure beyond what is expressly stated in the claimed scope. Additional steps may be provided before, during, and after method 1100, and some of the steps described may be moved, replaced, or deleted for other embodiments of method 1100. Additional components may be added to the semiconductor devices depicted in the drawings, and some of the components described below may be replaced, modified, or removed in other embodiments.

12A-12G are diagrams depicting enlarged views of an exemplary gate structure 1200 (similar to the top shown in FIGS. 2B-10B ) at various stages of fabricating a metal cap over a metal gate stack, in accordance with some embodiments. . In some drawings, some reference signs to illustrated components or features may be omitted to avoid confusing other components or features; this is for convenience in depicting the drawings.

A metal cap may be formed over the metal gate structure as an intermediary for connecting via gate (VG) conductors to the metal gate structure. Using a metal cap to connect the VG conductor to the metal gate structure reduces the gate resistance (Rg) compared to connecting the VG conductor directly to the metal gate structure. Therefore, using a metal cover improves the performance of the unit.

Anti-reaction layers can be included in metal gate structures to prevent P-metal and N-metal oxidation and improve device performance. However, the anti-reaction layer may hinder the formation of a metal cap over the metal gate structure. Method 1100 presents an exemplary process for forming a metal cap over a metal gate structure without an anti-reactive layer impeding the formation of the metal cap, and also for gate height scaling with a metal cap thickness of about 3-4 nm.

At block 1102 , the exemplary method 1100 includes receiving a gate structure having a high-k dielectric layer, a p-type work function layer over the high-k dielectric layer, and a p-type work function layer over the p-type work function layer. An n-type work function layer, an anti-reaction layer located above the n-type work function layer, and a glue layer located above the anti-reaction layer.

At block 1104, the top layer of the gate structure is planarized using a planarization process to create a horizontal surface by removing excess material. The planarization process may be, for example, a chemical mechanical polishing (CMP) process, an etch-back process, a combination thereof, or similar processes.

Figure 12A illustrates an example gate structure 1200 after metal gate (MG) formation and after the planarization process is completed in block 1104 (similar to the top portion shown in Figures 2B-10B). Exemplary gate structure 1200 includes a plurality of gate spacers 1212 and an MG or gate stack 1201 . Exemplary gate stack 1201 includes a high-k interlayer dielectric material 1210, a p-type work function layer 1208 adjacent to the high-k interlayer dielectric (ILD) material 1210, and a p-type work function layer 1208. The n-type work function layer 1206 is adjacent to the n-type work function layer 1206, the anti-reaction layer 1204 is adjacent to the n-type work function layer 1206, and the glue layer 1202 is adjacent to the anti-reaction layer 1204.

Exemplary gate stack 1201 may be used with n-channel metal oxide semiconductor (NMOS) or p-channel metal oxide semiconductor (PMOS). In embodiments for use with NMOS semiconductor devices, gate stack 1201 may include N-metal layer 1206 and P-metal layer 1208 , or gate stack 1201 may only include N-metal layer 1206 without P-metal layer 1208 . In embodiments used with PMOS semiconductor devices, gate stack 1201 may include N-metal layer 1206 and P-metal layer 1208 , or gate stack 1201 may include only P-metal layer 1208 without N-metal layer 1206 .

At block 1106, the surface of the gate structure is pre-cleaned to remove any excess soil or particles to ensure successful coverage of the gate structure during subsequent deposition operations. In one embodiment, the surface of the gate structure is pre-cleaned by rinsing with a deionized (DI) aqueous solution. For example, in one embodiment, the deionized water solution may be delivered for approximately 28 seconds. The cleaning solution can be at ambient temperature or can be heated or cooled to different temperatures.

At block 1108, the surface of the gate structure is pretreated to achieve surface modification and selective growth assistance. In some embodiments, the pre-treatment is a plasma treatment 1214, such as oxygen ( _O2 ) plasma or nitrogen/hydrogen ( _N2 / _H2 ) plasma. In some embodiments, light plasma treatment is applied. After the pretreatment process, part of the titanium nitride in the metal gate layers 1206 and 1208 has been transformed into titanium oxide or titanium oxynitride. In various embodiments, pretreatment may be used for metal gates such as nitride-based, carbide-based, and pure metals (eg, acids of Co and bases of Al) based on optimization processes. Both _O2 and _N2 / _H2 are suitable for pretreatment of TiN, TaC and TiC-based metal gates through process adjustment.

The plasma treatment procedure may be a plasma cleaning operation including hydrogen ( _H2 ) and nitrogen ( _N2 ) at a temperature of about 100°C to 300°C. In exemplary embodiments, by controlling the gas flow, the hydrogen:nitrogen ratio may range from about 10:1 to about 2:1, although other ratios may be used in other exemplary embodiments. In an exemplary embodiment, a gas flow of about 500sscm to about 5000sscm _H and about 500sscm to about 10000sscm _N may be used at a pressure of about 0.5 torr to about 50 torr and an inductively coupled plasma source power of 2500 watts. In other exemplary embodiments, the power used in the cleaning chamber may range from about 150W to about 3000W. Plasma pretreatment is used to passivate the surface of the gate structure instead of sputtering.

FIG. 12B illustrates gate structure 1200 after completion of pre-cleaning in block 1106 and pre-processing in block 1108 . Pretreatment results in surface modification using plasma treatment 1214.

At block 1110, a metallic material is deposited over the metal gate stack using selective deposition. Metallic materials can be deposited by CVD or ALD. In an exemplary embodiment, the metallic material is deposited via an ALD process. During deposition, chloride in the precursor reacts with titanium oxide in metal gate stack 1201 to form recesses in P-metal 1208, N-metal 1206, and the high-k material. The difference (delta) in etch rates between the metal and the high-k material affects the amount of the high-k material that is etched and the slope of the recesses in the high-k material. Metallic material is selectively deposited in the recesses and over the high-k material 1210 , P-metal 1208 and N-metal 1206 layers of gate stack 1201 . In various embodiments, WCl ₅ reacts with surface Ti-O to form WOCl _x and TiOCl _y in vapor form. The TiOCl _y vapor is extracted to help form the recess. The metal material forms a discontinuous metal cap 1216 over the gate stack 1201 . Because the anti-reactive layer has dielectric-like properties, the growth of the metal cap over the anti-reactive layer is inhibited.

Metal cap 1216 may be, for example, tungsten (W) or molybdenum (Mo). In some examples, WCl ₅ is used to deposit a W cap over anti-reactive layer 1204, which may be composed of a silicon-containing material such as silicon nitride (SiN) or silicon oxide ( _SiOx ).

In embodiments where the conductive cover material includes tungsten, a tungsten chloride (WCl ₅ ) precursor, hydrogen (H ₂ ) reducing gas and argon (Ar) carrier gas to deposit the conductive cap material. The tungsten chloride precursor can be provided at a temperature ranging from about 100°C to about 150°C. In some embodiments, the conductive cap material may also include chlorine at an atomic concentration ranging from about 0.5% to about 5%. Alternatively, a similar ALD process can be used to deposit Mo using molybdenum chloride (MoCl ₅ ) precursor, hydrogen (H ₂ ) reducing gas, and argon (Ar) carrier gas at a temperature of about 300°C to form the Mo cap.

After the deposition process of block 1110 is completed, a discontinuous metal cap 1216 has been formed over the metal gate stack 1201 . In some embodiments, the thickness of the discontinuous metal cap 1216 is approximately 1-2 nm. Due to the high atomic order of W relative to the metal gate, the thickness of the discontinuous metal cap 1216 may be non-uniform and may be determined by TEM analysis. Partial metal cap 1216 is used as an etch mask during subsequent process steps to ensure that P-metal 1208 and N-metal 1206 are not damaged during block 1112 when a portion of anti-reaction layer 1204 is removed.

FIG. 12C depicts gate structure 1200 after depositing metal material at block 1110 to form a partial metal cap. Gate structure 1200 has been modified to include discontinuous metal cap 1216 .

The anti-reaction layer 1204 inhibits deposition of metallic material because WCl ₅ is less reactive with the dielectric surface of the anti-reaction layer than the rest of the gate stack. A portion of the anti-reaction layer will be selectively removed to allow additional metal material to be deposited to create a continuous metal cap over gate stack 1201 . The anti-reaction layer 1204 may be composed of silicon-containing material. In some embodiments, anti-reaction layer 1204 may be SiN or _SiOx . The anti-reaction layer 1204 protects the P-metal 1208 and N-metal 1206 from the etching process, improves the characteristics of the metal cap 1220, such as threshold voltage shift (V _ts ), and prevents degradation. However, due to the dielectric properties of silicon-containing materials, the anti-reaction layer 1204 inhibits metal cap coverage.

At block 1112 , a portion of the anti-reactive layer 1204 is selectively removed to leave a plurality of recesses 1218 . Removal of the anti-reactive layer 1204 proceeds to a depth to which the discontinuous metal cap 1216 has been deposited, which may be about 1 to 2 nm, with the depth of the recess being an average 1215, the recess being defined as the gap towards the surface of the spacer. Therefore, a portion of the anti-reaction layer 1204 is removed such that the depth of the resulting recess 1218 is approximately equal to the thickness of the discontinuous metal cap 1216 . Removal of a portion of the anti-reaction layer 1204 may be accomplished through a wet chemical process. The wet chemical process dissolves and removes the anti-reaction layer 1204 (which may include silicon oxide or another dielectric material), but the wet chemical process does not dissolve portions of the metal material of the metal cap 1216 . The presence of partial metal cover 1216 protects P-metal 1208 and N-metal 1206 from wet chemical processes. In one embodiment, the entire gate structure 1200 is rinsed with etching solution.

The etching solution may be dilute hydrofluoric acid (HF). HF was diluted with deionized water. In some embodiments, the volume ratio of HF to deionized water is about 1:500. In other embodiments, the volume ratio of HF to deionized water is about 1:2000. Alternatively, the etching solution may be MR1, for example. Etching solution MR1 contains 1 part ammonium hydroxide (NH ₄ OH), about 1 to about 10 parts hydrogen peroxide (H ₂ O ₂ ), and about 5 to about 30 parts water (H ₂ O). In some embodiments, other etching solutions may be used, or the components of the etching solution may be mixed in different proportions.

12D illustrates gate structure 1200 after block 1112 selectively removes a portion of anti-reaction layer 1204 to form recess 1218.

At block 1114, additional metal material is deposited to form a continuous metal cap 1220. In some embodiments, the process in block 1114 is the same as the process in block 1110 . In other embodiments, variations of the process in block 1110 are used in block 1114 . In other embodiments, a different deposition process is used in block 1114 than in block 1110 .

Additional metal material is deposited over metal gate structure 1200 . Metallic materials may be deposited by CVD, ALD, electroless deposition (ELD), PVD, electroplating, a combination thereof, or another deposition technique. In an exemplary embodiment, the metallic material is deposited through an ALD process. The metal material deposited at block 1114 fills recess 1218 to form a continuous metal cap 1220 over metal gate stack 1201 . Metallic material may also partially cover spacer 1212.

The metal material deposited in block 1114 is the same as the metal material deposited in block 1110, and may be W or Mo, for example. In an exemplary embodiment, a tungsten chloride (WCl ₅ ) precursor, hydrogen (H ₂ ) reducing gas, and Argon (Ar) carrier gas deposition W. In some embodiments, the conductive cap material may also include chlorine at an atomic concentration ranging from about 0.5% to about 5%. Alternatively, the precursor may be tungsten fluoride (WF ₆ ) or molybdenum chloride (MoCl ₅ ).

The ALD cycle or other deposition process is controlled to obtain the desired thickness of metal cap 1220. In some embodiments, the metal deposited in block 1114 has a thickness of about 2 nm, such that the thickness of the entire metal cap 1220 is about 3-4 nm. In various embodiments, the thickness is limited to 3-4 nm to take advantage of gate reduction without affecting RC delay, as thicker metal may increase overall gate height and gate capacitance. The first metal cap from the first metal cap deposition process is used as a protective layer to avoid metal damage due to the wet process and to achieve the final thickness through the second metal cap deposition process.

12E illustrates gate structure 1200 after additional metal material is deposited in block 1114 to create a continuous metal cap 1220. In some embodiments, the additional metal material is the same type of metal material used for the discontinuous metal cap. In some embodiments, the additional metal material 1217 is different from the metal material of the discontinuous metal cap 1216, thereby forming a double layer metal cap, such as Mo on W or W on Mo, as shown in Figure 12F.

At block 1116, lateral growth of the metal cap 1220 is reduced and excess material is removed using a wet chemical process. The metal cap 1220 is constrained so that it covers the metal gate stack 1201 but not the sidewall spacers 1212 . Sidewall spacers 1212 may be composed of, for example, silicon, carbide, or nitride. In some embodiments, an ozone solution (eg, ozone deionized water solution (DIO ₃ )) is used to limit the growth of the metal cap 1220 . Alternatively, hot deionized water (HDI) can be used at a temperature of about 40°C to about 80°C.

In one embodiment, the growth of the metal cap is inhibited by applying a solution of deionized water and ozone for a period of about 5 seconds to about 60 seconds. In some embodiments, the solution includes ozone and hydrochloric acid mixed in water. In an exemplary embodiment, the solution includes DIO ₃ at a concentration of 5 to 100 ppm at room temperature and HCl at a concentration of 1:1 to about 1:50 at a temperature of about 25°C to about 50°C.

FIG. 12G depicts gate structure 1200 after lateral growth in region 1116 has been reduced. The continuous metal cover 1220 is now constrained so that it does not cover the spacer 1212.

One of the benefits of continuous metal cap 1220 is its ability to reduce the gate resistance of metal gate stack 1201 . Reduced gate resistance results in higher overall performance of the semiconductor device. In an exemplary embodiment, a semiconductor device with continuous metal cap 1220 has a gate resistance that is approximately 80% lower than a semiconductor device without continuous metal cap 1220 . 15 illustrates the difference between the gate resistance achievable for a semiconductor device with a continuous metal cap 1220 and the gate resistance that may be experienced without the metal cap. In the example of Figure 15, without metal cap 1220, the target gate resistance is approximately 300-400 ohms per square (Ω/sq), as measured by a four-point probe. Using metal cap 1220, the target resistance is reduced to approximately 80Ω/sq.

At block 1118, the example method 1100 includes a metal drain fabrication operation to form a metal drain (MD) over the source/drain regions. The metal drain fabrication operation may include removing the exposed portions of the ILD layer to form an opening exposing the underlying source/drain structure. The exposed portions of the ILD layer may be removed by a suitable etching process, such as wet etching, dry etching, or a combination thereof. During etching of the ILD layer, the etchant is selected to provide etch selectivity between the ILD layer and other structures (eg, gate spacer 1212 and metal cap 1220). For example, the ILD layer is less resistant to etchants than the gate spacers 1212 and metal caps 1220 such that the ILD layer can be etched while leaving the gate spacers 1212 and metal caps 1220 substantially intact.

The metal drain fabrication operation (block 1118) may also include removing the patterned mask and forming source/drain contacts in the openings. Forming the source/drain contact in the opening may include filling the opening contacting the source/drain region with a conductive material to form the source/drain contact. The source/drain contacts may include one or more layers. For example, in some embodiments, the source/drain contacts include liner and metal fill materials deposited by, for example, CVD, ALD, electroless deposition (ELD), PVD, electroplating, or another deposition technique. The liner (eg, diffusion barrier, adhesion layer, or the like) may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, ruthenium, nickel or the like. A planarization process such as CMP can be performed to remove excess pads and conductive material. The remaining pad and conductive material form source/drain contacts 702 in the openings.

At block 1120, the example method 1100 includes a via gate fabrication operation to form a via gate (VG). Via gate fabrication operations may include forming openings through interlayer dielectric (ILD) material to contact metal cap 1220 . Openings for via gate fabrication operations may be formed using acceptable photolithography and etching techniques. Via gates can be deposited by CVD, ALD, electroless deposition (ELD), PVD, electroplating or other deposition techniques.

FIG. 12H illustrates gate structure 1200 after VG 1222 is formed. Metal drain (MD) (not shown) and interlayer dielectric (ILD) 1224 have also been formed. VG 1222 may be or contain tungsten, cobalt, copper, ruthenium, aluminum, gold, silver, alloys thereof, the like, or combinations thereof. MD can be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, ruthenium, nickel or the like. ILD 1224 is a low-k material such as an oxide.

At block 1122, the example method 1100 includes performing further manufacturing operations. The semiconductor device may undergo further processing to form various features and regions known in the art. For example, subsequent processing may form contact openings, contact metals, and various contacts/vias/lines and multi-layer interconnect features (e.g., metal layers and interlayer dielectrics) over the substrate configured to connect Various components are used to form functional circuits that may include one or more multi-gate devices. In a further example, multi-level interconnects may include vertical interconnects (eg, vias or contacts) and horizontal interconnects (eg, metal lines). Various interconnect components can be made from a variety of conductive materials, including copper, tungsten, and/or silicide. In one example, a multi-level interconnect structure associated with copper is formed using damascene and/or dual damascene processes. Additionally, additional process steps may be performed before, during, and after method 1100 , and some of the foregoing process steps may be replaced or removed according to various embodiments of method 1100 .

13 is a process flow diagram depicting an exemplary method 1300 of semiconductor fabrication including metal drain (MD) fabrication and via gate (VG) fabrication, in accordance with some embodiments. Method 1300 is merely an example, and is not intended to limit the disclosure beyond what is expressly stated in the claims. Additional steps may be provided before, during, and after method 1300, and some of the steps described may be moved, replaced, or deleted for other embodiments of method 1300. Additional components may be added to the semiconductor devices depicted in the drawings, and some of the components described below may be replaced, modified, or removed in other embodiments.

Figure 13 illustrates example operations that may be performed between block 1118 and block 1120 of Figure 11, according to some embodiments. 13 is described in conjunction with FIGS. 14A-14E, which are enlarged views of an exemplary region 1400 illustrating various stages of semiconductor fabrication including metal drain fabrication and via gate fabrication, according to some embodiments. In some drawings, some reference signs to illustrated components or features may be omitted to avoid confusing other components or features; this is for convenience in depicting the drawings.

At block 1302, the example method 1300 includes providing a substrate having a metal gate, gate spacers over sides of the metal gate, a metal cap formed over the metal gate, an etch stop layer (ESL), and Interlayer dielectric (ILD) material located above the source/drain regions.

At block 1304, the example method 1300 includes forming a first ILD layer over the metal cap. The first ILD layer may comprise or be a material such as silicon nitride (SiN), although other suitable materials may also be used, such as silicon oxide (SiO ₂ ), aluminum oxide (AlO), silicon oxycarbide (SiOC), silicon carbide (SiC), zirconium nitride (ZrN), zirconium oxide (ZrO), combinations thereof or the like. The first ILD layer may be deposited using a deposition process such as plasma-assisted atomic layer deposition (PEALD), thermal atomic layer deposition (thermal ALD), plasma-assisted chemical vapor deposition (PECVD), and the like. Any suitable deposition process and process conditions may be used.

At block 1306, the example method 1300 includes forming a patterned mask that exposes a portion of the ILD material over the source/drain regions. The patterned mask may include a photoresist layer. Patterned masks can be produced by photoresist coating (e.g., spin coating), soft bake, mask alignment, exposure, post-exposure bake, developing photoresist, cleaning, drying (e.g., hard bake), and/or or a combination thereof. In some other embodiments, various imaging auxiliary layers may be formed under the photoresist layer to assist in pattern transfer. The imaging auxiliary layer may include three layers including a bottom organic layer, a middle inorganic layer, and a top organic layer. The imaging auxiliary layer may also include anti-reflective coating (ARC) materials, polymer layers, oxides from tetraethylorthosilicate (TEOS), silicon oxide or Si-containing anti-reflective coatings. layer (ARC) material, such as an ARC layer containing 42% Si. In still other embodiments, the patterned mask layer includes a hard mask layer. The hard mask layer includes an oxide material, silicon nitride, silicon oxynitride, amorphous carbon material, silicon carbide, or tetraethylorthosilicate (TEOS).

Referring to the example of FIG. 14A , in one embodiment after completion of blocks 1302 , 1304 , and 1306 , a region 1400 is shown that includes a substrate 1402 with a metal gate stack 1201 over the sides of the metal gate stack 1201 gate spacer 1212, metal cap 1220 formed over metal gate stack 1201, ESL 1416, ILD material 802 over source/drain regions 1404, first ILD layer 1414 over metal cap 1220, and exposed Patterned mask 1406 of a portion of ILD material 802 over source/drain regions 1404 .

At block 1308, the example method 1300 includes removing the ILD material over the source/drain regions to form openings exposing the underlying source/drain regions. The exposed portions of the ILD material can be removed by a suitable etching process, such as wet etching, dry etching, or a combination thereof.

At block 1310, the example method 1300 includes optionally forming a plurality of suicide contacts over the exposed source/drain regions. An optional suicide contact may include titanium (eg, titanium silicide (TiSi)) to reduce the Schottky barrier height of the contact. However, other metals may also be used, such as nickel, cobalt, erbium, platinum, palladium or the like. Silicide can be performed by blanket deposition of a suitable metal layer, followed by an annealing step to react the metal with the exposed silicon beneath the source/drain regions.

Referring to the example of FIG. 14B , in one embodiment after blocks 1308 and 1310 are completed, region 1400 includes openings 1408 exposing underlying source/drain regions 1404 and optionally in the already exposed source/drain regions. Silicide contact 1409 formed on top of 1404. The figure depicts that the ILD material 802 over the source/drain region 1404 has been removed to form an opening 1408 exposing the underlying source/drain region 1404.

At block 1312, the example method 1300 includes filling openings contacting source/drain regions with conductive material to form a plurality of source/drain contacts. Source/drain contact 702 may include one or more layers. For example, in some embodiments, the source/drain contacts include a liner and a metal fill material deposited by, for example, CVD, ALD, electroless deposition (ELD), PVD, electroplating, or another deposition technique (not separately shown). The lining layer (eg, diffusion barrier layer, adhesion layer, or the like) may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, ruthenium, nickel or the like. A planarization process such as CMP can be performed to remove excess liner and conductive material. The remaining liner and conductive material form source/drain contacts located in the openings.

Referring to the example of FIG. 14C , in one embodiment after block 1312 is completed, region 1400 includes conductive material that fills opening 1408 and contacts source/drain region 1404 to form source/drain contact 702 .

At block 1314, the example method 1300 includes forming a contact etch stop layer (CESL) over the source/drain and gate regions. CESL can be deposited using one or more low-temperature deposition processes, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

At block 1316, the example method 1300 includes forming a second ILD layer over the CESL layer. The second ILD layer may be formed from a dielectric material such as an oxide (eg, silicon oxide (SiO ₂ )) and may be deposited by any acceptable process (eg, CVD, PEALD, thermal ALD, PECVD, or similar processes) above CESL. The second ILD layer may also be formed from other suitable insulating materials (eg, PSG, BSG, BPSG, USG, or the like) deposited by any suitable method (eg, CVD, PECVD, flowable CVD, or similar processes). After formation, the second ILD layer can be cured, such as by a UV curing process.

Referring to the example of FIG. 14D , in one embodiment after blocks 1314 and 1316 are completed, region 1400 includes a CESL layer 1410 formed over the source/drain and gate regions and a second ILD formed over the CESL layer 1410 Layer 1412.

At block 1318, the example method 1300 includes forming contact via openings in the CESL and second ILD layers for via gate contacts and source/drain via contacts. Contact via openings for via gate contacts and source/drain via contacts are formed using one or more etching processes. According to some embodiments, the opening for the via gate contact is formed through the second ILD layer, the CESL, and the first ILD layer, and the opening for the source/drain via contact is formed through the second ILD layer. layer and CESL. The openings may be formed using any combination of acceptable photolithography and suitable etching techniques, such as dry etching processes (e.g., plasma etching, reactive ion etching (RIE)), physical etching (e.g., ion beam etching (IBE) ))), wet etching processes, combinations thereof or similar processes. However, the contact via openings may be formed using any suitable etching process.

At block 1320 , the example method 1300 includes forming via gate contacts and source/drain via contacts. A via gate contact is formed over and electrically coupled to the metal cap, and a source/drain via contact is formed over and electrically coupled to the source/drain contact. Via gate contacts and/or source/drain via contacts may be formed by depositing metallic material in the openings. Metallic materials can be deposited by CVD, ALD, electroless deposition (ELD), PVD, electroplating or another deposition technique. The via gate contacts and/or source/drain via contacts may be or include tungsten, cobalt, copper, ruthenium, aluminum, gold, silver, alloys thereof, the like, or combinations thereof.

Referring to the example of FIG. 14E , in one embodiment after blocks 1318 and 1320 are completed, region 1400 includes via gate contacts 1222 and source/drain via contacts (not shown).

At block 1322, the example method 1300 includes performing further manufacturing operations. The semiconductor device may undergo further processing to form various features and regions known in the art. For example, subsequent processing may form various contact vias/lines and multi-layer interconnect features (e.g., metal layers and interlayer dielectrics) over the substrate that are configured to connect the various features to form a device that may include Functional circuit of one or more multi-gate devices. In a further example, multi-level interconnects may include vertical interconnects (eg, vias or contacts) and horizontal interconnects (eg, metal lines). Various interconnect components can be made from a variety of conductive materials, including copper, tungsten, and/or silicide. In one example, a multi-level interconnect structure associated with copper is formed using damascene and/or dual damascene processes. Additionally, additional process steps may be performed before, during, and after method 1300, and some of the foregoing process steps may be replaced or removed according to various embodiments of method 1300.

Improved systems, fabrication methods, fabrication techniques, and articles have been described. The systems, methods, techniques, and articles described are applicable to a wide range of semiconductor devices, including GAA and FinFET devices.

In various embodiments, a semiconductor device includes a gate structure over a semiconductor substrate and a continuous metal cap over the gate structure. The gate structure includes: a high dielectric coefficient dielectric layer; a P-type work function layer; an N-type work function layer; an anti-reaction layer, including dielectric materials; and a glue layer. The continuous metal cap is formed by depositing a metal material over the gate structure during a plurality of first deposition operations, the metal material forming a discontinuous metal cap; and selectively placing the resist during a plurality of first wet chemical operations. A portion of the reactive layer is removed; additional metal material is deposited over the gate structure during a plurality of second deposition operations to create a continuous metal cap; and the continuous metal cap is suppressed during a plurality of second wet chemical operations grow.

In certain embodiments of the semiconductor device, the continuous metal cover includes tungsten (W) or molybdenum (Mo) material.

In certain embodiments of the semiconductor device, the gate structure is prepared to form a continuous metal cap over the gate structure by: planarizing the top layer of the gate structure using a planarization operation; using deionization ( DI) water rinsing to pre-clean the surface of the gate structure; and using oxidation or nitriding treatment to pre-treat the surface of the gate structure.

In certain embodiments of semiconductor devices, dilute hydrofluoric acid (HF) or an etching solution containing ammonium hydroxide (NH ₄ OH), hydrogen peroxide (H ₂ O ₂ ), and water (H ₂ O) is used to selectively Remove part of the anti-reaction layer.

In certain embodiments of the semiconductor device, the anti-reaction layer includes a silicon-containing material.

In certain embodiments of the semiconductor device, the gate structure has a gate resistance (Rg) less than or equal to 80 ohms per square (Ω/sq).

In various embodiments, a method of forming a continuous metal cap over a metal gate structure includes: receiving a gate structure having a high-k dielectric layer, a P-type work function layer, an N Type work function layer, anti-reaction layer including dielectric material and adhesive layer. The method includes pretreating the surface of the gate structure using an oxidation or nitriding process; using a plurality of first deposition operations to deposit a metal material over the gate structure, which forms a discontinuous metal cap; using a plurality of first deposition operations Wet chemical operations selectively remove a portion of the anti-reaction layer; use multiple second deposition operations to deposit additional metal material over the gate structure to create a continuous metal cap; and use multiple second wet chemical operations Inhibits continuous metal cap growth.

In a specific embodiment of this method, it further includes forming a via gate (VG) on the metal cover. Forming the via gate on the metal cap includes using a plurality of etching operations to form an opening through the interlayer dielectric material to contact the metal cap, and using a plurality of deposition operations to deposit a metal material in the opening.

In a specific embodiment of this method, the first deposition operation and the second deposition operation include a plurality of atomic layer deposition (ALD) operations, and the metal cover includes tungsten chloride (WC1 ₅ ) and hydrogen (H ₂ ) deposited Tungsten (W).

In a specific embodiment of this method, the first deposition operation and the second deposition operation include multiple atomic layer (ALD) deposition operations, and the metal cover includes tungsten fluoride (WF ₆ ) and hydrogen (H ₂ ) deposited Tungsten (W).

In a specific embodiment of this method, the first deposition operation and the second deposition operation include a plurality of atomic layer deposition (ALD) operations, and the metal cover includes molybdenum chloride (MoCl ₅ ) and hydrogen (H ₂ ) deposited Molybdenum (Mo).

In a specific embodiment of this method, the first wet chemical operation for removing the anti-reactive layer includes a rinse with dilute hydrofluoric acid (HF).

In a specific embodiment of this method, the first wet chemical operation for removing a portion of the anti-reactive layer includes rinsing with an etching solution containing ammonium hydroxide (NH ₄ OH), hydrogen peroxide (H ₂ O ₂ ) and water (H ₂ O).

In a specific embodiment of this method, the second wet chemical operation for inhibiting metal cap growth includes a wet etching operation using an ozone solution.

In another embodiment, a method of manufacturing a semiconductor device includes: receiving a gate structure having a high-k dielectric layer, a P-type work function layer, an N-type work function layer, and a dielectric anti-reaction layer and glue layer. The method of manufacturing a semiconductor device further includes: using oxygen (O ₂ ) or hydrogen/nitrogen (H ₂ /N ₂ ) plasma treatment to pretreat the surface of the gate structure; using multiple first atomic layer deposition (ALD) operations Depositing a first metal material including tungsten (W) material or molybdenum (Mo) material over the gate structure to form a discontinuous metal cover; using dilute hydrofluoric acid to selectively remove a portion of the anti-reaction layer ;Using multiple second atomic layer deposition operations to deposit a second metal material containing tungsten or molybdenum over the gate structure to create a continuous metal cap; by removing the unwanted metal material through a wet etching operation using an ozone solution Removing from the plurality of side spacers to inhibit growth of the metal cap; and forming a via gate (VG) over the metal cap. Forming the via gate over the metal cap includes using multiple etching operations to form openings through interlayer dielectric (ILD) material to contact the metal cap and using multiple deposition operations to deposit metallic material in the openings.

In a particular embodiment of this method of semiconductor device, the first atomic layer deposition operation and the second atomic layer deposition operation include depositing tungsten (W) by tungsten chloride ( _WC15 ) and hydrogen gas ( _H2 ).

In a particular embodiment of this method of semiconductor device, the first atomic layer deposition operation and the second atomic layer deposition operation include depositing tungsten by tungsten fluoride (WF ₆ ) and hydrogen gas (H ₂ ).

In a specific embodiment of this method of semiconductor device, the first atomic layer deposition operation and the second atomic layer deposition operation include depositing molybdenum (Mo) by molybdenum chloride (MoCl ₅ ) and hydrogen (H ₂ ).

In a specific embodiment of the method of semiconductor device, one of the first metallic material and the second metallic material includes tungsten, and the other of the first metallic material and the second metallic material includes molybdenum.

In a specific embodiment of the method for a semiconductor device, the method further includes planarizing a top layer of the gate structure using a plurality of chemical mechanical polishing (CMP) operations, and using a decontamination process before preprocessing the surface of the gate structure. Ionic (DI) water rinses pre-clean the surface of the gate structure.

Although at least one exemplary embodiment has been presented in the foregoing detailed description of the present disclosure, it should be understood that numerous variations exist. It should also be understood that the exemplary embodiment or exemplary embodiments are only examples, and are not intended to limit the scope, applicability, or configuration of the disclosure in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing exemplary embodiments of the present disclosure. It should be understood that various changes may be made in the function and arrangement of the elements described in the exemplary embodiments without departing from the scope of the disclosure as set forth in the appended claims.

Claims (10)

1. A semiconductor device, comprising:

a gate structure over a semiconductor substrate, the gate structure comprising:

a high-k dielectric layer;

a P-type work function layer;

an N-type work function layer;

an anti-reaction layer comprising a dielectric material; and

A glue layer; and

a continuous metal cap over the gate structure, the continuous metal cap formed by:

depositing a metal material over the gate structure during a plurality of first deposition operations, the metal material forming a discontinuous metal cap;

selectively removing a portion of the anti-reaction layer during a plurality of first wet chemical operations;

depositing additional metal material over the gate structure during a plurality of second deposition operations to create the continuous metal cap; and

The continuous metal cap is inhibited from growing during a plurality of second wet chemical operations.

2. The semiconductor device of claim 1, wherein the gate structure is prepared to form the continuous metal cap over the gate structure, the gate structure prepared by:

planarizing a top layer of the gate structure using a planarization operation;

Pre-cleaning the surface of the grid structure by using deionized water for flushing; and

The surface of the gate structure is pre-treated with an oxidation or nitridation process.

3. The semiconductor device of claim 1, wherein a portion of the anti-reaction layer is selectively removed using dilute hydrofluoric acid or an etching solution comprising ammonium hydroxide, hydrogen peroxide, and water.

4. A method of forming a continuous metal cap over a metal gate structure, comprising:

a receiving gate structure, the gate structure comprising:

a high-k dielectric layer;

a P-type work function layer;

an N-type work function layer;

an anti-reaction layer comprising a dielectric material; and

A glue layer;

pre-treating the surface of the gate structure using an oxidation or nitridation process;

depositing a metal material over the gate structure using a plurality of first deposition operations, which form a discontinuous metal cap;

selectively removing a portion of the anti-reaction layer using a plurality of first wet chemical operations;

depositing additional metal material over the gate structure using a plurality of second deposition operations to create the continuous metal cap; and

the continuous metal cap growth is inhibited using a plurality of second wet chemical operations.

5. The method of forming the continuous metal cap over a metal gate structure of claim 4, further comprising forming a via gate over the metal cap, wherein forming the via gate over the metal cap comprises:

forming an opening through the interlayer dielectric material using a plurality of etching operations to contact the metal cap; and

A metallic material is deposited in the opening using a plurality of deposition operations.

6. The method of claim 4, wherein the plurality of first deposition operations and the plurality of second deposition operations comprise a plurality of atomic layer deposition operations, and wherein the metal cap comprises tungsten deposited by tungsten chloride and hydrogen.

7. The method of forming the continuous metal cap over a metal gate structure as recited in claim 4 wherein the plurality of first wet chemical operations for removing the anti-reaction layer comprises rinsing with dilute hydrofluoric acid.

8. The method of forming the continuous metal cap over a metal gate structure as recited in claim 4, wherein the plurality of second wet chemical operations for inhibiting growth of the metal cap comprises a wet etching operation using an ozone solution.

9. A method of manufacturing a semiconductor device, comprising:

a receiving gate structure, the gate structure comprising:

a high-k dielectric layer;

a P-type work function layer;

an N-type work function layer;

an anti-reaction layer comprising a dielectric material; and

A glue layer;

pretreating the surface of the gate structure with oxygen or hydrogen/nitrogen plasma treatment;

depositing a first metal material comprising a tungsten material or a molybdenum material over the gate structure using a plurality of first atomic layer deposition operations, which form a discontinuous metal cap;

selectively removing a portion of the anti-reaction layer using dilute hydrofluoric acid;

depositing a second metal material comprising tungsten or molybdenum over the gate structure using a plurality of second atomic layer deposition operations to create a continuous metal cap;

inhibiting growth of the metal cap by removing unwanted metal material from the plurality of side spacers by a wet etching operation using an ozone solution; and

forming a via gate over the metal cap, wherein forming the via gate over the metal cap comprises:

forming an opening through the interlayer dielectric material using a plurality of etching operations to contact the metal cap; and

A metallic material is deposited in the opening using a plurality of deposition operations.

10. The method of manufacturing a semiconductor device of claim 9, further comprising planarizing a top layer of the gate structure using a plurality of chemical mechanical polishing operations and pre-cleaning the surface of the gate structure using a deionized water rinse prior to pre-treating the surface of the gate structure.