JP5202691B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device, particularly a semiconductor device including two semiconductor chips, and is particularly suitable when the operating voltages of the two chips are different.

In recent years, a highly functional semiconductor device has been manufactured by housing a plurality of semiconductor chips having different functions in one package. Such a semiconductor device is called a multichip package (MCP), and is disclosed in, for example, Patent Document 1. MCP is attracting attention because it has an advantage that it can be manufactured easily and at a lower cost than SoC (System-on-Chip) in which a plurality of functions are integrated on one chip.

For example, a logic chip and a memory chip may be packaged as the MCP. As for logic chips, miniaturization is progressing for higher performance and lower power consumption, and the operating voltage is remarkably lowered. On the other hand, a small capacity may be sufficient for a memory chip required for MCP. Then, a manufacturing technology several generations before is used for a memory chip with a small capacity, and the operating voltage may be relatively high.

In such a case, it is necessary to use a combination of semiconductor chips having different operating voltages.

When semiconductor chips having different operating voltages are used in combination, a data signal whose own operating voltage is at a high level is output from a semiconductor chip having a higher operating voltage to a semiconductor chip having a lower operating voltage as it is. There is a possibility that the transistor constituting the input circuit of the receiving-side semiconductor chip that operates with voltage is destroyed.

In addition, when a semiconductor chip operating at a low voltage transmits a data signal whose low voltage is high level to the semiconductor chip operating at a high voltage as it is, the logic of the input circuit of the semiconductor chip operating at a high voltage is normally determined. There is a possibility not to.

  Conventionally, these problems have been solved as follows.

For example, when a memory chip that operates at 1.5V and a logic chip that operates at 1.0V are combined, a power supply of 3.3V is provided for each of the memory chip and the logic chip, and an input that operates at 3.3V is provided in both chips. Each output circuit was provided. That is, a buffer circuit for matching input / output voltages between the two chips is provided in each of the two chips.

JP 2005-217205 A

The inventor of the present invention described above has a buffer circuit that operates at a voltage different from the operating voltage,
It has been found that there is a problem that the area of each semiconductor chip increases because it is necessary to provide the semiconductor chip on each of the data transmission side and the reception side.

For example, when the memory chip outputs a data signal with a data width of 16 bits, it is necessary to provide 16 buffer circuits that operate at a voltage different from the operating voltage, and the problem of increasing the chip area is serious.

In this specification, the “operating voltage” is a voltage for driving the internal circuit. The internal circuit means a circuit that performs arithmetic processing in the logic chip, and means a memory cell circuit, an X decoder / Y decoder, a sense amplifier, or the like in the memory chip.

In the present invention, the operating voltage of one semiconductor chip is supplied from the one semiconductor chip to the other semiconductor chip.

Due to this feature, the operating voltage of the one semiconductor chip is Hi.
A data signal at the gh level can be generated. Therefore, at least one of the semiconductor chips can receive a data signal whose high level is its own operating voltage from the other semiconductor chip. Therefore, a buffer circuit that operates at a voltage different from its own operating voltage is provided. There is no need to provide it separately.

For example, the present invention provides a first semiconductor chip that operates with a first power supply voltage, a second power supply voltage that is lower than the first power supply voltage, and supplies the second power supply voltage to the first semiconductor chip. 2 semiconductor chips , wherein the first semiconductor chip receives an output circuit that outputs a signal to the second semiconductor chip, and receives the second power supply voltage from the second semiconductor chip. And a voltage supply circuit for supplying a power supply voltage, wherein the voltage supply circuit is a circuit that receives the first power supply voltage and outputs the second power supply voltage. .

A semiconductor chip suitable for use in the semiconductor device is also included in the present invention. Such a semiconductor chip includes, for example, an output circuit that is connected in series with each other, has first and second transistors that are turned on and off in a complementary manner, and outputs a signal to a first external terminal; And a third transistor connected in series with the second transistor and having a gate electrode connected to the second external terminal.

According to the present invention, since it is not necessary to provide a buffer circuit that operates at a voltage different from the operating voltage, the area of the semiconductor chip can be reduced.

It is a figure for demonstrating the best embodiment of this invention. It is a figure for demonstrating the 1st Example of this invention. It is a figure for demonstrating the 2nd Example of this invention. It is a figure for demonstrating the 3rd Example of this invention. It is a figure for comparing the 1st example of the present invention and the 3rd example.

  An embodiment of the present invention will be described below with reference to FIG.

FIG. 1 is a diagram for explaining a semiconductor device 100 according to a first embodiment of the present invention.

The semiconductor device 100 includes a first semiconductor chip 10 and a second semiconductor chip 20. Hereinafter, although the present embodiment will be described using the first semiconductor chip 10 as a memory chip and the second semiconductor chip 20 as a logic chip, the present invention is not limited to these types of semiconductor chips.

The memory chip 10 has an internal circuit 12 including memory cells, a decoder, a sense amplifier, etc. (not shown). The internal circuit 12 is connected to a power supply line Vdd1, which is a first power supply voltage supply source,
A data signal SD1 is output that sets the first power supply voltage supplied from the power supply line Vdd1 to a high level. That is, the internal circuit 12 uses the first power supply voltage supplied from the power supply line Vdd1 as the operating voltage. In the present embodiment, the first power supply voltage is assumed to be 1.5V.

In the present specification, power supply lines with the same reference sign mean wirings for supplying the same power supply voltage. Therefore, the same wiring connected may be sufficient and the separated separate wiring may be sufficient.

Further, the memory chip 10 has an output circuit 14. The output circuit 14 receives the data signal SD1 output from the internal circuit 12 and outputs the data signal SD2 to the bump B1 that is the first external terminal.

The memory chip 10 has a power supply voltage supply circuit 16. The power supply voltage supply circuit 16 receives the voltage signal SV supplied to the bump B2 which is the second external terminal, and supplies the output circuit 14 with the same voltage as the voltage signal SV. Then, the output circuit 14 outputs the data signal SD2 whose High level is the voltage supplied from the power supply voltage supply circuit 16 to the bump B1.

The logic chip 20 has an internal circuit 22 that performs arithmetic processing. The internal circuit is 22nd
A second power supply voltage connected to the power supply line Vdd2 which is a power supply voltage supply source and supplied by the power supply line Vdd2 is used as the operating voltage. The second power supply voltage is lower than the first power supply voltage, and in the present embodiment, the second power supply voltage is described as 1.0 V.

The logic chip 20 also has an input circuit 28 that uses the second power supply voltage as its operating voltage. The input circuit 28 receives the data signal SD2 sent from the memory chip 10 via the bump B3, which is the third external terminal, and outputs the data signal SD3 whose High level is the second power supply voltage to the internal circuit 22. When the memory chip 10 and the logic chip 20 are flip-chip connected, the bumps B1 and B2 are the same.

Further, the logic chip 20 has a bump B4 which is a fourth external terminal. Bump B4
Are connected to the power supply line Vdd2 and electrically connected to the bump B2 of the memory chip 10. That is, the logic chip 20 supplies the second power supply voltage to the memory chip 10 via the bumps B4 and B2. Specifically, the logic chip 20 includes the memory chip 10.
The second power supply voltage is supplied to the power supply voltage supply circuit 16.

  The operation of the memory chip 10 will be described in relation to the logic chip 20.

First, the power supply voltage supply circuit 16 is connected to the logic chip 20 through the bumps B2 and B4.
. Upon receiving the voltage supply of 0V, 1.0V is output to the output circuit 14.

The internal circuit 12 receives a voltage supply of 1.5 V from the power supply line Vdd1, and outputs a data signal SD1 having a high level of 1.5 V to the output circuit 14.

Then, the output circuit 12 is supplied with the power supply voltage of 1.0 V from the power supply voltage supply circuit 16, and based on the data signal SD1 input from the internal circuit 12, the data signal SD2 having a high level of 1.0 V, Output to the logic chip 20.

The input circuit 28 of the logic chip 20 receives the data signal SD2 from the memory chip 10. At this time, the high level of the data signal SD2 is its own operating voltage.
0V. Therefore, even if it is received by, for example, an inverter operating at 1.0 V, no malfunction or transistor breakdown occurs. Therefore, it is not necessary to separately provide an input buffer circuit that operates at a voltage (eg, 3.3 V) different from its own operating voltage in the logic chip 20, and the chip area can be reduced.

FIG. 2 shows a semiconductor device 200 according to the first embodiment of the present invention. 2, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

The output circuit 14 of the memory chip 10 includes two transistors Tr1 and Tr2 that are turned on and off complementarily. In this embodiment, the PMOS transistor Tr1 and NMO
This will be described with reference to the S transistor Tr2.

The output circuit 14 constitutes a 3-state buffer circuit by the transistors Tr1 and Tr2, the NAND 142, the NOR 144, and the inverter 146. However, the configuration of the output circuit 14 is not limited to the 3-state buffer circuit, and may be an inverter composed of transistors Tr1 and Tr2.

The power supply voltage supply circuit is an NMOS transistor Tr3. NMOS transistor Tr
3 is connected in series between the PMOS transistor Tr1 and the NMOS transistor Tr2. The gate electrode of the NMOS transistor Tr3 is connected via the bump B2.
A power supply voltage of 1.0 V that is the logic chip 20 is applied.

A node N1, which is a connection point between the source terminal of the NMOS transistor Tr3 and the drain terminal of the NMOS transistor Tr2, is an output terminal of the output circuit 14, and is connected to the bump B1.

The channel region of the NMOS transistor Tr3 is not doped with impurities, and the on-voltage is substantially 0V. Therefore, the NMOS transistor Tr3 functions as a circuit that clamps the voltage applied to the drain terminal and outputs the voltage applied to the gate electrode to the source terminal.

The transistors Tr1, Tr2 and Tr3 will be described in more detail. The back gate of the PMOS transistor Tr1 is connected to the power supply line Vdd1 and biased to 1.5V. The back gates of the NMOS transistors Tr2 and Tr3 are connected to the ground GND1 and biased to the ground potential.

  The operation of the output circuit 14 will be described.

The high level (1.5 V) from the internal circuit 12 is applied to the mode selection terminal MT of the output circuit 14
When the mode selection signal SM1 is input, the output circuit 14 enters the output mode, and the data terminal D
In response to the data signal SD1 input to T, a high or low data signal SD2 is output to the node N1. The data signal SD2 is transmitted to the input circuit 28 of the logic chip 20 via the bumps B1 and B3.

When the mode selection signal SM1 becomes Low, regardless of the logic input to the data terminal DT,
The output of the NAND 142 becomes High level, and the output of the NOR 144 becomes Low level. Accordingly, both the PMOS transistor Tr1 and the NMOS transistor Tr2 are turned off, and the node N1 becomes high impedance. In this state, the memory chip 10 is
A data signal is received by the input circuit 18 via the bump B1.

More specifically, the output circuit 14 is in the output mode and the data terminal DT is connected to H
When the high level is input, the outputs of the NAND 142 and the NOR 144 are at the low level. Therefore, the PMOS transistor Tr1 is turned on and the NMOS transistor Tr2 is turned off.

Accordingly, the drain terminal of the NMOS transistor Tr3 is connected to the PM line from the power supply line Vdd1.
The operating voltage of 1.5 V that is the memory chip 10 is applied via the OS transistor Tr1.

Here, a voltage of 1.0 V is supplied from the logic chip 20 to the gate electrode of the NMOS transistor Tr3 via the bump B2. Therefore, NMOS transistor T
A voltage of 1.0 V is output to the source terminal of r3, that is, the node N1. Therefore, the output circuit 14 can output a data signal whose high level is 1.0 V of the operating voltage of the logic chip 20.

On the other hand, when a low level is input to the data terminal DT in the output mode, the outputs of the NAND 142 and the NOR 144 are both at a high level, the PMOS transistor Tr1 is turned off, and the NMOS transistor Tr2 is turned on. Therefore, node N1 has NMO
A ground potential is applied via the S transistor Tr2, and the output circuit 14 outputs a low level.

As shown in this embodiment, one semiconductor chip (memory chip 10) that receives supply of the power supply voltage (1.0 V) of the other semiconductor chip from the other semiconductor chip (logic chip 20) also has a chip area. Miniaturization can be achieved. The reason is as follows. Traditionally,
The output of the internal circuit was received again by the output buffer circuit operating at 3.3 V different from its own operating voltage, and then output to the outside of the chip. Since the well for forming the 3.3 V operation output buffer circuit and the well for forming the internal circuit of 1.5 V operation need to be electrically separated from each other, each well is provided separately. There is a need. Further, in order to electrically isolate each well, a relatively large element isolation region (for example, STI)
Etc.) and the distance between the two wells needs to be relatively large. As a result, the area of the semiconductor chip has been increased. On the other hand, in this embodiment, the NMOS transistor Tr3, which is a power supply voltage supply circuit, is incorporated in an output buffer circuit (output circuit 14 in this embodiment) that operates at 1.5V, so that an output buffer that operates at 3.3V. There is no need to provide a separate circuit. 1
. The output buffer circuit for 5V operation can be formed in a well for forming an internal circuit. Even if a well for an output buffer for 1.5V operation is separately provided, a well for forming an internal circuit is provided. Therefore, it is not necessary to leave that much. Therefore, in the present invention, the semiconductor chip area can be reduced as compared with the conventional technique.

Next, a case where the memory chip 10 receives a data signal from the logic chip 20 will be described.

The internal circuit 22 of the logic chip 20 is connected to the power supply line Vdd2, operates at 1.0V, and outputs a data signal SD3 having a high level of 1.0V to the output circuit 24.

The output circuit 24 of the logic chip 20 is connected to the power supply line Vdd2 and operates at 1.0V, and outputs a data signal SD4 having a high level of 1.0V in response to the data signal SD3 input from the internal circuit 22. .

The data signal SD4 output from the output circuit 24 of the logic chip 20 is bumps B3 and B1.
To the input circuit 18 of the memory chip 10. That is, the bumps B1 and B3 are input / output external terminals.

The input circuit 18 of the memory chip 10 includes PMOS transistors Tr4 and Tr6 and NMOS
A flip-flop circuit 182 composed of transistors Tr5 and Tr7, and an inverter 1
84. The input circuit 18 outputs the voltage at the node N2 between the PMOS transistor Tr6 and the NMOS transistor Tr7 to the internal circuit 12 as the data signal SD5.

The flip-flop circuit 182 operates at 1.5V and outputs a data signal SD5 having a high level of 1.5V. On the other hand, the inverter 184 receives a voltage supply from the bump B2 and operates at 1.0V, and outputs the signal SD6 having a high level of 1.0V to the NMOS transistor Tr7. The operation of the input circuit 18 is input to the bump B1. When the data signal SD4 to be output is at a high level, 1.5 V that is a high level is output to the node N2. On the other hand, the data signal S
When D4 is at the low level, the node N2 outputs the low level.

By configuring the input circuit 18 of the memory chip 10 in this way, the signal SD4 having a high level of 1.0V can be converted into a signal having a high level of 1.5V without generating a static through current. I can do it.

  A semiconductor device 300 according to a second embodiment of the present invention will be described with reference to FIG.

This embodiment differs from the first embodiment in the connection position of the NMOS transistor Tr3 which is the power supply voltage supply circuit 12. The NMOS transistor Tr3 of the present embodiment has a power supply line Vd.
It is connected between d1 and the PMOS transistor Tr1. With this configuration, NMOS
1.5 V is applied to the drain terminal of the transistor Tr1, and 1.0 V, which is a voltage applied to the gate electrode, is output to the source terminal.

That is, the output circuit 14 is supplied with 1.0 V from the NMOS transistor Tr3,
A data signal SD2 having a high level of 1.0 V is output.

  Other parts of this embodiment are the same as those of the first embodiment.

  A semiconductor device 400 according to a third embodiment of the present invention will be described with reference to FIG.

In this embodiment, the source terminal of the PMOS transistor Tr1 of the output circuit 14 is connected to the wiring 16.
2 is directly connected to the bump B2. That is, the wiring 162 is the power supply voltage supply circuit 16.

With this configuration, the output circuit 14 is supplied with 1.0 V from the logic chip 20 via the bump B2 and the wiring 162, and the data signal SD2 whose High level is 1.0 V.
Is output.

(Contrast between the first embodiment and the third embodiment)
Compared with the first embodiment, the third embodiment has an advantage that the configuration is simple because it is not necessary to form the NMOS transistor Tr3. On the other hand, the first embodiment has an advantage that the circuit area can be reduced as compared with the third embodiment. The reason will be described with reference to FIG.

FIG. 5A is a partial cross-sectional view of a semiconductor device 400 according to the third embodiment. As shown in the circuit diagram of FIG. 4, the back gate of the PMOS transistor Tr1 constituting the output circuit 14 is connected to the bump B2 and biased to 1.0V. On the other hand, for example, NAND142
Further, the back gate of the PMOS transistor Tr12 constituting the NOR 144 is biased to 1.5V.

Therefore, as shown in FIG. 5A, an N well Nw1 in which a PMOS transistor Tr1 is formed, and an N well Nw2 in which a PMOS transistor Tr12 that constitutes, for example, a NAND 142 or a NOR 144 is formed. Must be electrically separated. In order to electrically isolate the N wells Nw1 and Nw2 having different potentials, for example, ST
It is necessary to provide I (Shallow Trench Isolation) 30.

  On the other hand, FIG. 5B shows a partial cross-sectional view of the semiconductor device 200 according to the first embodiment.

As shown in the circuit diagram of FIG. 2, the back gate of the PMOS transistor Tr1 is connected to the power supply line Vd.
Connected to d1 and biased to 1.5V. Accordingly, as shown in FIG. 5A, for example, the PMOS transistor Tr12 and the PMO constituting the NAND 142 or the NOR 144 are arranged.
The S transistor Tr1 can be formed in the same N well Nw3. Therefore,
There is no need to form an STI for electrically separating N wells having different potentials.

In the output circuit 14 of the first embodiment, it is necessary to form one NMOS transistor Tr3 more than the output circuit of the third embodiment, but in general, the area of one MOS transistor is more potential. Are smaller than the STI area for separating N wells Nw1 and Nw2 having different sizes. Therefore, the circuit area of the semiconductor device according to the first embodiment can be made smaller than that of the semiconductor device according to the third embodiment.

The present invention is not limited to the above-described embodiments, and appropriate modifications and changes can be made so as not to depart from the spirit of the invention.

DESCRIPTION OF SYMBOLS 10 Memory chip 12 Internal circuit of memory chip 14 Output circuit of memory chip 16 Power supply voltage supply circuit of memory chip 18 Input circuit of memory chip 20 Logic chip 22 Internal circuit of logic chip 24 Output circuit of logic chip 28 Input circuit of logic chip 30 STI
SD1, SD2, SD3, SD4, SD5, SD6 Data signal SV Voltage signal Vdd1 Power supply line Vdd2 for supplying the first power supply voltage (1.5V) Power supply lines B1, B2, for supplying the second power supply voltage (1.0V) B3, B4 Bump GND1, GND2 Power line Tr MOS transistor for supplying ground potential

Claims (4)

A first semiconductor chip operating at a first power supply voltage;
A second semiconductor chip that operates at a second power supply voltage lower than the first power supply voltage and supplies the second power supply voltage to the first semiconductor chip;
With
The first semiconductor chip is
An output circuit for outputting a signal to the second semiconductor chip;
A voltage supply circuit that receives the second power supply voltage from the second semiconductor chip and supplies the second power supply voltage to the output circuit;
Have
The voltage supply circuit is a circuit that receives the first power supply voltage and outputs the second power supply voltage;
A semiconductor device characterized by the above. The voltage supply circuit includes:
A MOSFET connected between the power supply line for supplying the first power supply voltage and the output circuit, wherein the second power supply voltage is input to the gate of the MOSFET;
The semiconductor device according to claim 1 . The output circuit is
Having first and second transistors that are switched on and off in a complementary manner,
The voltage supply circuit includes:
Being connected between the first transistor and the second transistor;
The semiconductor device according to claim 1 . The voltage supply circuit is a MOSFET, and the second power supply voltage is input to a gate of the MOSFET;
The semiconductor device according to claim 3 .

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