JPH09129745A - Semiconductor device - Google Patents

Abstract

(57) 【Abstract】 PROBLEM TO BE SOLVED: An input high level maximum value V of an input buffer IB.
IHmax is increased to enhance system flexibility of a memory integrated circuit or the like. A high-level output P-channel MOSFET P3 and a data input / output terminal DIO provided between a power supply voltage VCC and a data input / output terminal DIO, for example.
And a ground potential VSS, and a PN type output buffer OB including a low level output N channel MOSFET N3, and its input terminal is the data input / output terminal DIO.
In the memory integrated circuit or the like including the input buffer IB commonly coupled to the high potential power supply voltage VCH whose absolute value is larger than the power supply voltage VCC in the well region of the high level output P-channel MOSFET P3 of the output buffer OB. Supply. As a result, the cathode potential of the junction diode parasitic between the well region and drain of the high-level output P-channel MOSFET P3 is increased, and the ON voltage seen from the data input / output terminal is increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, for example, a memory integrated circuit such as a dynamic RAM (random access memory) having a CMOS (complementary MOS) circuit as a basic element and its output buffer. Regarding effective technology.

[0002]

2. Description of the Related Art P-channel and N-channel MOSF
There is a so-called CMOS circuit in which ET (metal oxide semiconductor type field effect transistor. In this specification, MOSFET is used as a general term for an insulated gate field effect transistor), there is a so-called CMOS circuit, and such a CMOS circuit is a basic element. There is a memory integrated circuit such as a dynamic RAM. The memory integrated circuit captures write data supplied from an external device through a data input terminal and transmits the write data to the write circuit, and data read from a designated address through an external device through a data output terminal. And an output buffer for outputting to. In recent years, memory integrated circuits tend to have so-called multi-bits, and the data input terminal and the data output terminal are often shared as a data input / output terminal in order to reduce the number of external terminals.

[0003]

In the conventional memory integrated circuit, the output buffer is often a so-called tri-state type buffer, and is used for high level output provided between the power supply voltage of the circuit and the data output terminal. MOSF
ET, and a low-level output MOSFET provided between the data output terminal and the ground potential of the circuit. The output buffer is a so-called NN type buffer, and the MOSFETs for high level output and low level output that compose it are both N channel type MOSFETs. As is well known, in the NN type buffer, the output signal level at the time of high level output is lowered by the threshold voltage of the N channel MOSFET for high level output.
Level correction measures such as adding a circuit for output boosting are required.

On the other hand, the recent increase in the scale and capacity of memory integrated circuits is remarkable, and along with this, the miniaturization and high integration of elements are being advanced. This causes a decrease in the breakdown voltage of the element and an increase in power consumption of the memory integrated circuit. As one method for dealing with this, there is a reduction in the power supply voltage and a CMOS circuit including the output buffer. Considered an effective means. As described above, in the NN type buffer, there is a problem that the output high level is lowered due to the threshold voltage of the high level output MOSFET. From that point, the CMOS implementation of the output buffer is an effective means.

However, in the memory integrated circuit in which the data input terminal and the data output terminal are commonly used as the data input / output terminal, the input terminal of the input buffer and the output terminal of the output buffer are commonly coupled to each other. The input characteristics are affected by the circuit configuration of the output buffer, and the following problem particularly occurs in the input high level maximum value VIHmax. That is, in a CMOS, that is, in a so-called PN type buffer in which a high-level output MOSFET is a P-channel MOSFET, a P-type diffusion layer which becomes a drain of a high-level output P-channel MOSFET coupled to a data input / output terminal and its N A so-called PN junction diode is parasitic between the well region and the N well region, which is generally coupled to the source potential of the P-channel MOSFET, that is, the power supply voltage of the circuit. Therefore, the maximum input high level of the input buffer, which can be set to a relatively large value in the NN type buffer, is limited to a potential higher than the power supply voltage of the circuit by the threshold voltage of the high level output MOSFET. This reduces the system flexibility of the memory integrated circuit.

An object of the present invention is to increase the input high level maximum value of an input buffer whose input terminal is commonly coupled to the output terminal of a PN type buffer so that a system such as a memory integrated circuit including a PN type output buffer. To increase flexibility.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0008]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, for example, a PN including a high-level output P-channel MOSFET provided between the power supply voltage of the circuit and the data input / output terminal and a low-level output N-channel MOSFET provided between the data input / output terminal and the ground potential of the circuit. Type output buffer and an input buffer whose input terminal is commonly coupled to the data input / output terminal. In a memory integrated circuit, etc., a high-level output P channel MOSFE of the output buffer is provided.
A high-potential power supply voltage whose absolute value is larger than the power supply voltage of the circuit is supplied to the T well region as the substrate voltage.

According to the above means, the cathode potential of the junction diode parasitic between the well region and the drain of the high level output P-channel MOSFET forming the output buffer is increased, and the ON voltage seen from the data input / output terminal is increased. Thus, the maximum value of the input high level of the input buffer can be increased. As a result, it is possible to enhance the system flexibility of a memory integrated circuit including an input buffer and an output buffer while taking advantage of the fact that the output buffer is formed into a CMOS.

[0010]

FIG. 1 is a circuit diagram of an embodiment of an input buffer IB and an output buffer OB included in a memory integrated circuit to which the present invention is applied. Also,
FIG. 2 shows a partial cross-sectional structure diagram of an embodiment of the output buffer OB of FIG. 1, and FIG. 3 shows an input buffer IB of FIG.
An input characteristic diagram of one embodiment is shown. On the other hand, FIG. 4 shows an example of a circuit diagram of the input buffer IB and the output buffer OB included in the memory integrated circuit developed by the inventors of the present application prior to the present invention. Also, in FIG.
An example of a partial sectional structure diagram of the output buffer OB of FIG. 4 is shown, and an example of an input characteristic diagram of the input buffer IB of FIG. 4 is shown in FIG. Based on these figures, the configuration and operation of the memory integrated circuit of this embodiment and its input buffer IB and output buffer OB and its features will be described. Note that each circuit element in FIG. 1 is formed on one semiconductor substrate such as single crystal silicon by a known CMOS integrated circuit manufacturing technique together with other circuit elements (not shown) of a memory integrated circuit. Further, in the following circuit diagrams, the MOSFET whose channel (back gate) portion is provided with an arrow is a P-channel type (first conductivity type) and is an N-channel type (second conductivity type) without an arrow. It is shown separately from the MOSFET.

In FIG. 1, the memory integrated circuit (semiconductor device) of this embodiment has an input buffer IB whose input terminal is coupled to a predetermined external terminal, that is, a data input / output terminal DIO, and its output terminal which is used for inputting the data. An output buffer OB commonly connected to the output terminal DIO. The memory integrated circuit has a so-called multi-bit configuration and includes a plurality of other data input / output terminals DIO, an input buffer IB, and an output buffer OB (not shown). Hereinafter, the present invention will be described in detail by taking one input buffer IB and one output buffer OB shown in FIG. 1 as an example.

The input buffer IB of the memory integrated circuit is not particularly limited, but two P-channel MOSFETs P1 provided in series between the circuit power supply voltage VCC (first power supply voltage) and the data input / output terminal DIO. And P2
And the data input / output terminal DIO and the ground potential VS of the circuit
And an N-channel MOSFET N1 provided between S and S. Although the power supply voltage VCC is not particularly limited, it is a power supply voltage of a positive potential such as + 5V (volt), and the ground potential VSS is 0V.

MOSFET constituting the input buffer IB
The gate of P1 has an input control signal DICB from a timing generation circuit (not shown) of the memory integrated circuit (here, a so-called inverted signal which is selectively brought to a low level when it is valid is added to the end of its name). The gates of the MOSFETs P2 and N1 are commonly connected to the input terminal of the input buffer IB, that is, the data input / output terminal DIO. Also, MOS
The drains of the FETs P2 and N1 are commonly coupled to the input terminal of the inverter V1 and the gates thereof receive the N-channel MOSFET N2 which receives the input control signal DICB.
Is coupled to the ground potential VSS via. Inverter V1
Is supplied to the write amplifier in the subsequent stage (not shown) as write data WD. Part of that is MOSF
The N-well regions that are the channel parts of ETP1 and P2 are coupled to the power supply voltage VCC, and MOSFETs N1 and N2 are connected.
The P-well region serving as the channel portion of is connected to the ground potential VSS.

As a result, the input buffer IB receives the low level of the input control signal DICB and is brought into a selective transmission state, takes in the input data supplied from the external device via the data input / output terminal DIO, and writes the write data WD.
As a result, it is transmitted to the write amplifier in the subsequent stage. When the input control signal DICB is set to the high level, the MOSFET N2 is turned on in the input buffer IB, and the write data WD is fixed to the high level regardless of the logical level of the input data.

Next, the output buffer OB is not particularly limited, but a high level output P channel MOSF provided between the power supply voltage VCC and the data input / output terminal DIO.
ETP3, data input / output terminal DIO and ground potential VSS
N channel MO for low level output provided between
Includes SFETN3. Of these, the output signal of the NAND gate NA1 is supplied to the gate of the MOSFET P3, and the NOR (N
OR) The output signal of the gate NO1 is supplied. Further, a predetermined high potential power supply voltage VCH is supplied to the N-well region, a part of which serves as the channel portion of the MOSFET P3, and M
The ground potential VSS is supplied to the P-well region that serves as the channel portion of the OSFET N3. High level output MOS
Between the gate and the drain of the FET P3, a diode-coupled P-channel MOSFET P4 is provided in parallel so that the data input / output terminal DIO side serves as an anode. The high-potential power supply voltage VCH is a positive potential such as + 7V having an absolute value larger than that of the power supply voltage VCC. The MOSFET P4 is a high-level output MOSFE.
It is designed to have a sufficiently small threshold voltage as compared with TP3.

Read data RD from a read amplifier in the preceding stage (not shown) is supplied to one input terminal of the NAND gate NA1 and the NOR gate NO1 which form the output buffer OB.
Is supplied. Further, the other input terminal of the NOR gate NO1 is supplied with an output control signal DOCB from a timing generating circuit (not shown), and the other input terminal of the NAND gate NA1 is supplied with an inverted signal from the inverter V2.

As a result, the output buffer OB receives the low level of the output control signal DOCB to be selectively brought into the transmission state, and the read data R supplied from the read amplifier.
A high-level or low-level output signal according to D is output from the data input / output terminal DIO to an external device. That is, when the output control signal DOCB is set to the low level and the read data RD is set to the low level, the output signals of the NAND gate NA1 and the NOR gate NO1 are both set to the high level in the output buffer OB. Therefore, the low level output MOSFET N3 is turned on, the high level output MOSFET P3 is turned off, and a low level such as the ground potential VSS is output to the data input / output terminal DIO through the MOSFET N3. On the other hand, when the output control signal DOCB is set to the low level and the read data RD is set to the high level, the output signals of the NAND gate NA1 and the NOR gate NO1 are both set to the low level in the output buffer OB. Therefore, the low-level output MOSFET N3 is turned off, the high-level output MOSFET P3 is turned on instead, and a high level such as the power supply voltage VSS is output to the data input / output terminal DIO via the MOSFET P3. Needless to say, at this time, the high level at the data input / output terminal DIO is raised to the power supply voltage VCC without being affected by the threshold voltage of the MOSFET P3, and the level does not drop.

When the output control signal DOCB is set to the high level, the output gate OB has a NAND gate NA.
The output signal of 1 is set to high level, and the output signal of the NOR gate NO1 is set to low level. Therefore, the high-level output MOSFET P3 and the low-level output MOSF
Both ETN3 are turned off and the data input / output terminal D
IO is in a so-called high impedance state.

By the way, the high level output P-channel MOSFET P3 constituting the output buffer OB is shown in FIG.
As shown in, the pair of P type diffusion layers p ⁺ formed in the N well region NWELL of the P type semiconductor substrate PSUB are used as the source and drain thereof. Of these, MOSFE
The left P-type diffusion layer p ^{+ serving as} the source of TP3 is coupled to the power supply voltage VCC, and the right P-type diffusion layer p ^{+ serving} as the drain thereof is coupled to the data input / output terminal DIO, that is, the bonding pad PAD. A high potential power supply voltage VCH higher than the power supply voltage VCC by 2V is supplied as a substrate voltage to the N well region NWELL via the N type diffusion layer n ⁺ .
In addition, between the two P type diffusion layers p ⁺ , that is, the N well region N
A polysilicon layer serving as a gate is formed on a layer serving as a channel of the MOSFET P3 of the WELL, with a predetermined insulating film interposed therebetween.

Similarly, the low-level output N-channel MOSFET N3 constituting the output buffer OB has a pair of N-type diffusion layers n ⁺ formed in the P-well region PWELL of the P-type semiconductor substrate PSUB as its source and drain. . Of these, the right N-type diffusion layer n ^{+ serving as} the source of the MOSFET N3 is coupled to the ground potential VSS, and the left N-type diffusion layer n ^{+ serving} as the drain thereof is commonly coupled to the bonding pad PAD. P well region PWEL
The ground potential VSS is supplied to L as a substrate voltage via the P-type diffusion layer p ⁺ . In addition, between the two N-type diffusion layers n ⁺ , that is, in the upper layer of the P well region PWELL which becomes the channel of the MOSFET N3, a polysilicon layer serving as a gate is formed with a predetermined insulating film interposed therebetween.

As is well known, at the junction between the P-type diffusion layer p ⁺ which becomes the drain of the MOSFET P3 and the N well region NWELL, as shown by the dotted line, the P-type diffusion layer p ^+.
Exists as an anode, and this parasitic diode affects the input characteristics of the input buffer IB whose input terminal is commonly coupled to the bonding pad PAD, that is, the data input / output terminal DIO. That is, the input high level maximum value VIHmax of the input buffer IB viewed from the data input / output terminal DIO is the N well region NWEL.
When the potential of the substrate voltage at L is Vnw and the forward voltage of the parasitic diode is Vdf, there is a constraint by the value of VIHmax ≦ Vnw + Vdf.

Therefore, as shown in FIG. 4 and FIG. 5, for example, the MOSFET P which constitutes the output buffer OB is formed.
In the case of the conventional memory integrated circuit in which the power supply voltage VCC is supplied as the substrate voltage to the N well region NWELL of FIG.
, The input high level maximum value VIHmax of the input buffer IB is higher than the power supply voltage VCC by the forward voltage Vdf of the parasitic diode, for example, 5.5V to 6V.
Limited to a certain degree, the system flexibility of the memory integrated circuit is reduced as compared with the case of using the NN type buffer. However, when the high-potential power supply voltage VCH higher than the power supply voltage VCC by about 2 V is supplied to the N well region NWELL of the MOSFET P3 as in the present embodiment, as shown in FIG. 3, the input high level maximum of the input buffer IB is increased. Value VIHm
ax is higher than the high-potential power supply voltage VCH by the forward voltage Vdf of the parasitic diode, for example, 7.5V to 8V.
The value is as large as V. As a result, the output buffer OB
It is possible to enhance the system flexibility as a memory integrated circuit while taking advantage of the fact that it is made into a CMOS. In other words, in the input buffer IB of this embodiment, 7.5V to 8V is applied to the data input / output terminal DIO.
Even when a surge voltage having a relatively large absolute value is applied, the current flowing from the data input / output terminal DIO to the substrate portion of the high-level output MOSFET P3, that is, the N-well region is suppressed to prevent the latch-up of the MOSFET P3 and the like. It will be possible.

The MOSFET P4 is selectively turned on when a voltage close to the input high level maximum value VIHmax is input to the data input / output terminal DIO to prevent the high level output MOSFET P3 from being turned on. To work. As mentioned above, MOSFET P4 is
It has a threshold voltage sufficiently smaller than that of the high-level output MOSFET P3. Therefore, the high-level output MOSFET P3 remains in the off state even when a voltage close to the input high-level maximum value VIHmax is applied to the data input / output terminal DIO, whereby the data input / output terminal DIO moves to the power supply voltage VCC side. The current that flows can be suppressed.

The operational effects obtained from the above embodiments are as follows. That is, (1) For example, a high-level output P-channel MOSFE provided between the power supply voltage of the circuit and the data input / output terminal.
Low-level output N-channel MOSFET provided between T and data input / output terminals and circuit ground potential
In a memory integrated circuit or the like having a PN type output buffer including an input buffer and an input buffer whose input terminal is commonly coupled to the data input / output terminal, in the well region of the high level output P-channel MOSFET of the output buffer,
By supplying a high-potential power supply voltage whose absolute value is larger than the power supply voltage of the circuit as the substrate voltage, the cathode-side potential of the junction diode parasitic between the well region and the drain of the high-level output P-channel MOSFET forming the output buffer. And the ON voltage seen from the data input / output terminal can be increased. (2) According to the above item (1), it is possible to correspondingly increase the maximum value of the input high level of the input buffer. (3) According to the above item (1), even if a surge voltage close to the input high level maximum value is input to the data input / output terminal, the high level output MOSFE is output from the data input / output terminal.
The electric current that flows into the substrate portion of T can be suppressed, and by this
The effect that the latch-up of the OSFET P3 and the like can be prevented is obtained. (4) According to the above items (1) to (3), it is possible to enhance the system flexibility of a memory integrated circuit including an input buffer and an output buffer while taking advantage of the fact that the output buffer is formed into a CMOS. The effect is obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the input buffer IB and the output buffer OB can include a predetermined protection element. In addition, MOSFETs P3 and N3 forming the output buffer OB
Can be replaced by multiple P-channel or N-channel MOSFETs coupled in parallel. The specific circuit configurations of the input buffer IB and the output buffer OB can take various embodiments as long as the basic logical conditions thereof do not change. In FIG. 2, the device structure of each element constituting the output buffer OB is not restricted by this embodiment, and the arrangement and size thereof are also the same. The memory integrated circuit can have a so-called triple well structure. In this case, MOSFET N3
By setting the potential of the substrate voltage supplied to the P well region PWELL in which is formed to be a negative potential lower than the ground potential VSS, the minimum value of the input low level of the input buffer IB can be expanded. Further, when the polarity of the power supply voltage is inverted, the power supply voltage VCC is set to 0V, and the ground potential VSS is set to a negative potential, for example, the N channel MO of the output buffer OB.
The same effect can be obtained by making the absolute value of the substrate voltage supplied to the P well region PWELL of the SFET N3 larger than the power supply voltage.

In the above description, the case where the invention made by the present inventor is mainly applied to the memory integrated circuit and its output buffer, which are the fields of application as the background, has been described, but the invention is not limited thereto. For example, the present invention can be applied to various semiconductor devices including independently formed input buffers and output buffers and similar input buffers and output buffers. INDUSTRIAL APPLICABILITY The present invention can be widely applied to a semiconductor device including at least an external terminal commonly used as an input / output terminal and an input buffer and an output buffer having an input terminal and an output terminal commonly coupled to the external terminal.

[0027]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, for example, a high-level output P provided between the power supply voltage of the circuit and the data input / output terminal.
A PN type output buffer including a channel MOSFET, a data input / output terminal and an N channel MOSFET for low level output provided between the circuit ground potential and an input buffer whose input terminal is commonly coupled to the data input / output terminal. In a memory integrated circuit or the like provided therein, a high-level power supply voltage whose absolute value is larger than the power supply voltage of the circuit is supplied to the well region of the P-channel MOSFET for high-level output of the output buffer, thereby forming a high level The cathode potential of the junction diode parasitic between the drain and well regions of the output P-channel MOSFET can be increased and the ON voltage seen from the data input / output terminal thereof can be increased to increase the maximum input high level value of the input buffer. . As a result, the output buffer is CMO
The system flexibility of the memory integrated circuit and the like can be enhanced while making the most of the advantage of being S-type.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of an input buffer and an output buffer included in a memory integrated circuit to which the present invention is applied.

FIG. 2 is a partial sectional structural view showing one embodiment of the output buffer of FIG. 1;

FIG. 3 is an input characteristic diagram showing an embodiment of the input buffer of FIG.

FIG. 4 is a circuit diagram showing an example of an input buffer and an output buffer included in a memory integrated circuit developed by the inventors of the present application prior to the present invention.

5 is a partial cross-sectional structural view showing an example of the output buffer of FIG.

FIG. 6 is an input characteristic diagram showing an example of the input buffer of FIG.

[Explanation of symbols]

IB ... input buffer, OB ... output buffer, DIO
...... Data input / output terminal (external terminal), DIC ... Input control signal, DOC ... Output control signal, WD ... Write data, RD ... Read data, VCH ... High potential power supply voltage, VCC ... Power supply voltage , VSS ... Ground potential, P1
~ P4 ... P-channel MOSFET, N1-N3 ...
N-channel MOSFET, V1 to V2 ... Inverter, NA1 ... NAND gate, NO1 ...
NOR gate. PSUB ... P-type semiconductor substrate,
PWELL ... P well region, NWELL ... N well region, P ⁺ ... P type diffusion layer, N ⁺ ... N type diffusion layer, PA
D: Bonding pad (data input / output terminal), IB
…… Input buffer. VIHmax ... input high level maximum value, VIHmin ... input high level minimum value, VIL
max: Maximum input low level value, VILmin: Minimum input low level value.

Continued Front Page (72) Inventor Satoshi Udagawa 2326 Imai, Ome City, Tokyo Inside Hitachi Device Development Center

Claims (3)

[Claims] 1. An output terminal is coupled to a predetermined external terminal and is provided between a first power supply voltage and the external terminal, and has a well region having a predetermined absolute value larger than that of the first power supply voltage. A semiconductor device comprising: an output buffer including a MOSFET of the first conductivity type supplied with a high-potential power supply voltage; and an input buffer having an input terminal commonly coupled to the external terminal. 2. The output buffer is a second conductivity type MOSF provided between the external terminal and a second power supply voltage.
2. The semiconductor device according to claim 1, wherein the semiconductor device is a tri-state type output buffer including ET. 3. The semiconductor device according to claim 1, wherein the semiconductor device is a memory integrated circuit having a CMOS circuit as a basic element.