JP5187148B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device in which a semiconductor chip is mounted on a mounting substrate and fixed with an adhesive, and a manufacturing method thereof.

  Conventionally, when a semiconductor chip is mounted on a mounting substrate, electrodes on the mounting substrate and electrodes on the semiconductor chip are mechanically and electrically connected by metal bumps made of metal such as solder.

  As the degree of integration of the semiconductor chip improves and the electrodes become finer, the current density flowing through the metal bumps increases. For this reason, the metal atoms constituting the metal bump are easily moved by electromigration. The movement of metal atoms causes the disconnection of the bump.

  Furthermore, the temperature of the semiconductor chip and the mounting substrate becomes high during the solder fusion bonding. When the semiconductor chip and the mounting substrate are lowered to room temperature after mounting, stress is generated due to the difference in thermal expansion coefficient between them. Usually, the thermal expansion coefficient of the mounting substrate is 10 times or more that of the semiconductor chip. At this time, when the semiconductor chip and the mounting substrate are lowered to room temperature, the mounting substrate is further contracted. Thereby, a compressive stress in the in-plane direction is applied to the semiconductor chip. When stress is generated, fracture occurs in the mechanically weakest part. For example, metal bumps, low dielectric constant insulating materials of semiconductor chips, etc. are destroyed. A similar stress is also generated by a temperature change during operation after mounting.

  A technique for electrically connecting a contact of a mounting substrate and a contact of a semiconductor chip using carbon nanotubes is known (Patent Document 1). When carbon nanotubes are used, disconnection due to electromigration is less likely to occur than when metals are used. Due to the elasticity of the carbon nanotube, concentration of stress can be suppressed and mechanical destruction can be prevented.

JP 2007-311700 A

  Generally, after mounting a semiconductor chip on a mounting substrate, a sealing agent called underfill is poured into a gap between the two using a capillary flow (capillary flow) to fix the semiconductor chip to the mounting substrate. . If the sealing agent is cured while the connecting member having elasticity such as a carbon nanotube is wet with the sealing agent, the elasticity expected for the connecting member is impaired.

A semiconductor device for solving the above problems is as follows.
A mounting substrate having a plurality of electrodes formed on the mounting surface;
A semiconductor chip that is opposed to the mounting substrate with a gap, and an electrode is formed at a position corresponding to the electrode on the mounting substrate;
Electrically connecting the electrodes of the mounting substrate and the corresponding electrodes of the semiconductor chip , and a connecting member having elasticity ;
A spacer that is disposed between the mounting substrate and the semiconductor chip, secures a gap between the mounting substrate and the semiconductor chip, and surrounds an area in which the electrodes of the mounting substrate and the semiconductor chip are distributed in plan view. When,
The semiconductor is disposed outside a cavity surrounded by the spacer, the mounting substrate, and the semiconductor chip, and is in close contact with the first region on the surface of the semiconductor chip and the second region on the surface of the mounting substrate. A chip is fixed to the mounting substrate, and an adhesive having an affinity for the spacer is lower than both the affinity for the first region of the semiconductor chip and the affinity for the second region of the mounting substrate. Have.

A method of manufacturing a semiconductor device for solving the above problems is as follows.
Disposing a spacer having a planar shape surrounding a region where the electrodes are distributed on the mounting surface of the mounting substrate on which a plurality of electrodes are formed on the mounting surface;
A semiconductor chip is disposed on the mounting substrate via the spacer, and a plurality of electrodes formed on the surface of the semiconductor chip are respectively formed on a plurality of electrodes formed on the mounting surface of the mounting substrate . Electrically connecting the elastic connecting member ;
Outside the cavity surrounded by the spacer, the mounting substrate, and the semiconductor chip, the spacer is continuous with the spacer from the first region on the surface of the semiconductor chip to the second region on the surface of the mounting substrate. Applying an adhesive whose affinity is lower than both the affinity of the semiconductor chip for the first region and the affinity of the mounting substrate for the second region;
Curing the applied adhesive.

  Since the affinity between the adhesive and the spacer is low, it is difficult to enter the cavity surrounded by the mounting substrate, the semiconductor chip, and the spacer.

  Before describing the embodiments, an example of a method for fixing a semiconductor chip to a mounting substrate with an adhesive will be described.

  As shown in FIG. 4A, the mounting substrate 10 and the semiconductor chip 50 are arranged to face each other. Between the two, a frame-shaped spacer 20 is disposed along the outer peripheral line of the semiconductor chip 50. The spacer 20 is fixed to the mounting substrate 10 with an adhesive. The semiconductor chip 50 is fixed to the spacer 20 with an adhesive 30. The adhesive 30 is applied along the outer periphery of the semiconductor chip 50 with the surface near the outer periphery of the semiconductor chip 50 being in contact with the upper surface of the spacer 20. The electrodes of the semiconductor chip 50 and the electrodes of the mounting substrate 10 are electrically connected to each other by the carbon nanotubes 55.

  As illustrated in FIG. 4B, a gap 56 may be generated between the semiconductor chip 50 and the spacer 20 in a part of the outer periphery of the semiconductor chip 50 due to variations in the length of the carbon nanotubes 55. When the gap 56 is generated, the adhesive 30 enters the space between the mounting substrate 10 and the semiconductor chip 50 due to a capillary phenomenon when the adhesive 30 is applied. The adhesive 30 a that has entered the space is cured while being in contact with the carbon nanotube 55, and the elasticity of the carbon nanotube 55 is impaired.

  With reference to FIGS. 1A to 1E, a method of manufacturing a semiconductor device according to the first embodiment will be described.

  As shown in FIG. 1A, the mounting substrate 10 and the semiconductor chip 50 are arranged with the mounting surface of the mounting substrate 10 and the element formation surface of the semiconductor chip 50 facing each other. A plurality of electrodes 22 are formed on the mounting surface of the mounting substrate 10. The mounting board 10 is a printed wiring board on which a plurality of wiring layers are formed, for example. A region where the electrode 22 is not formed on the mounting surface of the mounting substrate 10 is covered with, for example, a solder resist 23. Spacers 21 are disposed on the mounting surface of the mounting substrate 10. The spacer 21 has a planar shape and dimensions along the outer peripheral line of the semiconductor chip 50. The spacer 21 is made of nonpolar resin such as paraffin. As the paraffin, it is necessary to use a paraffin having a melting point higher than the heating temperature in the subsequent step of curing the adhesive. For example, tetrachloronaphthalene having a melting point of 198 ° C. or hexachloronaphthalene having a melting point of 194 ° C. can be used. In addition to paraffin, polytetrafluoroethylene (PTFE) or the like can be used.

  A plurality of electrodes 51 are formed on the element formation surface of the semiconductor chip 50. The plurality of electrodes 51 are respectively arranged at positions corresponding to the electrodes 22 formed on the mounting surface of the mounting substrate 10. Of the element formation surface of the semiconductor chip 50, a region where the electrode 51 is not formed is covered with an insulating protective film 52. For the protective film 52, silicon oxide, silicon nitride, or the like is used.

  A plurality of carbon nanotubes 55 extend from each of the electrodes 51. A method of forming the carbon nanotube 55 is described in, for example, Japanese Patent Application Laid-Open No. 2007-311700. Hereinafter, a method for forming the carbon nanotube 55 will be described.

  An aluminum (Al) film having a thickness of 5 nm and an iron (Fe) film having a thickness of 2 nm are sequentially formed on a growth substrate made of silicon. Carbon nanotubes are grown on this growth substrate by chemical vapor deposition (CVD). Acetylene gas is used as the process gas, and argon gas or hydrogen gas is used as the carrier gas. The growth pressure is 100 Pa and the growth temperature is 600 ° C. The length of the carbon nanotube can be controlled by the growth time. In Example 1, the length of the carbon nanotube is 100 μm.

  An adhesive containing conductive fine particles, for example, silver (Ag) paste is applied to the surface of the electrode 51 of the semiconductor chip 50. The tip of the carbon nanotube grown on the growth substrate is pressed against the surface of the electrode 51 of the semiconductor chip 50. In this state, the carbon nanotube is fixed to the electrode 51 by curing the adhesive containing conductive fine particles. Thereafter, the growth substrate is separated from the semiconductor chip 50. The carbon nanotubes fixed to the electrode 51 remain on the semiconductor chip 50 side, and the other carbon nanotubes are separated from the semiconductor chip 50 together with the growth substrate.

  FIG. 1B shows a plan view of the mounting substrate 10 and the spacer 21. A cross-sectional view taken along one-dot chain line 1A-1A in FIG. 1B corresponds to FIG. 1A. The spacer 21 has a frame-like planar shape with a width of 0.5 mm, and is positioned so as to surround a region where the electrodes 22 are distributed. When the planar shape of the semiconductor chip 50 is a square, the spacer 21 has a shape along a square outer peripheral line. The spacer 21 is bonded and fixed to the mounting substrate 10 with an adhesive.

  As shown in FIG. 1C, the electrode 51 of the semiconductor chip 50 is aligned with the corresponding electrode 22 of the mounting substrate 10, and the tip of the carbon nanotube 55 is brought into contact with the electrode 22. A load is applied to the semiconductor chip 50 to bring the region near the outer peripheral portion of the element formation surface into contact with the spacer 21. At this time, the height of the spacer 21 is selected so that the carbon nanotube 55 is curved within the range of elastic deformation. A cavity 60 surrounded by the semiconductor chip 50, the mounting substrate 10, and the spacer 21 is defined. The carbon nanotube 55 is accommodated in the cavity 60.

  As shown in FIG. 1D, the adhesive 35 is applied in a state where the semiconductor chip 50 is in contact with the spacer 21. The adhesive 35 includes a first region 50A on the back surface (a surface opposite to the element formation surface) in contact with the outer peripheral line of the semiconductor chip 50 and a second region outside the spacer 21 on the mounting surface of the mounting substrate 10. 10A, and is continuous from the first region 50A to the second region 10A. As the adhesive 35, an adhesive having a lower affinity for the spacer 21 than both the affinity for the first region 50 </ b> A of the semiconductor chip 50 and the affinity for the second region 10 </ b> A of the mounting substrate 10 is used. For example, an epoxy resin, a phenoxy resin, or a cyanate ester resin can be used as the adhesive 35.

  The adhesive 35 is cured by heating at 150 ° C. for 30 minutes. Thereby, the semiconductor chip 50 is fixed to the mounting substrate 10. The adhesive 35 is disposed outside the cavity 60 and does not enter the cavity 60.

  As shown in FIG. 1E, after the adhesive 35 is cured, the load is released. In order to evaluate the reliability of the semiconductor device, a temperature cycle test of 500 cycles was performed between -25 ° C and 125 ° C. As a result, the rate of increase in resistance between the electrode 51 of the semiconductor chip 50 and the electrode 22 of the mounting substrate 10 was 10% or less. Moreover, when it was left for 1000 hours in an environment of a temperature of 121 ° C. and a humidity of 85%, the rate of increase in resistance was 10% or less.

  FIG. 2 is a cross-sectional view of the semiconductor device when a gap 56 is partially formed between the semiconductor chip 50 and the spacer 21. A gap may occur between the semiconductor chip 50 and the spacer 21 due to variations in the length of the carbon nanotubes 55. Since the adhesive 35 has a low affinity for the spacer 21, the adhesive 35 does not enter the cavity 60 through the gap 56.

  Since the adhesive 35 does not enter the cavity 60, the elasticity of the carbon nanotube 55 can be maintained even after the semiconductor chip 50 is fixed to the mounting substrate 10.

  In the first embodiment, the spacer 21 is bonded to the mounting substrate 10 with an adhesive. Since the position of the spacer 21 is fixed when the semiconductor chip 50 is opposed to the mounting substrate 10 and a load is applied, the positioning of the semiconductor chip 50 can be facilitated. However, since the semiconductor chip 50 is bonded to the mounting substrate 10 by the adhesive 35, the spacer 21 does not necessarily have to be bonded to the mounting substrate 10. The spacer 21 does not have a function of fixing the semiconductor chip 50 to the mounting substrate 10, but has a function of securing a cavity 60 between the semiconductor chip 50 and the mounting substrate 10.

  In Example 1 described above, a nonpolar resin was used for the spacer 21 and an adhesive 35 having a low affinity with the spacer was used. A resin having polarity can be used as the adhesive 35 having low affinity with the nonpolar spacer 21. The nonpolar resin is used for the spacer 21 and the polar resin is used for the adhesive 35 because the first region 50A of the semiconductor chip 50 and the second region 10A of the mounting substrate 10 and the adhesive 35 are used. This is to increase the affinity.

  On the contrary, when the affinity of the nonpolar adhesive is high for the first region 50A of the semiconductor chip 50 and the second region 10A of the mounting substrate 10, a nonpolar resin is used for the adhesive 35. The spacer 21 may be made of a resin having polarity.

  In the first embodiment, the electrode 51 of the semiconductor chip 50 and the electrode 22 of the mounting substrate 10 are electrically connected by the carbon nanotubes 55, but may be connected using another connecting member. In order to prevent disconnection due to stress, it is preferable to use an elastic connection member.

  FIG. 3 is a plan view of the mounting substrate 10 and the spacer 21 according to the second embodiment. In the first embodiment, as shown in FIG. 1B, the spacer 21 has a closed frame shape in plan view. However, in the second embodiment, the spacer 21 is formed at the center of a pair of opposite sides of a square. At the corresponding position, it is separated into two parts. When the two portions constituting the spacer 21 are arranged on the mounting surface of the mounting substrate 10, both ends of the two portions may be brought into contact with each other, or the end surfaces at both ends are opposed to each other with a gap 21A therebetween. Also good. If the gap 21A is narrowed to such an extent that the adhesive 35 does not enter, the adhesive 35 enters the cavity 60 when the adhesive 35 is applied in the step shown in FIG. Can be prevented.

  When the spacer 21 is formed by punching a plate of paraffin or the like, if the spacer 21 is a closed frame shape as in the first embodiment, the square or rectangular portion inside the spacer 21 is wasted. If the spacer 21 is divided into two parts as in the second embodiment, a useless part is not generated, and a plate made of paraffin or the like can be used effectively.

  Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

(1A) and (1B) are respectively a cross-sectional view and a plan view of the device in the course of manufacturing the semiconductor device manufacturing method according to the embodiment. (1C) and (1D) are cross-sectional views of the device in the process of manufacturing the semiconductor device according to the first embodiment, and (1E) is a cross-sectional view of the semiconductor device according to the first embodiment. 6 is a cross-sectional view of a semiconductor device according to a modification of Example 1. FIG. 6 is a plan view of a mounting substrate and spacers of a semiconductor device according to Example 2. FIG. (4A) and (4B) are cross-sectional views of a semiconductor device according to a comparative example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Mounting substrate 10A 2nd area | region 20, 21 Spacer 21A Gap 22 Electrode 23 Solder resist 30, 35 Adhesive 50 Semiconductor chip 50A 1st area | region 51 Electrode 52 Protective film 55 Carbon nanotube (connection member)
56 Clearance 60 Cavity

Claims (5)

A mounting substrate having a plurality of electrodes formed on the mounting surface;
A semiconductor chip that is opposed to the mounting substrate with a gap, and an electrode is formed at a position corresponding to the electrode on the mounting substrate;
Electrically connecting the electrodes of the mounting substrate and the corresponding electrodes of the semiconductor chip , and a connecting member having elasticity ;
A spacer that is disposed between the mounting substrate and the semiconductor chip, secures a gap between the mounting substrate and the semiconductor chip, and surrounds an area in which the electrodes of the mounting substrate and the semiconductor chip are distributed in plan view. When,
The semiconductor is disposed outside a cavity surrounded by the spacer, the mounting substrate, and the semiconductor chip, and is in close contact with the first region on the surface of the semiconductor chip and the second region on the surface of the mounting substrate. A chip is fixed to the mounting substrate, and an adhesive having an affinity for the spacer is lower than both the affinity for the first region of the semiconductor chip and the affinity for the second region of the mounting substrate. A semiconductor device having the same.   The semiconductor device according to claim 1, wherein the spacer is formed of a nonpolar resin, and the adhesive includes a resin having polarity.   The semiconductor device according to claim 1, wherein the connection member is a carbon nanotube, the carbon nanotube is curved, and has a restoring force in a direction to widen a gap between the mounting substrate and the semiconductor chip. Disposing a spacer having a planar shape surrounding a region where the electrodes are distributed on the mounting surface of the mounting substrate on which a plurality of electrodes are formed on the mounting surface;
A semiconductor chip is disposed on the mounting substrate via the spacer, and a plurality of electrodes formed on the surface of the semiconductor chip are respectively formed on a plurality of electrodes formed on the mounting surface of the mounting substrate . Electrically connecting the elastic connecting member ;
Outside the cavity surrounded by the spacer, the mounting substrate, and the semiconductor chip, the spacer is continuous with the spacer from the first region on the surface of the semiconductor chip to the second region on the surface of the mounting substrate. Applying an adhesive whose affinity is lower than both the affinity of the semiconductor chip for the first region and the affinity of the mounting substrate for the second region;
And a step of curing the applied adhesive.   5. The electrode of the semiconductor chip is electrically connected to the electrode of the mounting substrate through a carbon nanotube in the step of electrically connecting the electrode of the semiconductor chip to the electrode of the mounting substrate. Semiconductor device manufacturing method.

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