JP5173160B2 - Multilayer wiring board and manufacturing method thereof - Google Patents

Description

  The present invention relates to a multilayer wiring board manufactured using a build-up method. This multilayer wiring board can be applied to manufacture of a package on which a semiconductor device or the like is mounted, or can be applied as an interposer used for mounting a semiconductor device or the like on a circuit board or the like.

  The build-up multilayer wiring board is formed by forming a via opening in the insulating layer on the core substrate, then forming the wiring layer by the semi-additive method, and then repeating the formation of the insulating layer and the wiring layer as many times as necessary. It is manufactured as a multilayer wiring board provided with a wiring layer. The insulating layer is formed of a build-up resin typified by an epoxy resin. Since the build-up resin contains a filler, the via opening is generally formed by laser processing.

  FIG. 6 schematically shows a conventional build-up multilayer wiring board manufactured by such a method. The build-up multilayer wiring board in this figure has five wiring layers 103a, 103b, 103c, 103d, and 103e formed on the core substrate 101 made of, for example, glass cloth epoxy resin, and between adjacent wiring layers. Interlayer insulating films 105ab, 105bc, 105cd, and 105de are located. Vias 107 that connect adjacent wiring layers are formed in each interlayer insulating film, while upper and lower wiring layers (in the wiring substrate of FIG. 6, the uppermost wiring layer 103e and the lowermost layer are formed through two or more insulating layers. A via 107 ′ for connecting the wiring layer 103a) is also formed. The latter type of via 107 ′ is known as a “stack via” and is used for the purpose of shortening the wiring path. The stacked via 107 ′ has a structure in which vias 107 ′ a, 107 ′ b, 107 ′ c, and 107 ′ d individually formed in the respective insulating layers 105 ab, 105 bc, 105 cd, and 105 de are connected via lands 109. Generally, the via 107 and the vias 107′a, 107′b, 107′c, and 107′d of each insulating layer constituting the stacked via 107 ′ are also formed in the openings formed by laser processing in the respective insulating layers made of resin. It is formed by filling the wiring material. A protective layer 111 is formed by solder resist on the uppermost wiring layer 103e, and a pad 113 used for mounting a semiconductor device (not shown) or the like is provided in the opening. On the opposite side of the core substrate 101 shown in FIG. 6, solder bumps connected to the through holes 115 of the core substrate 101 may be provided, or a build-up structure similar to that illustrated may be formed. .

It is also known to form an insulating layer of a build-up multilayer wiring board with an inorganic material such as SiO ₂ instead of a resin. For example, Patent Document 1 discloses a via hole formed by etching on an insulating substrate in which an SiO ₂ insulating film is formed on an aluminum plate by vacuum deposition, using a wiring layer and a vacuum deposited SiO ₂ film having a thickness of 10 μm. There is described a substrate having a multilayer wiring structure in which insulating layers having n are alternately formed. It is described that a via hole is formed every time each insulating layer is formed.

Japanese Patent Laid-Open No. 1-257397

  In the conventional build-up multilayer wiring board as shown in FIG. 6, the thermal stress caused by using different materials having different thermal expansion coefficients causes the vias 107′a and 107 ′ of the insulating layers constituting the stack via 107 ′. b, 107′c, 107′d are likely to concentrate on the root portion, and there is a risk of causing disconnection at that portion. The thermal stress increases as the via diameter increases and the via depth increases (the insulating layer becomes thicker). The insulating layer made of the current build-up resin needs to have a minimum thickness of 30 μm from the viewpoint of insulation and workability. The lower limit of the diameter of the opening that can be laser-processed in the resin insulating layer is about 30 to 40 μm. These hinder the avoidance of disconnection of the stack via and become a factor that hinders the high density of wiring and vias in the current build-up multilayer wiring board.

  Furthermore, the stack via 107 ′ of the conventional build-up multilayer wiring board is formed by connecting individual vias 107′a, 107′b, 107′c, 107′d of a plurality of insulating layers. Depending on the formation accuracy of these individual vias, there is a problem that connection failure may occur.

  The present invention aims to solve such a problem, and has a multilayer wiring board that has a highly reliable via that spans two or more insulating layers and that enables high density wiring and vias. It is something to be offered.

  The multilayer wiring board of the present invention has a plurality of wiring layers and an interlayer insulating film, and a type of connecting upper and lower wiring layers via two or more interlayer insulating films, and a via that connects adjacent wiring layers. A multilayer wiring board having a plurality of vias, wherein at least part of the interlayer insulating film is formed of an inorganic insulating film, and the upper and lower wiring layers are connected via two or more interlayer insulating films However, it is characterized in that it is formed as a single via penetrating an interlayer insulating film formed of any inorganic insulating film.

Preferably, all of the interlayer insulating film is made of an inorganic insulating film.
Preferably, the inorganic insulating film is formed by a low temperature CVD method.
Preferably, the thickness of the inorganic insulating film is 0.5 to 2.0 μm, more preferably 0.5 to 1.5 μm, and most preferably 0.5 to 1.0 μm.

  In the multilayer wiring board of the present invention, vias of the type in which the upper and lower wiring layers are connected via two or more inorganic insulating films are formed, and the two or more inorganic insulating films are formed and then simultaneously formed by photolithography. It can be manufactured by a method characterized by using an opening formed by processing.

  According to the present invention, since a thin interlayer insulating film can be used by using an inorganic insulating film excellent in pressure resistance, including a via of a type that connects upper and lower wiring layers through two or more interlayer insulating films, The depth of the via connecting the wirings of different layers can be made extremely small. As a result, the thermal stress applied to the via can be reduced, and the risk of poor connection due to disconnection of the via that connects the upper and lower wiring layers through two or more interlayer insulating films is minimized. A highly reliable multilayer wiring board can be provided. At the same time, it is possible to realize higher density of wiring and vias that could not be realized with a multilayer wiring board manufactured using a conventional build-up resin.

  In addition, the present invention can be applied to a substrate using a material having low heat resistance by forming the inorganic insulating film by low-temperature CVD, and is excellent in versatility.

  FIG. 1 is a partial schematic view of a multilayer wiring board according to the present invention. The multilayer wiring board in this figure has five wiring layers 13a, 13b, 13c, 13d, and 13e formed on the core substrate 11, and interlayer insulating films 15ab, 15bc, 15cd, and 15de are provided between adjacent wiring layers. Is located. Vias 17 of the type that connect adjacent wiring layers are formed in each interlayer insulating film, while the upper and lower wiring layers (one with the uppermost wiring layer 13e in the wiring substrate of FIG. 1) are formed through two or more insulating layers. A via 17 'of the type connecting the lowermost wiring layer 13a) is formed. As will be described later, the via 17 ′ is formed at a time by filling a wiring material into an opening that penetrates two or more interlayer insulating films interposed between upper and lower wirings to be connected. Therefore, the via 17 ′ differs from the prior art via 107 ′ described above with reference to FIG. 6 and has the same number of individual vias 107′a, 107′b, 107′c, 107′d as the number of interlayer insulating films. It is not necessary to connect (FIG. 6), nor is the land 109 (FIG. 6) required for that purpose. A protective layer 19 is formed by solder resist on the uppermost wiring layer 13e, and a pad 21 used for mounting a semiconductor device (not shown) or the like is provided in the opening. On the opposite side of the core substrate 11 shown in FIG. 1, there may be solder bumps (not shown) connected to the through holes 23 of the core substrate 11, or a build-up multilayer wiring structure similar to that shown in FIG. You may prepare.

  As the core substrate 11 of the multilayer wiring board of the present invention, for example, a resin substrate made of glass cloth epoxy resin or a silicon substrate can be used. When a conductive substrate such as a silicon substrate is used, an insulating surface is used.

  The wiring layers 13a to 13e and the two types of vias 17 and 17 'can be formed from a general wiring material such as Cu by a method generally used for forming a multilayer wiring. When the wiring layer is formed by sputtering or vapor deposition, the thickness of the wiring layer may be, for example, about 0.5 to 1 μm, and when a thick film is further formed thereon by plating, for example, 5 to 10 μm. Can do.

In the present invention, an inorganic material is used as the material of the interlayer insulating films 15ab, 15bc, 15cd, and 15de. Preferably, the interlayer insulating film made of an inorganic material is formed at a temperature of 200 ° C. or lower by a low temperature CVD method. An interlayer insulating film formed from a build-up resin used in a conventional multilayer wiring board needs a thickness of 30 μm or more because of the necessity for insulation and workability. On the other hand, for example, the SiO ₂ interlayer insulation film has a thickness of 1 μm and a withstand voltage of 100 volts. Therefore, the SiO ₂ interlayer insulation film in the present invention exhibits a sufficient function at a thickness of 0.5 to 2 μm, for example. As described above, the interlayer insulating film in the multilayer wiring board of the present invention may be much thinner than the interlayer insulating film formed by the build-up resin in the conventional multilayer wiring board. For example, an interlayer insulating film having a thickness smaller than that of the wiring layer may be provided. In that case, in the multilayer wiring board of the present invention, the interlayer insulating film has a surface shape that strongly reflects the surface shape of the lower layer, and the cross section is stepped as shown in FIG.

As the interlayer insulating film, an inorganic insulating film such as SiO ₂ or Si ₃ N ₄ can be used, but SiO ₂ is preferable in terms of pressure resistance and productivity.

  An opening formed in each of the interlayer insulating films 15ab, 15bc, 15cd, and 15de, as well as a via 17 of a type connecting adjacent wiring layers and a via 17 'of a type connecting upper and lower wiring layers via two or more interlayer insulating films It is formed by filling the portion with a wiring material. In the case of a conventional multilayer wiring board in which an interlayer insulating film is formed of a build-up resin, a via opening is formed in the interlayer insulating film by laser processing. On the other hand, in the multilayer wiring board of the present invention, since the interlayer insulating film does not contain a different material such as a filler, the opening for forming the via in the interlayer insulating film can be formed by a photolithographic method using etching. . In the case of laser processing, the diameter of the opening is 30 μm or more, whereas in the case of the lithographic method, an opening with a diameter of 10 μm or less can be formed.

In a conventional multilayer wiring board in which an interlayer insulating film is formed of a build-up resin, since one interlayer insulating film is thick, it is difficult to form a via opening by simultaneously laser processing a plurality of stacked insulating films. is there. For this reason, vias of the type in which the upper and lower wiring layers are connected via two or more interlayer insulating films connect vias 107′a to 107′d (FIG. 6) individually formed in the openings of the interlayer insulating films. The land 109 (FIG. 6) exists at the connection portion of each individual via. In the multilayer wiring board according to the present invention, since one interlayer insulating film is thin, vias of the type in which the upper and lower wiring layers are connected via two or more interlayer insulating films are collectively formed by opening the openings of each interlayer insulating film by a lithographic method. And can be made by forming. Therefore, in the multilayer wiring board of the present invention, both types of vias are formed as a single via, and there are two or more types of vias that connect the upper and lower wiring layers via two or more interlayer insulating films. There are no intermediate lands (members indicated by 109 in FIG. 6) unique to the vias formed by connecting the single vias. When the thickness of one interlayer insulating film increases to increase the overall thickness of the laminated interlayer insulating film to be formed as a via opening, a thick resist film is required, and the via openings are collectively formed by dry etching. Is actually difficult. When using dry etching to form the opening of the SiO ₂ insulating film, the selection ratio of the SiO ₂ insulating film and the resist film for the current etchants (CF ₄ gas) is about 4. In the present invention, since one SiO ₂ interlayer insulating film may be about 1 μm, for example, when via openings are formed collectively in four layers of interlayer insulating films, a resist film thicker than 16 μm may be used.

  EXAMPLES Next, the present invention will be further described with reference to examples, but it should be understood that the present invention is not limited to these examples.

  As shown in FIG. 2A, the first wiring layer 35 is formed on the surface of the core substrate 31 made of glass cloth epoxy resin on which the through-hole electrode 33 is formed. The through-hole electrode 33 is formed by forming a metal layer 33a on the inner wall of a through-hole formed in the core substrate 31, and filling the gap in the hole with an insulating resin material 33b. For the wiring layer 35, a resist pattern (not shown) is formed on a seed layer (not shown) formed on the surface of the core substrate 31, and a Cu layer is grown by 4 μm on the exposed seed layer by electrolytic Cu plating. Is formed. At this time, the land 75 is formed on the through-hole electrode 33 on the back surface side of the core substrate 31 by a method similar to the formation of the wiring layer 35. Thereafter, the resist pattern and the seed layer are sequentially removed.

Subsequently, an SiO ₂ interlayer insulating film 37 having a thickness of 1 μm is formed on the entire surface by low-temperature plasma CVD at 180 ° C., for example, as shown in FIG. In the interlayer insulating film 37, an opening 39 (diameter 10 μm) for a via connecting the first wiring layer 35 already formed and the second wiring layer to be formed next (diameter 10 μm) (FIG. 2C). ). The opening 39 is formed by forming a resist pattern (not shown) on the interlayer insulating film 37 and dry-etching the insulating film 37 exposed in the opening with CF ₄ . Thereafter, the resist pattern is removed.

  Subsequently, the opening 39 is filled with a wiring material to form a via 41 as shown in FIG. 2D. At the same time, a second wiring layer 43 (with a thickness of 4 μm) is formed on the interlayer insulating film 37. Form. The via 41 and the wiring layer 43 are formed by forming a seed layer (not shown) on the surface of the core substrate on which the interlayer insulating film 37 is formed, and then forming a resist pattern (not shown) thereon to expose the exposed seed. It is performed by growing a Cu layer on the layer by electrolytic Cu plating. Thereafter, the resist pattern and the seed layer are sequentially removed.

2 (b) to 2 (d) are repeated, the four wiring layers 35, 43, 49, and 55, the insulating film 37 between the wiring layers, as shown in FIG. 3 (a), An intermediate product having insulating films 57 covering 45 and 51 and the uppermost wiring layer 55 and vias 41, 47 and 53 interconnecting adjacent wiring layers is obtained. Next, as shown in FIG. 3B, the fourth wiring layer 55 below and the fifth wiring layer to be formed next are formed on the uppermost insulating film 57 of the intermediate product. Via opening 58 for connecting via (diameter 20 μm), and via opening for connecting first wiring layer 35 and fifth wiring layer via four insulating films 37, 45, 51, 57. The part 59 (diameter 30 μm) is formed at the same time. The openings 58 and 59 are formed by a photolithography method using dry etching with CF ₄ , similarly to the formation of the opening 39 described above. Considering that the selection ratio of the SiO ₂ insulating film to the CF ₄ and the resist film is about 4, the thickness of the resist film in this case is about 20 μm.

  Next, the openings 58 and 59 are filled with a wiring material to form vias 61 and 63 as shown in FIG. 3C, and a fifth wiring layer 65 (on the interlayer insulating film 57). 4 μm thick). The vias 61 and 63 and the wiring layer 65 are formed in the same manner as the previous vias and wiring layers. A seed layer (not shown), a resist pattern (not shown) thereon, and an exposed seed layer are formed. It is performed by forming an electrolytic Cu plating layer on the top. Thereafter, the resist pattern and the seed layer are sequentially removed.

  Subsequently, as shown in FIG. 4, protective layers 67 and 67 ′ are formed by solder resist on the entire surface of the core substrate 31 on which the fifth wiring layer 65 is formed, and nickel is formed in the opening 69 of the protective layer 67. Plating and gold plating are sequentially performed to form a pad 71 used for mounting a semiconductor device (not shown) or the like. On the opposite side of the core substrate 31 thus formed with the multilayer wiring structure, metal bumps 73 connected to the through-hole electrodes 33 via the lands 75 in the openings of the protective layer 67 ′ formed of solder resist, for example, solder balls are used. It can be formed using. The multilayer wiring board of one embodiment of the present invention shown in FIG. 4 can be connected to another board (for example, a circuit board such as a mother board) by metal bumps 73.

  A similar multilayer wiring structure can be formed on the opposite side of the core substrate 31 on which the multilayer wiring structure of FIG. 4 is formed, and an example of such an embodiment is shown in FIG. In FIG. 5, the upper and lower multilayer wiring structures of the core substrate 31 are the same, and the same members in the upper and lower multilayer wiring structures are denoted by the same reference numerals.

In the above aspect of the present invention, all of the interlayer insulating film is formed of SiO ₂ , but an aspect in which a part thereof is formed of another material is also possible. For example, when it is only necessary to connect the uppermost wiring layer 65 to the wiring layer 55 immediately below the uppermost wiring layer 65 in the embodiment of FIG. 4, the insulating film 57 between the wiring layers 55 and 65 is an ordinary resin such as an epoxy resin. You may form with buildup resin.

It is a schematic diagram explaining the multilayer wiring board of this invention. It is a figure which illustrates typically the first half of the manufacturing process of the multilayer wiring board of this invention. It is a figure which illustrates typically the latter half of the manufacturing process of the multilayer wiring board of this invention. It is a schematic diagram explaining the one aspect | mode of the multilayer wiring board by this invention. It is a schematic diagram explaining another aspect of the multilayer wiring board by this invention. It is a figure explaining the multilayer wiring board of a prior art.

Explanation of symbols

11 Core substrate 13a-13e Wiring layer 15ab, 15bc, 15cd, 15de Interlayer insulation film 17, 17 'Via 19 Protective layer 21 Pad 23 Through hole 31 Core substrate 33 Through hole electrode 35, 43, 49, 55, 65 Wiring layer 37 , 45, 51, 57 Interlayer insulating film 41, 47, 53, 61, 63 Via 67, 67 'Protective layer 71 Pad 73 Metal bump

Claims (5)

A multilayer wiring board having a plurality of wiring layers and an interlayer insulating film, and having a type of via that connects adjacent wiring layers and a type of via that connects upper and lower wiring layers via two or more interlayer insulating films And at least a part of the interlayer insulating film is formed of an inorganic insulating film, and vias of a type connecting upper and lower wiring layers via two or more interlayer insulating films are both inorganic insulating films. the formed interlayer insulating film is formed as a single via which penetrates the interlayer insulating film formed of an inorganic insulating film is thinner than the wiring layer, and stepped to thereby reflecting the surface shape of the lower wiring layer A multilayer wiring board characterized by being formed.   The multilayer wiring board according to claim 1, wherein all of the interlayer insulating films are made of an inorganic insulating film.   The multilayer wiring board according to claim 1, wherein the inorganic insulating film is formed by a low temperature CVD method.   The multilayer wiring board according to claim 1, wherein the inorganic insulating film has a thickness of 0.5 to 2.0 μm.   5. The method for manufacturing a multilayer wiring board according to claim 1, wherein two or more vias of a type connecting upper and lower wiring layers through two or more inorganic insulating films are formed. A method for producing a multilayer wiring board, comprising: forming an inorganic insulating film, and then using an opening formed by simultaneously processing the inorganic insulating films by a photolithographic method.

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