JP6536710B2 - Multilayer wiring structure - Google Patents

Description

  The present invention relates to a multilayer wiring structure, and one disclosed embodiment relates to a laminated structure of a substrate and a multilayer wiring structure.

  In recent years, with the advancement of performance of integrated circuits, integrated circuits have become more complicated, and the number of elements such as transistors constituting the integrated circuit has increased. With the increase in the number of elements, the arrangement of interconnections connecting the elements is also complicated, and the area occupied by the interconnections in the integrated circuit substrate is increasing. Therefore, in the integrated circuit substrate, in order to reduce the occupied area in the plane direction of the wirings as much as possible, development of a multilayer wiring technology has been advanced in which a plurality of wirings are stacked and the wirings are drawn three-dimensionally. In particular, a multilayer wiring technology having a so-called stacked via structure in which vias are stacked in order to improve the wiring density has been developed (for example, Patent Document 1).

  In a multilayer wiring structure such as a stack via structure, the expansion and contraction of each layer in a thermal cycle (heat treatment process) may cause a crack in a via connecting the stacked wirings and an interlayer film separating the stacked wirings. The multilayer wiring structure and the substrate may be peeled off. When the wiring material diffuses into the cracks, a problem occurs that a leak current flows between the wiring and the substrate. In addition, the via and the wiring layer may be separated, and the conduction between the stacked wirings may not be obtained.

JP, 2006-173333, A

  An object of the present invention is to provide a multilayer wiring structure having high resistance to a heat treatment process in view of the above-mentioned situation.

  A multilayer wiring structure according to an embodiment of the present invention has a multilayer wiring structure in which a first wiring layer, a second wiring layer, and a third wiring layer are sequentially stacked from the substrate side on a substrate, and a multilayer wiring structure Includes a first via connecting the first wiring layer and the second wiring layer, and a second via connecting the second wiring layer and the third wiring layer, and isolates the multilayer wiring structure from the substrate. And an insulating intermediate layer having a Young's modulus lower than that of the substrate.

  A multilayer wiring structure according to an embodiment of the present invention has a multilayer wiring structure in which a first wiring layer, a second wiring layer, and a third wiring layer are sequentially stacked from the substrate side on a substrate, and a multilayer wiring structure Includes a first via connecting the first wiring layer and the second wiring layer, and a second via connecting the second wiring layer and the third wiring layer, and isolates the multilayer wiring structure from the substrate. And an insulating intermediate layer having a thermal expansion coefficient higher than that of the substrate and lower than that of the first wiring layer.

  According to this multilayer wiring structure, it is possible to relieve local stress due to expansion and contraction of each layer caused by the heat treatment process.

  In another preferred embodiment, the first via and the second via may overlap with each other in plan view.

  According to this multilayer wiring structure, the degree of freedom in design is high, and the occupied area in the planar direction can be reduced.

  In another preferred embodiment, the first inorganic insulating layer, the second inorganic insulating layer, and the first organic insulating layer may be provided on the first wiring layer.

  In another preferred embodiment, the third inorganic insulating layer, the fourth inorganic insulating layer, and the second organic insulating layer may be provided on the second wiring layer.

  According to this multilayer wiring structure, parasitic capacitance between stacked wiring layers can be reduced. In addition, warpage of the substrate can be suppressed.

  In another preferred embodiment, the intermediate layer may be a resin layer.

  According to this multilayer wiring structure, it is possible to relieve local stress due to expansion and contraction of each layer caused by the heat treatment process.

  In another preferred embodiment, the first wiring layer may have Cu, and the diffusion rate of Cu may be slower in the intermediate layer than in the substrate.

  According to this multilayer wiring structure, diffusion of Cu contained in the first wiring layer to the substrate can be suppressed.

  In another preferred embodiment, the dielectric constant of the first organic insulating layer is lower than the dielectric constant of each of the first inorganic insulating layer and the second inorganic insulating layer, and the dielectric constant of the second organic insulating layer is The dielectric constant of each of the inorganic insulating layer and the fourth inorganic insulating layer may be lower.

  According to this multilayer wiring structure, parasitic capacitance between stacked wiring layers can be reduced.

  In another preferable embodiment, the second wiring layer may have Cu, and the third inorganic insulating layer may have a slower diffusion rate of Cu as compared to the fourth inorganic insulating layer and the second organic insulating layer.

  According to this multilayer wiring structure, Cu contained in the second wiring layer can be diffused, and a short circuit between isolated wirings can be suppressed.

  A multilayer wiring structure according to an embodiment of the present invention is separated from the substrate by a substrate, an insulating intermediate layer disposed on the substrate, and an intermediate layer, and a first wiring layer, a first inorganic insulating layer A first wiring structure including a second inorganic insulating layer and a first organic insulating layer; a second wiring layer disposed above the first wiring structure; and a second organic insulating layer A second wiring structure, and a third wiring structure disposed above the first wiring structure and including a third wiring layer, a third inorganic insulating layer, a fourth inorganic insulating layer, and a third organic insulating layer; It has a first via connecting the first wiring layer and the second wiring layer or the third wiring layer, and a second via connecting the second wiring layer and the third wiring layer.

  According to this multilayer wiring structure, it is possible to relieve local stress due to expansion and contraction of each layer caused by the heat treatment process. In addition, parasitic capacitance between the stacked wirings can be reduced.

  In another preferred embodiment, the first via and the second via may overlap with each other in plan view.

  According to this multilayer wiring structure, the degree of freedom in design is high, and the occupied area in the planar direction can be reduced.

  Also, in another preferred embodiment, the intermediate layer may have a smaller Young's modulus than the substrate.

  In another preferred embodiment, the intermediate layer may have a thermal expansion coefficient higher than that of the substrate and lower than that of the first wiring layer.

  In another preferred embodiment, the intermediate layer may be a resin layer.

  According to this multilayer wiring structure, it is possible to relieve local stress due to expansion and contraction of each layer caused by the heat treatment process.

  In another preferred embodiment, the first wiring layer may have Cu, and the diffusion rate of Cu may be slower in the intermediate layer than in the substrate.

  According to this multilayer wiring structure, diffusion of Cu contained in the first wiring layer to the substrate can be suppressed.

  In another preferred embodiment, the dielectric constant of the first organic insulating layer is lower than the dielectric constant of each of the first inorganic insulating layer and the second inorganic insulating layer, and the dielectric constant of the second organic insulating layer is The dielectric constant of each of the inorganic insulating layer and the fourth inorganic insulating layer may be lower.

  According to this multilayer wiring structure, parasitic capacitance between stacked wiring layers can be reduced.

  In another preferable embodiment, the second wiring layer may have Cu, and the third inorganic insulating layer may have a slower diffusion rate of Cu as compared to the fourth inorganic insulating layer and the second organic insulating layer.

  According to this multilayer wiring structure, Cu contained in the second wiring layer can be diffused, and a short circuit between isolated wirings can be suppressed.

  According to the present invention, a multilayer wiring structure having high resistance to a heat treatment process can be provided.

FIG. 1 is a cross-sectional view of a multilayer wiring structure according to a first embodiment of the present invention. FIG. 7 is a cross-sectional view of a substrate on which a first conductive material and a lower second conductive material are formed in the method for manufacturing a multilayer wiring structure according to the first embodiment of the present invention. It is sectional drawing of the board | substrate with which the photoresist was formed on the lower 2nd conductive material in the manufacturing method of the multilayer wiring structure which concerns on 1st Embodiment of this invention. It is sectional drawing of the board | substrate with which the upper 2nd conductive material was formed on the 2nd lower conductive material in the manufacturing method of the multilayer wiring structure which concerns on 1st Embodiment of this invention. FIG. 7 is a cross-sectional view of the substrate from which the photoresist on the lower second conductive material has been removed in the method for manufacturing a multilayer wiring structure according to the first embodiment of the present invention. FIG. 7 is a cross-sectional view of the substrate on which the pattern of the first wiring layer is formed by etching in the method for manufacturing a multilayer wiring structure according to the first embodiment of the present invention. It is sectional drawing of the board | substrate with which the 1st inorganic insulating layer and the 2nd inorganic insulating layer were formed on the 1st wiring layer in the manufacturing method of the multilayer wiring structure concerning a 1st embodiment of the present invention. It is sectional drawing of the board | substrate with which the 1st organic insulating layer was formed on the 2nd inorganic insulating layer in the manufacturing method of the multilayer wiring structure which concerns on 1st Embodiment of this invention. FIG. 7 is a cross-sectional view of a substrate in which an opening is formed in the first inorganic insulating layer and the second inorganic insulating layer in the method for manufacturing a multilayer wiring structure according to the first embodiment of the present invention. It is sectional drawing of the board | substrate with which the 3rd electrically conductive material was formed on the 1st organic insulating layer in the manufacturing method of the multilayer interconnection structure which concerns on 1st Embodiment of this invention. It is sectional drawing of the board | substrate with which the lower 4th conductive material was formed on the 3rd conductive material in the manufacturing method of the multilayer wiring structure which concerns on 1st Embodiment of this invention. It is sectional drawing of the board | substrate with which the photoresist was formed on the lower 4th conductive material in the manufacturing method of the multilayer wiring structure which concerns on 1st Embodiment of this invention. It is sectional drawing of the board | substrate with which the upper 4th conductive material was formed on the lower 4th conductive material in the manufacturing method of the multilayer wiring structure which concerns on 1st Embodiment of this invention. FIG. 13 is a cross-sectional view of the substrate from which the photoresist on the lower fourth conductive material has been removed in the method for manufacturing a multilayer wiring structure according to the first embodiment of the present invention. FIG. 7 is a cross-sectional view of a substrate on which a pattern of a second wiring layer is formed by etching in the method of manufacturing a multilayer wiring structure according to the first embodiment of the present invention. It is sectional drawing of the board | substrate with which the 3rd inorganic insulating layer and the 4th inorganic insulating layer were formed on the 2nd wiring layer in the manufacturing method of the multilayer wiring structure concerning a 1st embodiment of the present invention. It is sectional drawing of the board | substrate with which the 2nd organic insulating layer was formed on the 4th inorganic insulating layer in the manufacturing method of the multilayer wiring structure which concerns on 1st Embodiment of this invention. FIG. 7 is a cross-sectional view of a substrate in which an opening is formed in the third inorganic insulating layer and the fourth inorganic insulating layer in the method for manufacturing a multilayer wiring structure according to the first embodiment of the present invention. FIG. 7 is a cross-sectional view of a substrate for describing the details of a method of etching a pattern of a wiring layer in the method of manufacturing a multilayer wiring structure according to the first embodiment of the present invention. FIG. 7 is a cross-sectional view of a substrate for describing the details of a method of forming an organic insulating layer in the method of manufacturing a multilayer wiring structure according to the first embodiment of the present invention. It is sectional drawing of the multilayer wiring structure which concerns on 2nd Embodiment of this invention. It is sectional drawing of the multilayer wiring structure which concerns on Example 1 of this invention.

First Embodiment
Hereinafter, a multilayer wiring structure according to a first embodiment of the present invention will be described in detail with reference to the drawings. The embodiments described below are merely examples of the embodiments of the present invention, and the present invention is not construed as being limited to these embodiments. In the drawings referred to in this embodiment, the same portions or portions having similar functions may be denoted by the same reference numerals or similar reference numerals, and repeated description thereof may be omitted. Further, the dimensional ratio of the drawings may be different from the actual ratio for convenience of explanation, or a part of the configuration may be omitted from the drawings.

[Configuration of multilayer wiring structure]
FIG. 1 is a cross-sectional view of a multilayer wiring structure according to a first embodiment of the present invention. In FIG. 1, as an example of the multilayer wiring structure, a cross-sectional view of a six-layer wiring structure will be described.

  In FIG. 1, first to fifth layers separating the first to sixth wiring layers (110, 120, 130, 140, 150, 160) and the first to sixth wiring layers on the substrate 100. The first to fourth vias (191, 191, 129, 139, 149, 159) connecting the adjacent wiring layers among the first to fifth wiring layers (110, 120, 130, 140, 150) , 192, 193, 194) are formed. Between the substrate 100 and the first wiring layer 110 which is the lowermost wiring layer of the multilayer wiring structure, an insulating intermediate layer 101 is formed to isolate the substrate 100 and the first wiring layer 110, and the first wiring is formed. Layer 110 and substrate 100 are electrically isolated.

  In FIG. 1, the first wiring layer 110 has a first conductive layer 111 and a second conductive layer 112. As the second conductive layer 112, a metal material having low electrical resistance is preferable. For example, copper (Cu), silver (Ag), gold (Au), aluminum (Al) or the like can be used. In addition, aluminum alloys such as aluminum-neodymium alloy (Al-Nd) and aluminum-copper alloy (Al-Cu) can be used. As the first conductive layer 111, it is preferable to use a material having adhesiveness or a barrier property to the second conductive layer 112. For example, when Cu is used as the second conductive layer 112, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), Cr (chromium) or the like may be used as the first conductive layer 111. It can be used. Although FIG. 1 exemplifies a laminated structure of two conductive layers as the wiring layer, the present invention is not limited to this structure, and may have a single layer structure of one conductive layer, and three or more conductive layers. It may be a laminated structure according to

  In FIG. 1, the first interlayer film 119 has a first inorganic insulating layer 113, a second inorganic insulating layer 114, and a first organic insulating layer 115. The first inorganic insulating layer 113 is formed to cover the first conductive layer 111, the second conductive layer 112, and the exposed intermediate layer 101. In addition, the second inorganic insulating layer 114 is formed to cover the first inorganic insulating layer 113, and the first organic insulating layer 115 is further formed thereon. Here, the dielectric constant of the first organic insulating layer 115 is preferably lower than the dielectric constant of each of the first inorganic insulating layer 113 and the second inorganic insulating layer 114. The first interlayer film 119 is not limited to the above three-layer structure, and may be configured to include at least one or more organic insulating layers or inorganic insulating layers.

The first inorganic insulating layer 113 is preferably made of a material having a barrier property to the second conductive layer 112. In other words, it is preferable that the first inorganic insulating layer 113 be a material whose diffusion speed of the second conductive layer 112 is slower than that of the second inorganic insulating layer 114 or the first organic insulating layer 115. For example, when Cu is used as the second conductive layer 112, silicon nitride (SiN), aluminum oxide (Al ₂ O ₃ ), aluminum nitride (AlN), silicon carbide (SiC) as the first inorganic insulating layer 113 Silicon nitride carbide (SiCN), carbon-doped silicon oxide (SiOC), etc. can be used. Further, the first inorganic insulating layer 113 is preferably formed under film forming conditions with good coverage. When Cu is used as the second conductive layer 112 and SiN is used as the first inorganic insulating layer 113, it is preferable that the film thickness be a certain thickness or more in order to obtain the diffusion preventing function of Cu, and SiN is a specific dielectric Since the ratio is as high as 7.5, in order to suppress parasitic capacitance between wiring layers, it is preferable to set the film thickness to a certain value or less. Specifically, the film thickness of the SiN film is preferably 10 nm or more and 200 nm or less. More preferably, the thickness is 50 nm or more and 100 nm or less.

  It is preferable that the first inorganic insulating layer 113 does not generate a crack in the first inorganic insulating layer 113 or a region having a rough film in the step portion formed by the first wiring layer 110. For example, it is desirable that the first inorganic insulating layer 113 be deposited under conditions where the deposition temperature is high, and preferably 200 ° C. or higher. More preferably, the temperature is 300 ° C. or higher. Further, in order to improve the coverage of the first inorganic insulating layer 113, the end face of the first wiring layer 110 may have a forward tapered shape inclined with respect to the surface of the intermediate layer 101. The taper angle of the first wiring layer 110 is preferably 30 degrees or more and 90 degrees or less. More preferably, 30 degrees or more and 60 degrees or less. Here, both of the first conductive layer 111 and the second conductive layer 112 included in the first wiring layer 110 may not be in the forward tapered shape, and either one may be in the forward tapered shape.

The second inorganic insulating layer 114 is preferably made of a material having good adhesion to the first inorganic insulating layer 113 and the first organic insulating layer 115 formed thereon. For example, as the second inorganic insulating layer 114, silicon oxide (SiO ₂ ), aluminum oxide (Al ₂ O ₃ ), or the like can be used. In addition, the second inorganic insulating layer 114 is preferably formed under film formation conditions with good coverage. Further, the SiO ₂ film is preferably a predetermined thickness or more in order to adjust the warpage of the substrate and to improve the reliability, and if the thickness is too large, the balance with the stress of PI can not be balanced. It is preferably thick. Specifically, the film thickness of the SiO ₂ film is preferably 1 μm to 8 μm. More preferably, the thickness is 2 μm or more and 5 μm or less.

  The first organic insulating layer 115 relieves or planarizes the step formed by the first wiring layer 110, and is a material having a dielectric constant lower than that of the first inorganic insulating layer 113 and the second inorganic insulating layer 114. Preferably, it is formed of, for example, a resin material such as photosensitive polyimide. The film thickness of the first organic insulating layer 115 is preferably at least the film thickness formed by the first wiring layer 110 or more. In order to reduce the parasitic capacitance between the wiring layers, the coating process can be performed. It is preferable to form as thick as possible. Specifically, the film thickness of the first organic insulating layer is preferably 4 μm or more and 24 μm or less. More preferably, it is 8 μm or more and 20 μm or less. Moreover, photosensitive acrylic, photosensitive siloxane, etc. can be used instead of photosensitive polyimide. Besides, benzocyclobutene having a low dielectric constant and a barrier property to Cu may be used. Moreover, you may use not only photosensitive resin but non-photosensitive resin.

  As non-photosensitive resin, epoxy resin, polyimide resin, benzocyclobutene resin, polyamide, phenol resin, silicone resin, fluorine resin, liquid crystal polymer, polyamide imide, polybenzoxazole, cyanate resin, aramid, polyolefin, polyester, BT resin , FR-4, FR-5, polyacetal, polybutylene terephthalate, syndiotactic polystyrene, polyphenylene sulfide, polyetheretherketone, polyether nitrile, polycarbonate, polyphenylene ether polysulfone, polyether sulfone, polyarylate, polyether imide, etc. Can be used. The above resins may be used alone or in combination of two or more resins. In addition, an inorganic filler such as glass, talc, mica, silica, alumina or the like may be used in combination with the above resin.

  An opening 181 is provided in the first interlayer film 119, and the inside of the opening 181 is filled with the first via 191. Although FIG. 1 illustrates the structure in which the first via 191 is formed by filling the opening 181 with a part of the second wiring layer 120, the present invention is not limited to this structure. For example, as the first via 191 The conductive layer different from the second wiring layer 120 may be used. Although FIG. 1 illustrates the structure in which the opening 181 and the first via 191 have a shape perpendicular to the substrate, the present invention is not limited to this structure, and the opening 181 and the first via 191 may It may have a forward taper shape, and the opening 181 and the first via 191 may have a reverse taper shape with respect to the substrate. Although FIG. 1 exemplifies a structure in which the opening 181 is filled with the conductive layer, the vias may be connected to adjacent wiring layers, and a part of the opening 181 may be hollow.

  When the second wiring layer 120 is used as the first via 191 as shown in FIG. 1, copper (Cu), silver (Ag), and the like having low electric resistance as the second conductive layer 112 are used as the fourth conductive layer 122. Gold (Au), aluminum (Al) or the like can be used. In addition, aluminum alloys such as aluminum-neodymium alloy (Al-Nd) and aluminum-copper alloy (Al-Cu) can be used. Further, as the third conductive layer 121, it is preferable to use a material having a barrier property to the fourth conductive layer 122 as in the first conductive layer 111. For example, when the fourth conductive layer 122 contains Cu, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), Cr (chromium) or the like is used as the third conductive layer 121. can do.

  The first via 191 is in contact with the second conductive layer 112 of the first wiring layer 110 at the bottom thereof, and the first wiring layer 110 and the second wiring layer 120 are electrically connected. Although the second wiring layers 126 and 127 are not connected to the upper and lower wiring layers in FIG. 1, they may be connected to the upper and lower wiring layers at places different from the cross section shown in FIG.

  A second interlayer film 129 is formed on the second wiring layer 120. The second interlayer film 129 has the same structure as the first interlayer film 119, and includes a third inorganic insulating layer 123, a fourth inorganic insulating layer 124, and a second organic insulating layer 125. In FIG. 1, since the material used for each layer of the second interlayer film 129 is the same material as each layer of the first interlayer film 119, the detailed description is omitted here. However, the material used for each layer of the second interlayer film 129 is not limited to the same material as each layer of the first interlayer film 119, and can be appropriately selected according to the purpose of the interlayer film.

  Thereafter, the third to fifth wiring layers (130, 140, 150) can be formed in the same manner as the second wiring layer 120. The fifth conductive layer 131 of the third wiring layer 130, the seventh conductive layer 141 of the fourth wiring layer 140, and the ninth conductive layer 151 of the fifth wiring layer 150 may be formed of the same material as the first conductive layer 111, respectively. it can. Also, the sixth conductive layer 132 of the third wiring layer 130, the eighth conductive layer 142 of the fourth wiring layer 140, and the tenth conductive layer 152 of the fifth wiring layer 150 are formed of the same material as the second conductive layer 112, respectively. be able to. However, these conductive layers do not necessarily have to be the same as the first conductive layer 111 or the second conductive layer 112, and can be appropriately selected according to the purpose of the wiring layer.

  Further, in the same manner as the second interlayer film 129, third to fifth interlayer films (139, 149, 159) can be formed. The fifth inorganic insulating layer 133 of the third interlayer film 139, the seventh inorganic insulating layer 143 of the fourth interlayer film 149, and the ninth inorganic insulating layer 153 of the fifth interlayer film 159 are the same materials as the first inorganic insulating layer 113, respectively. It can be formed. The sixth inorganic insulating layer 134 of the third interlayer film 139, the eighth inorganic insulating layer 144 of the fourth interlayer film 149, and the tenth inorganic insulating layer 154 of the fifth interlayer film 159 are the same as the second inorganic insulating layer 114, respectively. It can be formed of a material. The third organic insulating layer 135 of the third interlayer film 139, the fourth organic insulating layer 145 of the fourth interlayer film 149, and the fifth organic insulating layer 155 of the fifth interlayer film 159 are the same as the first organic insulating layer 115, respectively. It can be formed of a material. However, these insulating layers are not necessarily the same as the first inorganic insulating layer 113, the second inorganic insulating layer 114, or the first organic insulating layer 115, and may be appropriately selected according to the purpose of the insulating layer. it can.

  The first to fourth vias (191, 192, 193, 194) have a so-called stacked via structure stacked at the same plane coordinates. In other words, the first to fourth vias (191, 192, 193, 194) overlap each other in plan view. Here, the overlapping vias are not limited to the completely overlapping structure in plan view, and include, for example, a structure in which a part of the vias is overlapped. In the stacked via structure shown in FIG. 1, a structure in which all the stacked vias overlap each other in plan view is exemplified, but the present invention is not limited to this structure, and at least vias formed above and below a certain wiring layer can be viewed in plan It only needs to overlap each other. For example, the first via 191 under the second wiring layer 120 and the upper second via 192 may overlap at least partially in plan view.

  Although FIG. 1 illustrates a structure in which all of the first to fourth vias (191, 192, 193, 194) have the same diameter, the present invention is not limited to this structure, and even if the diameter of the via differs depending on the layer. Good. For example, the via (for example, the fourth via 194) in the upper layer may have a larger diameter than the via (for example, the first via 191) in the lower layer. Also, the diameter of the via of a particular layer may be different from the diameter of the via of another layer.

  In FIG. 1, the fifth wiring layer 150 is connected to the uppermost sixth wiring layer 160 through the opening 185 provided in the fifth interlayer film 159. The sixth wiring layer 160 includes an eleventh conductive layer 161, a twelfth conductive layer 162, and a thirteenth conductive layer 163. As the eleventh conductive layer 161, it is preferable to use a material having low electric resistance and good adhesion to the tenth conductive layer 152. For example, the same material as the tenth conductive layer 152 may be used, and Cu, Ag, Au, Al, Al-Nd, Al-Cu, or the like can be used.

  Further, as the thirteenth conductive layer 163, it is preferable to use a material that has high corrosion resistance, is not easily oxidized, and has low contact resistance with an external element. For example, Au, platinum (Pt), etc. can be used. Further, as the twelfth conductive layer 162, a material having good adhesion to the eleventh conductive layer 161 and the thirteenth conductive layer 163 is preferable. Further, for example, when the thirteenth conductive layer 163 is formed by plating, it is preferable to use a material suitable as a seed layer of the thirteenth conductive layer 163. For example, Ti, nickel (Ni) or the like can be used.

  Between the multilayer wiring structure described above and the substrate, an insulating intermediate layer 101 is formed which separates the multilayer wiring structure from the substrate. It is desirable that the intermediate layer 101 be softer than the substrate 100, that is, have a smaller Young's modulus, in order to reduce the transfer of the stress caused by the multilayer wiring structure to the substrate. In addition, the intermediate layer 101 is more easily expanded and contracted than the substrate 100 in order to reduce the transfer of the thermal expansion of the substrate to the multilayer wiring structure, and the intermediate layer 101 is easier than the first conductive layer 111 and the second conductive layer 112 of the first wiring layer 110. It is desirable that it is difficult to stretch. That is, it is desirable that the thermal expansion coefficient be higher than that of the substrate 100 and the thermal expansion coefficient be lower than that of the first wiring layer. Here, when the film thickness of the second conductive layer 112 is, for example, five or more times larger than the film thickness of the first conductive layer 111, the stress caused by the thermal expansion coefficient is dominated by the stress caused by the second conductive layer 112 In order to become transparent, the thermal expansion coefficient of the intermediate layer 101 may be lower than the thermal expansion coefficient of the second conductive layer 112. The intermediate layer is preferably a resin layer. The intermediate layer 101 is preferably made of a material having a barrier property to the second conductive layer 112. In other words, it is preferable that the intermediate layer 101 be a material whose diffusion rate of the second conductive layer 112 is slower than that of the substrate 100. For example, when the second conductive layer 112 contains Cu, a resin layer such as polyimide can be used as the intermediate layer 101. Although FIG. 1 illustrates a structure in which one intermediate layer is sandwiched between the multilayer wiring structure and the substrate, the present invention is not limited to this structure, and the intermediate layer and the multilayer wiring structure, or the intermediate layer and the substrate Other layers may be sandwiched between.

  Here, in FIG. 1, in order to provide a multilayer wiring structure having a high degree of freedom in design and also to provide a multilayer wiring structure having a small occupied area in the planar direction, a plurality of vias overlap each other in plan view. Stack via structures are disclosed. The degree of expansion and contraction due to the heat treatment step in the process differs between the organic insulating layer and the wiring layer or between the organic insulating layer and the substrate. Therefore, in the stack via structure, the degree of expansion and contraction due to the heat treatment process occurs in the region AB line in which the wiring layer and the via overlap and in the region CD line in which the organic insulating layer is formed between the wiring layers. The stresses that occur are very different.

  In particular, in the region A-B line in which the wiring layer having a higher Young's modulus, which is harder than the organic insulating layer, is stacked, D2 (three-dimensional) compared to the region C-D line in which the organic insulating layer is disposed between the wiring layers. A large stress is generated in the direction. In addition, stress in the D1 (planar) direction is also generated on the entire surface of the substrate between the organic insulating layer and the substrate due to the degree of expansion and contraction due to the heat treatment process.

  If a stack via structure is formed without providing an intermediate layer on the substrate as in the prior art, the generation of a crack in the via or the inorganic insulating layer or the via and the wiring due to the stress in the D1 direction or D2 direction described above. Problems such as peeling occur. However, according to the structure shown in FIG. 1, the stress in the D1 direction or the D2 direction can be relaxed by providing the intermediate layer 101 between the substrate 100 and the stacked wiring layer, and the via or the inorganic material can be relaxed. It is possible to suppress problems such as the occurrence of a crack in the insulating layer and the separation of the via and the wiring.

  Further, as in the conventional structure in which the multilayer wiring structure is formed without providing the intermediate layer on the substrate, particularly when the second conductive layer 112 of the first wiring layer 110 contains Cu, the first conductive layer 111 and the first conductive layer Even when a material having a barrier property to Cu is used as the inorganic insulating layer 113, Cu may be diffused to the substrate through the cracks generated in the first inorganic insulating layer 113 in the heat treatment step. For example, in the case of using a conductive or semiconductor material for the substrate 100, a problem occurs in which the first wiring layer 110 and the substrate 100 are shorted.

  As described above, by separating the substrate and the multilayer wiring structure between the substrate and the multilayer wiring structure and providing the insulating intermediate layer having the above features, the wiring layer and the via are overlapped by the heat treatment process. It is possible to relieve the three-dimensional stress generated in the region. Further, by providing the intermediate layer, the stress in the planar direction generated on the entire surface of the substrate by the heat treatment step can be relaxed. As a result, it is possible to suppress problems such as generation of cracks in the via and the inorganic insulating layer, and separation of the via and the wiring. Further, by providing an insulating intermediate layer having the above-described characteristics between the substrate and the multilayer wiring structure, it is possible to suppress the diffusion of Cu to the substrate in the heat treatment step. As a result, the problem of short circuit between the first wiring layer and the substrate can be suppressed. That is, it is possible to obtain a multilayer wiring structure of stacked via structure in which the above-mentioned problems are suppressed.

  Therefore, according to the first embodiment, an example of which is shown in FIG. 1, it is possible to suppress cracking and peeling in the heat treatment step and to suppress the diffusion of Cu into the substrate and the like. A structure can be provided. In addition, since a multilayer wiring structure having a stack via structure can be obtained, a multilayer wiring structure having a high degree of freedom in design can be provided. Also, a multilayer wiring structure with a small area occupied in the planar direction can be provided. In addition, by using a material having a dielectric constant lower than that of the inorganic insulating layer as the organic insulating layer, parasitic capacitance between the stacked wirings can be reduced, so that delay of a signal transmitted through the wirings can be suppressed. It is possible to provide a multilayer wiring structure that can be

[Method of manufacturing multilayer wiring structure]
Next, a method of manufacturing a multilayer wiring structure according to the first embodiment of the present invention will be described with reference to FIGS. In FIGS. 2 to 18, the same elements as those shown in FIG. 1 are denoted by the same reference numerals.

  FIG. 2 is a cross-sectional view of a substrate on which a first conductive material and a lower second conductive material are formed in the method for manufacturing a multilayer wiring structure according to the first embodiment of the present invention. As shown in FIG. 2, an insulating intermediate layer 101 using a resin material such as polyimide is formed on a substrate 100 such as a silicon substrate using a coating method. Next, the first conductive material 211 is deposited by sputtering, and the lower second conductive material 212 is deposited thereon. It is preferable to use low resistance Cu as the lower second conductive material 212, and in that case, it is preferable to use Ti having a barrier property to Cu as the first conductive material 211. The intermediate layer 101 and the first conductive material 211 play a role as a barrier layer for suppressing Cu from diffusing into the substrate 100 and shorting the first conductive material 211 and the substrate 100. The lower second conductive material 212 also serves as a seed layer for growing Cu by electrolytic plating. Here, TiN or a refractory metal such as Ta, TaN, or Cr may be used as the material of the barrier layer other than Ti.

  Next, as shown in FIG. 3, after a photoresist is applied on the lower second conductive material 212, exposure and development are performed to form a wiring pattern resist pattern 310. After that, the same material as the lower second conductive material 212 is grown on the lower second conductive material 212 exposed from the wiring formation resist pattern 310 using electrolytic plating, as shown in FIG. 2 form a conductive material 213; Although FIG. 4 illustrates the manufacturing method of growing the same material as the lower second conductive material 212 as the upper second conductive material 213, the present invention is not limited to this method, and the upper second conductive material 213 may be used as the lower second conductive material. Materials different from 212 may be grown.

  Next, after the upper second conductive material 213 is formed, the photoresist for forming the wiring pattern forming resist pattern 310 is removed by an organic solvent to obtain the structure of FIG. Note that instead of using an organic solvent, ashing with oxygen plasma can also be used to remove the photoresist.

  Next, as shown in FIG. 6, a portion of the lower second conductive material 212 and a portion of the first conductive material 211 which were covered by the wiring formation resist pattern 310 are etched with an acidic chemical solution, The conductive layer 111 and the second conductive layer 112 are formed. Since the film thickness of the upper second conductive material 213 becomes thin by this etching, it is preferable to set the film thickness of the upper second conductive material 213 in consideration of the influence of the thin film formation. In addition, ion milling, dry etching, or the like can be used instead of the above-described etching with a chemical solution.

  In the case of using an acidic aqueous solution, if the first conductive layer 111 has a faster etching rate than the second conductive layer 112, an undercut 301 is formed as shown in FIG. In particular, when the width of the wiring is 5 μm or less, sufficient adhesion between the first conductive layer 111 and the underlying intermediate layer 101 can not be obtained, and the first conductive layer 111 is peeled off by its own stress or the like. Sometimes. On the other hand, in the case of using ion milling or dry etching, such an undercut hardly occurs, and therefore, fine wiring can be formed.

Next, as shown in FIG. 7, a first inorganic insulating layer 113 such as a SiN film and a second inorganic insulating layer 114 such as a SiO ₂ film are formed on the second conductive layer 112 by plasma CVD. Do. In forming the SiN film, SiH ₄ can be used as a Si source and NH ₃ can be used as a nitrogen source. In addition, SiH ₄ can be used as a Si source and N ₂ O can be used as an oxygen source for forming a SiO ₂ film. Also, tetraethoxysilane (TEOS) can be used as a Si source. In addition, O ₂ can also be used as an oxygen source.

SiO ₂ film, in terms of suppressing the warp of the substrate 100, it is preferable to adjust the film stress in -100Mpa following compressive stress than -300 MPa. In particular, the film stress is preferably adjusted to -200 Mpa or more and -150 Mpa or less.

In the case where the second conductive layer 112 contains Cu, if copper oxide is present on the surface of Cu, the adhesion between the first inorganic insulating layer 113 and Cu decreases, so before the film formation of the first inorganic insulating layer 113. It is preferable to wash the Cu surface with dilute sulfuric acid or the like. Alternatively, before the film formation of the first inorganic insulating layer 113, the Cu surface can be exposed to NH ₃ plasma in the same chamber to remove copper oxide.

  When the second conductive layer 112 contains Cu, it is preferable to use a SiN film having a barrier property to Cu as the first inorganic insulating layer 113, and Cu atoms, Cu molecules, and Cu ions of the second conductive layer 112 are used. Acts as a barrier insulating layer that prevents heat diffusion from the side surface and the top surface of the second conductive layer 112 to the second inorganic insulating layer 114 and also prevents diffusion due to an electric field between adjacent wiring layers. Here, instead of using the SiN film as the barrier insulating layer, a SiC film (which may contain several percent to 10% of oxygen) can be used. A SiC film can also be formed by plasma CVD, and has an effect of preventing diffusion of Cu atoms, Cu molecules, and Cu ions of the second conductive layer 112.

Further, instead of the SiO ₂ film, a SiOC film, a SiOF film, or the like may be used as the second inorganic insulating layer 114. The SiOC film and the SiOF film can also be formed by plasma CVD. The SiOC film or the SiOF film has a dielectric constant lower than that of the SiO ₂ film, and the parasitic capacitance between the stacked wirings can be reduced.

  Next, a first organic insulating layer 115 such as polyimide is applied on the second inorganic insulating layer 114 by spin coating. Instead of polyimide, benzocyclobutene or the like may be used. Moreover, you may use not only photosensitive resin but non-photosensitive resin.

  As non-photosensitive resin, epoxy resin, polyimide resin, benzocyclobutene resin, polyamide, phenol resin, silicone resin, fluorine resin, liquid crystal polymer, polyamide imide, polybenzoxazole, cyanate resin, aramid, polyolefin, polyester, BT resin , FR-4, FR-5, polyacetal, polybutylene terephthalate, syndiotactic polystyrene, polyphenylene sulfide, polyetheretherketone, polyether nitrile, polycarbonate, polyphenylene ether polysulfone, polyether sulfone, polyarylate, polyether imide, etc. Can be used. The above resins may be used alone or in combination of two or more resins. In addition, an inorganic filler such as glass, talc, mica, silica, alumina or the like may be used in combination with the above resin.

  However, in the case of using a non-photosensitive resin, it is necessary to further apply a photosensitive resin and perform patterning by lithography. Therefore, the use of a non-photosensitive resin may increase the number of processes. In the first embodiment, a manufacturing method using photosensitive polyimide as the first organic insulating layer 115 will be described.

  In the case where the first organic insulating layer 115 is applied, development is performed after exposure using a photo mask, and as shown in FIG. 8, a recess 281 is formed at a necessary position above the second conductive layer 112. . Here, the “required position” refers to a position where it is necessary to arrange a via for connecting the second conductive layer 112 to a wiring formed thereabove.

  A thermal curing process is performed to cure the first organic insulating layer 115 applied after the formation of the recess 281. The heat curing treatment is preferably set to a temperature equal to or less than the glass transition temperature of the organic insulating layer used. When the curing is performed at a temperature exceeding the glass transition temperature, the shape of the concave portion 281 is deformed, and a problem such as an opening diameter larger than the designed size occurs. For example, when polyimide is used as the first organic insulating layer 115, heat treatment is preferably performed at 250 ° C. if the glass transition temperature of the polyimide is 280 ° C. For example, heat treatment under a nitrogen atmosphere at 250 ° C. for 1 hour It is good to do. In addition, it is preferable to perform not only the process of thermosetting, but the heat processing after this process so that the glass transition temperature of a polyimide may not be exceeded.

  When the first organic insulating layer 115 is thermally cured, a step 302 as shown in FIG. 20 may occur in the region other than the concave portion 281 due to the step due to the first wiring layer 110. Such a step becomes larger as the wiring layers are stacked, and causes a focus shift at the time of pattern exposure. For this reason, it becomes difficult to form a wiring pattern based on the design dimensions, and a problem of shorting adjacent wires or a problem of disconnection of wires occurs. In order to reduce the level difference 302 of the first organic insulating layer 115, it is preferable to use an organic material such as polyimide having a small thermal shrinkage (preferably, a thermal shrinkage of 15% or less). Moreover, in order to remove the unevenness | corrugation of the surface of a polyimide with high precision, a fly cutter can also be used.

Next, plasma etching is performed using the first organic insulating layer 115 as a mask to etch the first inorganic insulating layer 113 and the second inorganic insulating layer 114 at the bottom of the recess 281. Here, an etching method in the case where a SiN film is used as the first inorganic insulating layer 113, an SiO ₂ film is used as the second inorganic insulating layer 114, and polyimide is used as the first organic insulating layer 115 will be described in detail.

As an etching gas for the SiO ₂ film, a mixed gas of CF ₄ (flow rate 20 sccm) and H ₂ (flow rate 5 sccm) can be used. By changing the flow ratio of the mixed gas, it is possible to adjust the ratio of the etching rate of the cured polyimide and the SiO ₂ film. Here, it is preferable to adjust the ratio of the etching rate of the polyimide to the SiO ₂ film to be small. The etching gas is not limited to that described above, and CHF ₃ or CH ₂ F ₂ can be used instead of CF ₄ .

As an etching gas for the SiN film, a mixed gas of CF ₄ (flow rate 20 sccm) and O ₂ (flow rate ₂ sccm) can be used. Also in the etching of the SiN film, it is possible to adjust the ratio of the etching rate of the cured polyimide and the SiN film by changing the flow ratio of the mixed gas. As in the case of SiO ₂ , it is preferable to adjust the ratio of the etching rate of polyimide to the SiN film to be small.

  As described above, an opening for filling the first via 191 electrically connecting the first wiring layer 110 and the second wiring layer 120 by etching the first inorganic insulating layer 113 and the second inorganic insulating layer 114. The part 181 is formed. Immediately after the opening 181 is formed, a carbon compound containing Si or F may be attached to the side wall or the bottom of the opening 181. In order to remove this carbon compound, it may be washed with an organic solvent. In addition, the surface of the second conductive layer 112 exposed at the bottom of the opening 181 may be oxidized by plasma etching. In order to remove the oxide on the surface, washing with dilute sulfuric acid may be performed.

  The surface of the first organic insulating layer 115 may receive plasma damage due to plasma etching of the first inorganic insulating layer 113 and the second inorganic insulating layer 114, and the heat resistance inherent to the first organic insulating layer 115 may be impaired. . In this case, the damaged layer on the surface can be removed by performing heat treatment, for example, at a temperature equal to or lower than the glass transition temperature of the first organic insulating layer 115. Thus, the structure shown in FIG. 9 can be obtained.

  Next, as shown in FIG. 10, a third conductive material 221 is deposited by sputtering. When the second conductive layer 112 contains Cu, as the third conductive material 221, by using Ti, TiN, Ta, TaN, Cr, etc. as in the first conductive layer 111, Cu atoms, Cu molecules, Cu, etc. It can function as a barrier metal that prevents ions from diffusing.

  Next, as shown in FIG. 11, the lower fourth conductive material 222 is deposited by sputtering. It is preferable to use low resistance Cu as the lower fourth conductive material 222. The lower fourth conductive material 222 also serves as a seed layer for growing Cu by electrolytic plating.

  Next, as shown in FIG. 12, a photoresist is applied on the lower fourth conductive material 222, and then exposure and development are performed to form a wiring pattern resist pattern 320. Thereafter, the same material as the lower fourth conductive material 222 is grown on the lower fourth conductive material 222 exposed from the wiring formation resist pattern 320 using electrolytic plating, as shown in FIG. 4 form a conductive material 223; Although FIG. 13 exemplifies a manufacturing method of growing the same material as the lower fourth conductive material 222 as the upper fourth conductive material 223, the present invention is not limited to this method, and the upper fourth conductive material 223 may be a lower fourth conductive material. Materials different from 222 may be grown.

  Next, after the upper fourth conductive material 223 is formed, the photoresist for forming the wiring pattern forming resist pattern 320 is removed by an organic solvent to obtain the structure of FIG. Note that instead of using an organic solvent, ashing with oxygen plasma can also be used to remove the photoresist.

  Next, as shown in FIG. 15, a portion of the lower fourth conductive material 222 and a portion of the third conductive material 221 covered by the resist pattern 320 for wiring formation are etched with an acidic chemical solution, The conductive layer 121 and the fourth conductive layer 122 are formed. Since the film thickness of the upper fourth conductive material 223 is reduced by this etching, it is preferable to set the film thickness of the upper fourth conductive material 223 in consideration of the influence of the thin film formation. In addition, ion milling or the like can be used instead of the above-mentioned etching with a chemical solution.

Next, as shown in FIG. 16, the third inorganic insulating layer 123 and the fourth inorganic insulating layer 124 are formed on the fourth conductive layer 122. For example, when the fourth conductive layer 122 contains Cu, it is preferable to use, as the third inorganic insulating layer 123, a SiN film having a barrier property to Cu as in the case of the first inorganic insulating layer 113, and As the layer 124, it is preferable to use an SiO ₂ film as in the case of the second inorganic insulating layer 114. Instead of using a SiN film as the barrier insulating layer as the third inorganic insulating layer 123, a SiC film (which may contain several percent to 10% of oxygen) can be used. Further, instead of the SiO ₂ film, a SiOC film, an SiOF film, or the like may be used as the fourth inorganic insulating layer 124.

  Next, a second organic insulating layer 125 such as polyimide is applied on the fourth inorganic insulating layer 124 by spin coating. Instead of polyimide, benzocyclobutene or the like may be used. Moreover, you may use not only photosensitive resin but non-photosensitive resin.

  As non-photosensitive resin, epoxy resin, polyimide resin, benzocyclobutene resin, polyamide, phenol resin, silicone resin, fluorine resin, liquid crystal polymer, polyamide imide, polybenzoxazole, cyanate resin, aramid, polyolefin, polyester, BT resin , FR-4, FR-5, polyacetal, polybutylene terephthalate, syndiotactic polystyrene, polyphenylene sulfide, polyetheretherketone, polyether nitrile, polycarbonate, polyphenylene ether polysulfone, polyether sulfone, polyarylate, polyether imide, etc. Can be used. The above resins may be used alone or in combination of two or more resins. In addition, an inorganic filler such as glass, talc, mica, silica, alumina or the like may be used in combination with the above resin.

  In the first embodiment, a manufacturing method using photosensitive polyimide as the second organic insulating layer 125 will be described.

  In the case where the second organic insulating layer 125 is applied, development is carried out after exposure using a photomask, and as shown in FIG. 17, a recess 282 is formed at a necessary position above the fourth conductive layer 122. . Here, the “required position” refers to a position where it is necessary to arrange a via for connecting the fourth conductive layer 122 to the wiring formed in the upper layer.

  After the formation of the recess 281, in order to cure the second organic insulating layer 125, a thermosetting process is performed at a temperature equal to or lower than the glass transition temperature of the second organic insulating layer 125. For example, in the case of using polyimide as the second organic insulating layer 125, if the glass transition temperature of the polyimide is 280 ° C., the temperature is 250 ° C. as described above. In addition, it is preferable to perform not only the process of thermosetting, but the heat processing after this process, as it does not exceed the glass transition temperature of a polyimide.

  Next, by plasma etching using the second organic insulating layer 125 as a mask, the third inorganic insulating layer 123 and the fourth inorganic insulating layer 124 at the bottom of the recess 282 are etched. As a method of plasma etching, a method similar to the method of etching the first inorganic insulating layer 113 and the second inorganic insulating layer 114 can be used. By etching the third inorganic insulating layer 123 and the fourth inorganic insulating layer 124, an opening 182 for filling the second via 192 electrically connecting the second wiring layer 120 and the third wiring layer 130 is formed. Ru. Thus, the structure shown in FIG. 18 can be obtained.

  Thereafter, the multilayer wiring structure shown in FIG. 1 can be obtained by repeating the method described in FIGS.

Second Embodiment
Hereinafter, a multilayer wiring structure according to a second embodiment of the present invention will be described in detail with reference to the drawings. FIG. 21 is a cross-sectional view of a multilayer wiring structure according to a second embodiment of the present invention. FIG. 21 is similar to FIG. 1, but the second wiring layer 120 and the fourth wiring layer 140 have no inorganic insulating layer formed thereon, and only the organic insulating layer is formed. Is different from FIG.

  In the structure shown in FIG. 21, at least the second organic insulating layer 125 and the fourth organic insulating layer 145 in which the inorganic insulating layer is not formed are for the conductive material included in the second wiring layer 120 and the fourth wiring layer 140. It is preferable to have barrier properties.

  Further, FIG. 21 exemplifies a structure in which only the organic insulating layer is formed on the second wiring layer 120 and the fourth wiring layer 140 without forming the inorganic insulating layer on those wiring layers, but the structure is limited to this structure. Alternatively, other wiring layers may have a structure in which only an organic insulating layer is formed without forming an inorganic insulating layer on the wiring layer. For example, the fifth inorganic insulating layer 133 and the sixth inorganic insulating layer 134 formed on the third wiring layer 130 are not formed, and only the third organic insulating layer 135 is formed on the third wiring layer 130. It may be However, if all the interlayer films of the multilayer wiring structure shown in FIG. 21 are formed of the organic insulating layer, the substrate is warped due to the stress of each layer. Therefore, it is desirable that at least one layer includes an inorganic insulating layer. Preferably, in addition to the first inorganic insulating layer 113 and the second inorganic insulating layer 114 covering the first wiring layer 110 on the intermediate layer 101, an interlayer film above the first interlayer film 119 (in FIG. It is desirable that at least one inorganic insulating layer be included in the four interlayer films (129, 139, 149).

  The multilayer wiring structure of the second embodiment includes the substrate 100, the insulating intermediate layer 101 disposed thereon, and the first structure disposed on the intermediate layer 101. A first wiring structure including the wiring layer 110 and the first interlayer film 119, a second wiring structure disposed above the first wiring structure and including the second wiring layer 120 and the second interlayer film 129, and a first wiring structure And a third wiring structure including the third wiring layer 130 and the third interlayer film 139.

  Here, the first interlayer film 119 includes the first inorganic insulating layer 113, the second inorganic insulating layer 114, and the first organic insulating layer 115. In addition, the second interlayer film 129 has a second organic insulating layer 125. In addition, the third interlayer film 139 has a fifth inorganic insulating layer 133, a sixth inorganic insulating layer 134, and a third organic insulating layer 135. The first wiring layer 110 and the second wiring layer 120 are connected by the first via 191, and the second wiring layer 120 and the third wiring layer 130 are connected by the second via 192.

  Although FIG. 21 illustrates a structure in which the first wiring structure, the second wiring structure, and the third wiring structure are sequentially stacked, the present invention is not limited to this structure. For example, the first wiring structure, the third wiring structure, and the second It may be laminated in the order of the wiring structure. Further, the second wiring structure and the third wiring structure may not be alternately stacked so as to be stacked in the order of the first wiring structure, the second wiring structure, the second wiring structure, and the third wiring structure.

  By having the above-described structure, the same effect as that of the first embodiment can be obtained, and the number of inorganic insulating layers is smaller than that of the first embodiment. Since the number of etching steps can be reduced, the cost can be reduced by reducing the number of steps.

  Hereinafter, the present invention will be specifically described based on Example 1 shown in FIG. 22, but the present invention is not limited to only these examples. FIG. 22 is a cross-sectional view of a multilayer wiring structure according to Embodiment 1 of the present invention. In the first embodiment, an example in which two wiring layers are further added to the multilayer wiring structure of the first embodiment to fabricate an eight-layer wiring structure will be described.

  First, a silicon substrate with a thickness of 400 μm was prepared as the substrate 100. Next, a 10 μm polyimide was formed as an insulating intermediate layer 101 on the substrate 100 by spin coating. The Young's modulus of the polyimide is 3 to 3.5 GPa, and the Young's modulus of the silicon substrate is about 185 GPa. That is, the intermediate layer 101 has a Young's modulus lower than that of the substrate 100. In other words, the intermediate layer 101 is softer than the substrate 100. In addition, polyimide has a barrier property to Cu used in a wiring layer described later. That is, polyimide has a slower diffusion rate of Cu than a silicon substrate.

  The first wiring layer 110 is formed on the intermediate layer 101. The first wiring layer 110 is formed by stacking Ti of 50 nm in thickness as the first conductive layer 111 and Cu of 4 μm in thickness as the second conductive layer 112. Here, Ti of the first conductive layer 111 has a barrier property to Cu of the second conductive layer 112. Also, the wiring pattern of the first wiring layer 110 can be formed with a line width of 10 to 100 μm.

  In Example 1 shown in FIG. 22, the second to seventh wiring layers (120, 130, 140, 150, 160, 170) are also formed with the same layered structure and pattern line width as the first wiring layer 110. That is, the third, fifth, seventh, ninth, eleventh, and thirteenth conductive layers (121, 131, 141, 151, 161, and 171) are formed of the same Ti as the first conductive layer 111, and fourth, sixth, eighth, and tenth , 12, 14 conductive layers (122, 132, 142, 152, 162, 172) are formed of the same Cu as the second conductive layer 112.

When the first wiring layer 110 is formed on the intermediate layer 101, a first interlayer film 119 is formed to cover them. The first interlayer film 119 is a 10 nm thick SiN film as the first inorganic insulating layer 113, a 2 μm thick SiO ₂ film as the second inorganic insulating layer 114, and a 12 μm thick polyimide as the first organic insulating layer 115. And a stack of layers. Here, the SiN film of the first inorganic insulating layer 113 and the SiO ₂ film of the second inorganic insulating layer 114 are formed using a plasma CVD method. Further, the polyimide of the first organic insulating layer 115 relieves or planarizes the step formed by the first wiring layer 110. That is, the polyimide film thickness 115 b of the first organic insulating layer 115 on the first wiring layer 110 is smaller than the polyimide film thickness 115 a of the first organic insulating layer 115 on the intermediate layer 101 where the first wiring layer 110 does not exist. It will be formed thin. In Example 1 shown in FIG. 22, the film thickness 115 a was 12 μm, and the film thickness 115 b was 8 μm, which is approximately the thickness of the first wiring layer 110.

Subsequently, an opening 181 is formed in the first interlayer film 119. The opening 181 has a diameter of 15 μm. First, the opening 181 is coated with photosensitive polyimide as the first organic insulating layer 115, exposed using a photomask, and then developed to form the lower second inorganic insulating layer 114 at the position where the opening 181 is provided. Form a recess that exposes the The photosensitive polyimide of the first organic insulating layer 115 was used as a mask to form the second inorganic insulating layer 114 exposed in the concave portion and the lower first inorganic insulating layer 113 by plasma etching. In etching the SiO ₂ film of the second inorganic insulating layer 114, a mixed gas of CF ₄ (flow rate 20 sccm) and H ₂ (flow rate 5 sccm) was used. In addition, a mixed gas of CF ₄ (flow rate 20 sccm) and O ₂ (flow rate ₂ sccm) was used to etch the SiN film of the first inorganic insulating layer 113.

  Subsequently, the second wiring layer 120 and the first via 191 are formed in the same step on the first interlayer film 119 and in the opening 181. Similarly to the first wiring layer 110, the second wiring layer 120 and the first via 191 are a stack of Ti of 50 nm in thickness as the third conductive layer 121 and Cu of 4 μm in thickness as the fourth conductive layer 122. Form. Here, Ti of the third conductive layer 121 has a barrier property to Cu of the fourth conductive layer 122. The inside of the opening 181 is covered with Ti of the third conductive layer 121, and is formed so as to isolate Cu of the fourth conductive layer 122 and the inside of the opening 181 of the first interlayer film 119.

  The diameter 191 a of the first via 191 is 15 μm, which is the same as the diameter of the opening 181, and the diameter 191 b of the land located above the first via 191 is 30 μm. Also, the via pitch indicating the distance between the centers of adjacent vias is 40 μm where the pitch is the smallest.

  As described above, the first wiring layer, the first interlayer film, and the first via are formed. Similarly to these, second to seventh wiring layers, an interlayer film, and second to sixth vias are formed. Then, the uppermost eighth wiring layer 380 and the seventh via 197 are formed in the same step in the opening 187 provided on the seventh interlayer film 179 and in the seventh interlayer film 179. The eighth wiring layer 380 is formed by laminating Cu with a thickness of 3 μm as the fifteenth conductive layer 381, Ni with a thickness of 1 μm as a sixteenth conductive layer 382, and Au with a thickness of 1 μm as a seventeenth conductive layer 383. Be done.

  As described above, according to the first embodiment, the heat treatment process is performed by isolating the substrate and the multilayer wiring structure between the substrate and the multilayer wiring structure and providing the insulating intermediate layer having the above-described features. Stress in a three-dimensional direction generated in the region where the wiring layer and the via overlap can be relaxed. Further, by providing the intermediate layer, the stress in the planar direction generated on the entire surface of the substrate by the heat treatment step can be relaxed. As a result, it is possible to suppress problems such as generation of cracks in the via and the inorganic insulating layer, and separation of the via and the wiring. Further, by providing an insulating intermediate layer having the above-described characteristics between the substrate and the multilayer wiring structure, it is possible to suppress the diffusion of Cu to the substrate in the heat treatment step. As a result, the problem of short circuit between the first wiring layer and the substrate can be suppressed. That is, it is possible to obtain a multilayer wiring structure of stacked via structure in which the above-mentioned problems are suppressed.

  In addition, this invention is not limited to said embodiment, It is possible to change suitably in the range which does not deviate from the meaning.

100: substrate 101: intermediate layer 110: first wiring layer 111: first conductive layer 112: second conductive layer 113: first inorganic insulating layer 114: second inorganic insulating layer 115: first organic insulating layer 119: first Interlayer films 120, 126, 127: second wiring layer 121: third conductive layer 122: fourth conductive layer 123: third inorganic insulating layer 124: fourth inorganic insulating layer 125: second organic insulating layer 129: second layer Film 130: third wiring layer 131: fifth conductive layer 132: sixth conductive layer 133: fifth inorganic insulating layer 134: sixth inorganic insulating layer 135: third organic insulating layer 139: third interlayer film 140: fourth Wiring layer 141: seventh conductive layer 142: eighth conductive layer 143: seventh inorganic insulating layer 144: eighth inorganic insulating layer 145: fourth organic insulating layer 149: fourth interlayer film 150: fifth wiring layer 151: fifth 9 conductive layer 152: tenth conductive layer 153: ninth inorganic Edge layer 154: tenth inorganic insulating layer 155: fifth organic insulating layer 159: fifth interlayer film 160: sixth wiring layer 161: eleventh conductive layer 162: twelfth conductive layer 163: thirteenth conductive layer 181, 182, 185: Opening 191: first via 192: second via 193: third via 194: fourth via 211: first conductive material 212: lower second conductive material 213: upper second conductive material 221: third conductive material 222: lower fourth conductive material 223: upper fourth conductive material 281, 282: recess 301: undercut 302: step 310, 320: resist pattern for forming wiring

Claims (5)

On a substrate having a multilayer wiring structure in which a plurality of wiring layers are the product layer,
The multilayer interconnection structure includes a plurality of vias that connect the adjacent wiring layers,
Separates the multilayer wiring structure from the substrate and includes an insulating intermediate layer disposed directly on the substrate and having a lower Young's modulus than the substrate;
Wherein the plurality of vias, and superposition with each other in a plan view,
The multilayer interconnection structure is in contact with the non-machine insulating layer, and the covered wiring layer, an organic insulating layer in contact with, and covered with a multilayer wiring structure in which the wiring layers are stacked alternately. On a substrate having a multilayer wiring structure in which a plurality of wiring layers are the product layer,
The multilayer interconnection structure includes a plurality of vias that connect the adjacent wiring layers,
Separates the multilayer wiring structure from the substrate and includes an insulating intermediate layer disposed directly on the substrate and having a thermal expansion coefficient higher than that of the substrate,
Wherein the plurality of vias, and superposition with each other in a plan view,
The multilayer interconnection structure is in contact with the non-machine insulating layer, and the covered wiring layer, an organic insulating layer in contact with, and covered with a multilayer wiring structure in which the wiring layers are stacked alternately. The multilayer wiring structure according to claim 1, wherein the diameters of at least any two of the plurality of vias are different. The multilayer wiring structure according to any one of claims 1 to 3 , wherein the intermediate layer is provided using polyimide as a material. The multilayer wiring structure according to any one of claims 1 to 4 , wherein a lowermost wiring layer of the plurality of wiring layers is in contact with the intermediate layer.

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