JP5164446B2 - 半導体素子の微細パターン形成方法 - Google Patents
半導体素子の微細パターン形成方法 Download PDFInfo
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- JP5164446B2 JP5164446B2 JP2007164583A JP2007164583A JP5164446B2 JP 5164446 B2 JP5164446 B2 JP 5164446B2 JP 2007164583 A JP2007164583 A JP 2007164583A JP 2007164583 A JP2007164583 A JP 2007164583A JP 5164446 B2 JP5164446 B2 JP 5164446B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
- H01L21/31122—Etching inorganic layers by chemical means by dry-etching of layers not containing Si, e.g. PZT, Al2O3
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Inorganic Chemistry (AREA)
- Plasma & Fusion (AREA)
- Drying Of Semiconductors (AREA)
Description
22 エッチング対象層
23 第1ポリマー層
24 第2ポリマー層
25 フォトレジストパターン
Claims (16)
- エッチング対象層上に炭素含有量が質量割合で80〜95%の範囲である第1ポリマー層を形成するステップと、
該第1ポリマー層上にシリコン含有量が質量割合で30〜45%の範囲である第2ポリマー層を形成するステップと、
第1の基板温度で前記第2ポリマー層をパターニングするステップと、
パターニングされた前記第2ポリマー層をエッチングマスクとして、O2ガスを含まない第1エッチングガスにより、−10℃〜30℃の範囲の第2の基板温度で前記第1ポリマー層をエッチングするステップと、
エッチングされた前記第1ポリマー層及びパターニングされた前記第2ポリマー層をエッチングマスクとして、前記エッチング対象層をエッチングするステップとを含むことを特徴とする半導体素子の微細パターン形成方法。 - 前記第1の基板温度が、−10℃〜30℃の範囲であることを特徴とする請求項1に記載の半導体素子の微細パターン形成方法。
- 前記第2ポリマー層を、フッ素系ガスを含む第2エッチングガスによりパターニングすることを特徴とする請求項1に記載の半導体素子の微細パターン形成方法。
- 前記第2エッチングガスとして、CF4ガス、CF4/CHF3混合ガス及びCF4/O2混合ガスからなるグループから選択された少なくとも1つのエッチングガスを用いることを特徴とする請求項3に記載の半導体素子の微細パターン形成方法。
- 前記第1エッチングガスとして、N2/H2混合ガス、N2/H2/CO混合ガス、N2/H2/C2H4混合ガス、N2/H2/CH4混合ガス又はこれら混合ガスの少なくとも2つの混合ガスを用いることを特徴とする請求項1に記載の半導体素子の微細パターン形成方法。
- 前記N2/H2混合ガス、N2/H2/CO混合ガス、N2/H2/C2H4混合ガス、N2/H2/CH4混合ガス又はこれら混合ガスの少なくとも2つの混合ガスにおいて、
N2とH2とが、体積割合で、1:2〜1:4の範囲であり、C2H4又はCH4を含む場合、それらの流量が10sccm以下であることを特徴とする請求項5に記載の半導体素子の微細パターン形成方法。 - 前記第1ポリマー層及び前記第2ポリマー層を、
回転塗布法によって形成することを特徴とする請求項1に記載の半導体素子の微細パターン形成方法。 - 前記第2ポリマー層が、
シロキサン又はシルセスキオキサンを含むことを特徴とする請求項1に記載の半導体素子の微細パターン形成方法。 - 基板上にエッチング対象層を形成するステップと、
該エッチング対象層上に、炭素含有量が質量割合で80〜95%の範囲である第1ポリマー層を形成するステップと、
該第1ポリマー層上に、シリコン含有量が質量割合で30〜45%の範囲である第2ポリマー層を形成するステップと、
該第2ポリマー層上に、感光膜パターンを形成するステップと、
該感光膜パターンをエッチングマスクとして、第1の基板温度で前記第2ポリマー層をエッチングするステップと、
O2ガスを含まない第1エッチングガスにより、−10℃〜30℃の範囲の第2の基板温度で前記第1ポリマー層をエッチングするステップと、
エッチングされた前記第1ポリマー層及びエッチングされた前記第2ポリマー層をエッチングマスクとして、前記エッチング対象層をエッチングするステップとを含むことを特徴とする半導体素子の微細パターン形成方法。 - 前記第1の基板温度が、−10℃〜30℃の範囲であることを特徴とする請求項9に記載の半導体素子の微細パターン形成方法。
- 前記第2ポリマー層を、フッ素系ガスを含む第2エッチングガスによりエッチングすることを特徴とする請求項9に記載の半導体素子の微細パターン形成方法。
- 前記第2エッチングガスとして、CF4ガス、CF4/CHF3混合ガス及びCF4/O2混合ガスからなるグループから選択された少なくとも1つのエッチングガスを用いることを特徴とする請求項11に記載の半導体素子の微細パターン形成方法。
- 前記第1エッチングガスとして、
N2/H2混合ガス、N2/H2/CO混合ガス、N2/H2/C2H4混合ガス、N2/H2/CH4混合ガス又はこれら混合ガスの少なくとも2つの混合ガスを用いることを特徴とする請求項9に記載の半導体素子の微細パターン形成方法。 - 前記N2/H2混合ガス、N2/H2/CO混合ガス、N2/H2/C2H4混合ガス、N2/H2/CH4混合ガス又はこれら混合ガスの少なくとも2つの混合ガスにおいて、
N2とH2とが、体積割合で、1:2〜1:4の範囲であり、C2H4又はCH4を含む場合、それらの流量が10sccm以下であることを特徴とする請求項13に記載の半導体素子の微細パターン形成方法。 - エッチングされた第2ポリマー層をエッチングマスクとして、前記第1ポリマー層をエッチングすることを特徴とする請求項9に記載の半導体素子の微細パターン形成方法。
- 前記第2ポリマー層が、
シロキサン又はシルセスキオキサンを含むことを特徴とする請求項9に記載の半導体素子の微細パターン形成方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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KR1020060061421A KR100875653B1 (ko) | 2006-06-30 | 2006-06-30 | 반도체 소자의 미세 패턴 형성 방법 |
KR10-2006-0061421 | 2006-06-30 |
Publications (2)
Publication Number | Publication Date |
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JP2008016839A JP2008016839A (ja) | 2008-01-24 |
JP5164446B2 true JP5164446B2 (ja) | 2013-03-21 |
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JP2007164583A Expired - Fee Related JP5164446B2 (ja) | 2006-06-30 | 2007-06-22 | 半導体素子の微細パターン形成方法 |
Country Status (5)
Country | Link |
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US (1) | US7589026B2 (ja) |
JP (1) | JP5164446B2 (ja) |
KR (1) | KR100875653B1 (ja) |
CN (1) | CN101097843B (ja) |
TW (1) | TWI335048B (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2010141257A2 (en) * | 2009-06-03 | 2010-12-09 | Applied Materials, Inc. | Method and apparatus for etching |
US8901004B2 (en) * | 2009-07-27 | 2014-12-02 | Lam Research Corporation | Plasma etch method to reduce micro-loading |
CN109994379B (zh) * | 2017-12-29 | 2021-10-19 | 长鑫存储技术有限公司 | 双重图形化方法及双重图形化结构 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS60170238A (ja) * | 1984-02-15 | 1985-09-03 | Toyota Central Res & Dev Lab Inc | ドライエツチング方法 |
JPH0319335A (ja) * | 1989-06-16 | 1991-01-28 | Fujitsu Ltd | パターン形成方法 |
US5423945A (en) * | 1992-09-08 | 1995-06-13 | Applied Materials, Inc. | Selectivity for etching an oxide over a nitride |
JPH09270419A (ja) * | 1996-04-01 | 1997-10-14 | Sony Corp | プラズマエッチング方法 |
US5920796A (en) * | 1997-09-05 | 1999-07-06 | Advanced Micro Devices, Inc. | In-situ etch of BARC layer during formation of local interconnects |
US6949203B2 (en) * | 1999-12-28 | 2005-09-27 | Applied Materials, Inc. | System level in-situ integrated dielectric etch process particularly useful for copper dual damascene |
US6573030B1 (en) * | 2000-02-17 | 2003-06-03 | Applied Materials, Inc. | Method for depositing an amorphous carbon layer |
JP3403372B2 (ja) * | 2000-05-26 | 2003-05-06 | 松下電器産業株式会社 | 有機膜のエッチング方法、半導体装置の製造方法及びパターンの形成方法 |
JP3971088B2 (ja) * | 2000-06-30 | 2007-09-05 | 株式会社東芝 | パターン形成方法 |
KR100436220B1 (ko) * | 2001-08-30 | 2004-06-12 | 주식회사 네패스 | 바닥 반사방지막용 유기 중합체, 그의 제조방법 및 그를함유하는 조성물 |
KR100425467B1 (ko) * | 2001-09-29 | 2004-03-30 | 삼성전자주식회사 | 반도체소자를 위한 건식 식각방법 |
US20040018742A1 (en) * | 2002-07-25 | 2004-01-29 | Applied Materials, Inc. | Forming bilayer resist patterns |
US6787453B2 (en) * | 2002-12-23 | 2004-09-07 | Intel Corporation | Barrier film integrity on porous low k dielectrics by application of a hydrocarbon plasma treatment |
KR101155841B1 (ko) * | 2003-03-03 | 2012-06-20 | 램 리써치 코포레이션 | 이중 도핑된 게이트 애플리케이션에서 프로파일 제어 및n/p 로딩을 개선하는 방법 |
KR100510558B1 (ko) | 2003-12-13 | 2005-08-26 | 삼성전자주식회사 | 패턴 형성 방법 |
KR20060019668A (ko) | 2004-08-28 | 2006-03-06 | 엘지전자 주식회사 | 2층 하드마스크를 이용한 실리콘온인슐레이터 웨이퍼의식각방법 |
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2006
- 2006-06-30 KR KR1020060061421A patent/KR100875653B1/ko not_active IP Right Cessation
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2007
- 2007-04-30 TW TW096115226A patent/TWI335048B/zh not_active IP Right Cessation
- 2007-05-03 US US11/743,669 patent/US7589026B2/en not_active Expired - Fee Related
- 2007-06-22 JP JP2007164583A patent/JP5164446B2/ja not_active Expired - Fee Related
- 2007-06-22 CN CN2007101230405A patent/CN101097843B/zh not_active Expired - Fee Related
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Publication number | Publication date |
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TW200802539A (en) | 2008-01-01 |
US20080003834A1 (en) | 2008-01-03 |
JP2008016839A (ja) | 2008-01-24 |
CN101097843B (zh) | 2010-09-08 |
KR100875653B1 (ko) | 2008-12-26 |
US7589026B2 (en) | 2009-09-15 |
KR20080002536A (ko) | 2008-01-04 |
TWI335048B (en) | 2010-12-21 |
CN101097843A (zh) | 2008-01-02 |
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