JP5131321B2 - Switching power supply - Google Patents

Description

  The present invention relates to a switching power supply device that is highly efficient and has a high response speed. For example, the present invention relates to a ripple mode switching power supply device that performs output control based on a comparison between an output ripple component and a threshold value.

  With the rapid spread of mobile devices typified by mobile phones, the performance required for switching power supply devices for mobile devices is becoming increasingly severe. Technological development of a switching power supply device that operates at a low voltage, is highly efficient, has a quick response, and has a small number of components is being actively carried out.

FIG. 17 is a diagram illustrating a configuration example of a general voltage mode switching power supply device.
In the example of FIG. 17, the MOS transistors MH and ML, the inductor Lo, and the capacitor Co constitute a step-down converter. The step-down converter generates an output voltage Vo lower than the input voltage Vin by alternately turning on the high-side MOS transistor MH and the low-side MOS transistor ML. When a current flows continuously in the inductor Lo, an output voltage Vo that is substantially proportional to the duty ratio of the high-side MOS transistor MH (ratio of on-time to switching period) is obtained.

Resistors R31 to R34, capacitors C31 to C33, and operational amplifier 101 constitute an error amplification circuit. The error amplification circuit amplifies an error between the reference voltage Vref and VFB corresponding to the output voltage Vout. The comparator 102 compares the error signal output from the error amplifier circuit with the triangular wave signal output from the triangular wave generator 103, and generates a PWM signal corresponding to the comparison result. The pulse width of the PWM signal changes according to the level of the error signal. The gate drive circuit 105 has a low side driver that drives the gate of the MOS transistor ML and a high side driver that drives the gate of the MOS transistor MH. The low-side driver generates a gate drive voltage according to the PWM signal, and the high-side driver generates a drive voltage according to a signal obtained by inverting the PWM signal by the inverter 104.
With the above configuration, when the error between the output voltage Vout and the reference voltage Vref increases, the duty ratio of the MOS transistor MH is adjusted so as to reduce the error.

  In the voltage mode switching power supply, the loop gain in the high band is set to be relatively low in order to prevent the feedback control system from becoming unstable due to the phase delay caused by the resonance frequency of the inductor Lo and the capacitor Co. Therefore, the response speed is generally slow. In recent years, in order to reduce power consumption, a method of dynamically changing a power supply voltage according to an operation state of a device has been widely adopted, and a high-speed response is required for a switching power supply device. . However, since the voltage mode method has the above-described circumstances, it is not possible to sufficiently meet the demand for high speed. Further, since the resistors R33 to R34 and the capacitors C31 to C33 must be provided as single components (discrete components) for phase compensation, there is a disadvantage that the substrate area is increased and the mounting cost is increased, and appropriate elements thereof. There is also the disadvantage that it takes a lot of man-hours to evaluate the value.

  As a method for overcoming the above-described drawbacks of the voltage mode method, a ripple mode method is known (see Non-Patent Document 1). The ripple mode method is also called Bang-Bang control, hysteresis PWM control, D-cap mode, or the like.

FIG. 18 is a diagram illustrating a configuration example of a general ripple mode switching power supply device.
The series circuit of the resistors R31 and R32 divides the output voltage Vout and inputs it to the comparator 102 as the output feedback voltage VFB. The comparator 102 compares the output feedback voltage VFB and the reference voltage Vref, and outputs “1” when the output feedback voltage VFB becomes lower than the reference voltage Vref, and outputs “0” when the output feedback voltage Vref becomes higher than the reference voltage Vref. The control circuit 106 generates a control signal for turning on the MOS transistor MH and turning off the MOS transistor ML for a predetermined time when the output of the comparator 102 changes from “0” to “1”.

  When the MOS transistor MH is turned on and the MOS transistor ML is turned off, a voltage (Vin−Vout) is applied to the inductor Lo, so that the current flowing through the inductor Lo increases linearly. On the other hand, when the MOS transistor MH is turned off and the MOS transistor ML is turned on, the output voltage Vout having the opposite polarity to the above is applied to the inductor Lo, so that the current flowing through the inductor Lo decreases linearly. That is, a triangular wave ripple current flows through the inductor Lo. When this ripple current flows through an equivalent series resistance ESR (equivalent series resistance) of the capacitor Co, a ripple voltage similar to the ripple current is superimposed on the output voltage Vo. In the ripple mode type switching power supply device shown in FIG. 18, feedback control works so that the bottom of the ripple component superimposed on the output feedback voltage VFB and the reference voltage Vref are substantially equal in a steady state. The ripple mode method does not require phase compensation like the voltage mode method, and can realize a high-speed load response.

  However, in order to stably operate the control system in the ripple mode method, the output feedback voltage VFB must include a ripple component having an appropriate amplitude. When the ripple component of the output voltage Vout is “Vorp” and the resistance values of the resistors R31 and R32 are “r31” and “r32”, respectively, the ripple component Vfrp of the output feedback voltage VFB is expressed by the following equation.

(Equation 1)
Vfrp = Vorp × (r31 / (r31 + r32)) (1)

In order to increase the ripple component Vfrp of the output feedback voltage VFB in the ripple mode system shown in FIG. 18, for example, a method of changing the resistance ratio of the resistors R31 and R32 or connecting a capacitor in parallel with the resistor R32 is considered. It is done. However, if there is still a limit, the ripple component Vorp itself of the output voltage Vout must be increased.
The operating voltage of LSIs such as memories and CPUs has been decreasing year by year in order to reduce power consumption, and the output voltage required for the power supply system is becoming less than 1V. In such a situation, increasing the ripple component of the power supply voltage leads to a reduction in the operating margin of the LSI, which is not preferable from the viewpoint of system reliability.
Takashi Nabeshima et al., “Control characteristics of step-down converter by hysteresis PWM control using CR integration circuit”, IEICE Transactions, The Institute of Electronics, Information and Communication Engineers, May 2006, Vol. J89-B, no. 5, p. 664-672

  As a method for realizing stable feedback control without increasing the ripple component itself of the output voltage in the ripple mode method, for example, a method using a CR integration circuit as described in Non-Patent Document 1 is known. In this method, a signal similar to the ripple current flowing in the inductor Lo is extracted by a CR integration circuit connected in parallel with the inductor Lo, and this signal is superimposed on the output feedback voltage.

FIG. 19 is a diagram illustrating a configuration example of a ripple mode type switching power supply apparatus using a ripple signal extracted by a CR integration circuit.
In the switching power supply device shown in FIG. 19, a CR integration circuit including a series circuit of a resistor R35 and a capacitor C35 is connected in parallel with the inductor Lo. A ripple voltage similar to the ripple current flowing through the inductor Lo is generated in the capacitor C35. Since the connection node between the resistor R35 and the capacitor C35 is connected to the connection node between the resistors R31 and R32 via the capacitor C34, the ripple voltage generated in the capacitor C35 is superimposed on the output feedback voltage VFB.

FIG. 20 is a diagram illustrating signal waveforms at various parts in the switching power supply device shown in FIG.
Even when the ripple voltage of the output voltage Vout is relatively small (FIG. 20B), a ripple voltage Vrp having a sufficient amplitude can be obtained in the output feedback voltage VFB (FIG. 20C). When the bottom of the output feedback voltage VFB becomes lower than the reference voltage Vref, the gate-source voltage Vgs of the MOS transistor MH becomes high level for a certain time (FIG. 20A).

  The switching power supply device shown in FIG. 19 can stabilize the operation of the control system even when the ripple voltage of the output voltage Vout is relatively small by superimposing the ripple voltage Vrp having an appropriate amplitude on the output feedback voltage VFB. Has the advantage.

By the way, in the ripple mode method, since the control is performed so that the peak and bottom of the ripple component coincide with the reference voltage Vref, the amplitude of the ripple voltage Vrp cannot be increased so much. If the amplitude of the ripple voltage Vrp is too large, the difference between the DC level specified by the reference voltage Vref and the DC level of the actual output voltage Vout becomes large, which is disadvantageous in ensuring the DC accuracy of the output voltage Vout. Because it becomes. Therefore, the amplitude of the ripple voltage Vrp must be set within an appropriate range in consideration of the accuracy required for the output voltage Vout. However, in this case, the time constant of the CR integration circuit (R35, C35) may have to be made relatively large due to the balance with the switching frequency. When the capacitance of the capacitor is, for example, about several thousand pF, it is difficult to form the capacitor on the semiconductor chip, and it is necessary to mount it on the substrate as a discrete component.
In general, the switching power supply device shown in FIG. 19 has disadvantages such as an increase in substrate area and an increase in component mounting cost because the resistor R35 and capacitors C34 and C35 must be mounted on the substrate as discrete components.

  The present invention has been made in view of such circumstances, and an object thereof is to provide a ripple mode type switching power supply device capable of obtaining a ripple component having a required amplitude without using discrete components.

The switching power supply according to the present invention includes an input terminal that receives an input voltage, an output terminal that outputs an output voltage, a first switching transistor connected between the input terminal and a first node, and the first A second switching transistor connected between the first node and a reference potential and operating in a complementary manner with the first switching transistor; and an inductance element connected between the first node and the output terminal. An output capacitance element connected between the output terminal and a reference potential, a voltage dividing circuit connected to the output terminal and generating a feedback voltage according to the output voltage, and included in the output voltage. A ripple voltage detection circuit for detecting a ripple voltage corresponding to the switching operation of the switching transistor, and the feedback A comparison circuit that compares the sum voltage of the voltage and the ripple voltage with a reference voltage and outputs a comparison result; and a control circuit that controls on and off of the first and second switching transistors according to the comparison result; including. The ripple voltage detection circuit includes an integration circuit connected to the inductance element, and the on-time of the first switching transistor is a ratio between the output voltage and the input voltage, and the first and second switching transistors. Defined by the product of the switching period .

Preferably, the integration circuit may include a resistance element and a capacitance element connected in series between the first node and the output terminal.
The circuit further includes a voltage-current conversion circuit that inputs the ripple voltage and outputs a current signal corresponding to the ripple voltage, and the comparison circuit includes a first resistance element for converting the current signal into a voltage signal; And a differential circuit for comparing a sum voltage of the feedback voltage and the voltage signal with the reference voltage.

Further, the comparison circuit includes a first buffer circuit for inputting the feedback voltage, a second buffer circuit for inputting the reference voltage, and a second resistor coupled to the output of the second buffer circuit. The feedback voltage is supplied to the first input of the differential circuit via the first buffer circuit and the first resistance element, and the reference voltage is the second voltage. The voltage is supplied to the second input of the differential circuit via the buffer circuit and the second resistance element, and the voltage is applied to the connection midpoint between the first input of the differential circuit and the first resistance element. The first current is supplied from the current conversion circuit, and the second current is supplied from the voltage-current conversion circuit to the midpoint of connection between the output of the second buffer circuit and the second resistance element. Good.

Preferably, a differential amplifier circuit including a first transistor that inputs a voltage of one terminal of the capacitance element, and a second transistor that inputs a voltage of the other terminal of the capacitance element, and the first transistor A first current source circuit that outputs the first current corresponding to the current flowing through the transistor; and a second current source circuit that outputs the second current corresponding to the current flowing through the second transistor. May include.

  According to the present invention, by converting the amplitude of the ripple voltage generated in the capacitor of the integration circuit to generate a ripple signal, a ripple mode method capable of obtaining a ripple component having a required amplitude without using discrete components. A switching power supply device can be provided.

It is a figure which shows an example of a structure of the switching power supply device which concerns on 1st Embodiment. It is a figure which shows an example of a structure of a voltage current conversion circuit. It is a figure which shows an example of a structure of the comparator in the switching power supply device shown in FIG. It is a figure which illustrates the waveform of the voltage which arises in CR integration circuit, and the electric current of a voltage current conversion circuit. It is a figure which illustrates the signal waveform of each part of the comparator shown in FIG. It is a figure which shows an example of a structure of the switching power supply device which concerns on 2nd Embodiment. It is a figure which shows an example of a structure of the switching power supply device which concerns on 3rd Embodiment. It is a figure which shows an example of a structure of the switching power supply device which concerns on 4th Embodiment. It is a figure which shows an example of a structure of the ripple signal generation circuit in the switching power supply device shown in FIG. It is a figure which illustrates the relationship between the synthesized signal and reference voltage in the switching power supply device shown in FIG. It is a figure which shows an example of a structure of the switching power supply device which concerns on 5th Embodiment. It is a figure which shows an example of a structure of the comparator in the switching power supply device shown in FIG. The figure which shows an example of a structure of the switching power supply device which concerns on 6th Embodiment It is a figure which shows one structural example of the ripple signal generation circuit in the switching power supply device shown in FIG. It is a figure which illustrates the relationship between the synthetic | combination signal and output feedback voltage in the switching power supply device shown in FIG. It is a figure which shows the other structural example of the ripple signal generation circuit in the switching power supply device shown in FIG. It is a figure which shows the structural example of the switching power supply device of a general voltage mode system. It is a figure which shows the structural example of the switching power supply device of a general ripple mode system. It is a figure which shows the structural example of the switching power supply device of the ripple mode system which uses the ripple signal taken out by CR integration circuit. It is a figure which illustrates the signal waveform of each part in the switching power supply device shown in FIG.

<First Embodiment>
FIG. 1 is a diagram illustrating an example of a configuration of a switching power supply device according to a first embodiment of the present invention.
The switching power supply device shown in FIG. 1 includes a ripple signal generation circuit 1, a comparator 2, a control circuit 3, a drive circuit 4, resistors Rf1 and Rf2 for voltage feedback, n-type MOS transistors ML and MH, It has an inductor Lo and a capacitor Co. The ripple signal generation circuit 1 includes a CR integration circuit 11 composed of a series circuit of a capacitor Ci and a resistor Ri, and a voltage / current conversion circuit 12.
Capacitor Co is an embodiment of the first capacitor in the present invention.
The inductor Lo is an embodiment of the inductor in the present invention.
MOS transistors ML and MH are an embodiment of the switching circuit in the present invention.
The ripple signal generation circuit 1 is an embodiment of the ripple signal generation circuit in the present invention.
The comparator 2 is an embodiment of the comparison circuit in the present invention.
The control circuit 3 is an embodiment of the control circuit in the present invention.
The CR integration circuit 11 is an embodiment of the integration circuit in the present invention.
The capacitor Ci is an embodiment of the second capacitor in the present invention.
The voltage-current conversion circuit 12 is an embodiment of the voltage-current conversion circuit in the present invention.

  The MOS transistor ML is connected between the node Nsw and the reference potential G, and the MOS transistor MH is connected between the supply line of the input voltage Vin and the node Nsw. The drive circuit 4 drives the gate of the MOS transistor ML according to the control signal SL, and drives the gate of the MOS transistor MH according to the control signal SH.

The inductor Lo is connected between the node Nsw and the node Nout. The capacitor Co is connected between the node Nout and the reference potential G. The capacitor Co has an equivalent series resistance ESR.
A load RL is connected to the node Nout. The load RL represents an electronic circuit such as an LSI that operates by receiving the voltage Vout generated at the node Nout, for example.

  The resistors Rf1 and Rf2 are connected in series between the node Nout and the reference potential G. The resistor Rf1 is connected between the node Nfb and the reference potential G, and the resistor Rf2 is connected between the node Nout and the node Nfb. At node Nfb, output feedback voltage VFB is generated by dividing output voltage Vout by a series circuit of resistors Rf1 and Rf2.

The CR integration circuit 11 is configured by a series circuit of a resistor Ri and a capacitor Ci, and is connected in parallel with the inductor Lo. The resistor Ri is connected between the node Nsw and the node Nci, and the capacitor Ci is connected between the node Nci and the node Nout.
When one cycle period of switching by the MOS transistors ML and MH is sufficiently shorter than the time constant of the CR integration circuit 11, the change in the voltage of the capacitor Ci (that is, the amplitude of the ripple voltage of the capacitor Ci) in this one cycle period is an inductor. The amplitude of the square wave voltage applied to Lo is sufficiently small and can be ignored. In this case, the current flowing through the resistor Ri is substantially proportional to the voltage applied to the inductor Lo. Since the capacitor Ci is charged and discharged by the current flowing through the resistor Ri, the voltage generated in the capacitor Ci is substantially proportional to the integrated value of the voltage applied to the inductor Lo. Here, since the current flowing through the inductor Lo is proportional to the integral value of the voltage applied to the inductor Lo, the waveform of the ripple voltage generated in the capacitor Ci is similar to the waveform of the ripple current flowing through the inductor Lo.

  The voltage-current conversion circuit 12 is a circuit that converts a voltage generated in the capacitor Ci into a current, and generates a current Iq corresponding to a product of the voltage generated in the capacitor Ci and a predetermined mutual conductance gm, for example, as shown in the following equation. To do.

(Equation 2)
Iq = (Vci−Vout) × gm = Vid × gm (2)

FIG. 2 is a diagram illustrating an example of the configuration of the voltage / current conversion circuit 12.
The voltage-current conversion circuit 12 shown in FIG. 2 includes p-type MOS transistors M1 to M6, n-type MOS transistors M7 to M10, npn transistors Q1 and Q2, resistors R1 and R2, and a current source CS1.

The emitter of npn transistor Q1 is connected to node Nm via resistor R1, its collector is connected to the drain of MOS transistor M1, and its base is connected to node Nout. The emitter of npn transistor Q2 is connected to node Nm via resistor R2, its collector is connected to the drain of MOS transistor M2, and its base is connected to node Nci.
The current source CS1 is connected between the node Nm and the reference potential G.
The sources of the MOS transistors M1 to M6 are connected to the power supply line Vdd. The gate and drain of the MOS transistor M1 are connected in common, and the gates of the MOS transistors M3 and M4 are connected to the gate of the MOS transistor M1. The gate and drain of the MOS transistor M2 are connected in common, and the gates of the MOS transistors M5 and M6 are connected to the gate of the MOS transistor M2. The drain of the MOS transistor M3 is connected to the drain of the MOS transistor M7. The drain of the MOS transistor M4 is connected to the drain of the MOS transistor M8.
The sources of the MOS transistors M7 to M10 are connected to the reference potential G. The gate and drain of the MOS transistor M7 are connected in common, and the gate of the MOS transistor M9 is connected to the gate of the MOS transistor M7. The gate and drain of the MOS transistor M8 are connected in common, and the gate of the MOS transistor M10 is connected to the gate of the MOS transistor M8. The drain of the MOS transistor M9 and the drain of the MOS transistor M5 are commonly connected to the node N1. The drain of the MOS transistor M10 and the drain of the MOS transistor M6 are commonly connected to the node N4.

  The voltage Vci is applied to the base of the npn transistor Q2, and the voltage Vout is applied to the base of the npn transistor Q1. A current difference corresponding to the voltage difference Vid (= Vci−Vout) is generated in the collector currents of the npn transistors Q1 and Q2 forming a pair.

The MOS transistors M1, M3, M4, M7, M8, M9, and M10 constitute a current mirror circuit, and the drain currents of the MOS transistors M9 and M10 are proportional to the drain current of the MOS transistor M1. On the other hand, the MOS transistors M2, M5, and M6 constitute a current mirror circuit, and the drain currents of the MOS transistors M5 and M6 are proportional to the drain current of the MOS transistor M2.
Here, if the drain currents of the MOS transistors M9 and M10 and the drain current of the MOS transistor M1 are equal, and the drain currents of the MOS transistors M5 and M6 and the drain current of the MOS transistor M2 are equal, the voltages from the nodes N1 and N2 respectively. A current Iq corresponding to the difference Vid is output.
The mutual conductance gm of the voltage-current conversion circuit 12 shown in FIG.

(Equation 3)
gm = 1 / [r1 + (0.026 × 2 / Ics2)] (3)

In Expression (3), “r1” indicates the resistance values of the resistors R1 and R2, and “Ics2” indicates the current value of the current source CS2.
The above is the description of the voltage-current conversion circuit 12.

  The comparator 2 compares the combined signal of the ripple signal of the capacitor Ci taken out by the voltage-current conversion circuit 12 and the output feedback voltage VFB corresponding to the output voltage Vout with the reference voltage Vref, and generates a signal Scp corresponding to the comparison result. Output. In the comparator 2, the current Iq of the voltage-current conversion circuit 12 is injected into a resistor provided in the transmission path of the output feedback voltage VFB, and a synthesized signal of the output feedback voltage VFB and the ripple signal generated thereby is referred to Compare with voltage Vref.

FIG. 3 is a diagram illustrating an example of the configuration of the comparator 2.
The comparator 2 shown in FIG. 1 includes pnp transistors Q3 and Q4, npn transistors Q5 and Q6, resistors R3 and R4, current sources CS2 to CS6, and an output amplifier circuit 21.
The circuit including the pnp transistor Q3 and the current source CS3 is an embodiment of the first buffer circuit in the present invention.
The circuit including the pnp transistor Q4 and the current source CS4 is an embodiment of the second buffer circuit in the present invention.
A circuit including npn transistors Q5 and Q6 and current sources CS2, CS5 and CS6 is an embodiment of the amplification stage in the present invention.
The resistor R3 is an embodiment of the first resistor in the present invention.

The collectors of the pnp transistors Q3 and Q4 are connected to the reference potential G. The emitter of the pnp transistor Q3 is connected to the power supply line Vdd via the current source CS3, and its base is connected to the node Nfb. The emitter of the pnp transistor Q4 is connected to the power supply line Vdd via the current source CS4, and the reference voltage Vref is input to its base.
The emitters of npn transistors Q5 and Q6 are connected in common, and current source CS2 is connected between the emitter and reference potential G. The collector of npn transistor Q5 is connected to power supply line Vdd via current source CS5, and its base is connected to the emitter of pnp transistor Q3 via resistor R3. The collector of npn transistor Q6 is connected to power supply line Vdd via current source CS6, and its base is connected to the emitter of pnp transistor Q4 via resistor R4.
In FIG. 3, node N1 represents the emitter of pnp transistor Q3, node N2 represents the emitter of pnp transistor Q4, node N3 represents the base of npn transistor Q5, and node N4 represents the base of npn transistor Q6.

  The output amplifier circuit 21 amplifies the difference between the collector voltages of the npn transistors Q5 and Q6 and generates a signal Scp having a high level or a low level.

  The pnp transistor Q3 and the current source CS3 constitute a buffer circuit (emitter follower circuit) having a high input impedance and a low output impedance. At the emitter (node N1) of the pnp transistor Q3, a voltage Vn1 obtained by level shifting the output feedback voltage VFB by a substantially constant base-emitter voltage is generated. The pnp transistor Q4 and the current source CS4 also form a similar buffer circuit (emitter follower circuit), and a voltage Vn2 obtained by level shifting the reference voltage Vref is generated at the emitter (node N2) of the pnp transistor Q4.

Output voltages Vn1 and Vn2 of the two buffer circuits described above are input to a differential amplifier circuit composed of npn transistors Q5 and Q6 and current sources CS2, CS5 and CS6. The differential amplifier circuit amplifies the difference between the voltages input to the bases of the npn transistors Q5 and Q6, and outputs the amplified difference as the collector voltage difference.
When the injection of the current Iq is not considered, in this differential amplifier circuit, the voltage difference between the voltages Vn1 and Vn2, that is, the voltage difference between the output feedback voltage VFB and the reference voltage Vref is amplified.

  In the comparator 2 shown in FIG. 3, a resistor R3 is provided on the path for transmitting the voltage Vn1 from the buffer circuit (Q3, CS3) to the differential amplifier circuit. A transistor Q5 is connected to the resistor R3. Current Iq is injected from the base side (node N3 side). When the base resistance of the npn transistor Q5 is sufficiently large, most of the current Iq flows to the buffer circuit (Q3, CS3) via the resistor R3, so that a voltage corresponding to the current Iq is generated at both ends of the resistor R3. A voltage Vn3 obtained by adding the voltage generated at the resistor R3 and the voltage Vn1 at the node N1 is input to the base of the npn transistor Q5.

On the other hand, a resistor R4 is also provided in a path for transmitting the voltage Vn2 from the buffer circuit (Q4, CS4) to the differential amplifier circuit. In this path, the output side of the buffer circuit, that is, the emitter of the pnp transistor Q4 ( Current Iq is injected into node N2).
By injecting the current Iq into the node N2, the equivalent current Iq is injected into the two buffer circuits described above. As a result, the direct current balance of the emitter currents of the pnp transistors Q3 and Q4 is improved, and the unbalance between the base-emitter voltages of both is reduced, so that the effect of reducing the input offset voltage is obtained.

  Since the output impedance of the buffer circuit (Q4, CS4) is sufficiently smaller than the base of the npn transistor Q6, most of the current Iq injected into the node N2 does not flow to the resistor R4 but to the buffer circuit (Q4, CS4). Flowing. When the base current of npn transistor Q6 is ignored, voltage Vn4 input to the base of npn transistor Q6 is substantially equal to voltage Vn2 of node N2. That is, the voltage Vn4 on which the ripple signal due to the current Iq is not superimposed is input to the base of the npn transistor Q6.

As described above, in the differential amplifier circuit including the npn transistors Q5 and Q6, the difference between the voltage Vn3 on which the ripple signal due to the current Iq is superimposed and the voltage Vn4 on which the ripple signal is not superimposed is amplified. The amplification result is further amplified in the output amplifier circuit 21, thereby generating a logic signal Scp.
The above is the description of the comparator 2.

  The control circuit 3 generates control signals SL and SH for controlling on / off of the MOS transistors ML and MH according to the signal Sp output from the comparator 2. For example, when the control circuit 3 receives the signal Sp of the comparator 2 indicating that the voltage Vn3 on which the ripple signal is superimposed is lower than the voltage Vn4, the control circuit 3 turns on the MOS transistor MH and turns off the MOS transistor ML for a certain time. Signals SL and SH are generated. Thereby, in a steady state, the output voltage Vout is controlled so that the bottom of the voltage Vn3 is substantially equal to the voltage Vn4. For example, assuming that the switching cycle is T, the input voltage is Vin, the output voltage is Vout, and the on period of the transistor MH (the off period of the transistor HL) is Ton, the relational expression Ton = T · (Vout / Vin) holds. .

  Here, the operation of the switching power supply device having the above-described configuration will be described.

FIG. 4 is a diagram illustrating waveforms of the voltage Vci generated in the CR integration circuit 11 and the current Iq of the voltage / current conversion circuit 12.
For example, the MOS transistor MH is periodically turned on in response to a gate-source voltage Vgs as shown in FIG. 4A, and the MOS transistor ML is turned off in synchronization with the ON period of the MOS transistor MH. When the MOS transistors ML and MH are alternately turned on, the voltage waveform of the inductor Lo becomes a square wave.

When the switching cycle of the MOS transistors ML and MH is sufficiently shorter than the time constant of the CR integration circuit 11, the current charging / discharging the capacitor Ci through the resistor Ri is similar to the square wave voltage of the inductor Lo. In this case, a ripple voltage Vrc similar to the ripple current flowing through the inductor Lo is generated in the capacitor Ci.
Ripple voltage Vrc is generally expressed by the following equation.

(Equation 4)
Vrc = (VL / r3) × (1 / c2) × (Vout / Vin) × (1 / fs) (4)

  In Expression (4), “VL” represents the voltage (Vin−Vout) of the inductor Lo, and “fs” represents the switching frequency.

  As shown in FIG. 4B, the output voltage Vout also has a ripple voltage similar to the ripple current of the inductor Lo, but its amplitude is smaller than the amplitude of the ripple voltage included in the voltage Vci. By using an element having a small ESR such as a ceramic capacitor for the capacitor Co, the ripple voltage of the output voltage Vout becomes very small.

  The voltage (Vci−Vout) of the capacitor Ci is converted into a current Iq in the voltage / current conversion circuit 12. For example, as shown in FIG. 4B, the voltage Vci of the node Nci oscillates around the output voltage Vout. In this case, since the voltage (Vci−Vout) of the capacitor Ci vibrates positively and negatively, the current Iq output from the voltage-current conversion circuit 12 also vibrates positively and negatively (FIG. 4C).

FIG. 5 is a diagram illustrating signal waveforms at various parts of the comparator 2 shown in FIG.
As shown in FIGS. 5A and 5B, the output feedback voltage VFB is a voltage level-shifted to the high potential side by the base-emitter voltage Vbe of the pnp transistor Q3 at the output of the buffer circuit (Q3, CS3). Vn1. The reference voltage Vref becomes a voltage Vn2 level-shifted to the high potential side by the base-emitter voltage Vbe of the pnp transistor Q4 at the output of the buffer circuit (Q4, CS4).
When the base-emitter voltages of the pnp transistors Q3 and Q4 are equal (Vbe), the potential difference between the voltages Vn1 and Vn2 is equal to the potential difference between the output feedback voltage VFB and the reference voltage Vref. The voltages Vn1, Vn2 are input to the differential amplifier circuits (Q5, Q6, CS2, CS5, CS6) via the resistors R3, R4.

  The current Iq injected into the node N3 of the comparator 2 does not flow to the base of the npn transistor Q5 having a large impedance, but most of it flows to the buffer circuit (Q3, CS3) via the resistor R3. Therefore, the voltage Vn3 of the node N3 is, as shown in the waveform of the chain line in FIG. 5C, a ripple voltage (Iq × r3) generated in the resistor R3 (resistance value r3) by the current Iq and the voltage Vn1 of the node N1. It becomes almost equal to the added voltage.

On the other hand, most of the current Iq injected into the node N4 of the comparator 2 flows through the low impedance buffer circuit (Q4, CS4). Therefore, the current flowing through the resistor R4 is very small, and the voltage Vn4 at the node N4 is almost equal to the voltage Vn2 at the node N2.
Accordingly, the differential amplifier circuit (Q5, Q6, CS2, CS5, CS6) receives the voltage Vn3 on which the ripple signal due to the current Iq is superimposed and the voltage Vn4 on which the ripple signal is not superimposed.

  In the differential amplifier circuit (Q5, Q6, CS2, CS5, CS6), the voltage difference between the voltages Vn3 and Vn4 is amplified, and the amplification result is further amplified by the output amplifier circuit 21, whereby the magnitude relationship between the voltages Vn3 and Vn4. A high level or low level logic signal Scp is generated according to the above.

  When the signal Scp indicating that the voltage Vn3 is lower than the voltage Vn4 is generated in the comparator 2, the control circuit 3 sets the MOS transistor MH on for a certain period of time and the MOS transistor ML off. When the MOS transistor MH is turned on, the voltage of the node Nsw becomes higher than the voltage of the node Nout, so that the voltage of the capacitor Ci rises linearly, and the voltage Vn3 rises linearly accordingly. When the MOS transistor MH is turned off and the MOS transistor ML is turned on after a certain time, the voltage at the node Nsw becomes lower than the voltage at the node Nout, so that the voltage at the capacitor Ci decreases linearly, and the voltage Vn3 also varies linearly accordingly To drop. Therefore, in the steady state, the level near the bottom at which the voltage Vn3 turns from rising to rising is equal to the voltage Vn4.

  As described above, in the switching power supply device shown in FIG. 1, a voltage corresponding to the integrated value of the voltage applied to the inductor Lo is generated in the capacitor Ci of the CR integration circuit 11. The ripple voltage generated in the capacitor Ci has a waveform similar to the ripple current flowing in the inductor Lo. The voltage of the capacitor Ci is converted into a current Iq in the voltage-current conversion circuit 12 and injected into a resistor R3 provided on the transmission path of the output feedback voltage VFB in the comparator 2. A ripple voltage (Iq × r3) corresponding to the ripple current flowing through the inductor Lo is generated in the resistor R3 (resistance value r3). As a result, the comparator 2 generates a voltage Vn3 that is a combined signal of the ripple voltage (Iq × r3) corresponding to the ripple current of the inductor Lo and the voltage Vn1 corresponding to the output feedback voltage VFB, and this voltage Vn3 is referred to The voltage Vn4 corresponding to the voltage Vref is compared. The control circuit 3 controls the switching of the MOS transistors ML and MH so that the bottom (or peak) of the voltage Vn3 is equal to the voltage Vn4 according to the output signal Scp of the comparator 2.

Meanwhile, the amplitude of the ripple voltage (Iq × r3) generated in the resistor R3 (resistance value r3) of the comparator 2 can be arbitrarily set according to the mutual inductance gm and the resistance value r3 of the voltage-current conversion circuit 12. When the time constant of the CR integration circuit 11 is small, the amplitude of the ripple voltage Vrc generated in the capacitor Ci may become larger than necessary. Even in this case, by setting the mutual inductance gm and the resistance value r3 appropriately. The amplitude of the ripple voltage (Iq × r3) generated in the resistor R3 can be converted to be appropriately reduced. That is, it is possible to generate a ripple signal that is similar to the ripple voltage generated in the capacitor Ci and has an amplitude smaller than that of the ripple voltage and synthesize it with the output feedback voltage VFB.
Therefore, according to the switching power supply device shown in FIG. 1, the time constant of the CR integration circuit 11 can be set small so that the element values of the capacitor Ci and the resistor Ri become values that can be formed on the semiconductor chip. is there. Thereby, the capacitor Ci and the resistor Ri can be integrated on the semiconductor chip, and the number of discrete components can be reduced.
Since discrete components can be reduced, the circuit area can be reduced as compared with the prior art, and the costs associated with component mounting can be reduced. Moreover, the mounting design of the parts becomes easy, and the design man-hour can be shortened.

  Further, according to the switching power supply device shown in FIG. 1, even if the ripple voltage of the output voltage Vout is very small as shown in FIG. 4B, a ripple signal having a sufficient amplitude is extracted and the output feedback voltage VFB is obtained. Therefore, a low ESR type capacitor can be used as the capacitor Co.

Conventionally, in a ripple mode type switching power supply, in order to obtain a ripple voltage having an appropriate amplitude in the output voltage, a capacitor having a relatively large ESR, such as a functional polymer aluminum electrolytic capacitor or a conductive polymer aluminum solid capacitor, is used. It was used. Ceramic capacitors are less expensive than these capacitors and have the advantage of a small occupied area. However, since the ESR is very small, they have not been generally used in the ripple mode system.
According to the switching power supply device shown in FIG. 1, since a ceramic capacitor having a small ESR can be used for the capacitor Co, the component cost can be reduced and the circuit area can be reduced as compared with the case where an aluminum electrolytic capacitor or the like is used.
Further, since a ceramic capacitor is generally in an open state at the time of a failure, the use of a ceramic capacitor for the capacitor Co can improve the reliability as compared with the case of using a capacitor that is in a short state at the time of a failure.

  Furthermore, according to the switching power supply device shown in FIG. 1, since a low ESR type capacitor such as a ceramic capacitor can be used as the output capacitor Co, the ripple voltage of the output voltage Vout can be reduced. Thereby, when the voltage Vout is used as the power supply voltage, the operation margin of the electronic circuit can be expanded, and the reliability can be improved.

  Further, the switching power supply device shown in FIG. 1 is provided with a buffer circuit (Q3, CS3) for inputting the output feedback voltage VFB and a buffer circuit (Q4, CS4) for inputting the reference voltage Vref, respectively. A current equivalent to the current Iq injected into the resistor R3 connected to the output of the circuit (Q3, CS3) is also injected into the output of the latter buffer circuit (Q3, CS3). As a result, the balance of the currents flowing through the two buffer circuits is improved, so that the input offset voltage of the two buffer circuits can be reduced.

<Second Embodiment>
Next, a second embodiment of the present invention will be described.

FIG. 6 is a diagram illustrating an example of the configuration of the switching power supply according to the second embodiment.
The switching power supply device shown in FIG. 6 is obtained by replacing the ripple signal generation circuit 1 in the switching power supply device shown in FIG. 1 with a ripple signal generation circuit 1A described below. The other components are the switching power supply shown in FIG. Same as the device.

The ripple signal generation circuit 1A includes a voltage dividing circuit 13 that divides the voltage generated in the capacitor Ci in addition to the same configuration (CR integration circuit 11 and voltage-current conversion circuit 12) as the ripple signal generation circuit 1 in FIG.
The voltage dividing circuit 13 is an embodiment of the voltage dividing circuit in the present invention.

  The voltage dividing circuit 13 includes resistors R5 and R6 connected in series. One terminal of the resistor R6 is connected to the node Nci, and the other terminal is connected to the node Nout through the resistor R5. The voltage-current conversion circuit 12 converts the voltage divided by the voltage dividing circuit 13, that is, the voltage at both ends of the resistor R5, into a current Iq.

  When the element values of the capacitor Ci and the resistor Ri are set to values that can be integrated in the semiconductor chip, the time constant of the CR integration circuit 11 becomes small, and the amplitude of the ripple voltage generated in the capacitor Ci becomes larger than necessary. Conceivable. If the amplitude is too large, the input range of the voltage / current conversion circuit 12 may be insufficient. In the present embodiment, the amplitude of the ripple voltage generated in the capacitor Ci is divided by the voltage dividing circuit 13 and input to the voltage / current conversion circuit 12, thereby setting the ripple voltage input to the voltage / current conversion circuit 12 within an appropriate range. can do.

<Third Embodiment>
Next, a third embodiment of the present invention will be described.

FIG. 7 is a diagram illustrating an example of the configuration of the switching power supply according to the third embodiment.
The switching power supply device shown in FIG. 7 is obtained by replacing the ripple signal generation circuit 1 in the switching power supply device shown in FIG. 1 with a ripple signal generation circuit 1B described below. The other components are the switching power supply shown in FIG. Same as the device.

The ripple signal generation circuit 1B includes a CR integration circuit 11B, a voltage / current conversion circuit 12, and voltage dividing circuits 13B and 14.
The voltage dividing circuit 13B is an embodiment of the first voltage dividing circuit in the present invention.
The voltage dividing circuit 14 is an embodiment of the second voltage dividing circuit in the present invention.

  The CR integration circuit 11B includes a resistor Ri and a capacitor Ci connected in series, and is connected in parallel with a series circuit of an inductor Lo and a capacitor Co. One terminal of the resistor Ri is connected to the node Nsw, and the other terminal is connected to the reference potential G through the capacitor Ci.

  The voltage dividing circuit 13B divides the voltage generated in the capacitor Ci. The voltage dividing circuit 13B includes resistors R5 and R6 connected in series. One terminal of the resistor R6 is connected to a connection node (node Nci) of the resistor Ri and the capacitor Ci, and the other terminal is connected via the resistor R5. To the reference potential G.

  The voltage dividing circuit 14 divides the voltage generated in the capacitor Co by a voltage dividing ratio equivalent to that of the voltage dividing circuit 13B. The voltage dividing circuit 14 includes resistors R7 and R8 connected in series. One terminal of the resistor R8 is connected to the node Nout, and the other terminal is connected to the reference potential G via the resistor R7.

  The voltage-current conversion circuit 12 converts the difference between the voltages divided by the voltage dividing circuits 13B and 14 into a current Iq. In the example of FIG. 7, the voltage difference (Vdp−Vdn) between the intermediate connection node of the resistors R5 and R6 and the intermediate connection node of the resistors R7 and R8 is converted into a current. The voltage-current conversion circuit 12 has a configuration shown in FIG. 2, for example.

In the switching power supply device shown in FIG. 7, a CR integration circuit 11B is connected in parallel with a series circuit of an inductor Lo and a capacitor Co. The voltage applied to the CR integration circuit 11B is higher by the voltage Vout of the capacitor Co than the voltage applied to the CR integration circuit 11 (FIG. 1) connected in parallel only to the inductor Lo. Therefore, if the voltage Vout is subtracted from the voltage generated in the capacitor Co of the CR integration circuit 11B, a voltage equivalent to the voltage generated in the capacitor Co of the CR integration circuit 11 (FIG. 1) can be obtained.
Here, if the voltage dividing ratio of the voltage dividing circuits 13B and 14 is “γ”, the voltage Vpn obtained by dividing the voltage of the capacitor Co of the CR integrating circuit 11B by the voltage dividing circuit 13B is CR connected in parallel only to the inductor Lo. The voltage of the integrating circuit 11 (FIG. 6) becomes higher by “γ × Vout” than the voltage obtained by dividing the voltage by the voltage dividing ratio γ. Therefore, as shown in FIG. 7, the difference (Vdp−Vdn) between the voltage “γ × Vout” obtained by the voltage dividing circuit 14 and the voltage Vpn obtained by the voltage dividing circuit 13B is obtained by dividing the voltage of the CR integrating circuit 11. This is equivalent to the voltage divided by the pressure ratio γ (see FIG. 6).

According to the switching power supply device shown in FIG. 7, the amplitude of the ripple voltage generated in the capacitor Ci can be appropriately reduced according to the input range of the voltage-current conversion circuit 12, as in the switching power supply device shown in FIG. 6.
In the switching power supply device shown in FIG. 7, the input common-mode voltage of the voltage-current conversion circuit 12 is substantially “γ × Vout”, and the input common-mode voltage “of the current-voltage conversion circuit 12 in the switching power supply device shown in FIG. It becomes lower than “Vout”. As a result, the power supply voltage used for the operation of the voltage-current conversion circuit 12 can be made lower than “Vout”, which is advantageous for integration in a recent low-voltage IC.

<Fourth Embodiment>
Next, a fourth embodiment of the present invention will be described.

FIG. 8 is a diagram illustrating an example of the configuration of the switching power supply according to the fourth embodiment.
The switching power supply device shown in FIG. 8 is obtained by replacing the ripple signal generation circuit 1 in the switching power supply device shown in FIG. 1 with a ripple signal generation circuit 1C described below. The other components are the switching power supply shown in FIG. Same as the device.

The ripple signal generation circuit 1C includes the same CR integration circuit 11 as the ripple signal generation circuit 1, and also includes a signal synthesis circuit 15 that outputs a synthesized signal Vci_fb obtained by synthesizing the ripple voltage generated in the capacitor Ci and the output feedback voltage VFB.
The signal synthesis circuit 15 is an embodiment of the first signal synthesis circuit in the present invention.

FIG. 9 is a diagram illustrating an example of the configuration of the ripple signal generation circuit 1C.
A ripple signal generation circuit 1C illustrated in FIG. 9 includes amplifiers 151 to 153 and resistors R9 to R14.
The non-inverting input terminal of the amplifier 151 is connected to the node Nci, and its output terminal is connected to the inverting input terminal. The non-inverting input terminal of the amplifier 152 is connected to the node Nfb, and its output terminal is connected to the inverting input terminal. The inverting input terminal of the amplifier 153 is connected to the output terminal of the amplifier 151 through the resistor R9, and is connected to the output terminal of the amplifier 152 through the resistor R10. The output terminal of the amplifier 153 is connected to its inverting input terminal via the resistor R11. The non-inverting input terminal of the amplifier 153 is connected to the node Nout through the resistor R12 and is connected to the reference voltage Vref through a parallel circuit of the resistors R13 and R14. The synthesized signal Vci_fb is output from the amplifier 153.
The comparator 2 compares the synthesized signal Vci_fb with the reference voltage Vref, and generates a signal Scp according to the comparison result.

  In the signal synthesis circuit 15 shown in FIG. 9, the amplifiers 151 and 152 constitute a buffer circuit, and outputs the voltages Vci and VFB input with high impedance with low impedance. The resistors R9 to R11 and the amplifier 153 constitute an inverting amplifier circuit, and multiply the voltages Vci and VFB input by the amplifiers 151 and 152 by respective predetermined gains and add them. The gain of the inverting amplifier circuit is negative, and the phase of each input signal is inverted by the inverting amplifier circuit.

A combined voltage Vb obtained by combining the output voltage Vout and the reference voltage Vref at a predetermined ratio is input to the non-inverting input terminal of the amplifier 153. The combined voltage Vb is expressed by the following equation, for example.

(Equation 5)
Vb = α · Vout + β · Vref (5)

  The component (α · Vout) of the output voltage Vout in the combined voltage Vb generates a component proportional to the voltage (Vci−Vout) of the capacitor Ci together with the component of the voltage Vci input to the amplifier 151. The ratio α is set so that a component proportional to the voltage (Vci−Vout) of the capacitor Ci is generated in the combined signal Vci_fb.

  On the other hand, the component (β · Vref) of the reference voltage Vref in the combined voltage Vb generates a DC offset component in the combined signal Vci_fb. The ratio β is generated when the output voltage Vout is input instead of the voltage Vci in the amplifier 151 (that is, the voltage of the capacitor Ci is set to zero), and the reference voltage Vref is input instead of the output feedback voltage VFB in the amplifier 152. The synthesized signal Vci_fb is set to be equal to the reference voltage Vref.

  Here, the operation in the steady state of the switching power supply device shown in FIG. 8 will be described with reference to FIG. FIG. 10 is a diagram illustrating the relationship between the composite signal Vci_fb and the reference voltage Vref.

The components of the output feedback voltage VFB and the voltage of the capacitor Ci (Vci−Vout) included in the combined signal Vci_fb are both inverted in phase. That is, when the output feedback voltage VFB or the voltage (Vci−Vout) of the capacitor Ci increases, the level of the combined signal Vci_fb decreases. Conversely, when these voltages decrease, the level of the combined signal Vci_fb increases.
On the other hand, in this embodiment, when the signal Scp indicating that the combined signal Vci_fb is larger than the reference voltage Vref is input from the comparator 2, the control circuit 3 turns on the MOS transistor MH for a certain period of time (FIG. 10A). When the MOS transistor MH is turned on, the current flowing through the inductor Lo increases, and the voltage (Vci−Vout) of the capacitor Ci increases accordingly, so that the composite signal Vci_fb decreases (FIG. 10B). When the control circuit 3 turns off the MOS transistor MH after the predetermined time (FIG. 10A), the current flowing through the inductor Lo is decreased and the voltage (Vci−Vout) of the capacitor Ci is also decreased. Therefore, the combined signal Vci_fb Rises (FIG. 10B). Therefore, in the steady state, as shown in FIG. 10B, the peak of the composite signal Vci_fb and the reference voltage Vref are substantially equal.

  In the signal combining circuit 15 shown in FIG. 9, the DC offset component of the combined signal Vci_fb is the combined signal Vci_fb when the voltage of the capacitor Ci is zero and the reference voltage Vref is input instead of the output feedback voltage VFB. And the reference voltage Vref are set to be equal. Therefore, when the peak of the composite signal Vci_fb and the reference voltage Vref are substantially equal (FIG. 10B), the output feedback voltage VFB approximates the reference voltage Vref if the minute ripple voltage of the capacitor Ci is ignored. That is, the steady-state output voltage Vout approximates the target voltage determined by the voltage division ratio between the reference voltage Vref and the resistors Rf1 and Rf2.

  According to the switching power supply device shown in FIG. 8, the gain of the voltage (Vci−Vout) in the signal synthesis circuit 15 can be arbitrarily set. For this reason, even when the time constant of the CR integration circuit 11 is reduced and the voltage amplitude of the capacitor Ci is increased, the amplitude of the voltage component of the capacitor Ci included in the composite signal Vci_fb can be converted to be appropriately reduced. is there. Therefore, also in the switching power supply device shown in FIG. 8, the CR integration circuit 11 can be integrated on the semiconductor chip, and the same effect as the switching power supply device shown in FIG. 1 can be obtained.

<Fifth Embodiment>
Next, a fifth embodiment of the present invention will be described.

  FIG. 11 is a diagram illustrating an example of the configuration of the switching power supply according to the fifth embodiment. The switching power supply device shown in FIG. 11 is obtained by replacing the ripple signal generation circuit 1 in the switching power supply device shown in FIG. 1 with a ripple signal generation circuit 1D described below, and further replacing the comparator 2 with a comparator 2D. The elements are the same as those of the switching power supply device shown in FIG.

  The ripple signal generation circuit 1D includes the same CR integration circuit 11 as the ripple signal generation circuit 1, and also includes an amplitude conversion circuit 16 that converts the voltage amplitude of the capacitor Ci.

  The amplitude conversion circuit 16 generates a ripple signal Vci_X that is similar to the ripple voltage generated in the capacitor Ci and has a smaller amplitude than the ripple voltage. In the example of FIG. 11, the ripple signal Vci_X is a signal based on the output voltage Vout.

  The comparator 2D amplifies the difference between the output feedback voltage VFB and the reference voltage Vref, amplifies the ripple signal Vci_X, combines these amplification results, and further amplifies them to generate the logic signal Scp.

FIG. 12 is a diagram illustrating an example of the configuration of the comparator 2D.
The comparator 2D illustrated in FIG. 12 includes npn transistors Q7 to Q10, current sources CS7 to CS10, resistors R15 to R18, and an output amplifier circuit 21.
A circuit including npn transistors Q7 and Q8, resistors R15 and R16, and a current source CS9 is an embodiment of the first amplification stage of the present invention.
A circuit including npn transistors Q9 and Q10, resistors R17 and R18, and a current source CS10 is an embodiment of the second amplification stage of the present invention.
The current source CS7 is an embodiment of the first load circuit of the present invention.
The current source CS8 is an embodiment of the second load circuit of the present invention.
The output amplifier circuit 21 is an embodiment of the third amplifier stage of the present invention.

The emitter of npn transistor Q7 is connected to node Nm1 via resistor R15, its collector is connected to current combining node NS1 (first current combining node), and reference voltage Vref is input to its base. The emitter of npn transistor Q8 is connected to node Nm1 via resistor R16, the collector thereof is connected to current synthesis node NS2 (second current synthesis node), and the base thereof is connected to node Nfb. The current source CS9 is connected between the node Nm1 and the reference potential G.
Npn transistor Q9 has an emitter connected to node Nm2 via resistor R17, a collector connected to current combining node NS1, and a base connected to node Nout. The emitter of npn transistor Q10 is connected to node Nm2 via resistor R18, its collector is connected to current combining node NS2, and ripple signal Vci_x is input to its base. The current source CS10 is connected between the node Nm2 and the reference potential G.
The current source CS7 is connected between the current synthesis node NS1 and the power supply line Vdd, and the current source SC8 is connected between the current synthesis node NS2 and the power supply line Vdd.

The npn transistors Q7 and Q8, the resistors R15 and R16, and the current source CS9 constitute a differential amplifier circuit that converts a differential voltage into a differential current. According to the difference between the output feedback voltage VFB and the reference voltage Vref, A difference (Iq8−Iq7) between collector currents of npn transistors Q7 and Q8 is generated.
The npn transistors Q9 and Q10, the resistors R17 and R18, and the current source CS10 also form a differential amplifier circuit that converts the differential voltage into a differential current, and the difference between the ripple signal Vci_X and the output voltage Vout (ie, the capacitor) In accordance with (Ci voltage), a difference (Iq10-Iq9) between collector currents of npn transistors Q9 and Q10 is generated.
Current Iq7 and current Iq9 are combined at current combining node NS1 and flow to current source CS7, and current Iq8 and current Iq10 are combined at current combining node NS2 and flow to current source CS8.
Accordingly, the difference between the voltages generated in the current sources CS7 and CS8 (that is, the voltages at the current combining nodes NS1 and NS2) is a component generated by the differential current (Iq8-Iq7) and a component generated by the differential current (Iq10-Iq9). Is a composite of For example, when the output feedback voltage VFB rises with respect to the reference voltage Vref or when the ripple signal Vci_X rises with respect to the output voltage Vout, the current (Iq8 + Iq10) of the current synthesis node NS2 increases, so that current synthesis The voltage at the node NS2 decreases with respect to the voltage at the current synthesis node NS1. Conversely, when the output feedback voltage VFB decreases with respect to the reference voltage Vref, or when the ripple signal Vci_X decreases with respect to the output voltage Vout, the current (Iq8 + Iq10) of the current synthesis node NS2 decreases, so that the current The voltage at the synthesis node NS2 rises with respect to the voltage at the current synthesis node NS1.
By further amplifying the voltages of the current combining nodes NS1 and NS2 in the output amplifier circuit 21, a logic signal Scp having a high level or a low level is generated.

As described above, in the switching power supply device shown in FIG. 11, the ripple signal Vci_X is synthesized with the signal obtained by amplifying the difference between the output feedback voltage VFB and the reference voltage Vref, and the synthesized result is further amplified, whereby the comparator 2D A logic signal Scp is generated. Therefore, when the difference between the output feedback voltage VFB and the reference voltage Vref is large, the logic signal Scp becomes constant at a high level or a low level, and when the difference between the output feedback voltage VFB and the reference voltage Vref becomes sufficiently small, the ripple signal Vci_X The logic signal Scp is switched to a high level or a low level so as to indicate the peak or the bottom.
Therefore, the switching power supply device shown in FIG. 11 can also operate in a ripple mode system.

  Further, according to the switching power supply device shown in FIG. 11, since the voltage amplitude of the capacitor Ci can be arbitrarily converted in the amplitude conversion circuit 16, the CR integration circuit 11 can be integrated on the semiconductor chip. The same effect as the switching power supply device shown can be obtained.

<Sixth Embodiment>
Next, a sixth embodiment of the present invention will be described.

  FIG. 13 is a diagram illustrating an example of the configuration of the switching power supply according to the sixth embodiment. The switching power supply device shown in FIG. 13 is obtained by replacing the ripple signal generation circuit 1 in the switching power supply device shown in FIG. 1 with a ripple signal generation circuit 1E described below, and the other components are the switching power supply shown in FIG. Same as the device.

The ripple signal generation circuit 1E includes the same CR integration circuit 11 as the ripple signal generation circuit 1, and also includes a signal synthesis circuit 17 that outputs a synthesized signal Vref_ci obtained by synthesizing the ripple voltage generated in the capacitor Ci and the reference voltage Vref.
The signal synthesis circuit 17 is an embodiment of the second signal synthesis circuit in the present invention.

FIG. 14 is a diagram illustrating a configuration example of the ripple signal generation circuit 1E.
A ripple signal generation circuit 1E shown in FIG. 14 includes a voltage / current conversion circuit 171 and a resistor R19.
The voltage-current conversion circuit 171 converts the voltage (Vci−Vout) generated in the capacitor Ci into a current Irp. A positive current (discharge current) is generated when the voltage Vci is lower than the voltage Vout, and a negative current (drawn current) is generated when the voltage Vci is higher than the voltage Vout. The voltage-current conversion circuit 171 has the same configuration as the voltage-current conversion circuit 12 shown in FIG. 2, for example.
One terminal of the resistor R19 is connected to the current output terminal of the voltage-current conversion circuit 171, and the reference voltage Vref is applied to the other terminal. A composite signal Vref_ci is generated at a connection node between the current output terminal of the voltage-current conversion circuit 171 and the resistor R19.
The comparator 2 generates a logic signal Scp according to the comparison result between the synthesized signal Vref_ci and the output feedback voltage VFB.

  Here, the operation in the steady state of the switching power supply device shown in FIG. 13 will be described with reference to FIG. FIG. 15 is a diagram illustrating the relationship between the composite signal Vref_ci and the output feedback voltage VFB.

  When the input impedance of the comparator 2 is sufficiently high, most of the current output from the voltage-current conversion circuit 171 flows through the resistor R19. Therefore, when the resistance value of the resistor R19 is “r19”, the combined signal Vref_ci is expressed by the following equation.

(Equation 6)
Vci_fb = r19 × Irp + Vref (6)

The control circuit 3 sets the MOS transistor MH on for a certain period of time in response to the signal Scp of the comparator 2 indicating that the composite signal Vref_ci has become higher than the output feedback voltage VFB. When the MOS transistor MH is turned on, the current of the inductor Lo increases and the voltage of the capacitor Ci increases. Since the current Irp is positive when “Vci <Vout” and negative when “Vci> Vout”, the composite signal Vci_fb decreases when the voltage of the capacitor Ci increases. When the control circuit 3 turns off the MOS transistor MH after a certain time, the current of the inductor Lo decreases and the voltage of the capacitor Ci decreases, so that the composite signal Vci_fb increases. When the composite signal Vref_ci becomes higher than the output feedback voltage VFB, the MOS transistor MH is turned on again.
In this way, as shown in FIG. 15B, the output feedback voltage VFB is substantially equal to the peak of the composite signal Vref_ci.

  As described above, according to the switching power supply device shown in FIG. 13, the voltage (Vci−Vout) of the signal synthesis circuit 17 is adjusted by adjusting the mutual conductance of the voltage-current conversion circuit 171 and the resistance value of the resistor R19. Since the gain can be set arbitrarily, even when the time constant of the CR integration circuit 11 is reduced to increase the voltage amplitude of the capacitor Ci, the amplitude of the voltage component of the capacitor Ci included in the composite signal Vci_fb can be appropriately reduced. Is possible. Therefore, also in the switching power supply device shown in FIG. 13, the CR integration circuit 11 can be integrated on the semiconductor chip, and the same effect as the switching power supply device shown in FIG. 1 can be obtained.

FIG. 16 is a diagram illustrating another configuration example of the ripple signal generation circuit 1E.
A ripple signal generation circuit 1E illustrated in FIG. 16 includes amplifiers 172 to 174 and resistors R20 to R24.
The inverting input terminal of the amplifier 172 is connected to the node Nout through the resistor R20. The output terminal of the amplifier 172 is connected to its inverting input terminal via a resistor R21. The non-inverting input terminal of the amplifier 174 is connected to the node Nci. The inverting input terminal of the amplifier 174 is connected to its output terminal. The inverting input terminal of the amplifier 173 is connected to the output terminal of the amplifier 172 via the resistor R22, and is connected to the output terminal of the amplifier 174 via the resistor R23. The output terminal of the amplifier 173 is connected to its inverting input terminal via a resistor R24. A reference voltage Vref is applied to the non-inverting input terminals of the amplifiers 172 and 173.

The amplifier 174 constitutes a buffer circuit that inputs the voltage Vci of the node Nci with a high impedance and outputs a voltage substantially equal to this with a low impedance.
The amplifier 172 and the resistors R20 and R21 constitute an inverting amplifier circuit that amplifies the voltage Vout by inverting the phase with a predetermined gain.
The amplifier 173 and the resistors R22 to R24 amplify the output voltage of the preceding inverting amplifier circuit (172, R20, R21) and the output voltage Vci of the buffer circuit (174) by inverting the phase with a predetermined gain, An inverting amplifier circuit to be added is configured. By appropriately setting the gain of each inverting amplifier circuit, a component proportional to the voltage (Vci−Vout) of the capacitor Ci is generated in the composite signal Vci_fb output from the amplifier 173. Further, since the two inverting amplifier circuits both perform amplification based on the reference voltage Vref, when the voltage (Vci−Vout) of the capacitor Ci is zero, the combined signal Vci_fb becomes equal to the reference voltage Vref.
Therefore, even with the circuit configuration shown in FIG. 16, it is possible to generate the composite signal Vci_fb equivalent to the ripple signal generation circuit 1E shown in FIG.

  As mentioned above, although several embodiment of this invention was described, this invention is not limited only to embodiment mentioned above, Various modifications are included.

In the embodiment described above, a method (fixed on-time method) in which the MOS transistor MH is turned on for a certain time at the bottom or peak of the ripple current flowing in the inductor Lo and thereby increases the current in the inductor Lo is exemplified. The present invention is not limited to this. For example, the present invention can also be applied to a method (fixed off time method) in which the MOS transistor MH is turned off for a certain time at the bottom or peak of the ripple current flowing through the inductor Lo, thereby reducing the current in the inductor Lo. The present invention can also be applied to a method of suppressing fluctuations in the switching frequency by adaptively changing the on time and the off time according to the input voltage Vin and the output voltage Vout.
Alternatively, the present invention can also be applied to a hysteresis PWM control method in which a comparator that compares a ripple component and a reference voltage has hysteresis characteristics to generate a PWM signal.
That is, the present invention is widely applicable to various ripple mode type switching power supply devices.

The second and third embodiments described above can be applied to other embodiments.
For example, in the switching power supply device shown in FIG. 9, the voltage dividing circuit 13 (FIG. 6) may be provided in parallel with the capacitor Ci, and the output voltage of the voltage dividing circuit 13 may be input to the signal synthesis circuit 15. Alternatively, the CR integration circuit 11 is replaced with a CR integration circuit 11B (FIG. 7), and a voltage dividing circuit 13B (FIG. 7) is provided in parallel with the capacitor Ci, and the output voltage of the voltage dividing circuit 13B is supplied to the signal synthesis circuit 15. You may enter.
In the switching power supply device shown in FIG. 11, the voltage dividing circuit 13 (FIG. 6) may be provided in parallel with the capacitor Ci, and the output voltage of the voltage dividing circuit 13 may be input to the amplitude conversion circuit 16. Alternatively, the CR integrating circuit 11 is replaced with a CR integrating circuit 11B (FIG. 7), a voltage dividing circuit 13B (FIG. 7) is provided in parallel with the capacitor Ci, and a voltage dividing circuit 14 for dividing the output feedback voltage VFB is provided. Thus, the difference between the output voltages of the voltage dividing circuits 13B and 14 may be input to the amplitude conversion circuit 16.
In the switching power supply device shown in FIG. 13, the voltage dividing circuit 13 (FIG. 6) may be provided in parallel with the capacitor Ci, and the output voltage of the voltage dividing circuit 13 may be input to the signal synthesis circuit 17. Alternatively, the CR integrating circuit 11 is replaced with a CR integrating circuit 11B (FIG. 7), a voltage dividing circuit 13B (FIG. 7) is provided in parallel with the capacitor Ci, and a voltage dividing circuit 14 for dividing the output feedback voltage VFB is provided. Thus, the difference between the output voltages of the voltage dividing circuits 13B and 14 may be input to the signal synthesis circuit 17.

  In the first embodiment described above, the current Iq is injected into the resistor R3 provided in the transmission path of the output feedback voltage VFB, but the present invention is not limited to this. For example, contrary to the above, the current Iq may be injected into the resistor R4 in the path through which the reference voltage Vref is transmitted. That is, a combined signal of the reference voltage Vref and the ripple signal may be generated. In this case, by injecting the same current Iq into the node N1, the DC balance of the current flowing through the pnp transistors Q3 and Q4 can be improved, and the input offset voltage error can be reduced.

1, 1A to 1E ... ripple signal generation circuit,
2,2D ... Comparator,
3 ... Control circuit,
4 ... Drive circuit,
11, 11B ... CR integration circuit,
12, 171 ... voltage-current conversion circuit,
13, 13B, 14 ... voltage dividing circuit,
15, 17 ... signal synthesis circuit,
16: Amplitude conversion circuit,
21 ... Output amplifier circuit,
151-153, 172, 173 ... amplifiers,
Lo ... Inductor,
Ci, Co ... capacitors
CS1 to CS10 ... current source,
MH, ML ... MOS transistors,
M1 to M10: MOS transistors,
Q1, Q2, Q5-Q10 ... npn transistors,
Q3, Q4 ... pnp transistors,
R1-R24 ... resistance,
Rf1, Rf2 ... resistance,
Vref: reference voltage,
VFB ... Output feedback voltage

Claims (4)

An input terminal for receiving an input voltage;
An output terminal for outputting an output voltage;
A first switching transistor connected between the input terminal and a first node;
A second switching transistor connected between the first node and a reference potential and operating complementarily to the first switching transistor;
An inductance element connected between the first node and the output terminal;
An output capacitance element connected between the output terminal and a reference potential;
A voltage dividing circuit connected to the output terminal and generating a feedback voltage according to the output voltage;
A ripple voltage detection circuit that is included in the output voltage and detects a ripple voltage corresponding to a switching operation of the switching transistor, the ripple voltage detection circuit including an integration circuit connected to the inductance element ;
A voltage-current conversion circuit that inputs the ripple voltage and outputs a current signal corresponding to the ripple voltage;
A comparison circuit that compares the sum voltage of the feedback voltage and the ripple voltage with a reference voltage and outputs a comparison result , the first resistance element for converting the current signal into a voltage signal, and the feedback voltage And a differential circuit for comparing a sum voltage of the voltage signal with the reference voltage ;
A control circuit for controlling on / off of the first and second switching transistors according to the comparison result;
Including
The on-time of the first switching transistor is defined by the product of the ratio of the output voltage to the input voltage and the switching period of the first and second switching transistors;
Switching power supply. The switching power supply device according to claim 1,
The integrating circuit includes a resistance element and a capacitance element connected in series between the first node and the output terminal.
Switching power supply. The switching power supply device according to claim 1 or 2 ,
The comparison circuit includes a first buffer circuit for inputting the feedback voltage, a second buffer circuit for inputting the reference voltage, and a second resistance element coupled to the output of the second buffer circuit. In addition,
The feedback voltage is supplied to a first input of the differential circuit via the first buffer circuit and the first resistance element, and the reference voltage is supplied to the second buffer circuit and the second buffer circuit. Is supplied to the second input of the differential circuit via a resistance element of
A first current is supplied from the voltage-current conversion circuit to a midpoint of connection between the first input of the differential circuit and the first resistance element, and the output of the second buffer circuit and the second resistance are supplied. A second current is supplied from the voltage-current conversion circuit to a midpoint of connection with the element.
Switching power supply. The switching power supply device according to claim 3 ,
The voltage-current converter circuit is
A differential amplifier circuit including a first transistor that inputs a voltage of one terminal of the capacitance element, and a second transistor that inputs a voltage of the other terminal of the capacitance element;
A first current source circuit that outputs the first current corresponding to the current flowing through the first transistor;
A second current source circuit for outputting the second current corresponding to the current flowing through the second transistor;
including,
Switching power supply.

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