CN102957319B - Power converter pulse width modulation control circuit and its control method - Google Patents

Abstract

The invention discloses a power supply conversion pulse width modulation control circuit and a control method thereof, the pulse width modulation control circuit comprises a virtual current ripple pulse width modulation circuit, the virtual current ripple pulse width modulation circuit is provided with an integration and direct current bias eliminating unit for inputting the phase node voltage signal and a signal reflecting output voltage, and generates a virtual current ripple parameter signal positioned at a direct current reference voltage level, a phase synthesizing unit for synthesizing the virtual current ripple parameter signal and an output voltage signal slope vector into a pulse width modulation parameter signal, a double-track reference voltage level generating unit for generating an upper direct current reference voltage level and a lower direct current reference voltage level, and the pulse width modulation parameter signal is compared with the upper direct current reference voltage level and the lower direct current reference voltage level to generate a pulse width modulation signal to be input into a driver. The invention can not only reduce the manufacturing cost of the power converter, but also reduce the volume of the power supply.

Description

Power converter pulse width modulation control circuit and its control method

technical field

The invention relates to a pulse width modulation control circuit of a power converter and a control method thereof, in particular to a pulse width modulation control circuit and a control method thereof free from closed loop stability compensation adjustment.

Background technique

For general electronic equipment, the power converter plays a pivotal role. It converts the power supply to provide the voltage required for the operation of the electronic equipment. For users, the continuity of the working time of electronic equipment is often one of the main considerations when purchasing electronic equipment. Therefore, how to make electronic equipment work for a long time has become the main design goal of power converters. .

At present, the design of power converters is mainly based on switching power supplies. Switching power converters determine the output power, output voltage or output current required by the load, and use PWM Pulse-width Modulation) means that when the power converter outputs electric energy, it can more accurately control the electric energy output to the load and use it for the load. Therefore, when the switching power converter is used, it is less likely to generate redundant electric energy waste, thereby saving electric energy loss.

Please refer to the patent case of US Patent Publication No. US6433525, which is a switching power converter proposed by Intersil Corporation, which mainly uses a circuit to detect the inductor current to detect whether the polarity of the current changes, and uses a counter to measure The time when the current state of the load starts to change, and the output mode of electric energy is selected, so when the switching power converter is in a high current load state, the pulse width modulation regulation control circuit will be selected to control the output electric energy; while at low current In the load state, a hysteresis (ripple) control circuit will be selected to control the output power; thereby achieving the purpose of saving power output and prolonging the continuous working time of electronic equipment.

However, there will be a time gap between the counter of this switching power converter detecting the change of the current state of the load and selecting a suitable power output mode, which makes the switching power converter unable to accurately match the current state of the load , to provide suitable power, for example: when the load changes from a high current state to a low current state, the AC power converter still uses the hysteresis (ripple) regulation control circuit to control the output due to the time error when the counter is working The electric energy, resulting in the output of electric energy can not meet the needs of the load, resulting in the loss of electric energy. Therefore, such a switching power converter using a counter has poor regulation effect on output power and will generate redundant power loss.

In addition to the design of this switching power converter, in order to stabilize the output power to the load, the pulse width modulation control circuit must compensate and adjust the power input to the load, and it needs to be equipped with a hysteresis (ripple) regulation control circuit, or other circuit, it is impossible to use only a single control circuit to achieve the effect of stabilizing the output voltage, and the design cost of this switching power converter is relatively high, and the volume is relatively large. It is necessary to improve the design of the converter.

Contents of the invention

The purpose of the present invention is to provide a converter that can reduce the influence of the inductance and capacitance characteristics of the output side of the converter on the pulse width modulation control signal, and has the effect of precise control and cost reduction.

The converter involved in the present invention includes at least one upper bridge component and one lower bridge component, and the upper and lower bridge components are electrically connected to the input power supply, and the upper and lower bridge components are connected through phase nodes, and the phase nodes are controlled by pulse width modulation The driver action controlled by the variable signal makes the upper and lower bridge components perform switching actions, and the phase node is connected to the output inductor and the output capacitor, and controls the output inductor current to charge the output capacitor to generate an output voltage, wherein the pulse width modulation of the present invention The control circuit includes a virtual current ripple pulse width modulation circuit. The virtual current ripple pulse width modulation circuit has an integration and DC bias elimination unit, a phase synthesis unit, and a dual-rail reference voltage level generation unit. The integration and DC bias The elimination unit inputs the aforementioned phase node voltage signal and the signal reflecting the output voltage, and generates a virtual current ripple parameter signal at the DC reference voltage level, and the phase synthesis unit synthesizes the virtual current ripple parameter signal and the slope vector of the output voltage signal Pulse width modulation parameter signal, the dual-rail reference voltage level generating unit generates upper and lower DC reference voltage levels, and compares the pulse width modulation parameter signal with the upper and lower DC reference voltage levels to generate a pulse width modulation signal input the aforementioned drive.

The virtual ripple current pulse width modulation circuit of the present invention includes a DC reference voltage level unit, an integration and DC bias elimination unit, a phase synthesis unit, a dual-rail reference voltage level generation unit, and a PWM generation unit. unit, wherein the DC reference voltage level unit provides a reference DC voltage level; the input terminal of the integration and DC bias elimination unit is connected to the aforementioned phase node voltage signal, and connected to the reference voltage level unit, and makes the phase node voltage signal square The wave is integrated and DC bias eliminated to form a triangular wave at the DC reference level, and the slope of the triangular wave can reflect the change of the phase node voltage signal; the phase synthesis unit receives the integrated waveform voltage output by the integration and DC bias elimination unit and the converter The output voltage is proportionally superimposed to generate a synthetic approximate triangular wave voltage, and the voltage is used as a pulse width modulation parameter signal; and the input side of the dual-rail reference voltage level generating unit is connected to a DC reference voltage level unit, and output to the pulse width modulation A generation unit, and the dual-rail reference voltage level generation unit generates dual-rail upper and lower DC reference voltages corresponding to the positive and negative differences of the reference voltage level voltage, and the input side of the pulse width modulation generation unit is connected to the output terminal of the phase synthesis unit and the output terminal of the dual-rail reference voltage level generation unit, and compare the pulse width modulation parameter signal input by the phase synthesis unit with the upper DC reference level and the lower DC reference level of the dual-rail reference voltage level generation unit, and generate a pulse The pulse width modulation signal is input to the driver to control the action of the upper and lower bridge components.

In this way, the present invention uses the virtual ripple current pulse width modulation circuit to design the power converter, and does not need to precisely control the component characteristic impedance of the output inductance and filter capacitor and the frequency response characteristics of the external line adjustment error amplifier to achieve high stability. The design of the high-precision and easy-to-use power converter enables the virtual ripple current pulse width modulation circuit to achieve the purpose of stabilizing the power output regardless of whether the power converter is in a high-load state or a low-load state. Reducing the production cost of the power converter can also reduce the size of the power supply, and solve the shortcomings of the prior art.

The present invention also provides a pulse width modulation control method free from closed loop stabilization compensation adjustment, comprising the following steps:

a. Take the square wave voltage signal of the phase node, and set the DC reference voltage level, and the signal is processed by integration and DC bias elimination to generate a virtual current ripple parameter signal located at the DC reference voltage level;

b. superimposing the response output voltage signal and the virtual current ripple parameter signal to synthesize a pulse width modulation parameter signal with an approximate triangular wave;

c. Detecting the pulse width modulation parameter signal and generating a pulse width modulation signal to control the action of the upper and lower bridge components.

The detection method of the aforementioned step c is set to correspond to the upper and lower DC reference voltage levels with the same positive and negative voltage difference, and the rising and falling waves of the pulse width modulation parameter signal are located at the upper and lower DC voltage levels respectively. The pulse width modulation signal can be generated when the level of the reference level signal is reached.

Description of drawings

FIG. 1 is a schematic diagram of the circuit structure of the present invention.

FIG. 2 is a schematic block diagram of a virtual current ripple PWM circuit of the present invention.

FIG. 3 is a schematic diagram of the virtual current ripple pulse width modulation circuit and the operating waveform state of the present invention.

Fig. 4 is a schematic diagram of the action waveform of the present invention.

FIG. 5 is a schematic circuit diagram of an integration and DC bias elimination unit according to an embodiment of the present invention.

FIG. 5A is a schematic diagram of waveforms corresponding to FIG. 5 in the present invention.

FIG. 6 is a schematic diagram of a partial circuit for eliminating DC bias voltage according to another embodiment of the present invention.

FIG. 6A is a schematic diagram of waveforms corresponding to FIG. 6 in the present invention.

FIG. 6B is a schematic diagram of waveforms corresponding to FIG. 6 in the present invention.

FIG. 7 is a schematic circuit diagram of a phase synthesis unit according to an embodiment of the present invention.

FIG. 8 is a schematic circuit diagram of a dual-rail reference voltage level generation unit according to an embodiment of the present invention.

FIG. 9 is a schematic circuit diagram of a pulse width modulation unit according to an embodiment of the present invention.

Fig. 10 is a schematic diagram of multi-phase application of the present invention.

In the picture:

Q1 upper bridge assembly Q2 lower bridge assembly

Phase A node 91 drivers

92 output inductance 93 output capacitor

94 resistors 95 resistors

1 Virtual current ripple pulse width modulation circuit

2 DC reference voltage level unit

3 integration and DC bias elimination unit

4 phase synthesis unit

5 dual-rail reference voltage level generation unit

6 PWM generating units

61 soft start circuit 31 integral part

32 DC bias elimination part 33 DC bias elimination part.

detailed description

In order to further explain the technical solution of the present invention, the present invention will be described in detail below through specific examples.

Please refer to FIG. 1, which is a circuit diagram of the converter circuit of the present invention. The converter of the present invention includes an upper bridge component Q1 and a lower bridge component Q2, and the upper and lower bridge components Q1 and Q2 are electrically connected to the input The power supply VIN, and the upper and lower bridge components Q1, Q2 are connected through the phase node A, and the phase node A is operated by the driver 91 to make the upper and lower bridge components Q1, Q2 perform switching operations, and the aforementioned lower bridge component Q2 can also be Diode (not marked in the figure), and the phase node A is connected to the output inductor 92, the output capacitor 93, and the current of the output inductor 92 is controlled to charge the output capacitor 93 to generate the output voltage VOUT, and in this embodiment, the voltage dividing resistor 94, The divided voltage of 95 is used to detect the change of the output voltage VOUT, and the present invention has a virtual current ripple pulse width modulation circuit 1, and the virtual current ripple pulse width modulation circuit 1 inputs the aforementioned phase node A voltage signal and responds The output voltage VOUT signal is output to the driver 91 to control the switching action of the upper and lower bridge components Q1 and Q2.

Please refer to FIG. 1 to FIG. 4 together, the virtual current ripple pulse width modulation circuit 1 of the present invention includes a DC reference voltage level unit 2, an integration and DC bias elimination unit 3, and a phase synthesis unit 4 , a dual-rail reference voltage level generation unit 5, a pulse width modulation generation unit 6, wherein the DC reference voltage level unit 2 provides a reference DC voltage level VREF (referring to FIG. 4 ), and an integration and DC bias elimination unit 3. The input end is connected to the phase node A voltage VSW signal, and connected to the DC reference voltage level unit 2, and has an integrating part 31 and a DC bias canceling part 32.

As shown in Figures 3 and 4, the square wave of the phase node A voltage signal is integrated and the DC bias elimination unit 3 forms a triangular wave Vint at the DC reference level, its waveform is as shown in Figure 4, and the slope of the triangular wave can be It reflects the change of the voltage signal of the phase node A, and the Vint waveform shown in FIG. 4 of this embodiment is an anti-phase type, and can also be an in-phase type.

The phase synthesis unit 4 receives the integral waveform voltage output by the integration and DC bias elimination unit 3 and the feedback detection output voltage VFB of the converter to superimpose and synthesize the triangular wave voltage in proportion. Its waveform is VEA in Figure 4, and the VEA voltage is used as the pulse Wide modulation parameter signal, and VEA in the figure is the inversion of Vint to form the corresponding VSW in-phase waveform.

The input side of the dual-rail reference voltage level generation unit 5 is connected to the DC reference voltage level unit 2, and is output to the pulse width modulation generation unit 6, and the dual-rail reference voltage level generation unit 6 generates the corresponding reference voltage level VREF as shown in Figure 4 Dual-rail upper and lower DC reference levels VREF+ and VREF- with the same positive and negative voltage difference.

The input side of the pulse width modulation generation unit 6 is connected to the output end of the phase synthesis unit 4 and the output end of the dual-rail reference voltage level generation unit 5, and is generated by the pulse width modulation parameter signal VEA input by the phase synthesis unit 4 and the dual-rail reference voltage level The upper DC reference level VREF+ input by the unit 5 is compared with the lower DC reference level VREF- to generate a pulse width modulation signal, and the pulse width modulation signal is input to the driver 91 to control the action of the upper and lower bridge components Q1 and Q2.

Please refer to Fig. 4, the output feedback voltage of the converter of the present invention is VFB, and when the VFB voltage decreases at time T1, the upper bridge component Q1 is turned on, and the voltage of VSW rises, and the upper and lower bridge components Q1 and Q2 are phased. The VSW voltage of node A is the VIN voltage, and when the output voltage VOUT rises at time T2, the lower bridge component Q2 is turned on, and the VSW voltage is reduced, and the voltage of the parallel phase node A is the ground potential, and due to the internal resistance of the output capacitor 93 (Fig. not marked in ) is charged by the current of the output inductor 92, the ripple of the feedback VFB corresponds to the different peak values of the characteristics of the output capacitor 93, and the Vint is the output voltage of the integration and DC bias elimination unit 3, and can generate a corresponding VSW voltage The triangular wave voltage of the reference voltage VREF level, and the triangular wave voltage of this embodiment is the reverse phase of the VSW voltage, and can also be designed as the same phase, and VEA is the phase synthesis unit 4 input converter output feedback voltage VFB and Vint voltage superimposed and reversed The pulse width modulation parameter voltage of the direction, and because the VEA is to invert the aforementioned Vint waveform, it can generate the corresponding VSW voltage in-phase waveform, and the VREF+ and VREF- are the positive and negative DC reference level voltages located at the reference voltage VREF , and the slope of the VEA voltage waveform of the present invention can be more responsive to the voltage change of VFB, and can generate an approximate triangular wave. Therefore, when the VEA voltage drops to T1 time and VREF- handover position or VEA voltage rises to T2 time and VREF+ handover position C When in position, the pulse width modulation unit can generate pulse width modulation signals to control the actions of the driver 91 and the upper and lower bridge components Q1 and Q2, and the present invention can accurately respond to output voltage changes to improve output voltage stability.

The integration and DC bias elimination unit 3, the phase synthesis unit 4, the dual-rail reference voltage level generation unit 5, and the pulse width modulation generation unit 6 involved in the present invention can be designed in various ways to achieve the aforementioned functional design, as shown in Figures 1 to 5 As shown, the integration and DC bias elimination unit 3 involved in the present invention has an integration part 31 and a DC bias elimination part 32, and the integration part 31 has a first operational amplifier OP1, and its inverting input terminal is connected to the first resistor R1 and The phase node A signal SW is electrically connected, the inverting input terminal is connected to the second resistor R2 and the output bias of the DC bias canceling part 32 is connected, and the output terminal of the first operational amplifier OP1 is connected to the inverting input terminal with the first capacitor C1, and the integral time constant is determined by R1 and C1, and its non-inverting input terminal is connected to the output contact REF of the DC reference voltage level unit 2, and the phase node A voltage VSW of the square wave can be integrated to form a triangular wave signal, and the voltage generated by bias can be Adjust the output DC level, and the DC bias elimination part 32 has an integrating circuit and an error amplifier circuit, and the input terminal of the integrating circuit is connected to the output terminal of the integrating part 31, and the error amplifier circuit is connected to the output terminal of the integrating circuit and the DC reference voltage level The quasi-unit output contact REF makes the integral part 31 form different DC level triangular waves (refer to FIG. 3 ) corresponding to the square wave duty ratio of the phase node A signal VSW, and can form the corresponding DC level waveform through the integration circuit, and then by the error The amplifying circuit compares the DC level waveform with the DC reference voltage level VREF of the DC reference voltage level unit 2, and the DC error amount is amplified and then input into the integral part 31, so that the integral part 31 outputs triangular wave voltages of different DC levels. It is adjusted to the triangular wave Vint located at the DC reference voltage level VREF, and the DC bias elimination part 32 has a second operational amplifier OP2, a third operational amplifier OP3, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a fifth resistor R5. Six resistors R6, the second capacitor C2, and the inverting input terminal of the second operational amplifier OP2 is connected to the third resistor R3 and the output terminal of the first operational amplifier OP1, and the fourth resistor R3 is connected in parallel between the inverting input terminal and the output terminal. Resistor R4 and second capacitor C2, and its non-inverting input terminal is connected to the output contact REF of the DC reference voltage level unit 2, and makes the second operational amplifier OP2 form an integrating circuit; and the inverting input terminal of the third operational amplifier OP3 is connected to the first The fifth resistor R5 is connected to the output terminal of the second operational amplifier OP2, and the sixth resistor R6 is connected between its inverting input terminal and output terminal, and its non-inverting input terminal is connected to the output contact REF of the DC reference voltage level unit 2 .

Please refer to Fig. 5 and Fig. 5A together, when the Vint output of the present invention has no DC error, the Vint output is VCR (output capacitor 93 internal resistance voltage) triangular wave plus VREF level after VSW integration; and when the aforementioned circuit makes the integral part 31 When the triangular wave signal input to the second operational amplifier OP2 has a DC error, the VCR can be eliminated through the second operational amplifier OP2 inverting and integrating to form a corresponding DC waveform signal Vdet output, and the DC waveform voltage output by the second operational amplifier OP2 is input to the third operational amplifier. OP3 is compared with the reference level voltage, and after being amplified by the error, it becomes the Vbias voltage and then fed into the inverting input terminal of the first operational amplifier OP1 of the integration part 31, so that the integration and DC bias elimination unit 3 outputs the VCR after VSW integration The triangular wave is added to the level of VREF to form a virtual ripple current triangular wave signal Vint corresponding to the level of the DC reference voltage.

Please refer to Fig. 1 to Fig. 6, the integration part 31 of another embodiment of the present invention is the same as Fig. 5, and the DC bias elimination part 33 is made up of comparison circuit, inverting integration circuit, and the comparison circuit of the present embodiment has the fourth operation Amplifier OP4, and its inverting input terminal is connected to the output of the integral part 31, and its non-inverting input terminal is connected to the output contact REF of the DC reference voltage level unit 2, and the integrating circuit has a seventh resistor R7, a third capacitor C3, and a fifth operation Effect amplifier OP5, and the inverting input terminal of the fifth operational amplifier OP5 is connected to the seventh resistor R7 and the output of the fourth operational amplifier OP4 of the comparison circuit, and the inverting input terminal is connected to the third capacitor C3 and the fifth operational amplifier. The output terminal of OP5 is connected, and the non-inverting input terminal of the fifth operational amplifier OP5 is connected to the output contact REF of the DC reference voltage level unit 2, so that when the Vint output has no DC error, the Vint output is the VCR triangular wave after VSW integration plus VREF As shown in Fig. 6, Fig. 6A and Fig. 6B, when the Vint output has a DC error, the integral waveform received by the integral part 31 takes the DC reference voltage level as the DC reference level VREF, and the comparison circuit and the DC reference The level VREF is compared, and the generated square wave is shown in the dotted line in Figure 6A. If the DC root mean square value is the same as the reference level voltage, the duty cycle of the square wave is 50%, and the output Vcomp of the comparison circuit is 2x reference The level voltage, where K=2, is integrated by the integrating circuit to generate a Vbias voltage corresponding to the Vint DC error amount, and as shown in Figure 5 and Figure 6B, the Vbias voltage can be input to the bias terminal of the aforementioned integrating part 31, which The phase can offset the DC error of Vint to adjust the output DC level of the integrating part 31 and form a triangular wave Vint signal corresponding to the DC reference voltage level.

Please refer to FIG. 1 to FIG. 4 and FIG. 7, the phase synthesis unit 4 has an error amplifier, and the input side inputs the integration and DC bias elimination unit 3 output voltage Vint and the converter output feedback voltage VFB, and the output pulse width is synthesized by superimposition modulation parameter signal, and the present embodiment has a sixth operational amplifier OP6, and the inverting input terminal of the sixth operational amplifier OP6 is connected to the eighth resistor R8 and the output contact Vint of the integral DC bias elimination unit 3, and the inverting input The ninth resistor R9 is connected to the output terminal of the sixth operational amplifier OP6, and the inverting input terminal is connected to the phase node between the eighth resistor R8 and the ninth resistor R9, and the non-inverting input terminal of the sixth operational amplifier OP6 is connected The converter outputs the feedback voltage contact FB, and the resistance values of the eighth resistor R8 and the ninth resistor R9 can be adjusted to obtain the corresponding integral and the appropriate ratio of the output voltage of the DC bias canceling unit 3 and the converter output feedback voltage VFB, which is relatively Preferably, Vint 1/20 corresponds to the VFB voltage, and the aforementioned voltage is superimposed and synthesized with the converter output feedback voltage VFB, and the slope of the triangular wave signal of the output voltage of the integration and DC bias elimination unit 3 is related to the converter output feedback voltage The slope vector of VFB is synthesized to form the output pulse width parameter signal VEA.

Please refer to FIG. 1 to FIG. 4 and FIG. 8, the dual-rail reference voltage level generation unit 5 has two comparison circuits, and one input end of the two comparison circuits is connected to a DC reference level signal, and the two comparison circuits are connected to a resistor, and The upper and lower DC reference levels corresponding to the same positive and negative difference of the DC reference voltage level are respectively outputted by setting the resistance value of the resistor. In this embodiment, it has a seventh operational amplifier OP7 and an eighth operational amplifier OP8, and the non-inverting input terminals of the seventh operational amplifier OP7 and the eighth operational amplifier OP8 are connected to the output contact REF of the DC reference voltage level unit 2, and The inverting input terminal of the seventh operational amplifier OP7 is connected to the tenth resistor R10 to be grounded, and the inverting input terminal is connected to the eleventh resistor R11 to be connected to the output terminal, and the output terminal of the seventh operational amplifier OP7 generates an upper DC reference level VREF+, And the inverting input end of the eighth operational amplifier OP8 is connected to the output end of the twelfth operational amplifier OP7 connected to the twelfth resistor R12, and the inverting input end is connected to the thirteenth resistor R13 to be connected to the output end of the eighth operational amplifier OP8, And the twelfth resistor R12 and the thirteenth resistor R13 and the inverting input terminal of the eighth operational amplifier OP8 have a phase node, and the output terminal of the eighth operational amplifier OP8 generates a lower DC reference level VREF-, and the upper The DC reference voltage level VREF+ is VREF+ (VREF ＊ R11/R10), and the DC reference voltage level VREF- is [(VREF+-VREF)*-1]+VREF. If the reference level VREF voltage is 1V, the The ten resistor R10 is 99K, and the eleventh resistor R11 has a resistance value of 1K, then VREF+=1+(1 * 1K/99K)=1.01V, and VREF-=[(1.01V-1V)*-1]+1V= 0.99V.

Please refer to FIG. 1 to FIG. 4 and FIG. 9, the pulse width modulation generating unit 6 of the present invention has two comparison circuits, and the input end of the comparison circuit is connected to the pulse width modulation parameter signal EA and the upper DC reference level REF+, and the other The input terminal of the comparison circuit is connected with the pulse width modulation parameter signal EA and the lower DC reference level REF-, and the output of the two comparison circuits forms a square wave signal reflecting the slope change of the pulse width modulation parameter signal, and the square wave signal can be normalized The inverter amplifies and cooperates with the soft-start circuit to generate a pulse width modulation signal, and the present embodiment has the ninth operational amplifier OP9, the tenth operational amplifier OP10, the RS flip-flop, and the soft-start circuit 61, and the soft-start circuit 61 is a power supply The known technology of the converter is no longer described, and the non-inverting input terminal of the ninth operational amplifier OP9 is connected to the pulse width modulation parameter signal EA input by the phase synthesis unit 4, and the inverting input terminal of the ninth operational amplifier OP9 Connect the upper DC reference level REF+, and connect the inverting input terminal of the tenth operational amplifier OP10 to the pulse width modulation parameter signal EA input by the phase synthesis unit 4, and connect the non-inverting input terminal to the lower DC reference level REF-. The output terminals of the nine operational amplifiers OP9 and the tenth operational amplifier OP10 are respectively connected to the R terminal and the S terminal of the RS flip-flop, and the Q terminal of the RS flip-flop and the output terminal of the soft start circuit 61 are connected to an AND gate, and the AND gate The output generates a pulse width modulation signal PWM, so that when the slope of the voltage waveform of VEA rises to the VREF+ level, the ninth operational amplifier OP9 outputs a high potential square wave, and makes the RS flip-flop output Q a low potential to reduce the output voltage of the converter , and when the slope of the voltage waveform of VEA decreases to VREF-level, the tenth operational amplifier OP10 outputs a high-potential square wave, and makes the RS flip-flop output Q a high potential to increase the output voltage of the converter.

Please refer to FIG. 10, the present invention has a pulse width modulation structure consisting of a virtual current ripple pulse width modulation circuit 1, a driver 91, and upper and lower bridge components Q1, Q2, and the input ends of each pulse width modulation structure are connected to the same response Output voltage signals, and each pulse width modulation structure is connected to a corresponding output inductor, and the corresponding output inductors are respectively connected to the same output capacitor for multi-phase configuration, so that the present invention can increase the output current according to the load demand, and the figure shown in the figure It is shown that two sets of PWM architectures are connected in parallel, and more than two sets of PWM architectures can be set in parallel with the load.

The foregoing circuits of the present invention are examples of the present invention, and are not intended to limit the scope of the patent application of the present invention. All equivalent changes shown according to the spirit of the present invention shall also fall within the scope of the patent application of the present invention.

Claims (10)

1. A power converter pulse width modulation control circuit, the power converter includes at least one upper bridge component and a lower bridge component, and the upper and lower bridge components are electrically connected to the input power supply, and the upper and lower bridge components are passed through The phase node is connected, and the parallel phase node is operated by the driver controlled by the pulse width modulation signal to make the upper and lower bridge components switch. In addition, the phase node is connected to the output inductor and output capacitor, and the output inductor current is controlled to charge the output capacitor. Generate an output voltage; it is characterized in that the pulse width modulation control circuit includes a virtual current ripple pulse width modulation circuit, and the virtual current ripple pulse width modulation circuit has an integration and DC bias elimination unit, a phase synthesis unit and A dual-rail reference voltage level generation unit, the integration and DC bias elimination unit inputs the aforementioned phase node voltage signal and the signal reflecting the output voltage, and generates a virtual current ripple parameter signal at the DC reference voltage level, and the phase synthesis unit enables The virtual current ripple parameter signal and the slope vector of the output voltage signal synthesize a pulse width modulation parameter signal, and the dual-rail reference voltage level generation unit generates an upper and lower DC reference voltage level, and the pulse width modulation parameter signal is combined with the upper and lower DC reference voltage levels. The lower DC reference voltage level is compared to generate a pulse width modulation signal that is input to the aforementioned driver. 2. The power converter pulse width modulation control circuit according to claim 1, wherein the virtual current ripple pulse width modulation circuit further comprises a DC reference voltage level unit and a pulse width modulation generating unit , the DC reference voltage level unit provides a reference DC voltage level; the input terminal of the integration and DC bias elimination unit is connected to the aforementioned phase node voltage signal, and connected to the reference voltage level unit, and makes the square wave of the phase node voltage signal After integration and DC bias elimination, a triangular wave at the DC reference level is formed. The slope of the triangular wave can reflect the change of the phase node voltage signal. The phase synthesis unit receives the integrated waveform voltage output by the integration and DC bias elimination unit and the output voltage of the converter. Perform proportional superposition to generate a synthetic approximate triangular wave voltage, and use the voltage as a pulse width modulation parameter signal; the input side of the dual-rail reference voltage level generating unit is connected to a DC reference voltage level unit, and is output to the pulse width modulation generating unit; The dual-rail reference voltage level generation unit generates a dual-rail DC reference voltage unit corresponding to the positive and negative reference voltage level voltage difference; the input side of the pulse width modulation generation unit is connected to the output terminal of the phase synthesis unit and the dual-rail reference voltage level generation unit The output terminal of the unit, and compare the pulse width modulation parameter signal input by the phase synthesis unit with the upper DC reference level and the lower DC reference level of the dual-rail reference voltage level generation unit, and generate a pulse width modulation signal. 3. The power converter pulse width modulation control circuit as claimed in claim 2, wherein the integration and DC bias elimination unit has an integration part and a DC bias elimination part, and the integration part connects the upper and lower bridge components The signal integration of the square wave at the phase node forms a triangular wave signal. The DC bias elimination part has an integration circuit and an error amplifier circuit. The input terminal of the integration circuit is connected to the output terminal of the integration part. The reference voltage level unit outputs, and makes the output of the integral part correspond to the phase node signal of the upper and lower bridge components. The corresponding DC level waveform can be formed through the integration circuit, and then the error amplifier circuit makes the DC level waveform and the DC reference voltage level The DC reference voltage level of the unit is compared, and the DC error voltage is amplified and then input to the integral part, so that the triangular wave voltage output by the integral part at different DC levels can be adjusted to a triangular wave at the DC reference voltage level. 4. The power converter pulse width modulation control circuit according to claim 2, wherein the integration and DC bias elimination unit has an integration part and a DC bias elimination part, and the integration part connects the upper and lower bridge components The signal integration of the square wave at the phase node forms a triangular wave signal. The DC bias elimination part is composed of a comparison circuit and an integration circuit. The input terminal of the comparison circuit is connected to the output signal of the integration part and the output signal of the DC reference voltage level unit. The integration circuit The input terminal is connected to the comparison circuit and the output signal of the DC reference voltage level unit, so that the integral waveform received by the integral part takes the DC reference voltage level as the DC reference level, and is compared with the DC reference level voltage by the comparison circuit, and then integrated by the integration circuit Then generate a DC error output voltage corresponding to the DC reference voltage level corresponding to the reference level voltage, and input the voltage into the aforementioned integration part to adjust the output DC level of the integration part, and form a triangle wave at the corresponding DC reference voltage level. 5. The pulse width modulation control circuit of a power converter as claimed in claim 2, wherein the phase synthesizing unit has an error amplifier, and the input side of the error amplifier is input to an integration and DC bias elimination unit and a converter output back Supplied voltage, and output pulse width modulation parameter signal through superposition synthesis. 6. The pulse width modulation control circuit of a power converter as claimed in claim 2, wherein the dual-rail reference voltage level generation unit has two comparison circuits, and an input terminal of the two comparison circuits is connected to a DC reference level, The two comparator circuits are connected with resistors, and the resistance values of the resistors are used to set the upper and lower DC reference levels corresponding to the same positive and negative difference of the DC reference voltage levels. 7. The pulse width modulation control circuit of a power converter according to claim 2, wherein the pulse width modulation generation unit has two comparison circuits, and one of the comparison circuit input terminals of the two comparison circuits is connected to the pulse width modulation circuit. The parameter signal and the upper DC reference level signal are modulated, and the input terminal of the other comparison circuit of the two comparison circuits is connected to the pulse width modulation parameter signal and the lower DC reference level signal, and the output of the two comparison circuits forms a reaction pulse width modulation A square wave signal with a parameter signal slope change. 8. The power converter pulse width modulation control circuit according to claim 2, characterized in that it comprises a pulse width modulation architecture composed of a virtual current ripple pulse width modulation circuit, a driver, and upper and lower bridge components, The input terminals of each PWM structure are connected to the same response output voltage signal, and each PWM structure is respectively connected to a corresponding output inductor, and the corresponding output inductors are respectively connected to the same output capacitor for multi-phase configuration. 9. A pulse width modulation control method for a power converter, the power converter includes at least one upper bridge component and a lower bridge component, and the upper and lower bridge components are electrically connected to the input power supply, and the upper and lower bridge components are passed through The phase node is connected, and the parallel phase node is operated by the driver controlled by the pulse width modulation signal to make the upper and lower bridge components switch. In addition, the phase node is connected to the output inductor and output capacitor, and the output inductor current is controlled to charge the output capacitor. Generate an output voltage; it is characterized in that, the pulse width modulation control method comprises the following steps: a. Take the square wave voltage signal of the phase node, and set the DC reference voltage level, and the signal is processed by integration and DC bias elimination to generate a virtual current ripple parameter signal at the DC reference voltage level; b. Superimpose the response output voltage signal and the virtual current ripple parameter signal to synthesize a pulse width modulation parameter signal with an approximate triangular wave; c. Detect the pulse width modulation parameter signal and generate a pulse width modulation signal to control the action of the upper and lower bridge components. 10. The pulse width modulation control method of a power converter as claimed in claim 9, wherein the detection method of the aforementioned step c is provided with an upper and a lower DC reference voltage corresponding to the same positive and negative voltage difference of the DC reference voltage level. The voltage level, and the pulse width modulation signal can be generated when the rising and falling waves of the pulse width modulation parameter signal are respectively at the level of the upper and lower DC reference level signals.