JP5116127B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device excellent in high-speed and low-power operation characteristics.

  As described in “Identifying defects in deep-submicron CMOS Ics”, IEEE Spectrum, pp. 66-71, September, 1996 (hereinafter referred to as Reference 1) Leakage current (junction leakage current such as subthreshold leakage current, gate tunnel leakage current, GIDL (Gate-Induced Drain Leakage) current) is increasing. Those leakage currents increase the current consumption of the chip. As a conventional example of a method for reducing the subthreshold leakage current, “A Low Power Data Holding Circuit with an Intermittent Power Supply scheme”, Symposium on VLSI Circuits Digest of Technical Papers, pp. 14-15, 1996 (hereinafter referred to as Reference 2) There is a method described in the above. In Reference 2, the power supply of the circuit block is configured in series with a MOS transistor having a threshold voltage whose absolute value is sufficiently larger than the absolute value of the threshold voltage of the MOS transistor constituting the circuit block. Insert the power switch on the power supply side and ground side. In this specification, the word MOS transistor is used as a general term for an insulated gate field effect transistor. The power supply voltage supplied to the circuit is defined as a high potential and a low potential, but these terms are used to represent a high potential for the power supply and a low potential for the ground. When the chip is on standby, the sub-threshold leakage current passing through the circuit block is cut off by turning off the power switch. Normally, when the power switch is turned off, the power supply to the circuit block is cut off. Therefore, the information holding circuit included in the circuit block (for example, static memory, flip-flop, latch, register file, etc.) holds volatile information. The information stored in the functional circuit is lost. However, in practice, a certain time (TR) is required from when the power switch is turned off until information in the information holding circuit is lost. For this reason, in Document 2, the power switch is turned on again before the TR time has elapsed since the power switch was turned off (hereinafter, this re-power-on is referred to as a refresh operation). Thereafter, the power switch is turned off again after a certain time, and this is repeated to prevent the loss of information in the information holding circuit and reduce the power consumption of the circuit block due to the subthreshold leakage current.

  In the method described in “A Novel Powering-down Scheme for Low Vt CMOS Circuits”, Symposium on VLSI Circuits Digest of Technical Papers, pp. 44-45, 1998 (hereinafter referred to as Reference 3), the power switch The circuit block connection relationship is the same as that of Document 2. In Document 3, a diode is connected in parallel with the power switch to clamp an excessive drop in the voltage of the power supplied to the circuit block (potential difference between the power supply side and the ground side) when the power switch is turned off. The information loss of the information holding circuit inside is prevented. In the numerical example illustrated in Document 3, the voltage difference of the power supplied to the circuit block when the power switch is turned off is 0.7 V or more, and the threshold voltage of the MOS transistor constituting the circuit block (PMOS is -0.14V, NMOS is 0.31V).

“Identifying defects in deep-submicron CMOS Ics”, IEEE Spectrum, pp. 66-71, September, 1996 “A Low Power Data Holding Circuit with an Intermittent Power Supply scheme”, Symposium on VLSI Circuits Digest of Technical Papers, pp. 14-15, 1996 “A Novel Powering-down Scheme for Low Vt CMOS Circuits”, Symposium on VLSI Circuits Digest of Technical Papers, pp. 44-45, 1998

  The power switch is composed of a MOS transistor having a sufficiently large threshold voltage. In the method of Document 2, the power switch is repeatedly turned on and off during standby of the chip, and the node in the circuit block is Repeated charging / discharging. In general, a large-size MOS transistor is used for a power switch in order to prevent speed deterioration during operation of a circuit block. Further, the parasitic capacitance of all nodes of the circuit block depends on the circuit scale and may exceed several nF. Therefore, repeated ON / OFF of the power switch and repeated charging / discharging of the nodes in the circuit block increase the power consumption of the chip.

  On the other hand, in the method of Document 3, the voltage of the power supply (potential difference between the power supply side and the ground side) supplied to the circuit block when the power switch is turned off is the threshold voltage (PMOS is the PMOS) of the circuit block. -0.14V, NMOS is larger than the absolute value of 0.31V).

  The present inventors have found that even when the power supply voltage when the power switch is turned off is lower than the absolute value of the threshold voltage of the MOS transistor, information of the information holding circuit can be maintained, and information of the information holding circuit is maintained. However, the present inventors have invented a configuration that can further reduce leakage power.

  A typical embodiment of the present invention for solving the above problems is a semiconductor integrated circuit device comprising a circuit block having a first MOS transistor and a leakage current control circuit having a second MOS transistor and a current source. The source / drain path of the second MOS transistor is provided between a potential point to which an operating potential is supplied and the power supply line of the circuit block, the current source is connected to the power supply line, In the state, the power line is driven to the first voltage by the second MOS transistor, and in the second state, the power line is controlled to the second voltage by the current flowing through the current source, The voltage applied to the source-drain voltage of the first MOS transistor in the state is smaller than the voltage applied to the source-drain voltage of the first MOS transistor in the first state. That.

  When the circuit block is in a standby state, information stored in the information holding circuit in the circuit block can be held while reducing various leak currents (subthreshold leak current, GIDL current, gate tunnel leak current, etc.). Further, when the circuit block is in an operating state, the circuit block can be operated at high speed.

It is a figure which shows the Example of the leakage current reduction method of this invention. It is a figure which shows the timing chart of the operation example of FIG. It is a figure which shows the drain-source voltage dependence of the threshold voltage of a MOS transistor. It is a figure which shows the timing chart at the time of discharging a pseudo power supply line completely. It is a figure which shows the characteristic at the time of operation | movement of an inverter. It is a figure which shows the characteristic at the time of standby of an inverter. It is a figure which shows the characteristic at the time of standby of an inverter. It is a figure which shows the structural example which controlled the substrate bias potential of the circuit block. It is a figure which shows the timing chart of the operation example of FIG. It is a figure which shows the characteristic at the time of standby of an inverter in the structure of FIG. It is a figure which shows another structural example which controlled the substrate bias potential of the circuit block. It is a figure which shows the structural example using the current source different from FIG. It is a figure which shows the timing chart of the operation example of FIG. It is a figure which shows the structural example using the current source different from FIG. It is a figure which shows the structural example using resistance as a current source of FIG. It is a figure which shows the structural example using a constant current circuit as a current source of FIG. It is a figure which shows the structural example using the voltage source instead of the current source of FIG. It is a figure which shows the structural example which implement | achieves a deep standby state. It is a figure which shows the timing chart of the operation example of FIG. It is a figure which shows the structural example using an NMOS transistor as a power switch. It is a figure which shows the structural example at the time of using both a PMOS transistor and an NMOS transistor as a power switch. It is a figure which shows the structural example of the external interface of a power switch controller. It is a figure which shows the structural example of the power switch controller which performs the slew rate control of a virtual power line. FIG. 24 is a diagram illustrating a timing chart of the operation example of FIG. 23. It is a figure which shows another structural example of the power switch controller which performs the slew rate control of a virtual power line. It is a figure which shows the timing chart of the operation example of FIG. It is a figure which shows another structural example of the power switch controller which performs the slew rate control of a virtual power line. It is a figure which shows the timing chart of the operation example of FIG. It is a figure which shows another structural example of the power switch controller which performs the slew rate control of a virtual power line. It is a figure which shows the timing chart of the operation example of FIG. It is a figure which shows the structural example of the static memory of this invention. FIG. 32 is a diagram illustrating a timing chart of the operation example of FIG. 31. It is a figure which shows another structural example of the static memory of this invention. It is a figure which shows the timing chart of the operation example of FIG. It is a figure which shows the structural example of the chip | tip of this invention. It is a figure which shows the structural example of the chip | tip at the time of inputting three types of power supplies. It is a figure which shows the structural example of the chip | tip which produced | generated one power supply with the internal voltage reduction circuit. It is a figure which shows the structural example which merged the power switch and the pressure | voltage fall circuit. It is a figure which shows the structural example of the chip | tip at the time of comprising a power switch using an NMOS transistor. It is a figure which shows the structural example of the latch type level conversion circuit of this invention. It is a figure which shows the definition of the threshold voltage Vth of a MOS transistor.

<First Embodiment>
FIG. 1 shows a basic configuration example of the present invention. CKT is a circuit block, PSW1 is a power switch, PSW2 is a current source, VDD is a power supply and a voltage is, for example, 1.0V, VVDD is a virtual power supply line, VSS is ground, a voltage is 0V, and PSC is a power switch controller. As shown in FIG. 1, the circuit block CKT includes, for example, a logic circuit LG1 including an inverter INV, a NAND circuit NAND, a NOR circuit NOR, a flip-flop circuit FF, a memory cell array MARY, a word decoder DEC, and a sense amplifier SA. It consists of memory MEM1 etc. The circuit block CKT may be configured to include only the logic circuit LG1 or only the memory MEM1. One feature is that an information holding circuit is included such as the flip-flop FF and the memory cell array MARY of the logic circuit LG1. Here, the information holding circuit is a circuit having a volatile information holding function, and in particular, the information is determined by CMOS logic.

  The power controller PSC controls on / off of the power switch PSW1 connected between the power supply VDD and the virtual power supply line VVDD, and controls the current flowing through the virtual power supply line VVDD and the power supply VDD. A current source is also connected between the power supply VDD and the virtual power supply line VVDD to limit the current flowing from the power supply VDD to the virtual power supply line VVDD. The circuit block CKT is connected between the virtual power supply line VVDD and the ground VSS, and the virtual power supply line corresponds to a substantial power supply for the circuit block CKT. That is, the current supplied to the circuit block during operation is mainly supplied from the power switch PSW1, and the current supplied to the circuit block during standby is mainly supplied from the current source PSW2. Although not shown in FIG. 1, the potential of the power supply VDD is the operating potential of the circuit block CKT and is supplied from a stabilized power supply circuit.

  Hereinafter, an operation example of FIG. 1 will be described with reference to a timing chart of FIG. Before time T1, the gate signal PSWGATE1 of the power switch PSW1 is driven to a low level by the power switch controller PSC, and the power switch PSW1 is in the on state. In this state, since power is supplied to the circuit block CKT via the power switch PSW1, the virtual power supply line VVDD is at the VDD potential, and the circuit block CKT is in an operable state (operating state). At time T1, the power switch controller PSC drives the gate signal PSWGATE1 of the power switch PSW1 to a high level, and the power switch PSW1 is turned off. When the power switch PSW1 is turned off, the virtual power supply line VVDD is gradually discharged by a leak current flowing from the virtual power supply line VVDD of the circuit block CKT to the ground VSS. As the potential of the virtual power supply line VVDD decreases, Ioff (CKT) (leakage current flowing through the circuit block CKT is expressed as Ioff (CKT), which is large at the beginning (time T1) gradually). (Time between time T1 and time T2). Eventually, the virtual power supply line VVDD converges to a certain voltage level VFNL (between time T2 and time T3). This converged voltage level is determined by the leakage current (Ioff (CKT)) flowing from the virtual power supply line VVDD of the circuit block CKT to the ground VSS, and the off current (Ioff (PSW1) of the power switch PSW1 flowing from the power supply VDD to the virtual power supply line VVDD. ) And the current I (PSW2) flowing from the power supply VDD to the virtual power supply line VVDD via the current source PSW2 is determined to be equal to the value.

  Although not particularly limited, for the sake of simplicity, the condition of Ioff (PSW1) << I (PSW2) is set. For example, the absolute value of the threshold voltage of the PMOS transistor constituting the power switch PSW1 may be made larger than the absolute value of the threshold value of the PMOS transistor constituting the current source PSW2. In this case, the condition for the virtual power supply line VVDD to converge is Ioff (CKT) = I (PSW2). As described above, the current source PSW2 is used for the purpose of preventing an excessive decrease in the voltage of the virtual power supply line VVDD. As a result, even if Ioff (CKT) at the initial stage (time T1) is large, the potential of the virtual power supply line VVDD is lowered so that it eventually becomes equal to I (PSW2) and automatically reaches a stable point. The value of Ioff (CKT) is restricted by the value of I (PSW2). That is, the current source PSW2 functions as a leakage current limiting circuit for the circuit block CKT.

  In this specification, the threshold voltage Vth of a MOS transistor is the value of the gate voltage when the drain current of the MOS transistor (this current does not include the subthreshold leakage current) starts to flow. The definition is widely used. In a saturation region where the gate voltage Vgs is sufficiently large and the drain voltage Vds is also sufficiently large, the drain current Ids is proportional to (Vgs−Vth) to the γ power. Therefore, the drain current Ids raised to the 1 / γ power is a straight line at a sufficiently large gate voltage Vgs as shown in FIG. Therefore, for example, the threshold voltage Vth can be read as shown in FIG. 41 from the tangent of the linear part of (Vgs−Vth) to the 1 / γ power as shown in FIG. Note that the value of γ greatly depends on the gate length of the MOS transistor. In general, in a long channel MOS transistor having a gate length Lg of about 1 μm, γ is a value of about 2, and in a short channel MOS transistor having a gate length Lg of 0.25 μm or less, γ is a value smaller than 2, for example, a value of about 1.4. Become.

  As described above, in the present invention, the magnitude of all the leakage currents such as the standby subthreshold leakage current and the gate tunnel leakage current of the circuit block CKT is determined by the current source PSW2, and the value is determined during operation. It becomes a value smaller than the leak current flowing through. Hereinafter, the mechanism will be described in detail.

Generally, Ioff (CKT) decreases as the potential of the virtual power supply line VVDD decreases. The reason for this will be described by taking the leakage current flowing through the inverter INV in the circuit block CKT as an example.
(1) As the potential of the virtual power supply line VVDD becomes smaller, the source potential of the PMOS transistor MP1 becomes a smaller voltage. On the other hand, the substrate potential of the PMOS transistor MP1 is connected to the power supply VDD and is a constant voltage. Therefore, a reverse bias is applied between the source and the substrate, and the threshold voltage of the PMOS transistor MP1 rises due to the substrate bias effect. This reduces the subthreshold leakage current flowing between the source and drain of the PMOS transistor MP1.
(2) Since the potential of the virtual power supply line VVDD is reduced, the voltage between the source and drain of the PMOS transistor and the NMOS transistor is reduced. Thereby, the threshold voltage of the PMOS transistor and the NMOS transistor is increased by the DIBL (Drain Induced Barrier Lowering) effect. As a result, the subthreshold leakage current flowing between the PMOS transistor and the source / drain of the NMOS transistor is reduced. The DIBL effect appears more prominently when the substrate and the source are reverse-biased as in (1) above.
(3) Since the potential of the virtual power supply line VVDD is reduced, the source-gate voltage and the drain-gate voltage of the PMOS transistor and the NMOS transistor are reduced. This reduces the gate tunnel current flowing through the gate insulating film. Further, a GIDL (Gate Induced Drain Leakage) current flowing from the drain or source to the substrate is also reduced.

  FIG. 3 is an actual measurement example showing the effect of reducing leakage according to the present invention. The measured value of the drain-source voltage VDS dependency of the threshold voltage Vth of the NMOS transistor is shown. The manufacturing process is 0.13 μm CMOS (gate oxide film thickness is 1.9 nm), and the measurement temperature is room temperature. The source-substrate voltage VBS is used as a parameter. By reverse biasing VBS and reducing VDS, the threshold voltage is increased by about 0.15V. This means that when the subthreshold slope coefficient S is 75 mV / dec, the leakage current flowing between the drain and the source can be reduced by about two orders of magnitude.

  Further, in the present invention, as shown in FIG. 2, in order to hold the information stored in the information holding circuit in the circuit block CKT, the convergence voltage value VFNL of the virtual power supply line VVDD during standby is information It is higher than the minimum voltage VRTN that can hold the information stored in the holding circuit. In the numerical example of FIG. 2, VDD is 1.0V, VFNL is 0.4V, and VRTN is 0.2V. Since there is no equivalent to the current source PSW2 in Document 2, the power supply of the circuit block is completely shut off during standby, and the virtual power supply line VVDD potential is discharged until Ioff (CKT) = Ioff (PSW1) ≈ 0. It becomes 0V. Therefore, as shown in FIG. 4, VFNL = 0 <VRTN, and the information stored in the information holding circuit cannot be held. On the other hand, in Document 3, the standby power supply voltage is set to a value larger than the absolute value of the threshold voltage of the MOS transistors constituting the circuit block CKT. This is presumed that if the power supply voltage is made lower than the threshold voltage of the MOS transistor during standby, the on-state MOS transistor is cut off and the logic is lost. However, in a CMOS logic circuit, making the power supply voltage smaller than the threshold voltage of the MOS transistor is not equivalent to losing its logic state. In the CMOS logic circuit in which the first conductivity type MOS transistor and the second conductivity type MOS transistor are connected in series, the inventors are in an off state and a current that can flow through the first conductivity type MOS transistor in the on state. It has been noted that whether or not the logic state is maintained is determined by the on / off ratio with the current that can flow through the MOS transistor of the second conductivity type.

  As a representative example of the CMOS logic circuit, an inverter INV in the circuit block CKT is taken as an example to explain a leakage current reduction mechanism and a mechanism for maintaining information by the information holding circuit. FIG. 5 is a characteristic diagram during operation of the inverter INV. The horizontal axis represents the input voltage of the inverter and corresponds to the gate signal voltage of the PMOS transistor MP1 and the NMOS transistor MN1. The vertical axis represents the logarithm of the drain current value I (ds) at each gate voltage. When the input of the inverter INV is at a high level (the power supply voltage VDD as a voltage), the PMOS transistor MP1 is in an off state, becomes a point d1 in the characteristic diagram, and the drain current of MP1 flows by Ioff1_p. Further, the NMOS transistor MN1 is in an on state, and becomes a point c1 in the characteristic diagram, and the drain current of MN1 flows by Ion1_n. On the other hand, when the input of the inverter is at a low level (the voltage is ground VSS), the PMOS transistor MP1 is in an on state and becomes a point a1 in the characteristic diagram, and the drain current of MP1 flows by Ion1_p. Further, the NMOS transistor MN1 is in an off state, and becomes a point b1 in the characteristic diagram, and the drain current of MN1 flows by Ioff1_n. It can be seen that there is an on / off ratio of Ion1_n / Ioff1_p when the input of the inverter is at a high level, and an on / off ratio of Ion1_p / Ioff1_n when the input of the inverter is at a low level. In any case, it can be seen that a sufficient on / off ratio of 1 or more is obtained. Regarding the leakage current, it can be seen that the current Ioff1_n flows when the input of the inverter is at a low level, and the current Ioff1_p flows when the input of the inverter is at a high level. On the other hand, FIG. 6 is a characteristic diagram of the inverter INV when the potential of the virtual power supply line VVDD is discharged to V1 when the circuit block CKT is on standby. As shown in FIG. 6, the potential V1 is made smaller than the absolute value of the threshold voltage of the MOS transistor at the normal time. However, even in this case, there is an on / off ratio of Ion2_n / Ioff2_p when the input of the inverter is high, and there is an on / off ratio of Ion2_p / Ioff2_n when the input of the inverter is low. Recognize. In any case, it can be seen that a sufficient on / off ratio of 1 or more is obtained. Therefore, since the logic state can be normally maintained as the logic circuit, the information stored in the information storage circuit that stores information based on the CMOS logic can be correctly held. There is also no need for a special holding circuit to maintain the logic state. Further, regarding the leakage current, it can be seen that the current Ioff2_n flows when the input of the inverter is at a low level, and the current Ioff2_p flows when the input of the inverter is at a high level. Ioff2_n <Ioff1_n and Ioff2_p <Ioff1_p due to the effects described above (substrate bias effect, DIBL effect, gate leak reduction effect, GIDL current reduction effect), etc. In the case of FIG. 6 as compared to FIG. The leak current of the inverter is small. Here, focusing on the on / off ratio of the MOS transistor, we examined whether the CMOS circuit can maintain the logic state normally. For example, in the case of an inverter, even when the on / off ratio is 1 or more, the on / off ratio characteristic is generally poor, and the absolute value of the amplification factor of the inverter becomes 1 or less at all input voltage levels. In this case, it cannot be guaranteed that the logic state can be normally maintained in the entire inverter connected in multiple stages. In this specification, a state where a sufficient on / off ratio is obtained is a state in which the logic state can be normally maintained in a multistage CMOS circuit or a circuit having a positive feedback loop such as an SRAM memory cell. Say.

  Next, the minimum voltage VRTN that can hold the information stored in the information holding circuit in the circuit block CKT, for example, the SRAM cell and the flip-flop circuit FF, will be considered.

  FIG. 7 is a characteristic diagram of the inverter INV when the potential of the virtual power supply line VVDD is discharged to a voltage V2 lower than the voltage V1 of FIG. 6 when the circuit block CKT is on standby. When the input of the inverter is high level, there is an on / off ratio of Ion3_n / Ioff3_p, and a sufficient on / off ratio of 1 or more is obtained, but when the input of the inverter is low level, Ion3_p / Ioff3_n < 1 indicates that a sufficient on / off ratio is not obtained. At this time, when the input of the inverter is at a low level, the logic of the inverter may be inverted.

  6 and 7, the standby voltage of the virtual power supply line VVDD for normally maintaining the logic state of the inverter INV can be determined as a value between V1 and V2. Similarly, even in the case of a so-called complete CMOS static RAM (SRAM) using, for example, six transistors, the minimum virtual power supply voltage for normal operation can be determined. Here, the normal operation means that information in the information holding circuit can be held. Since there is no need to operate in an AC manner, there is little need to pay attention to the static noise margin (SNM) of SRAM. When the lower limit voltage VRTN is reduced, there is a concern about deterioration of the soft error tolerance. However, measures such as adding a capacity to the storage node of the information holding circuit and adding an error correction circuit such as ECC. The treatment is effective.

  In the present invention, a voltage that allows the circuit in the circuit block CKT to maintain its DC state (logic state) during standby is determined as VRTN. This value does not need to be larger than the absolute value of the threshold voltage of the MOS transistor as in the numerical example of Reference 3, and in the present invention, the voltage is smaller than the absolute value of the threshold voltage of the MOS transistor. It was shown that the information in the information holding circuit can be held during standby. Further, in Document 3, the voltage corresponding to VFNL is determined by the clamp voltage of the diode, but in the configuration of FIG. 1, it is automatically determined by the balance of Ioff (CKT) and I (PSW2). This point will be described later.

  In the embodiment of FIG. 1, the substrate potential applied to the substrate terminal of the MOS transistor is basically the power supply VDD for the PMOS transistor and the ground VSS for the NMOS transistor. In this specification, the substrate potential is described based on the connection shown in FIG. 1, but the substrate potential is not particularly limited to this potential. The connection method of FIG. 1 has an advantage that it is not necessary to drive a substrate having a large capacity. However, it can be driven as required as will be described later. However, it goes without saying that in the case of connection with a substrate potential different from that in FIG. A modified example in which the leakage current reduction effect is further enhanced by lowering the substrate potential of the MOS transistor will be described.

  In the present invention, the minimum value VFNL of the virtual power line potential during standby is larger than the voltage VRTN. In addition, the smaller the VFNL, the greater the leakage reduction effect of the circuit block CKT during standby. Therefore, if the voltage VRTN can be reduced to a small value, VFNL can be reduced accordingly, and the leakage current of the circuit block CKT can be reduced. FIG. 8 shows a modification for setting VRTN to a value smaller than that of the embodiment of FIG.

  From the study of FIG. 7, the reason why Ion3_p / Ioff3_n <1 during standby and the logic state cannot be maintained is that the on-current (Ion3_p) of the PMOS transistor MP1 is discharged during the discharge of the virtual power line VVDD during standby. It can be seen that the cause is that the amount of decrease in the off-state current (Ioff3_n) of the NMOS transistor MN1 is smaller than the amount of decrease. Therefore, in the embodiment of FIG. 8, the substrate potential of the NMOS transistor MN1 is controlled during standby to increase the threshold voltage of the NMOS transistor. This makes it possible to satisfy Ion3_p / Ioff3_n> 1 even with a low virtual power supply line VVDD potential. VBC is a substrate bias control circuit, and VBN is a substrate bias signal of the NMOS transistor. A timing chart of this substrate potential control is shown in FIG. During standby (between times T1 and T3), the off-current (Ioff3_n) of the NMOS transistor MN1 is controlled by applying −1.5 V as the substrate bias signal VBN. FIG. 10 is a characteristic diagram of the inverter in the configuration example of FIG. As the threshold voltage of the NMOS transistor becomes higher, the curve of the NMOS transistor during standby shifts downward than in the case of FIG. As a result, even when the potential of the virtual power supply line VVDD is discharged to the same voltage V2 as in FIG. 7 during standby, the on / off ratio (Ion4_p / Ioff4_n) when the input of the inverter is low level is a sufficiently large value of 1 or more. ing.

  Thus, if the characteristics of the MOS transistors in the circuit block CKT are controlled well during standby, VRTN can be made smaller than when not controlled. The substrate bias control in FIG. 8 is an example of a method for effectively controlling the characteristics of the transistor. FIG. 11 shows an embodiment for controlling the substrate bias of the PMOS transistor and the NMOS transistor in the circuit block CKT. Since a low voltage is applied to the circuit block as a power source during standby, it is desirable to adjust the balance between the threshold voltages of the PMOS transistor and the NMOS transistor in order to operate the circuit normally. In FIG. 11, in addition to the embodiment of FIG. 8, the substrate bias signal VBP of the PMOS transistor is also controlled. Increasing the threshold voltage of the PMOS transistor acts to increase VRTN, but when reducing the leakage current as a whole, or in order to balance the threshold voltage of the PMOS transistor and the NMOS transistor, the PMOS transistor A configuration capable of independently controlling the threshold voltage of the NMOS transistor is effective.

  The substrate bias signals VBP and VBN at the time of operation are not particularly limited, but in order to operate the circuit block CKT at high speed, a low voltage (for example, VDD or lower voltage) is used for VBP, and a high voltage ( For example, a voltage of VSS or higher may be applied. Furthermore, an optimum potential may be applied to the substrate bias signals VBP and VBN according to the operation speed required for the circuit block CKT. 8 and 11 show the configuration example of the inverter INV in the circuit block CKT, but this is only shown as a typical example of the CMOS logic circuit, and holds information as shown in the circuit block of FIG. Needless to say, the present invention can be applied to various circuits including a circuit. Especially in substrate bias control, if the value of the substrate bias voltage applied to the substrate of the MOS transistor is determined according to the process, temperature, and power supply voltage, process variations and temperature / power supply voltage fluctuations can be compensated, and VRTN is a smaller value. Can be.

  Next, a specific configuration of the current source PSW2 will be described.

  VFNL is the off-state current Ioff (PSW1) of the power switch PSW1 flowing from the virtual power supply line VVDD of the circuit block CKT to the ground VSS, the off current Ioff (PSW1) of the power switch PSW1 flowing from the power supply VDD, and the current source from the power supply VDD This is determined under the condition that the current I (PSW2) flowing to the virtual power supply line VVDD via PSW2 is equal to the added value. If the condition of Ioff (PSW1) << I (PSW2) is satisfied as described above, the setting of VFNL becomes easy. The potential of the virtual power supply line VVDD during standby when this condition is satisfied is a value that satisfies Ioff (CKT) = I (PSW2) in a steady state. The condition Ioff (PSW1) << I (PSW2) can be satisfied by selecting device parameters of the power switch PSW1 and the current source PSW2. Further, the configuration example of FIG. 12 overdrives the gate signal of the power switch PSW1 to VDD + α during standby as shown in FIG. As a result, a reverse bias is applied between the source and gate of the power switch PSW1, and Ioff (PSW1) is reduced. This is a method for realizing the condition of Ioff (PSW1) << I (PSW2). Hereinafter, a configuration example of the current source PSW2 that satisfies the predetermined VFNL will be described with reference to FIGS.

  In the configuration examples of FIGS. 1 and 12, I (PSW2) connects the gate signal of the PMOS transistor PSW2 to the power supply VDD, so I (PSW2) is determined by the off-current of the PMOS transistor PSW2. Also, Ioff (CKT) is mainly determined by the off-state current of the MOS transistor. The drain-source current of the MOS transistor is mainly composed of diffusion current and drift current, the on-current is mainly drift current, and the off-current is mainly composed of diffusion current. The drift current and the diffusion current are characterized by their temperature characteristics being reversed. Since both I (PSW2) and Ioff (CKT) are mainly off-state current of MOS transistors and mainly sub-threshold leakage currents, the characteristic variation regarding temperature, power supply voltage VDD variation, process variation, etc. is the same. It is easy to become. That is, if I (PSW2) increases due to temperature changes, etc., Ioff (CKT) also increases, and if I (PSW2) decreases, Ioff (CKT) also decreases, resulting in fluctuations in the potential of the pseudo power supply line VVDD. Can be kept small. This has the advantage that the standby leakage current can be determined only by the gate width W of one MOS transistor, and the design of VFNL becomes easy.

  FIG. 14 shows a configuration example when the gate signal of the PMOS transistor constituting the current source PSW2 of FIG. 1 is connected to VSS. I (PSW2) is determined by the on-current of the PMOS transistor PSW2. As described above, Ioff (CKT) is mainly determined by the off-state current of the transistor. Therefore, in the case of the configuration of FIG. 14, the characteristic variation with respect to the temperature of I (PSW2) and Ioff (CKT), power supply voltage VDD variation, etc. May be different. Therefore, the design of the VFNL determined by the balance between I (PSW2) and Ioff (CKT) needs to be performed with careful attention to the above characteristic variation. However, the value of I (PSW2) can be determined by the on-current of the PMOS transistor PSW2, which means that the current consumption during standby of the circuit block CKT can be determined by the on-current of the PMOS transistor PSW2, as shown in FIG. Compared with the case where it is determined by the off-state current of the PMOS transistor PSW2, there is an advantage that the temperature dependency is small and the operation characteristics are stable. In addition, it is necessary to supply the current source PSW2 with a current sufficient to maintain information stored in the information holding circuit in the circuit block CKT. By supplying this current with the on-state current of the transistor, the current source PSW2 can be realized with a small area. There is an advantage.

  FIG. 15 shows an embodiment in which I (PSW2) is determined by the resistor R1. The method for implementing the resistance is not particularly limited. It may be a diffused resistor, a well resistor, or a gate wiring resistor. When realized by a resistor, there is an advantage that a current source PSW2 having a small temperature dependency can be realized.

  FIG. 16 shows an embodiment in which I (PSW2) is realized by a constant current circuit. The constant current circuit IS1 includes PMOS transistors MP10 and MN11 and a constant current source IS10. By configuring with a constant current circuit, the leakage current value of the circuit block during standby can be determined by the current determined by the constant current circuit without depending on the potential of the virtual power supply line VVDD or the scale of the circuit block CKT. There are advantages.

  Heretofore, various configuration examples of the current source PSW2 have been shown. In the present invention, power is supplied to the circuit block CKT mainly by the power switch PSW1 in the operating state, and power is supplied to the circuit block CKT mainly by the current source PSW2 in the standby state. It is important that the standby VFNL is determined by the balance between Ioff (CKT) and the current of the current source PSW2, and it is important that VFNL> VRTN is satisfied, and the structure of the current source is not limited to that described above. Therefore, the current source PSW2 is omitted, the VFNL is determined by the balance between the off currents Ioff (PSW1) and Ioff (CKT) of the power switch PSW1 during standby, and the size and threshold of the power switch PSW1 so that VFNL> VRTN It is also possible to determine the voltage or gate insulating film thickness (in this specification, the gate insulating film thickness is an effective gate insulating film thickness considering the dielectric constant of the gate insulating film material), the gate signal amplitude, etc. It is.

  For example, assuming that the current required to flow through the power switch PSW1 during operation is several A and the leakage current of the circuit block CKT during standby is several hundred μA, the on / off ratio of the power switch PSW1 may be four digits. Thus, when the on / off ratio required for the power switch PSW1 is small, the current source PSW2 is omitted from the configuration of FIG. 1, and the leakage reduction method of the present invention can be realized by controlling the power switch PSW1. Such a configuration excluding the current source PSW2 has the advantage of reducing the overhead of the circuit, while the advantage of installing the current source PSW2 is that the degree of design freedom is large. For example, if the on / off ratio of the power switch is large, the design of the power switch PSW1 that can realize the on / off ratio may be considered, and the balance between Ioff (PSW1) and Ioff (CKT) during standby There is no need to consider that. The current supplied to the circuit block CKT during operation is supplied from the power switch PSW1, and the current supplied to the circuit block CKT during standby is supplied from the current source PSW2, which makes it easy to design these leakage current control circuits. To do.

  FIG. 17 is another configuration example for setting the VFNL during standby. In FIG. 17, a predetermined step-down voltage VFNL is generated from the voltage source VFNLGEN during standby, and the virtual power line VVDD is driven. In the operating state, power is supplied to the circuit block by the power switch PSW1, and in the standby state, power is supplied to the circuit block by the voltage source VFNLGEN. The value of VFNL generated from the voltage source VFNLGEN during standby may be a value greater than or equal to VRTN, but it goes without saying that the lower the voltage, the smaller the leakage current of the circuit block CKT during standby. The structure of the voltage source VFNLGEN is not particularly limited. When the voltage source VFNLGEN is integrated on the same chip as the chip on which the circuit block CKT is integrated, for example, the power supply voltage VDD can be realized by a configuration that generates a desired VFNL by a known step-down circuit. Moreover, you may install outside the chip | tip. When the VFNL is directly generated by the voltage source VFNLGEN as shown in FIG. 17, there is an advantage that the potential of the virtual power supply line VVDD can be designed to a voltage close to VRTN. Further, the output voltage VFNL of the voltage source VFNLGEN can be automatically controlled according to the voltage, temperature, process conditions, etc. of the power supply VDD.

  The present invention is characterized in that it has a standby state in which the power consumption due to the leakage current of the circuit block is greatly reduced while the information in the information holding circuit in the circuit block is held. This standby state is called a retention standby state. In addition to this retention standby state, a state in which VFNL is made smaller (value below VRTN) by reducing the current flowing through current source PSW2 or reducing the voltage of voltage source VFNLGEN (configuration in FIG. 17). May be provided. With this configuration, information stored in the information holding circuit in the circuit block is lost, but the standby state is lower in power than the retention standby state (referred to as a deep standby state in contrast to the retention standby state). Then, these terms are used to distinguish the two).

  As an example, FIG. 18 shows a configuration example for realizing the deep standby state in the configuration example of FIG. In FIG. 18, the gate signal PSWGATE1a of the current source PSW2 is controlled by the power switch controller PSC. FIG. 19 is a timing chart showing an example of the operation of FIG. From time T1 to time T2, in the retention standby state, the power switch controller PSC applies a low level to the gate signal of the current source PSW2 as in the case of the embodiment of FIG. From time T2 to time T3 is a deep standby state, and a high level is applied to the gate signal of the current source PSW2 by the power switch controller PSC. In the retention standby state, I (PSW2) is determined by the ON current of the PMOS transistor PSW2, and VFNL is determined by the relationship between the ON current and Ioff (CKT), and VFNL> VRTN is satisfied. However, since the PMOS transistor PSW2 is turned off from the time T2 to the time T3, the VFNL is a value close to 0V (naturally a value equal to or less than the VRTN). The deep standby state has an advantage that the leakage current is lower than that of the retention standby state, although the information holding circuit cannot hold the information. When it is not necessary to hold information in the information holding circuit, it is possible to shift to a deep standby state and further reduce power consumption.

  In the above configuration example, a PMOS transistor is used for the power switch PSW1, and the current flowing between the power supply VDD and the virtual power supply line VVDD is controlled during standby. However, as shown in FIG. 20, the NMOS transistor PSW1n may be used as a power switch to control the current flowing between the virtual ground line VVSS and the ground VSS during standby. A configuration corresponding to the current source PSW2 of FIG. 1 is realized by the NMOS transistor PSW2n in FIG. Since the impedance of the virtual power supply line VVDD or the virtual ground line VVSS can be reduced when the on-resistance of the power switch during operation is smaller, the speed reduction of the circuit block CKT due to the application of the present invention can be prevented. In general, NMOS transistors have a smaller on-resistance per gate width than PMOS transistors. Therefore, the configuration example of FIG. 20 can suppress the speed reduction of the circuit block during operation with the same area overhead as the configuration example of FIG. 1, or a circuit having the same operation speed with a small area overhead. A block can be realized. FIG. 21 shows a configuration combining FIG. 1 and FIG. In the configuration example of FIG. 21, both the current source PSW2 and the current source PSW2n are provided, but a configuration in which only one of them is possible is also possible. It goes without saying that various modifications described in this specification can be applied to these configurations. However, the polarity may be different. For example, in order to apply the substrate bias control described in FIG. 8 in the configuration example of FIG. 20, it is necessary to increase the threshold voltage of the PMOS transistor instead of the NMOS transistor as in FIG. In the following description, a configuration using a PMOS transistor as a power switch and a current source will be described as an example, but it goes without saying that these can be realized by the configuration of FIG. 20 or FIG.

  The thickness and material of the gate insulating film of the MOS transistor constituting the power switch are not limited. In terms of reducing the on-resistance per area of the power switch PSW1 during operation, it is preferable that the MOS transistor constituting the power switch PSW1 also has a thin gate insulating film and the absolute value of the threshold voltage is small. However, if the gate insulating film thickness is thin, a large voltage may not be applied to the gate electrode. In order to reduce the gate tunnel leakage current during standby, a MOS transistor having a gate tunnel leakage current smaller than the total gate tunnel leakage current of the MOS transistors constituting the circuit block CKT was used for the power switch PSW1. Better. One configuration that satisfies all these trade-offs is to increase the gate insulating film thickness of the MOS transistor that constitutes the power switch PSW1 compared to the MOS transistor that constitutes the circuit block CKT. In addition, the voltage amplitude applied to the gate terminal of the power switch PSW1 is made larger than that of the power supply VDD power supply. When such a configuration is adopted, the MOS transistor constituting the power switch PSW1 includes an I / O circuit (an input buffer or an output buffer) for interfacing with the outside of the chip in a chip in which the circuit block CKT is integrated. The MOS transistor used in (1) can be used. This is because, in general, a MOS transistor used for an input buffer or an output buffer uses a gate insulating film thickness larger than that of the MOS transistor constituting the circuit block in order to increase the breakdown voltage. If the transistors used for the power switch and the I / O circuit are made common in this way, the types of insulating film thickness of the MOS transistors used in the entire chip can be reduced, and the cost can be reduced. In this case, the amplitude of the gate signal PSWGATE1 can be the same as the I / O voltage. As a result, the on-resistance can be reduced during operation, and a power switch with a sufficiently small leakage current can be realized during standby.

  Further, the threshold voltage of the power switch PSW1 may be higher than the threshold voltage of the MOS transistors constituting the circuit block. As a result, the condition of Ioff (PSW1) << I (PSW2) can be easily satisfied, and VFNL can be determined by I (PSW2), thereby facilitating the design of the present invention. Further, the gate length of the current source PSW2 may be larger than the gate length of the MOS transistors constituting the circuit block CKT. Such a configuration can reduce the variation in threshold value due to the process, and makes the magnitude of the leakage current flowing in the circuit block CKT in the standby state insensitive to the process variation.

  Next, an embodiment of the power switch controller PSC will be shown.

  FIG. 22 shows an embodiment of the interface of the power switch controller PSC. The power switch controller PSC that controls the power switch PSW1 and the current source PSW2 is controlled by the power control circuit PMG. As a result, the design of the low leakage mechanism for each circuit block CKT and the design of the power control circuit PMG for reducing the power consumption of the entire chip can be performed independently. On / off of the power switch PSW1 is controlled by the handshake between the power control circuit PMG and the power switch controller PSC by the request line REQ and the response line ACK to control the state of the circuit block. Here, the power switch PSW1 is turned on by setting the request line REQ to a high level, and the circuit block CKT is controlled to be in an operating state. After the power switch PSW1 is completely turned on and the potential of the power supply VDD is charged to the virtual power supply line VVDD, the response line ACK goes high, so that the circuit block operates outside the power switch controller (power control circuit PMG) Notify that the status has been changed. Conversely, the power switch PSW1 is turned off by setting the request line REQ to the low level, and the circuit block is controlled to be in a standby state. When the power switch PSW1 is completely turned off and the response line ACK becomes low level, the fact that the circuit block has shifted to the standby state is notified outside the power switch controller.

  In the device using the circuit block, when the circuit block is used in a state where the power switch PSW1 is not completely turned on, the circuit block may malfunction. In the embodiment of FIG. 22, it is possible to detect by the response line ACK that the circuit block has transitioned to the operating state, and the circuit block can be completely used, so this malfunction can be prevented.

  FIG. 23 shows a more detailed embodiment of the power switch controller PSC. C1 is a driving circuit for a gate signal PSWGATE1 having a small driving capability (hereinafter referred to as a high impedance driving circuit), and C2 is a driving circuit for a gate signal PSWGATE1 having a driving capability larger than that of C1 (hereinafter referred to as a low impedance driving circuit). , C3 is a potential detection circuit for the gate signal PSWGATE1, C1DRV is a C1 control circuit, C2DRV is a C2 control circuit, and TM1 is a timer.

  Hereinafter, the operation example of FIG. 23 will be described with reference to the timing chart of FIG. When transitioning from the standby state to the operating state, the request line REQ goes high at time T1, so that the gate signal PSWGATE1 is first driven with high impedance by C1 via the C1 control circuit C1DRV. The potential detection circuit C3 detects that the gate signal PSWGATE1 has been driven to a certain level (Vth1) at time T1A, and TRG1 is driven to high level by the timer TIM1. Thus, the gate signal PSWGATE1 is driven to a low impedance by C2 via the C2 control circuit C2DRV. The timer TM1 measures the time TA from the time T1 to the time T1A, and sets the response line ACK to high after a certain time TB (time T1B in the example of FIG. 24) determined with a predetermined relationship (for example, 1/2) with the time TA. Drive to level. The characteristics of the timer (relationship between time TA and time TB) are not particularly limited, but at time T1B, the gate signal PSWGATE1 is driven completely low, and the virtual power supply line VVDD is fully charged to the potential of the power supply VDD. What should I do?

  When transitioning from the operating state to the standby state, the request line REQ goes low at time T2, so that the gate signal PSWGATE1 is first driven with high impedance by C1 via the C1 control circuit C1DRV. The potential detection circuit C3 detects that the gate signal PSWGATE1 has been driven to a certain level Vth2 at time T2A, and TRG1 is driven to a low level by the timer TIM1. As a result, the gate signal PSWGATE1 is driven to a low impedance by C2 via the C2 control circuit C2DRV. The timer drives the response line ACK to the low level after a certain time (time T2B) based on the time from time T2 to time T2A. The characteristics of the timer (the relationship between time TA ′ from time T2B to time T2A and time TB ′ from time T2A to time T2B) are not particularly limited. For example, TA ′ / TB ′ = 2 may be used.

  In the standby state of the present invention, information in the information holding circuit is held. Naturally, the information in the information holding circuit must be held at the time of transition from the standby state to the operation state and at the time of transition from the operation state to the standby state. At the time of transition from the standby state to the operating state, there is a concern that information in the information holding circuit is destroyed due to coupling noise from the virtual power supply line VVDD. The configuration example of FIG. 23 addresses this problem, and the gate signal PSWGATE1 is driven using a high-impedance drive circuit C1 and a low-impedance drive circuit C2 so as to reduce the slew rate. Coupling noise from the virtual power line VVDD can be reduced to prevent information destruction in the information holding circuit.

  Here, the method for determining the slew rate dV / dt of the virtual power supply line VVDD at the time of transition from the standby state to the operating state is not particularly limited. For example, assuming that the coupling capacitance between the virtual power supply line VVDD and its storage node is Cp, a current of Cp * dV / dt flows out to the storage node. Slew rate dV / dt may be determined so as to satisfy Imax> Cp * dV / dt, where Imax is the upper limit of the outflow current from the storage node that does not destroy the memory even though it flows to the storage node. For Imax, for example, Ion2_n is a guide in the example of FIG. When the input of the inverter of FIG. 6 is at a high level (V1 in voltage), when a current larger than Ion2_n is applied to the output of the inverter, the current (Ion2_n) of the NMOS transistor that drives the output voltage of the inverter to a low level Larger current flows, and the inverter output cannot be held at a low level, resulting in malfunction.

  In general, at the time of transition from the standby state to the operating state, it is necessary to charge a large capacity up to the potential of the power supply VDD, such as charging the virtual power supply line VVDD and charging a high level node in the circuit block CKT. is there. There is a concern that a large inrush current flows to the power supply VDD during this charging. A large inrush current causes a voltage drop of the power supply VDD, and there is a risk that other circuits using the power supply VDD may malfunction. In the configuration example of FIG. 23, since the slew rate of the virtual power supply line VVDD is small, the large capacity is charged slowly, so that the inrush current can be reduced and malfunction can be prevented.

  In the configuration example of FIG. 25, the potential of the gate signal PSWGATE1 is detected as in the configuration example of FIG. 23, and the response line ACK is not generated using a timer, but the potential of the virtual power supply line VVDD is detected. Response line ACK is generated. SENS1 is a virtual power line potential detection circuit.

  The operation example of FIG. 25 is shown using the timing chart of FIG. When transitioning from the standby state to the operating state, the request line REQ goes high at time T1, so that the gate signal PSWGATE1 is first driven with high impedance by C1 via the C1 control circuit C1DRV. The virtual power supply line potential detection circuit SENS1 detects that the virtual power supply line VVDD is driven to a certain level Vth3 at time T1C, and drives the response line ACK to the high level. At the same time, the gate signal PSWGATE1 is driven to a low impedance by C2 via the C2 control circuit C2DRV. When transitioning from the operating state to the standby state, the request signal REQ goes low at time T2, and the gate signal PSWGATE1 is driven with high impedance by C1 via the C1 control circuit C1DRV, and via the C2 control circuit C2DRV. , C2 drives the gate signal PSWGATE1 to a low impedance.

  In FIG. 27, the virtual power line VVDD is driven by the power switch PSW1s different from the power switch PSW1 at the transition from the standby state to the operating state. The power switch PSW1s has a smaller driving force (smaller area) than the power switch PSW1. FIG. 28 is a timing chart of an operation example. When transitioning from the standby state to the operating state, the power supply switch PSW1s is first turned on via the C1 control circuit C1DRV when the request line REQ goes high at time T1. The virtual power supply line potential detection circuit SENS1 detects that the virtual power supply line VVDD is driven to a certain level Vth3 at time T1C, and drives the response line ACK to the high level. At the same time, the gate signal PSWGATE1 is driven to a low impedance by C2 via the C2 control circuit C2DRV. When transitioning from the operating state to the standby state, when the request line REQ goes low at time T2, the power switch PSW1s is turned off by the C1 control circuit C1DRV, and the gate signal PSWGATE1 is lowered by C2 through the C2 control circuit C2DRV. Driven by impedance. In this way, in the configuration example of FIG. 27, the slew rate control of the virtual power supply line VVDD is realized by driving the virtual power supply line VVDD using the small power switch PSW1s.

  FIG. 29 is a configuration example in which the method for generating the response line ACK signal in FIG. 23 and the slew rate control of the virtual power supply line VVDD in FIG. 27 are used together. SENS2 is a virtual power line potential detection circuit, and TIM2 is a timer. FIG. 30 is a timing chart of an operation example. When transitioning from the standby state to the operating state, the power supply switch PSW1s is first turned on via the C1 control circuit C1DRV when the request line REQ goes high at time T1. At time T1C, the virtual power supply line VVDD is driven to a certain level Vth3, which is detected by the virtual power supply line potential detection circuit SENS2, and the gate signal PSWGATE1 is driven to low impedance by C2 via the C2 control circuit C2DRV. The The potential detection circuit C3 detects that the gate signal PSWGATE1 has been driven to a certain level Vth1 at time T1A, and TRG2 is driven to high level by the timer TIM2.

  The timer TIM2 drives the response line ACK to a high level after a certain time (time T1B) based on the time from time T1C to time T1A. The characteristics of the timer (the relationship between time TA from time T1C to time T1A and time TB from time T1A to time T1B) are not particularly limited, but at time T1B, the gate signal PSWGATE1 is completely driven to the low level, and the virtual power supply The line VVDD may be completely charged to the potential of the power supply VDD. For example, TA / TB = 2 may be used. When transitioning from the operating state to the standby state, when the request line REQ goes low at time T2, the power switch PSW1s is turned off by the C1 control circuit C1DRV, and the gate signal PSWGATE1 is lowered by C2 through the C2 control circuit C2DRV. Driven by impedance. The potential detection circuit C3 detects that the gate signal PSWGATE1 has been driven to a certain level Vth2 at time T2A, and TRG2 is driven to a low level by the timer TIM2. The timer TIM2 drives the response line ACK to low level after a certain time (time T2B) based on the time from time T2 to time T2A. The characteristics of the timer (relationship between time TA ′ from time T2B to time T2A and time TB ′ from time T2A to time T2B) are not particularly limited. For example, TA ′ / TB ′ = 2 may be used.

The configuration example of the power switch controller PSC has been described above. It is characterized in that the potential of the power switch PSW1 and virtual power supply line VVDD is controlled so that the information in the information holding circuit can be retained at the transition from the standby state to the operation state and from the operation state to the standby state. Have.
<Second Embodiment>
Hereinafter, an example in which the power control method of the present invention is applied to a more specific circuit will be described.

  FIG. 31 is a diagram in which the present invention is applied to a static memory. CELL11 to CELLm1, CELL1n to CELLmn are static memory cells, BL1 to BLm are bit lines, / BL1 to / BLm are complementary signals to the bit lines BL1 to BLm, and WL1 to WLn are word lines. PS1 to PSn are virtual power line control circuits of the present invention, and include a power switch PSW1 and a current source PSW2. The virtual power line of the memory cells (CELL11 to CELLm1) to which the word line WL1 is connected is VL1, and the virtual power line of the memory cells (CELL1n to CELLmn) to which the word line WLn is connected is VLn.

  FIG. 32 is a timing chart of the operation example of FIG. At time T1, the virtual power supply line VL1 of the memory cell is driven to the power supply VDD by the virtual power supply line control circuit PS1. After the potential of the virtual power supply line VVDD is completely driven to the potential of the power supply VDD, the word line WL1 is driven to a high level at time T1 ′. As a result, the bit lines BL1 to BLm and / BL1 to / BLm are driven by the memory cells CELL11 to CELLm1 selected by the word line WL1, and information in the memory cells appears on the bit lines. Although not shown in FIG. 31 for simplicity, information on the bit line is amplified by a sense amplifier connected to the bit line. If the word line is driven to a high level while the potential of the virtual power supply line VVDD is not completely driven to the potential of the power supply VDD, there is a risk that the information stored in the memory cell is destroyed by the current from the bit line. There is. This is not possible with the procedure of the present invention.

  At time T2, the word line WL1 is driven to a low level, and then the power switch PSW1 is turned off at time T2 ′. Thus, according to the leakage reduction method of the present invention, the leakage current flowing through the memory cell can be reduced while the information stored in the memory cell by the current source PSW2 is retained. Note that if the potential of the virtual power supply line VVDD is not discharged after confirming that the word line is driven to the low level, there is a risk that information stored in the memory cell is destroyed by the current from the bit line. This is not possible with the procedure of the present invention. Although not shown in FIG. 31 for the sake of simplicity, a bit line equalizer is connected to each bit line pair from the bit line pair BL1 and / BL1 to the bit line pair BLm and / BLm. At time T3, the bit line is equalized to the potential of the power supply VDD by this bit line equalizer.

  If the gate tunnel leak of the memory cell is so large that it cannot be ignored, the bit line may be driven to a potential lower than the power supply VDD during standby (when the word line is at low level). Thereby, the gate-source voltage of the transfer transistor of the memory cell can be reduced during standby, and the gate tunnel leakage current flowing through the transfer transistor can be reduced. Of course, in that case, before the word line is driven to the high level at time T1, it is necessary to drive the bit line potential to the potential of the power supply VDD as shown in FIG. 32 (referred to as a bit line reset operation). Of course, this is not necessary if the bit line is VSS precharged. FIG. 33 shows an example in which the reset operation of the bit line is not necessary even if the bit line is VDD precharged.

  In the configuration example of FIG. 33, the power switch is configured by using an NMOS transistor instead of configuring the power switch by a PMOS transistor in FIG. PS1 to PSn are virtual power line control circuits of the present invention, and include a power switch PSW1n and a current source PSW2n configured using NMOS transistors. The virtual ground line of the memory cells (CELL11 to CELLm1) to which the word line WL1 is connected is SL1, and the virtual ground line of the memory cells (CELL1n to CELLmn) to which the word line WLn is connected is SLn.

  FIG. 34 is a timing chart of the operation example of FIG. At the time T1, the word line WL1 is driven to a high level, and at the same time, the virtual power supply line SL1 of the memory cell to which the word line is connected is driven to the power supply VSS by the virtual power supply line control circuit PS1. As a result, the bit lines BL1 to BLm and / BL1 to / BLm are driven by the memory cells CELL11 to CELLm1 selected by the word line WL1, and the information in the memory cells appears on the bit lines. Although not shown in FIG. 33 for simplicity, the information on the bit line is amplified by a sense amplifier connected to the bit line. In FIG. 31, the word line is driven to the high level after the potential of the virtual power supply line VVDD is completely driven to the potential of the power supply VDD. However, in the configuration example of FIG. 34, the driving of the virtual ground line VVSS and the driving of the word line WL may be performed simultaneously. This is because there is no risk that the information stored in the memory cell is destroyed by the current from the bit line. Rather, since the drive of the virtual ground line VVSS allows the word line to be driven to a high level before the potential of the virtual ground line VVSS is completely driven to the ground potential, both drive operations can overlap, and the memory cell is read. The speed can be increased.

  At time T2, when the word line WL1 is driven to a low level, the power switch PSW1n is turned off. Thus, according to the method of the present invention, the leakage current flowing through the memory cell can be reduced while the information stored in the memory cell by the current source PSW2 is retained. Although not shown in FIG. 33 for simplicity, a bit line equalizer is connected to each bit line pair from the bit line pair BL1 and / BL1 to the bit line pair BLm and / BLm. At time T2, the word line WL1 is driven to the low level, and at the same time, the bit line is driven to the potential of the power supply VDD by the bit line equalizer.

  In the configuration example of FIG. 34, the word line potential before time T1 and after time T2 is the potential of ground VSS, but it is driven to a potential of VSS or more and VFNL or less so that no GIDL or gate tunnel leakage current flows. May be. The low level of WL1 may be the potential of the virtual ground line SL1, and similarly the low level of WL2 may be the potential of the virtual ground line SL2. This can be realized, for example, by grounding the word line driver from the virtual ground line.

  31 and 33, the power supply voltage applied to the memory cell may be higher than the power supply voltage applied to the sense amplifier. Even in this case, the precharge level of the bit line may be the same voltage as the power supply voltage applied to the sense amplifier. In this case, it is desirable that the gate insulating film thickness of the MOS transistor constituting the memory cell is thicker than the gate insulating film thickness of the MOS transistor constituting the sense amplifier. Of course, the precharge level of the bit line may be the same as the power supply voltage applied to the memory cell. In that case, since the sense amplifier inputs and amplifies a voltage higher than its own power supply voltage, the gate insulating film thickness of the MOS transistor constituting the sense amplifier is that of the MOS transistor constituting the memory cell. When it is thinner than the gate insulating film thickness, the sense amplifier needs a withstand voltage relaxation MOS transistor or the like.

  Of course, various specific examples and modifications disclosed in the first embodiment can be applied to the power switches PS1 to PSn in the second embodiment.

<Third Embodiment>
FIG. 35 shows a configuration example of a chip CHP1 to which the present invention is applied. Many of the grounding power supply and signal wiring are omitted for simplicity. The circuit block CKT1 is a circuit block that is directly supplied with power from the power supply VDD without going through the leakage reduction circuit of the present invention. The circuit blocks CKT2a and CKT2b are supplied with power from the power supply VDD through the leakage reduction circuits PSM2a and PSM2b of the present invention. The circuit block CKT3 is a circuit block in which power is directly supplied from a power supply VCC different from the power supply VDD without going through the leakage reduction circuit of the present invention. MP20, MP21a, MP22b, and MP23 are PMOS transistors, and MN20, MN21a, MN22b, and MN23 are NMOS transistors. CTLa and CTLb are leak control lines of the leak reduction circuit of the present invention corresponding to the request line REQ and response line ACK of FIG. In FIG. 35, the circuit block CKT1 is a circuit that needs to be powered on at all times. For example, a circuit that controls the leak reduction circuits PSM2a and PSM2b, a real-time clock (RTC), an interrupt processing circuit, a DRAM refresh circuit, a memory, and the like. The circuit block CKT3 is an I / O circuit. The power supply VCC is a power supply for interfacing with the outside of the chip, and the power supply VCC has a higher potential than the power supply VDD. For example, the potential of VDD is 1.8V, and the potential of VCC is 3.3V or 2.5V. The gate insulating film thickness of the MOS transistors MP23 and MN23 constituting the input buffer or the output buffer is thicker than the gate insulating film thickness of the other MOS transistors.

  As shown in FIG. 35, by providing a plurality of leak control circuits and dividing the circuits integrated on the chip into a plurality of parts to control the leak current, the leak current of the entire chip can be efficiently reduced.

  The configuration example of FIG. 36 is an embodiment in which the power source of the circuit block CKT1 and the power sources of the circuit blocks CKT2a and CKT2b are supplied from different power source terminals in the configuration example of FIG. As described above, the circuit block CKT1 is a circuit that needs to be in an operable state with the power on at all times. Even if the leak reduction circuit of the present invention is applied to such a circuit, the effect is small. However, the circuit configured as the circuit block CKT1 is a circuit as listed in the description of FIG. 35, and the operation frequency required for them is the operation required for the circuits mounted on the circuit blocks CKT2a and CKT2b. In many cases, it may be lower than the frequency. Therefore, when the same MOS transistor is used for the circuit block CKT1 and the circuit blocks CKT2a and CKT2b, the power consumption due to the leakage current with respect to the power consumption due to the operation current of the circuit block CKT1 becomes significant compared to the circuit block CKT2. In order to prevent this, it is desirable to increase the threshold voltage of the MOS transistors constituting the circuit block CKT1. In this case, the gate insulating film thickness may be the same in the circuit blocks CKT1 and CKT2, and the channel impurity concentration may be changed or the substrate bias value may be changed. Alternatively, the gate insulating film thickness of the MOS transistor of the circuit block CKT2 may be made larger than the gate insulating film thickness of the MOS transistor of the circuit block CKT1. In this case, it is desirable that the voltage of the power supply VDD2 applied to the circuit block CKT1 is higher than the voltage of the power supply VDD. Thereby, the leakage current of the whole chip can be efficiently reduced. The gate insulating film thickness of the MOS transistor is increased in the order of the MOS transistor constituting the circuit block CKT2a or CKT2b, the MOS transistor constituting the circuit block CK1, and the MOS transistor constituting the circuit block CKT3. May be. The MOS transistor constituting the circuit block CK1 may have the same gate insulating film thickness as the MOS transistor constituting the circuit block CKT3.

  FIG. 37 shows an embodiment in which the power supply VDD is stepped down from the power supply VDD2 when the voltage of the power supply VDD2 is made higher than the voltage of the power supply VDD power supply in FIG. VDC is a step-down circuit. The structure of the step-down circuit is not particularly limited, but may be a series regulator system or a switching regulator system. The type of power supplied to the chip can be reduced.

  In the configuration example of FIG. 37, the components of the step-down circuit VDC and the leakage control circuit PSM2a or PSM2b can be merged. FIG. 38 shows an example of the configuration. PSW1 is a power switch, PSW2 is a current source, OPAMP is an operational amplifier, and VREF is a reference power supply. During operation, the potential VDD can be supplied to the virtual power supply line VVDD2a by applying the VDD potential to VREF. On the other hand, when the power switch PSW1 is turned off, a sufficiently low voltage (for example, 0 V or less) may be applied to VREF. PSW1s is a power switch having a smaller driving force than the power switch PSW1. Although used for noise reduction at the transition from the standby state to the operation state, the operation method is the same as the operation method described in relation to FIG. Here, the threshold voltage of the power switch PSW1 and the gate insulating film thickness are not particularly limited, but an optimum one may be used according to the potential of the power supply VDD2.

  The step-down circuit may monitor the potential of the virtual power supply line VVDD2a or VVDD2b and control so that the desired voltage VDD is applied to the virtual power supply line even when the current consumption of the circuit blocks CKT2a and CKT2b increases. When the path from the power supply terminal of the chip to the circuit in the circuit block has a high impedance, a so-called IR drop occurs due to the consumption current of the circuit blocks CKT2a and CKT2b. By the above method, IR drop can be prevented. In addition, the voltage of the virtual power supply line VVDD2a or VVDD2b during operation changes based on chip manufacturing variation information and environmental variation information, and the characteristics of the circuit blocks CKT2a and CKT2b change due to the above variations and variations. You may make it compensate.

  The configuration example of FIG. 38 can also be used for a method of directly applying the VFNL potential to the virtual power supply line VVDD during standby, like the configuration example of FIG. In this case, PSW2 in FIG. 38 is not necessary. In this case, there are two types of control methods. In the first method, during operation, the VDD potential is applied to VREF as described above, and the potential VDD is supplied to the virtual power supply line VVDD2a. During standby, a VFNL (<VDD) potential is applied to VREF, and the potential VFNL is supplied to the virtual power supply line VVDD2a. In the configuration example of FIG. 17, the voltage source VFNLGEN is necessary, but there is an advantage that it can be replaced by the operational amplifier OPAMP and the power switch PSW1. In the second method, in addition to the operational amplifier OPAMP and the power switch PSW1, a voltage source VFNLGEN is installed on the virtual power line VVDD2a as in the configuration example of FIG. During operation, the VDD potential is applied to VREF as described above, and the potential VDD is supplied to the virtual power supply line VVDD2a. During standby, 0 V is applied to VREF, and the potential VFNL is supplied from the voltage source VFNLGEN to the virtual power supply line VVDD2a.

  Either method has an advantage that the potential of the virtual power supply line VVDD2a during standby can be designed to a voltage close to VRTN by directly applying VFNL to the virtual power supply line VVDD2a during standby. Further, the value of VFNL to be directly applied can be automatically controlled according to the voltage of the power supply VDD, temperature, process conditions, and the like.

  In the configuration examples of FIGS. 35 to 38, the example in which the power switch uses a PMOS transistor is shown. However, as described above, the NMOS transistor PSW1n may be used as the power switch. FIG. 39 shows an embodiment in which leak control circuits PSM2a2 and PSM2b2 using NMOS transistors are used as power switches in the embodiment of FIG. In general, NMOS transistors have a smaller on-resistance per gate width than PMOS transistors. In the configuration example of FIG. 39, it is easier to suppress the speed reduction of the circuit block during operation than in the configuration example of FIG.

  Of course, various specific examples and modifications disclosed in the first embodiment can be applied to the leakage reduction circuit in the third embodiment.

  In FIG. 35 to FIG. 39, the signal transmission / reception mode between circuit blocks is omitted. However, when the leakage reduction method of the present invention is used, the voltage supplied to the circuits in the circuit block is reduced during standby. . Therefore, the amplitude of the signal output from the circuit becomes small. In order to propagate the signal having the reduced amplitude to another circuit block without generating an abnormal current, it is necessary to provide a level conversion circuit between the circuit blocks. FIG. 40 shows a configuration example of the level conversion circuit. MP30, MP31, MP32, and MP33 are PMOS transistors, and MN30 and MN31 are NMOS transistors. The threshold voltage and gate insulating film thickness of each transistor are not particularly limited.

  When the circuit block CKT2a enters the standby state by the leak reduction method of the present invention, the signal amplitude of d1s and its complementary signal / d1s is smaller than the signal amplitude VDD in the operating state. However, in the embodiment of FIG. 40, the voltage is amplified to the voltage amplitude of the power supply VDD by the latch type level conversion circuit LVL1 and output as d1e. Even if the power supply voltage applied to the CMOS circuit for inputting d1e is VDD, signals can be exchanged without generating an abnormal current.

  In general, the toggle frequency of the latch type level converter circuit LVL1 greatly depends on the input signal amplitude. However, in the present invention, when the input amplitude of the latch type level conversion circuit LVL1 becomes small, the circuit (circuit block CKT2a) that outputs it is in a standby state, and the logic level of the input signal does not toggle. Accordingly, it is sufficient for the latch type level conversion circuit LVL1 to maintain the logic level and continue to amplify only the signal amplitude, and thus the above-described reduction in the toggle frequency is not a problem.

  When the deep standby state described in FIGS. 18 and 19 is performed on the circuit block CKT2a, and d1s and / d1s are in a floating state in the deep standby state, an abnormal current is generated in the latch type level conversion circuit LVL1. There is a possibility of flowing. In order to prevent this, for example, the method disclosed in JP-A-11-195975 can be used. FIG. 40 shows an embodiment of a latch-type level conversion circuit effective when a PMOS transistor is used as a power switch as shown in FIG. 1, but when an NMOS transistor is used as a power switch as shown in FIG. A level conversion circuit of a complementary type to the latch type level conversion circuit of FIG. 40 can be applied.

  The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the embodiments, and various modifications can be made without departing from the scope of the invention. Not too long. For example, the specific structure and layout structure of the circuit can take various embodiments.

CKT, CKT1, CKT2a, CKT2b, CKT3 circuit block
PSW1, PSW1n Power switch
PSW2, PSW2n Current source
VVDD, VL1, VLn, VVDD2a, VVDD2b Virtual power supply line
VVSS, SL1, SLn, VVSS2a, VVSS2b Virtual ground wire
PSC power switch controller
INV inverter
NAND NAND circuit
NOR NOR circuit
FF flip-flop
LG1 logic circuit
MARY memory cell array
DEC word decoder
SA sense amplifier
MEM1 memory circuit
a0, a1, a2, an address signal
d0, d1, d2, dn data signals
IN input signal
OUT output signal
VBC substrate bias control circuit
MP1, MP10, MP20, MP21a, MP22b, MP23, MP30, MP31, MP32, MP33 PMOS transistors
MN1, MN10, MN20, MN21a, MN22b, MN23, MN30, MN31 NMOS transistors
PSWGATE1, PSWGATE1a, PSWGATE2, PSWGATEn Power switch PSW1 gate signal
PSWGATE1n Gate signal for power switch PSW1n
R1 resistance
IS10 constant current source
IS1 constant current circuit
VFNLGEN voltage source
REQ request line
ACK response line
PMG power control circuit (power manager)
TIM1, TIM2 timer
SENS1, SENS2 Virtual power line potential detection circuit
WL1, WLn Word line
BL1, BLm, / BL1, / BLm bit lines
CELL11, CELLm1, CELL1n, CELLmn memory cells
PSM2a, PSM2b, PSM2a2, PSM2b2 Leakage reduction circuit
CTLa, CTLb Leak control line
VDC step-down circuit
OPAMP operational amplifier
LVL1 Latch type level conversion circuit

Claims (14)

A first power line having a first potential;
A second power supply line having a second potential lower than the first potential;
A third power supply line having a third potential lower than the second potential;
A first transistor connected between the second power line and the third power line;
A circuit block connected between the first power supply line and the second power supply line;
A drive control unit having a first drive circuit and a second drive circuit,
The drive control unit controls a gate of the first transistor;
The first transistor is turned off in a standby state and turned on in an operating state;
When transitioning from the standby state to the operation state, the drive control unit changes the gate voltage of the first transistor at a first rate, and then a second rate that is faster than the first rate. To change
The drive capability of the first drive circuit is lower than the drive capability of the second drive circuit,
The output of the first drive circuit and the output of the second drive circuit are connected in common to the gate of the first transistor,
The semiconductor device, wherein the first transistor is an NMOS transistor. The semiconductor device according to claim 1,
In the case of transition from the standby state to the operation state, the second driving circuit changes the gate voltage of the first transistor to a predetermined voltage level after the first driving circuit changes the gate voltage of the first transistor. A semiconductor device for driving The semiconductor device according to claim 1,
Request line,
An electric potential detector;
The first driving circuit drives the gate of the first transistor when the request line is first enabled;
The semiconductor device, wherein the second drive circuit drives the gate of the first transistor when the potential detection unit detects that the gate voltage of the first transistor has reached a predetermined voltage level. The semiconductor device according to claim 3.
A timer,
A response line;
The response line is enabled when the timer detects that a predetermined time has elapsed since the detection of the gate voltage of the first transistor at a predetermined voltage level by the potential detector. . The semiconductor device according to claim 1,
A voltage detection unit;
The semiconductor device, wherein the second drive circuit drives the gate of the first transistor when the voltage detection unit detects that the potential of the second power supply line has become a predetermined potential. The semiconductor device according to claim 5.
A response line;
The semiconductor device, wherein the response line is set to a high level when the voltage detection unit detects that the potential of the second power supply line has become a predetermined potential. The semiconductor device according to claim 1,
A current source;
The current source is connected between the second power line and the third power line,
The circuit block includes a semiconductor device including an information holding circuit having a volatile information holding function. The semiconductor device according to claim 7.
The information holding circuit is a semiconductor device which is a flip-flop circuit or a memory cell array. A first power line having a first potential;
A second power supply line having a second potential lower than the first potential;
A third power supply line having a third potential lower than the second potential;
A first transistor connected between the second power line and the third power line;
A circuit block connected between the first power supply line and the second power supply line;
A drive control unit having a first drive circuit and a second drive circuit,
The drive control unit controls a gate of the first transistor;
The first transistor is turned off in a standby state and turned on in an operating state;
When transitioning from the operating state to the standby state, the drive control unit changes the gate voltage of the first transistor at a first rate, and then a second rate that is faster than the first rate. To change
The drive capability of the first drive circuit is lower than the drive capability of the second drive circuit,
The output of the first drive circuit and the output of the second drive circuit are connected in common to the gate of the first transistor,
The semiconductor device, wherein the first transistor is an NMOS transistor. The semiconductor device according to claim 9.
When transitioning from the operating state to the standby state, the second driving circuit changes the gate voltage of the first transistor to a predetermined voltage level, and then the second driving circuit changes the gate voltage of the first transistor. A semiconductor device for driving The semiconductor device according to claim 9.
Request line,
An electric potential detector;
The first driving circuit drives the gate of the first transistor when the request line is disabled;
The semiconductor device, wherein the second drive circuit drives the gate of the first transistor when the potential detection unit detects that the gate voltage of the first transistor has reached a predetermined voltage level. The semiconductor device according to claim 11.
A timer,
A response line;
The response line is disabled when the timer detects that a predetermined time has elapsed after the potential detection unit detects that the gate voltage of the first transistor has reached a predetermined voltage level. apparatus. The semiconductor device according to claim 9.
A current source;
The current source is connected between the second power line and the third power line,
The circuit block includes a semiconductor device including an information holding circuit having a volatile information holding function. The semiconductor device according to claim 13.
The information holding circuit is a semiconductor device which is a flip-flop circuit or a memory cell array.

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