JP5096125B2 - Switching regulator control circuit - Google Patents

Description

  The present invention relates to a step-down switching regulator.

  Step-down switching regulators are mounted on electronic devices such as televisions and personal computers. The switching regulator steps down the input power supply voltage and supplies it to other circuit blocks mounted on the electronic device.

JP 2000-354365 A

  The step-down switching regulator includes a switching transistor, a rectifying element, an inductor and an output capacitor, and a control circuit that controls on / off of the switching transistor. It is convenient if the circuit operation can be changed by using one control circuit and changing the topology of circuit elements such as an external switching transistor and a rectifying element.

  The present invention has been made in such a situation, and an object thereof is to provide a highly versatile control circuit capable of switching between a single channel output and a plurality of channel outputs.

An embodiment of the present invention relates to a control circuit of a switching regulator. The control circuit includes a first input terminal for feeding back a first feedback voltage corresponding to the output voltage of the first channel, and a second input terminal for feeding back a second feedback voltage corresponding to the output voltage of the second channel. A first error amplifier that amplifies the error between the first feedback voltage and the predetermined first reference voltage, a second error amplifier that amplifies the error between the second feedback voltage and the predetermined reference voltage, and outputs from the first error amplifier a first pulse modulation comparator for comparing the first error voltage to a predetermined periodic voltage to be, and the second pulse modulation comparator for comparing the second error voltage periodic voltage outputted from the second error amplifier, a first pulse A first driver that amplifies the first pulse signal from the modulation comparator; and a second driver that amplifies the second pulse signal from the second pulse modulation comparator. The control circuit is set to the first mode when a two-channel diode rectification step-down switching regulator is controlled, and is set to the second mode when a single-channel synchronous rectification step-down switching regulator is controlled. Is set. In the first mode, the output signals of the first and second drivers are supplied to the high side transistors of the diode rectification step-down switching regulators of the first and second channels, and in the second mode, the output of the first driver. The signal is supplied to a high-side transistor of a single channel synchronous rectification step-down switching regulator, and the output signal of the second driver is set to a value corresponding to the first feedback voltage, To the low-side transistor of the synchronous rectification step-down switching regulator.

  According to this aspect, the single channel and multi-channel outputs can be switched and driven by a single control circuit.

The second pulse modulation comparator compares the second error voltage output from the second error amplifier with a predetermined periodic voltage in the first mode, and the first error voltage output from the first error amplifier in the second mode. A voltage corresponding to the above may be compared with a predetermined periodic voltage.
According to this configuration, the duty ratio of the output signal of the second driver can be set to a value corresponding to the first feedback voltage.

In the second mode, the second pulse modulation comparator may compare a voltage obtained by level shifting the first error voltage with a periodic voltage.
By generating a voltage corresponding to the first error voltage by shifting the level of the first error voltage, a dead time can be set for the high-side transistor and the low-side transistor.

The control circuit according to an aspect may further include a switch and a resistor provided in series between the output terminal of the first error amplifier and the output terminal of the second error amplifier. The switch may be turned off in the first mode and turned on in the second mode.
In this case, when the switch is turned on, a current flows through the resistor, causing a voltage drop. Therefore, the first error voltage output from the first error amplifier can be level-shifted by this voltage drop, and the length of the dead time can be adjusted according to the resistance value.

  The second driver amplifies the second pulse signal from the second pulse modulation comparator in the first mode, and outputs a signal having a duty ratio corresponding to the first pulse signal from the first pulse modulation comparator in the second mode. It may be amplified.

A control circuit according to an aspect includes a third input terminal for feeding back a third feedback voltage according to the output voltage of the third channel, and a third error for amplifying an error between the third feedback voltage and a predetermined third reference voltage. an amplifier, a third pulse modulation comparator which compares the third error voltage periodic voltage outputted from the third error amplifier, and a third driver for amplifying a third pulse signal from the third pulse modulation comparator, a further You may prepare. The control circuit may be set to the third mode when the step-down switching regulator of 3 channels of the diode rectification system controlled. In the third mode, the output signals of the first to third drivers may be supplied to the high-side transistors of the diode rectification step-down switching regulators of the first to third channels.

  The control circuit may control a synchronous rectification step-down switching regulator including two high-side transistors connected in parallel, and may be set to the fourth mode when the two high-side transistors are complementarily turned on. . In the fourth mode, the first pulse signal is divided and distributed to the first and third drivers, the output signals of the first and third drivers are supplied to the two high-side transistors, and the output signal of the second driver is The duty ratio may be set to a value corresponding to the first feedback voltage and supplied to the low-side transistor of the single channel synchronous rectification step-down switching regulator.

  The control circuit may control a synchronous rectification step-down switching regulator including two high-side transistors connected in parallel, and may be set to the fifth mode when the two high-side transistors are simultaneously turned on. In the fifth mode, the first pulse signal is distributed to the first and third drivers, the output signals of the first and third drivers are supplied to the two high-side transistors, and the output signal of the second driver has its duty ratio May be set to a value corresponding to the first feedback voltage and supplied to the low-side transistor of the single-channel synchronous rectification step-down switching regulator.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, etc. are also effective as an aspect of the present invention.

  According to the present invention, it is possible to switch between single channel output and multiple channel output.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

  In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are physically directly connected, or the member A and the member B are in an electrically connected state. Including the case of being indirectly connected through other members that do not affect the above. Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical condition. It includes the case of being indirectly connected through another member that does not affect the connection state.

(First embodiment)
FIG. 1 is a circuit diagram showing a configuration of a control circuit 100 of a step-down switching regulator according to the first embodiment. The control circuit 100 is a functional IC integrated on a single semiconductor substrate, and includes a first input terminal Pi1, a second input terminal Pi2, a first output terminal Po1, and a second output terminal Po2.
The control circuit 100 controls a first mode for controlling a two-channel diode rectification step-down switching regulator and a second mode for controlling a single-channel synchronous rectification step-down switching regulator according to the arrangement of peripheral circuit elements. and mode, switching can be configured.

  The first input terminal Pi1 is provided to feed back a first feedback voltage Vfb1 corresponding to the output voltage Vout1 of the first channel, and the second input terminal Pi2 is a second feedback corresponding to the output voltage Vout2 of the second channel. Provided to feed back voltage Vfb2. When used as a single-channel control circuit, the output voltage Vout is fed back only to the first input terminal Pi1. From the first output terminal Po1 and the second output terminal Po2, a control signal for controlling on / off of a switching transistor connected to the outside is output.

  The first error amplifier EA1 amplifies an error between the first feedback voltage Vfb1 and a predetermined reference voltage Vref, and generates a first error voltage Verr1. Similarly, the second error amplifier EA2 amplifies an error between the second feedback voltage Vfb2 and a predetermined reference voltage Vref, and generates a second error voltage Verr2.

  The oscillator 10 generates a periodic voltage Vosc of a triangular wave (or sawtooth wave) having a predetermined frequency.

  A first pulse modulation comparator (hereinafter referred to as a first comparator) CMP1 compares the first error voltage Verr1 output from the first error amplifier EA1 with the periodic voltage Vosc. The first comparator CMP1 outputs a first pulse signal Spwm1 whose level transitions at each intersection of two voltages. The first pulse signal Spwm1 is pulse width modulated, and its duty ratio is adjusted by feedback so that the first feedback voltage Vfb1 matches the reference voltage Vref.

  Similarly, a second pulse modulation comparator (hereinafter referred to as a second comparator) CMP2 compares the second error voltage Verr2 output from the second error amplifier EA2 with the periodic voltage Vosc, and generates a second pulse signal Spwm2.

  The first driver DRV1 amplifies the first pulse signal Spwm1 from the first comparator CMP1. The second driver DRV2 amplifies the second pulse signal Spwm2 from the second comparator CMP2.

The control circuit 100 is set to the first mode when a 2-channel diode rectification step-down switching regulator is to be controlled, and is set to the second mode when a single-channel synchronous rectification step-down switching regulator is to be controlled. Set to The first mode and the second mode are switched according to a signal given to a control terminal (not shown).

  2A and 2B are circuit diagrams showing configurations of switching regulators 200a and 200b including the control circuit 100 of FIG. 2A shows the configuration of a two-channel diode rectification switching regulator 200a, and FIG. 2B shows the configuration of a single-channel synchronous rectification switching regulator 200b.

  The configuration of FIG. 2A will be described. The first channel CH1 includes a first high-side transistor MH1, a first rectifying diode D1, a first inductor L1, and a first output capacitor C1, and the second channel CH2 includes a second high-side transistor MH2, It includes a two-rectifying diode D2, a second inductor L2, and a second output capacitor C2. The circuit topology of each channel is a general synchronous rectification switching regulator.

  The control circuit 100 is set to the first mode in the case of FIG. A voltage obtained by dividing the output voltage Vout1 of the first channel CH1 by the resistors R11 and R12 is fed back to the first input terminal Pi1 as the first feedback voltage Vfb1. A voltage obtained by dividing the output voltage Vout2 of the second channel CH2 by the resistors R21 and R22 is fed back to the second input terminal Pi2 as the second feedback voltage Vfb2.

  In the first mode, the output signals Sd1 and Sd2 of the first driver DRV1 and the second driver DRV2 are output from the first output terminal Po1 and the second output terminal Po2, and the switching regulators of the first channel CH1 and the second channel CH2 respectively. The high-side transistors MH1 and MH2 are supplied to control terminals (gates).

  In the first mode, individual feedback functions in each of the first channel and the second channel, and the two output voltages Vout1 and Vout2 are stabilized at the respective target values.

  The configuration of FIG. 2B will be described. The switching regulator 200b is a single channel synchronous rectification switching regulator and includes a first high-side transistor MH1, a first low-side transistor ML1, a first inductor L1, and a first output capacitor C1. The circuit topology is common.

  A voltage obtained by dividing the output voltage Vout by the resistors R11 and R12 is input to the first input terminal Pi1 of the control circuit 100 as the feedback voltage Vfb.

In the second mode, the output signal Sd1 of the first driver DRV1 is supplied to the first high-side transistor MH1 of the switching regulator 200b.
In the second mode, the feedback loop using the first error amplifier EA1 is invalidated. The output signal Sd2 of the second driver DRV2 is set to a value corresponding to the first feedback voltage Vfb1 and supplied to the first low-side transistor ML1 of the switching regulator 200b.

  Returning to FIG. In the second mode, the control circuit 100 sets the duty ratio of the first pulse signal Spwm1 and the second pulse signal Spwm2 based on the feedback voltage Vfb input to the first input terminal Pi1. As a result, the first high-side transistor MH1 and the second high-side transistor MH2 in FIG. 2B are alternately turned on and off alternately, and the output voltage Vout is stabilized to a target value corresponding to the reference voltage Vref1. Let

  The above is the overall configuration and function of the control circuit 100.

  The function of the second comparator CMP2 is switched between the first mode and the second mode. In the first mode, the second comparator CMP2 compares the second error voltage Verr2 output from the second error amplifier EA2 with the periodic voltage Vosc.

  On the other hand, in the second mode, the voltage Verr1 'corresponding to the first error voltage Verr1 output from the first error amplifier EA1 is compared with the periodic voltage Vosc. Specifically, a voltage (Verr1 + ΔV) obtained by level shifting the first error voltage Verr1 is compared with the periodic voltage Vosc. In order to realize this function, the control circuit 100 includes a level shifter 12 provided between the output terminal of the first error amplifier EA1 and the output terminal of the second error amplifier EA2.

  The level shifter 12 receives a mode control signal MODE1 for switching modes. The level shifter 12 is disabled in the first mode. In this state, error voltages Verr1 and Verr2 generated by the error amplifiers EA1 and EA2 are output to the subsequent comparators CMP1 and CMP2, respectively.

  The level shifter 12 is activated in the second mode. In this state, the level shifter 12 generates a voltage Verr1 + ΔV obtained by level shifting the first error voltage Verr1 and outputs the voltage Verr1 + ΔV to the second comparator CMP2.

  For example, the level shifter 12 includes a first resistor R1, a second resistor R2, and a switch (transfer gate) SW provided in series between the output terminal of the first error amplifier EA1 and the output terminal of the second error amplifier EA2.

  A mode control signal MODE1 is input to the switch SW, and is turned off in the first mode and turned on in the second mode. When the switch SW is turned on in the second mode, a current flows through the resistors R1 and R2, and a voltage drop ΔV is generated. Therefore, the first error voltage Verr1 output from the first error amplifier EA1 can be level-shifted by this voltage drop ΔV.

  FIG. 3 is a time chart showing an operation state in the second mode of the control circuit 100 of FIG. The first pulse signal Spwm1 is at a high level when Vosc> Verr1, and is at a low level when Vosc <Verr1. The second pulse signal Spwm2 is at a high level when Vosc> Verr2, and is at a low level when Vosc <Verr2. In the switching regulator 200b of FIG. 2B, the first high-side transistor MH1 is turned on when the first pulse signal Spwm1 is at a low level, and the first low-side transistor ML1 is turned on when the second pulse signal Spwm2 is at a high level.

  Since the error voltage Verr 'is a voltage obtained by level shifting the first error voltage Verr1, the high-level period of the second pulse signal Spwm2 is shorter than that of the first pulse signal Spwm1. Therefore, the dead time DT according to the level shift amount ΔV by the level shifter 12 can be set. In the configuration of FIG. 1, the length of the dead time DT can be adjusted according to the values of the resistors R1 and R2.

  The above is the configuration and operation of the control circuit 100. According to the control circuit 100, a single channel output and a plurality of channel outputs can be switched, and the versatility of the control circuit 100 can be improved.

(Second Embodiment)
FIG. 4 is a circuit diagram showing a configuration of the control circuit 100a of the step-down switching regulator according to the second embodiment. The control circuit 100a includes a third input terminal Pi3 and a third output terminal Po3 in addition to the control circuit 100 of FIG. In the following, the difference from FIG. 1 will be mainly described.

  The control circuit 100a controls a third mode for controlling a three-channel diode rectification step-down switching regulator and a fourth mode for controlling a single-channel synchronous rectification step-down switching regulator according to the arrangement of peripheral circuit elements. The fifth mode can be switched.

  The third input terminal Pi3 is provided to feed back the third feedback voltage Vfb3 corresponding to the output voltage Vout3 of the third channel. When used as a single-channel control circuit, the output voltage Vout is fed back only to the first input terminal Pi1. From the first output terminal Po1 to the third output terminal Po3, a control signal for controlling on / off of a switching transistor connected to the outside is output.

  The third error amplifier EA3 amplifies an error between the third feedback voltage Vfb3 and a predetermined reference voltage Vref to generate a third error voltage Verr3.

  The third comparator CMP3 compares the third error voltage Verr3 output from the third error amplifier EA3 with the periodic voltage Vosc. The third comparator CMP3 outputs a third pulse signal Spwm3 whose level transitions at each intersection of two voltages.

  The third driver DRV3 amplifies the third pulse signal Spwm3 from the third comparator CMP3.

The control circuit 100a is set to the third mode when a two-channel diode rectification step-down switching regulator is to be controlled, and is set to the fourth mode when a single-channel synchronous rectification step-down switching regulator is to be controlled. The fifth mode is set. The third to fifth modes are switched according to a signal given to a control terminal (not shown).

  FIGS. 5A and 5B are circuit diagrams showing configurations of switching regulators 200c and 200d including the control circuit 100a of FIG. 5A shows a configuration of a three-channel diode rectification switching regulator 200c, and FIG. 5B shows a configuration of a single-channel synchronous rectification switching regulator 200d.

  The configuration of FIG. 5A will be described. The third channel CH3 includes a third high-side transistor MH3, a third rectifying diode D3, a third inductor L3, and a third output capacitor C3.

  The control circuit 100a is set to the third mode in the case of FIG. A voltage obtained by dividing the output voltage Vout3 of the third channel CH3 by the resistors R31 and R32 is fed back to the third input terminal Pi3 as the third feedback voltage Vfb3.

  In the third mode, the output signals Sd1 to Sd3 of the first driver DRV1 to the third driver DRV3 are supplied to the gates of the high side transistors MH1 to MH3 of the switching regulators of the first to third channels CH1 to CH3, respectively.

  In the third mode, individual feedback functions in each of the first channel CH1 to the third channel CH3, and the three output voltages Vout1 to Vout3 are stabilized to their target values.

  The configuration of FIG. 5B will be described. The switching regulator 200d is a single-channel synchronous rectification switching regulator, and includes two high-side transistors MH1 and MH2 connected in parallel.

  A voltage obtained by dividing the output voltage Vout by the resistors R11 and R12 is input as the feedback voltage Vfb to the first input terminal Pi1 of the control circuit 100a. The second input terminal Pi2 and the third input terminal Pi3 are grounded.

  When the switching regulator of FIG. 5B is to be controlled, the control circuit 100a is set to either the fourth mode or the fifth mode.

The fourth mode is a mode (alternative mode) in which the two high-side transistors MH1 and MH2 are complementarily turned on.
In the fourth mode, the feedback loop using the first error amplifier EA1 and the feedback loop using the third error amplifier EA3 are invalidated. The output signal Sd2 of the second driver DRV2 has its duty ratio set to a value corresponding to the first feedback voltage Vfb1, and is supplied to the gate of the first low-side transistor ML1 of the switching regulator 200d. This operation is the same as in the second mode of the control circuit 100 of FIG.

  In the fourth mode, the first pulse signal Spwm1 is divided and distributed to the first driver DRV1 and the third driver DRV3. Output signals Sd1 and Sd3 of the first driver DRV1 and the third driver DRV3 are supplied to the gates of the two high-side transistors MH1 and MH2.

  Returning to FIG. A frequency divider 14 is provided after the first comparator CMP1. The frequency divider 14 divides the high-side pulse signal Spwm1. The divided pulse signals Spwm1a and Spwm1b are input to the selectors SEL1 and SEL3.

  The selector SEL1 selects either the divided pulse signal Spwm1a or the pulse signal Spwm1 before frequency division, and outputs it to the first driver DRV1. The selector SEL3 selects one of the divided pulse signal Spwm1b and the pulse signal Spwm3, and outputs it to the third driver DRV3.

  The selectors SEL1 and SEL3 are switched according to the mode control signal MODE2. In the third mode, the selector SEL1 selects the first pulse signal Spwm1, and the selector SEL3 selects the third pulse signal Spwm3. In the fourth mode, the selector SEL1 selects the pulse signal Spwm1a, and the selector SEL3 selects the pulse signal Spwm3b.

  FIG. 6 is a circuit diagram illustrating a configuration example of the frequency divider 14. The inverter 30 inverts the high-side pulse signal Spwm1. The D flip-flop 32 receives the pulse signal # Spwm1 inverted by the inverter 30 at the clock terminal (# indicates logic inversion). The inverting terminal #Q of the D flip-flop 32 is connected to the input terminal D. The D flip-flop 32 divides the high-side pulse signal Spwm1 by ½.

  The NOR gate 36 outputs a negative logical sum of the output of the inverter 30 and the output of the D flip-flop 32 as a pulse signal Spwm1a. Inverter 34 inverts the output of inverter 30. The AND gate 38 outputs a logical product of the output of the inverter 34 and the output of the D flip-flop 32 as a pulse signal Spwm1b. The configuration of the frequency divider 14 in FIG. 6 is an example, and the present invention is not limited to this.

  FIG. 7 is a time chart showing an operation state in the fourth mode of the control circuit 100a of FIG.

  In the fourth mode, the pulse signal Spwm1 is divided by 1/2 by the frequency divider 14, and the divided pulse signals Spwm1a and Spwm1b are supplied to the high-side transistor MH1 and the high-side transistor MH2, respectively. Here, since the pulse signals Spwm1a and Spwm1b correspond to the drive signals Sd1 and Sd3, the two high-side transistors MH1 and MH2 are alternately turned on. That is, the switching regulator 200 repeatedly performs the operations of turning on the first high-side transistor MH1, turning on the low-side transistor ML1, turning on the second high-side transistor MH2, and turning on the low-side transistor ML1.

  As a result, the first high-side transistor MH1 and the second high-side transistor MH2 can each suppress the continuous flow of the pulse current as compared with the case where a single high-side transistor is provided.

  In the experiment, the ambient temperature of the high-side transistors MH1 and MH2 was measured by operating the switching regulator 200d in FIG. 5B under the conditions of Vin = 7V, Vout = 3.3V, and the switching frequency of 1 MHz. C was obtained. For comparison, when a temperature was measured by operating a single high-side transistor under the same conditions, 74 ° C. was obtained. That is, it was confirmed that the temperature was lowered by about 10 ° C.

  Thus, according to the fourth mode, heat generation can be suppressed. In addition, since the heat generation can be suppressed, the switching frequency can be increased as compared with the conventional case. In this case, the stability of the output voltage Vout can be improved.

  In addition to the fourth mode (alternative mode) in which the plurality of switching transistors MH1 and MH2 are turned on in a time-sharing manner, the control circuit 100a is configured to drive the plurality of switching transistors MH1 and MH2 with the same pulse signal (normally). Mode) and can be switched.

The control circuit 100a is set to the fifth mode when the two high-side transistors MH1 and MH2 are simultaneously turned on. In the fifth mode, the first pulse signal Spwm1 is not divided and distributed to the first driver DRV1 and the third driver DRV3. In other words, Sd1 = Sd3 can be set.
The function and operation of the second driver DRV2 are the same as in the fourth mode.

  In the fifth mode, the high side transistor MH1 and the high side transistor MH2 can be switched at the same timing, and the same operation mode as a conventional switching regulator in which a single high side transistor is provided can be realized.

Alternatively, by providing the normal mode, it is possible to drive even when only a single switching transistor (one of the high-side transistors MH1 and MH2) is provided outside the control circuit 100a.
That is, by making it possible to switch between the normal mode (fifth mode) and the alternative mode (fourth mode), the versatility of the control circuit 100a can be enhanced.

  Those skilled in the art will understand that the above-described embodiment is an exemplification, and that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are also within the scope of the present invention. is there.

The second driver DRV2 may amplify a signal having a duty ratio corresponding to the first pulse signal Spwm1 from the first comparator CMP1 in the second mode, the fourth mode, or the fifth mode.
In this case, a selector that selects either the signal corresponding to the first pulse signal Spwm1 or the second pulse signal Spwm2 may be provided before the second driver DRV2.

  In FIG. 5B, the case where the synchronous rectification switching regulator is the driving target has been described, but a rectifying diode may be provided instead of the low-side transistor ML1.

  In the fourth mode, the case where two high-side transistors are provided has been described, but three or more high-side transistors may be provided. In this case, the effect of heat dispersion can be further enhanced.

Further, in the fourth mode of the second embodiment, the case where the pulse signal Spwm1 is divided by 1/2 and the high side transistors MH1 and MH2 are alternately turned on has been described, but the present invention is not limited to this. .
When generalized, n (natural number) continuous pulses may be taken as one set to generate two sets of pulses, and each set may be distributed to the high-side transistors MH1 and MH2. That is, the time chart of FIG. 7 shows a case where n = 1, but n may be 2 or more.

  In the embodiment, the case where the high-side transistor MH is a P-channel MOSFET has been described, but it may be an N-channel MOSFET.

  In the switching regulator according to the embodiment, the switching transistor may be incorporated in the control circuit 100.

  Although the present invention has been described above based on the embodiments, it should be understood that the embodiments merely illustrate the principles and applications of the present invention, and the embodiments are within the scope of the claims. Needless to say, many modifications and arrangements can be made without departing from the concept of the present invention.

1 is a circuit diagram illustrating a configuration of a control circuit of a step-down switching regulator according to a first embodiment. FIG. 2A and 2B are circuit diagrams illustrating the configuration of a switching regulator including the control circuit of FIG. 3 is a time chart showing an operation state in a second mode of the control circuit of FIG. 1. It is a circuit diagram which shows the structure of the control circuit of the pressure | voltage fall type switching regulator which concerns on 2nd Embodiment. 5A and 5B are circuit diagrams showing the configuration of a switching regulator including the control circuit of FIG. It is a circuit diagram which shows the structural example of a frequency divider. 6 is a time chart showing an operation state in a fourth mode of the control circuit of FIG. 4.

Explanation of symbols

Pi1 ... first input terminal, Pi2 ... second input terminal, Pi3 ... third input terminal, Po1 ... first output terminal, Po2 ... second output terminal, Po3 ... third output terminal, EA1 ... first error amplifier, EA2 2nd error amplifier, EA3 ... 3rd error amplifier, CMP1 ... 1st comparator, CMP2 ... 2nd comparator, CMP3 ... 3rd comparator, DRV1 ... 1st driver, DRV2 ... 2nd driver, DRV3 ... 3rd driver, MH1 ... first high side transistor, MH2 ... second high side transistor, MH3 ... third high side transistor, ML1 ... first low side transistor, D1 ... first rectifying diode, D2 ... second rectifying diode, D3 ... third Rectifier diode, L1 ... first inductor, L2 ... second inductor, L3 ... third inductor, C1 ... first output Capacitors, C2 ... second output capacitor, C3 ... third output capacitor, 100 ... control circuit, 10 ... oscillator 12 ... level shifter, 14 ... divider, 200 ... switching regulator.

Claims (10)

A first input terminal for feeding back a first feedback voltage corresponding to the output voltage of the first channel;
A second input terminal for feeding back a second feedback voltage according to the output voltage of the second channel;
A first error amplifier for amplifying an error between the first feedback voltage and a predetermined first reference voltage;
A second error amplifier for amplifying an error between the second feedback voltage and a predetermined second reference voltage;
A first pulse modulation comparator that compares a first error voltage output from the first error amplifier with a predetermined periodic voltage;
A second pulse modulation comparator for comparing the second error voltage output from said second error amplifier and said periodic voltage,
A first driver for amplifying a first pulse signal from the first pulse modulation comparator;
A second driver for amplifying a second pulse signal from the second pulse modulation comparator;
With
The control circuit is set to the first mode when a 2-channel diode rectification step-down switching regulator is to be controlled, and is set to the second mode when a single-channel synchronous rectification step-down switching regulator is to be controlled. Set to
In the first mode, the output signals of the first and second drivers are supplied to the high-side transistors of the first and second channel diode rectification step-down switching regulators,
In the second mode, the output signal of the first driver is supplied to a high side transistor of a single channel synchronous rectification step-down switching regulator, and the output signal of the second driver has a duty ratio of the first signal. A switching regulator control circuit which is set to a value corresponding to a feedback voltage and is supplied to a low-side transistor of a single-channel synchronous rectification step-down switching regulator. The second pulse modulation comparator, in the first mode, the second error voltage output from said second error amplifier and compared with the cyclic voltage in the second mode is outputted from the first error amplifier The control circuit according to claim 1, wherein a voltage corresponding to a first error voltage is compared with the periodic voltage.   3. The control circuit according to claim 2, wherein the second pulse modulation comparator compares a voltage obtained by level-shifting the first error voltage with the periodic voltage in the second mode. A switch and a resistor provided in series between the output terminal of the first error amplifier and the output terminal of the second error amplifier;
The control circuit according to claim 3, wherein the switch is turned off in the first mode and turned on in the second mode.   The second driver amplifies the second pulse signal from the second pulse modulation comparator in the first mode, and responds to the first pulse signal from the first pulse modulation comparator in the second mode. The control circuit according to claim 1, wherein a signal having a duty ratio is amplified. A third input terminal for feeding back a third feedback voltage corresponding to the output voltage of the third channel;
A third error amplifier for amplifying an error between the third feedback voltage and a predetermined third reference voltage;
A third pulse modulation comparator which compares the third error voltage output from said third error amplifier and the periodic voltage,
A third driver for amplifying a third pulse signal from the third pulse modulation comparator;
Further comprising
The control circuit is set to the third mode when the step-down switching regulator of 3 channels of the diode rectification system and the controlled object,
In the third mode, output signals of the first to third drivers are supplied to high-side transistors of the diode rectification step-down switching regulators of the first to third channels, respectively. control circuit according to any one of claim 1 5. The control circuit is set to a fourth mode when a synchronous rectification step-down switching regulator including two high-side transistors connected in parallel is controlled, and when the two high-side transistors are complementarily turned on,
In the fourth mode, the first pulse signal is divided and distributed to the first and third drivers, the output signals of the first and third drivers are supplied to the two high-side transistors, The output signal of the two drivers is supplied to a low-side transistor of a single channel synchronous rectification step-down switching regulator with a duty ratio set to a value corresponding to the first feedback voltage. Item 7. The control circuit according to Item 6 . The control circuit is set as a fifth mode when a synchronous rectification step-down switching regulator including two high-side transistors connected in parallel is controlled, and when the two high-side transistors are simultaneously turned on,
In the fifth mode, the first pulse signal is distributed to the first and third drivers, the output signals of the first and third drivers are supplied to the two high-side transistors, and the output of the second driver signal, according to claim 6, characterized in that the duty ratio is set to a value corresponding to the first feedback voltage is supplied to the low-side transistor of the step-down switching regulator of a synchronous rectification type of single channel Control circuit.   A third driver;
  The control circuit is set to a fourth mode when a synchronous rectification step-down switching regulator including two high-side transistors connected in parallel is controlled, and when the two high-side transistors are complementarily turned on,
  In the fourth mode, the first pulse signal is divided and distributed to the first and third drivers, the output signals of the first and third drivers are supplied to the two high-side transistors, The output signal of the two drivers is supplied to a low-side transistor of a single channel synchronous rectification step-down switching regulator with a duty ratio set to a value corresponding to the first feedback voltage. Item 6. The control circuit according to any one of Items 1 to 5.   A third driver;
  The control circuit is set as a fifth mode when a synchronous rectification step-down switching regulator including two high-side transistors connected in parallel is controlled, and when the two high-side transistors are simultaneously turned on,
  In the fifth mode, the first pulse signal is distributed to the first and third drivers, the output signals of the first and third drivers are supplied to the two high-side transistors, and the output of the second driver 6. The signal is supplied to a low-side transistor of a single channel synchronous rectification step-down switching regulator with a duty ratio set to a value corresponding to the first feedback voltage. The control circuit according to any one of the above.

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