JP5078759B2 - Wiring board built-in electronic components and wiring board - Google Patents

Description

  The present invention relates to a wiring board built-in electronic component built in a wiring board and a wiring board containing the electronic component.

  In recent years, semiconductor integrated circuit elements (IC chips) used as computer microprocessors and the like have become increasingly faster and more functional, with an accompanying increase in the number of terminals and a tendency to narrow the pitch between terminals. . In general, a large number of terminals are densely arranged on the bottom surface of an IC chip, and such a terminal group is connected to a terminal group on the motherboard side in the form of a flip chip. However, it is difficult to connect the IC chip directly on the mother board because there is a large difference in the pitch between the terminals on the IC chip side terminal group and the mother board side terminal group. For this reason, a method is generally employed in which a package is prepared by mounting an IC chip on an IC chip mounting wiring board, and the package is mounted on a motherboard. In a wiring board for mounting an IC chip constituting this type of package, it has been proposed to provide a capacitor (also referred to as a “capacitor”) in order to reduce switching noise of the IC chip and stabilize the power supply voltage. . For example, a wiring substrate in which a capacitor is embedded in a resin core substrate (see, for example, Patent Document 1) and a wiring substrate in which a capacitor is embedded in a buildup layer formed on the front surface or the back surface of the resin core substrate have been proposed. .

  As a capacitor built in the wiring board, a via array type ceramic capacitor has been put into practical use. The ceramic capacitor includes a ceramic sintered body in which a plurality of ceramic dielectric layers and a plurality of internal electrode layers are alternately stacked. In the ceramic sintered body, a plurality of via conductors in the capacitor that are electrically connected to the internal electrode layers through the ceramic dielectric layers are arranged in an array. Furthermore, external electrodes connected to the end portions of the via conductors in the capacitors are provided on the front and back surfaces of the ceramic sintered body.

Each external electrode in the ceramic capacitor includes, for example, a metallized metal layer formed mainly of nickel and a copper plating layer formed on the surface thereof. In the external electrode, the resistance of the external electrode is reduced by forming a copper plating layer on the surface of the metallized metal layer. Further, by roughening the surface of the copper plating layer in the external electrode, the contact area with the resin insulating layer constituting the wiring board is increased when the capacitor is embedded in the wiring board. Improved adhesion.
JP 2002-1000087 A

  By the way, in the conventional ceramic capacitor, after forming the copper plating layer in the external electrode, the copper plating layer is cured by performing a heat treatment (for example, annealing at 400 ° C. for about 1 hour), and performance such as wear resistance is obtained. To increase. In this heat treatment, the copper particles constituting the copper plating layer grow, and the maximum particle size becomes 7 to 8 μm or more. However, in the copper plating layer, when the maximum particle size of the copper particles is 7 to 8 μm or more, the grain boundary region to be roughened becomes small in the surface roughening treatment. For this reason, a sufficient contact area with the resin insulating layer cannot be ensured, and adhesion with the resin insulating layer is lowered.

  Moreover, when the particle size of the copper particle in a copper plating layer becomes large, adhesiveness with a metallized metal layer will fall. For this reason, when the peel test (peeling test) of the external terminal is performed, the copper plating layer may be peeled off at the interface with the metallized metal layer, and sufficient reliability cannot be obtained.

  The present invention has been made in view of the above problems, and the object thereof is to appropriately perform surface roughening of the copper plating layer formed on the surface of the external electrode, and to provide a resin insulating layer for the wiring board. An object of the present invention is to provide an electronic component with a built-in wiring board that can sufficiently ensure adhesion. Another object of the present invention is to provide a suitable wiring board incorporating the electronic component.

And as means (means 1) for solving the above-mentioned problems, there are electronic components incorporated in the wiring board, which are a ceramic sintered body having a main surface and a back surface, and a main surface and a back surface of the ceramic sintered body. And an external electrode formed by forming a copper plating layer on the surface of the metallized metal layer, the maximum particle size of the copper particles constituting the copper plating layer is 1 μm or less, and There is an electronic component for incorporating a wiring board, which is smaller than the maximum particle size of conductive metal particles constituting a metallized metal layer .

Therefore, according to the electronic component for wiring board built-in means 1, the maximum particle size of the copper particles constituting the copper plating layer is 1 μm or less and smaller than the maximum particle size of the conductive metal particles constituting the metallized metal layer. Therefore, the copper particles can surely adhere to the conductive metal particles of the metallized metal layer at the interface between the metallized metal layer and the copper plated layer constituting the external electrode, and the copper plated layer is hardly peeled off from the metallized metal layer. Moreover, since the particle size of a copper particle is small as mentioned above, in the surface roughening process of a copper plating layer, the grain boundary area | region roughened becomes large, and surface roughening can be performed reliably. Therefore, by roughening the surface of the copper plating layer, it is possible to sufficiently secure the adhesion between the resin insulating layer and the external electrode in the wiring board.

  It is preferable that two or more of the copper particles are in contact with one particle of the conductive metal particles constituting the metallized metal layer at the interface between the metallized metal layer and the copper plating layer. Thus, a copper plating layer excellent in exfoliation resistance can be formed by a plurality of copper particles being securely adhered to the conductive metal particles of the metallized metal layer.

  At the interface between the metallized metal layer and the copper plating layer, it is preferable that the copper particles are in contact with the conductive metal particles in a state of entering the gap between the conductive metal particles constituting the metallized metal layer. If it does in this way, the adhesiveness of a metallization metal layer and a copper plating layer can be improved more.

  Examples of the ceramic sintered body include a sintered body mainly composed of a perovskite oxide. Moreover, it is preferable that the metallized metal layer in this ceramic sintered body is mainly composed of nickel particles as conductive metal particles, and a perovskite oxide is added as co-material particles. Thus, by using nickel as a material for forming the metallized metal layer, the manufacturing cost of the ceramic sintered body can be suppressed as compared with the case of using relatively expensive palladium. Also, by adding perovskite type oxide as co-material particles to the metallized metal layer, the difference in thermal shrinkage of the metallized metal layer in the ceramic sintered body can be suppressed, and problems such as cracks and delamination can be avoided. it can.

  The maximum particle size of the co-material particles made of the perovskite oxide is preferably larger than the maximum particle size of the copper particles. In this case, since the copper particles are smaller than the nickel particles or the common material particles, the copper particles can enter the gaps between the particles and reliably adhere to the nickel particles. Thereby, the adhesiveness of a metallized metal layer and a copper plating layer can be improved. The maximum particle size of the co-material particles may be smaller or larger than the maximum particle size of the nickel particles.

  Examples of the wiring board built-in electronic component include a chip capacitor and a ceramic capacitor. Further, as a suitable ceramic capacitor, a ceramic sintered body having a main surface and a back surface is provided, and a plurality of internal electrodes are laminated on the ceramic sintered body via a ceramic dielectric layer, and the plurality of internal capacitors are arranged. A plurality of via conductors in the capacitor connected to the electrode, and the external electrode is connected to at least one end of the main surface side and the back surface side of the plurality of via conductors in the capacitor. Can be mentioned. The ceramic capacitor is preferably a via array type ceramic capacitor in which the plurality of capacitor via conductors are arranged in an array as a whole. With such a structure, the inductance of the capacitor can be reduced, and noise absorption and voltage stabilization can be achieved. In addition, it is easy to reduce the size of the entire capacitor, and it is also easy to reduce the size of the entire wiring board. Moreover, a high electrostatic capacity is easily achieved for a small amount, and a more stable power supply can be achieved.

  Examples of the perovskite oxide include barium titanate, lead titanate, and strontium titanate. Since this kind of oxide has a high dielectric constant, it is extremely suitable as a dielectric in a capacitor, and by using it, a high-capacity capacitor can be easily realized.

  The copper plating layer is not limited to the plating layer covering the metallized metal layer, and may be a copper post having a height of 150 μm or more. In this case, the surface of the copper post can be reliably roughened, and the adhesion with the resin insulating layer of the wiring board can be improved.

  Further, as another means (means 2) for solving the above-mentioned problem, the electronic component for wiring board in which the surface of the external electrode is roughened is a resin having a core main surface and a core back surface. There is a wiring board characterized in that it is housed in a core board or in a wiring laminated part having a structure in which a resin interlayer insulating layer and a conductor layer are laminated.

  Therefore, according to the wiring board of means 2, since the surface roughening of the copper plating layer constituting the external electrode can be reliably performed in the electronic component built in the wiring board, the external electrode and the resin interlayer insulation layer of the wiring board can be obtained. And the contact area with the resin interlayer insulating layer can be sufficiently enhanced.

  Specific examples of the resin core substrate include an EP resin (epoxy resin) substrate, a PI resin (polyimide resin) substrate, a BT resin (bismaleimide / triazine resin) substrate, and a PPE resin (polyphenylene ether resin) substrate. In addition, a substrate made of a composite material of these resins and organic fibers such as glass fibers (glass woven fabric or glass nonwoven fabric) or polyamide fibers may be used. Alternatively, a substrate made of a resin-resin composite material obtained by impregnating a thermosetting resin such as an epoxy resin with a three-dimensional network fluorine-based resin base material such as continuous porous PTFE may be used.

  The wiring laminated portion constituting the wiring board has a structure in which a resin interlayer insulating layer mainly composed of a polymer material and a conductor layer are laminated. In addition, the wiring lamination | stacking part may be formed only in any one on the said core main surface and the said core back surface, and may be formed in both on the said core main surface and the said core back surface. Is preferably formed on both the core main surface and the core back surface. With this configuration, an electric circuit can be formed in both the wiring laminated portion formed on the core main surface and the wiring laminated portion formed on the back surface of the core, thereby further enhancing the functionality of the wiring board. Can be planned.

  The resin interlayer insulation layer can be appropriately selected in consideration of insulation, heat resistance, moisture resistance and the like. Preferred examples of the material for forming the resin interlayer insulating layer include thermosetting resins such as epoxy resins, phenol resins, urethane resins, silicone resins, and polyimide resins, and thermoplastic resins such as polycarbonate resins, acrylic resins, polyacetal resins, and polypropylene resins. Etc. In addition, composite materials of these resins and organic fibers such as glass fibers (glass woven fabrics and glass nonwoven fabrics) and polyamide fibers, or three-dimensional network fluorine-based resin base materials such as continuous porous PTFE, epoxy resins, etc. A resin-resin composite material impregnated with a thermosetting resin may be used.

  The conductor layer is patterned on the resin interlayer insulating layer by a known method such as a subtractive method, a semi-additive method, or a full additive method. Examples of the metal material used for forming the conductor layer include copper, copper alloy, nickel, nickel alloy, tin, tin alloy and the like.

  Hereinafter, an embodiment in which the present invention is embodied in a wiring board will be described in detail with reference to the drawings.

  As shown in FIG. 1, the wiring board 10 of the present embodiment is a wiring board for mounting an IC chip. The wiring substrate 10 includes a substantially rectangular plate-shaped resin core substrate 11, a first buildup layer 31 (wiring laminated portion) formed on the core main surface 12 (upper surface in FIG. 1) of the resin core substrate 11, a resin It consists of a second buildup layer 32 (wiring laminate) formed on the core back surface 13 (the lower surface in FIG. 1) of the core substrate 11.

  The first buildup layer 31 formed on the core main surface 12 of the resin core substrate 11 includes two resin interlayer insulating layers 33 and 35 made of thermosetting resin (epoxy resin), and a conductor layer 42 made of copper. Are alternately stacked. Terminal pads 44 are formed in an array at a plurality of locations on the surface of the second resin interlayer insulation layer 35. Further, the surface of the resin interlayer insulating layer 35 is almost entirely covered with a solder resist 37. An opening 46 for exposing the terminal pad 44 is formed at a predetermined position of the solder resist 37. A plurality of solder bumps 45 are provided on the surface of the terminal pad 44. Each solder bump 45 is electrically connected to the surface connection terminal 22 of the IC chip 21 having a rectangular flat plate shape. Note that an area including the terminal pads 44 and the solder bumps 45 is an IC chip mounting area 23 on which the IC chip 21 can be mounted. The IC chip mounting area 23 is set on the surface 39 of the first buildup layer 31. Also, via conductors 43 are formed at a plurality of locations in the second resin interlayer insulating layer 35. The lower end of each via conductor 43 is connected to the conductor layer 42 formed on the surface of the resin interlayer insulating layer 33, and the upper end of each via conductor 43 is the surface of the resin interlayer insulating layer 35. It is connected to the terminal pad 44 formed above. The via conductor 43 electrically connects the conductor layer 42 and the terminal pad 44 to each other.

  The second buildup layer 32 formed on the core back surface 13 of the resin core substrate 11 has substantially the same structure as the first buildup layer 31 described above. That is, the second buildup layer 32 has a structure in which two resin interlayer insulating layers 34 and 36 made of thermosetting resin (epoxy resin) and conductor layers 42 are alternately laminated. Via conductors 47 are formed at a plurality of locations in the first resin interlayer insulation layer 34. The lower end of each via conductor 47 is connected to a conductor layer 42 formed on the surface of the resin interlayer insulating layer 34. Via conductors 43 are formed at a plurality of locations in the second resin interlayer insulation layer 36, and via conductors 43 are disposed at the lower end of each via conductor 43 on the lower surface of the resin interlayer insulation layer 36. The BGA pads 48 electrically connected to the conductor layer 42 are formed in a lattice shape. The lower surface of the resin interlayer insulating layer 36 is almost entirely covered with a solder resist 38. An opening 40 for exposing the BGA pad 48 is formed at a predetermined portion of the solder resist 38. A plurality of solder bumps 49 that can be electrically connected to a mother board (not shown) are disposed on the surface of the BGA pad 48. The wiring board 10 shown in FIG. 1 is mounted on a mother board (not shown) by each solder bump 49.

  The resin core substrate 11 of the present embodiment has a substantially rectangular plate shape in plan view of 25 mm long × 25 mm wide × 0.90 mm thick. The resin core substrate 11 includes a base material 161 made of glass epoxy, a sub-base material 164 formed on an upper surface and a lower surface of the base material 161 and made of an epoxy resin to which an inorganic filler such as silica filler is added, and the base material 161. A conductor layer 163 made of copper is formed on the upper and lower surfaces. Further, a plurality of through-hole conductors 16 are formed in the resin core substrate 11 so as to penetrate the core main surface 12, the core back surface 13, and the conductor layer 163. The through-hole conductor 16 connects and conducts the core main surface 12 side and the core back surface 13 side of the resin core substrate 11 and is electrically connected to the conductor layer 163. The inside of the through-hole conductor 16 is filled with a closing body 17 such as an epoxy resin. The upper end of the through-hole conductor 16 is electrically connected to a part of the conductor layer 42 on the surface of the resin interlayer insulating layer 33, and the lower end of the through-hole conductor 16 is on the lower surface of the resin interlayer insulating layer 34. It is electrically connected to a part of a certain conductor layer 42. Further, a conductor layer 41 made of copper is patterned on the core main surface 12 and the core back surface 13 of the resin core substrate 11, and each conductor layer 41 is electrically connected to the through-hole conductor 16. Further, the resin core substrate 11 has one accommodation hole 90 that is rectangular in plan view and opens at the center of the core main surface 12 and the center of the core back surface 13. That is, the accommodation hole 90 is a through hole. The accommodating hole 90 has chamfered portions with chamfer dimensions of 0.1 mm or more and 2.0 mm or less at the four corners.

  In the accommodation hole 90, the ceramic capacitor 101 (wiring board built-in electronic component) shown in FIGS. 2, 3 and the like is accommodated in an embedded state. The ceramic capacitor 101 is accommodated with the capacitor main surface 102 facing the same side as the core main surface 12 and the capacitor back surface 103 facing the same side as the core back surface 13. The ceramic capacitor 101 according to the present embodiment has a substantially rectangular plate shape in plan view of 12.0 mm long × 12.0 mm wide × 0.74 mm thick. The ceramic capacitor 101 is disposed in a region immediately below the IC chip mounting region 23 in the resin core substrate 11. The area of the IC chip mounting region 23 (the area of the surface on which the surface connection terminals 22 are formed in the IC chip 21) is set to be smaller than the area of the capacitor main surface 102 of the ceramic capacitor 101. When viewed from the thickness direction of the ceramic capacitor 101, the IC chip mounting region 23 is located in the capacitor main surface 102 of the ceramic capacitor 101.

  As shown in FIG. 1 and the like, the gap between the inner surface of the accommodation hole 90 and the capacitor side surface 106 of the ceramic capacitor 101 is filled with a resin made of a polymer material (in this embodiment, a thermosetting resin such as epoxy). It is filled with part 92. The resin filling portion 92 has a function of fixing the ceramic capacitor 101 to the resin core substrate 11. Ceramic capacitor 101 has a substantially square shape in plan view, and has chamfered portions with chamfering dimensions of 0.55 mm or more (in this embodiment, chamfering dimensions of 0.6 mm) at four corners. As a result, when the ceramic capacitor 101 is built in the wiring board 10 or when the resin filling portion 92 is deformed due to a temperature change, stress concentration on the corner portion of the ceramic capacitor 101 can be alleviated. Can be prevented.

  As shown in FIGS. 1 to 3 and the like, the ceramic capacitor 101 of the present embodiment is a so-called via array type ceramic capacitor. The ceramic sintered body 104 constituting the ceramic capacitor 101 includes one capacitor main surface 102 (upper surface in FIG. 1), one capacitor back surface 103 (lower surface in FIG. 1), and four capacitor side surfaces 106 (left surface in FIG. 1). , Right side).

  As shown in FIG. 2, the ceramic sintered body 104 is formed by alternately laminating power supply internal electrode layers 141 (internal electrodes) and ground internal electrode layers 142 (internal electrodes) via ceramic dielectric layers 105. It has the structure. The ceramic dielectric layer 105 is made of a sintered body of barium titanate, which is a kind of high dielectric constant ceramic, and functions as a dielectric (insulator) between the power internal electrode layer 141 and the ground internal electrode layer 142. To do. Each of the power supply internal electrode layer 141 and the ground internal electrode layer 142 is a layer formed mainly of nickel, and is disposed in every other layer in the ceramic sintered body 104.

  As shown in FIGS. 1, 2, etc., a large number of via holes 130 are formed in the ceramic sintered body 104. These via holes 130 penetrate the ceramic sintered body 104 in the thickness direction and are arranged in a lattice shape (array shape) over the entire surface of the ceramic sintered body 104. In each via hole 130, a plurality of in-capacitor via conductors 131 and 132 that communicate between the capacitor main surface 102 and the capacitor back surface 103 of the ceramic sintered body 104 are formed using nickel as a main material. In this embodiment, since the diameter of the via hole 130 is set to about 100 μm, the diameter of the via conductors 131 and 132 in the capacitor is also set to about 100 μm. Each power supply capacitor internal via conductor 131 passes through each power supply internal electrode layer 141 and electrically connects them to each other. Each ground capacitor via conductor 132 passes through each ground internal electrode layer 142 and electrically connects them to each other. Each power source capacitor via conductor 131 and each ground capacitor inner via conductor 132 are arranged in an array as a whole.

  As shown in FIG. 2, FIG. 3, etc., on the capacitor main surface 102 of the ceramic sintered body 104, a plurality of main surface side power source plane electrodes 111 (external electrodes) and a plurality of main surface side grounding electrodes are provided. A plain electrode 112 (external electrode) is provided. The respective planar electrodes 111 and 112 are arranged in parallel to each other on the capacitor main surface 102, and are strip-shaped patterns having a width of 300 μm × thickness of 25 μm and a substantially rectangular shape in plan view (see FIG. 3). The main-surface-side power-use plane-like electrode 111 is directly connected to the end face on the capacitor main-surface 102 side of the plurality of power-source capacitor via conductors 131. It is directly connected to the end surface on the capacitor main surface 102 side in the via conductor 132 for grounding capacitor.

  Further, as shown in FIG. 2 and the like, on the capacitor back surface 103 of the ceramic sintered body 104, a plurality of back side power plane electrodes 121 (external electrodes) and a plurality of back side ground plane electrodes 122 ( External electrode). The respective planar electrodes 121 and 122 are arranged in parallel with each other on the capacitor back surface 103, and are a belt-like pattern having a width of 300 μm and a thickness of 25 μm and a substantially rectangular shape in plan view. The back-side power plain electrode 121 is directly connected to the end face on the capacitor back surface 103 side of the plurality of power-source capacitor via conductors 131, and the back-side ground plain electrode 122 includes a plurality of ground capacitors. The inner via conductor 132 is directly connected to the end surface on the capacitor back surface 103 side. Therefore, the power supply plane electrodes 111 and 121 are electrically connected to the power supply capacitor inner via conductor 131 and the power supply inner electrode layer 141, and the ground plane electrodes 112 and 122 are connected to the ground capacitor inner via conductor 132 and the ground. The internal electrode layer 142 is electrically connected.

  As shown in FIG. 4, the plain electrodes 111, 112, 121, 122 are composed of a metallized metal layer 151 and a copper plating layer 152. The metallized metal layer 151 is disposed on the capacitor main surface 102 and the capacitor back surface 103 and is mainly composed of nickel particles. For example, 30 vol% barium titanate (perovskite oxide) is added to the metallized metal layer 151 of the present embodiment as co-material particles with respect to the nickel particles as the main material.

  The copper plating layer 152 has higher conductivity than nickel and covers the entire surface of the metallized metal layer 151. In the present embodiment, the maximum particle size of the copper particles constituting the copper plating layer 152 is 1 μm or less. Furthermore, the surface of the copper plating layer 152 is roughened, and the arithmetic average roughness Ra of the surface of the copper plating layer 152 is set to 0.4 μm. The “arithmetic average roughness Ra” is an arithmetic average roughness Ra defined in JIS B0601. The measurement method of arithmetic average roughness Ra shall be in accordance with JIS B0651.

  As shown in FIGS. 1 to 4, protruding conductors 50 project from the respective planar electrodes 111, 112, 121, 122. The number of the protruding conductors 50 is equal to the number of the via conductors 131 and 132 in the capacitor, and is 50 or more in the present embodiment. Each protruding conductor 50 is a cylindrical conductor (copper post) formed by copper plating. That is, the protruding conductor 50 is formed in a cylindrical shape mainly composed of copper, which is the same metal material as the copper plating layer 152. The maximum particle diameter of the copper particles constituting the protruding conductor 50 is also 1 μm or less like the copper plating layer 152. The diameter of each protruding conductor 50 is set to be smaller than the width (about 300 μm) of the plane electrodes 111, 112, 121, 122 and larger than the diameter (about 100 μm) of the via conductors 131, 132 in the capacitor. In this embodiment, it is set to about 250 μm. Further, the height of the protruding conductor 50 is set to 150 μm or more and 200 μm or less.

  The height (thickness) of each protruding conductor 50 is substantially equal to the thickness of the resin interlayer insulating layer 33, and the surface of the top portion 52 of the protruding conductor 50 protruding on the plane electrodes 111 and 112. Is at the same position as the surface of the resin interlayer insulation layer 33. Further, the surface of each protruding conductor 50 is roughened. The arithmetic average roughness Ra of the surface of the protruding conductor 50 is equal to the arithmetic average roughness Ra of the surface of the copper plating layer 152, and specifically, is set to 0.4 μm. The protruding conductor 50 protruding on the plain electrodes 111 and 112 is connected to the conductor layer 42 formed on the surface of the resin interlayer insulating layer 33. On the other hand, the protruding conductors 50 protruding on the plane electrodes 121 and 122 are connected to via conductors 47 formed at a plurality of locations in the resin interlayer insulating layer 34.

  As shown in FIG. 1, the planar electrodes 111 and 112 on the capacitor main surface 102 side are connected to the surface of the protruding conductor 50, the conductor layer 42, the via conductor 43, the terminal pad 44, the solder bump 45, and the IC chip 21. It is electrically connected to the IC chip 21 through the terminal 22. On the other hand, the plain electrodes 121 and 122 on the capacitor back surface 103 side are provided on a mother board (not shown) through the protruding conductor 50, the via conductor 47, the conductor layer 42, the via conductor 43, the BGA pad 48, and the solder bump 49. Electrically connected to the electrode.

  For example, when energization is performed from the mother board side through the plain electrodes 121 and 122 and a voltage is applied between the power internal electrode layer 141 and the ground internal electrode layer 142, for example, a positive charge is applied to the power internal electrode layer 141. For example, negative charges accumulate in the ground internal electrode layer 142. As a result, the ceramic capacitor 101 functions as a capacitor. In the ceramic capacitor 101, the via-conductor 131 for power supply capacitor and the via-conductor 132 for ground capacitor are alternately arranged adjacent to each other, and the via-conductor 131 for power-supply capacitor and the via-conductor 132 for ground capacitor are connected to each other. The directions of the flowing currents are set to be opposite to each other. Thereby, the inductance component is reduced.

  Next, a method for manufacturing the ceramic capacitor 101 of the present embodiment will be described.

  First, a green sheet of a dielectric material mainly composed of barium titanate is formed, and a nickel paste for internal electrode layers is screen-printed on the green sheet and dried. As a result, a power internal electrode portion that will later become the power internal electrode layer 141 and a ground internal electrode portion that will be the ground internal electrode layer 142 are formed. Next, the green sheets with the power supply internal electrode portions and the green sheets with the ground internal electrode portions are alternately stacked, and each green sheet is integrated by applying a pressing force in the sheet stacking direction. To form a green sheet laminate.

  Further, a number of via holes 130 are formed through the green sheet laminate using a laser processing machine, and a via conductor nickel paste is filled into each via hole 130 using a paste press-fitting and filling device (not shown). Next, a nickel paste for an electrode is printed on the upper surface of the green sheet laminate, and the metallized metal layer 151 of the plain electrodes 111 and 112 is formed so as to cover the upper end surface of each conductor portion on the upper surface side of the green sheet laminate. Form. Also, a nickel paste for an electrode is printed on the lower surface of the green sheet laminate, and the metallized metal layer 151 of the planar electrodes 121 and 122 is formed so as to cover the lower end surface of each conductor portion on the lower surface side of the green sheet laminate. To do.

  Thereafter, the green sheet laminate is dried to solidify each metallized metal layer 151 to some extent. Next, the green sheet laminate is degreased and fired at a predetermined temperature for a predetermined time. As a result, barium titanate and nickel in the paste are simultaneously sintered to form a ceramic sintered body 104.

  Next, electrolytic copper plating (thickness: 15 μm) is performed on each metallized metal layer 151 included in the obtained ceramic sintered body 104. As a result, the copper-plated layer 152 is formed on each metallized metal layer 151, whereby the respective planar electrodes 111, 112, 121, 122 are formed.

In the present embodiment, the plating conditions are set so that the maximum particle size of the copper particles constituting the copper plating layer 152 is 1 μm or less. Specifically, using a copper pyrophosphate plating bath, a temperature of about 50 ° C. to 60 ° C., a current density of about 1.0 A / m ^{2 to} 3.0 A / m ² , a deposition time of about 20 minutes to 25 minutes, etc. Electrolytic copper plating is performed under the conditions. The copper plating bath contains an additive (for example, a brightener) for suppressing the grain growth of copper particles.

  The inventor cut the plane electrode 111 after forming the copper plating layer 152 in the thickness direction, and observed the cut surface with an electron microscope (SEM). FIG. 5 shows an SEM photograph at the cut surface of the plain electrode 111. Here, in order to facilitate observation of the copper plating layer 152, the cut surface of the plane electrode 111 was etched after CP processing (chemical polishing processing). In this etching, an etching solution consisting of ultrapure water (19 ml), 60% ammonia (10 ml), and hydrogen peroxide (1 ml) was used for 7 seconds.

  As shown in FIG. 5, the maximum particle size of the copper particles 154 constituting the copper plating layer 152 is 1 μm or less (the average particle size is about 0.3 μm). There is no change in size, and copper particles 154 having a substantially uniform size are distributed. The maximum particle diameter of the nickel particles 155 constituting the metallized metal layer 151 is about 10 μm, and the maximum particle of the barium titanate 156 added as a co-material is about 5 μm. Accordingly, a plurality of copper particles 154 are in contact with one of the nickel particles 155 constituting the metallized metal layer 151 at the interface between the metallized metal layer 151 and the copper plating layer 152.

  And after forming the copper plating layer 152 of each planar electrode 111,112,121,122, on the capacitor | condenser main surface 102 and the capacitor | condenser back surface 103 of the ceramic sintered compact 104, it is an opening part 182 (inside diameter 250 micrometers) on a predetermined place. A photoresist material 181 having a thickness of 200 μm is laminated (see FIG. 6). These openings 182 are formed by exposure and development, and a part of the surface of the planar electrodes 111, 112, 121, 122 is exposed. A metal mask (thickness: 200 μm) is laminated on the capacitor main surface 102 and the capacitor back surface 103 of the ceramic sintered body 104, and drilling using a drill is performed on the metal mask, thereby opening the opening. A metal mask having the portion 182 may be formed.

  Then, as shown in FIG. 7, electrolytic copper plating is performed on the planar electrodes 111, 112, 121, 122 via a photoresist material 181. Further, the photoresist material 181 is removed. As a result, as shown in FIG. 8, the protruding conductor 50 having a height of 150 μm or more and 200 μm or less is formed on the plane electrodes 111, 112, 121, 122, and the ceramic capacitor 101 is completed. When forming the protruding conductor 50, electrolytic copper plating is performed under the same plating conditions as when forming the copper plating layer 152 of the planar electrodes 111, 112, 121, and 122. As a result, the maximum particle size of the copper particles constituting the protruding conductor 50 is 1 μm or less. Note that the protruding conductor 50 may be formed by electrolytic plating using a copper sulfate plating bath.

  Next, a method for manufacturing the wiring board 10 of the present embodiment will be described.

  First, in the core substrate preparation step, an intermediate product of the resin core substrate 11 is prepared by a conventionally known technique and prepared in advance.

  The intermediate product of the resin core substrate 11 is manufactured as follows. First, a copper clad laminate (not shown) in which copper foil is pasted on both surfaces of a base material 161 having a length of 400 mm × width of 400 mm × thickness of 0.65 mm is prepared. Next, the copper foil on both sides of the copper clad laminate is etched to pattern the conductor layer 163 by, for example, a subtractive method. Specifically, after the electroless copper plating, electrolytic copper plating is performed using the electroless copper plating layer as a common electrode. Further, the dry film is laminated, and the dry film is exposed and developed to form a dry film in a predetermined pattern. In this state, unnecessary electrolytic copper plating layer, electroless copper plating layer and copper foil are removed by etching. Thereafter, the dry film is peeled off. Next, after roughening the upper and lower surfaces of the base material 161 and the conductor layer 163, an epoxy resin film (thickness of 80 μm) to which an inorganic filler has been added is attached to the upper and lower surfaces of the base material 161 by thermocompression bonding. The sub-base material 164 is formed.

  Next, a conductor layer 41 (thickness: 50 μm) is patterned on the upper surface of the upper sub-base material 164 and the lower surface of the lower sub-base material 164. Specifically, after performing electroless copper plating on the upper surface of the upper sub-base material 164 and the lower surface of the lower sub-base material 164, an etching resist is formed, and then electrolytic copper plating is performed. Further, the etching resist is removed and soft etching is performed. Next, the laminated body composed of the base material 161 and the sub base material 164 is drilled using a router to form through holes to be the accommodation hole portions 90 at predetermined positions, and the intermediate product of the resin core substrate 11 (See FIG. 9). The intermediate product of the resin core substrate 11 is a multi-piece core substrate having a structure in which a plurality of regions to be the resin core substrate 11 are arranged vertically and horizontally along the plane direction.

  In the subsequent housing process, using the mounting device (manufactured by Yamaha Motor Co., Ltd.), the core main surface 12 and the capacitor main surface 102 are directed to the same side, and the core back surface 13 and the capacitor back surface 103 are directed to the same side. In this state, the ceramic capacitor 101 is accommodated in the accommodation hole 90 (see FIG. 10). The opening on the core back surface 13 side of the accommodation hole 90 is sealed with a peelable adhesive tape 171. The adhesive tape 171 is supported by a support base (not shown). The ceramic capacitor 101 is affixed and temporarily fixed to the adhesive surface of the adhesive tape 171.

  In this state, a resin filling portion 92 (NAMICS Co., Ltd.) made of a thermosetting resin is used in the gap between the inner surface of the accommodation hole portion 90 and the capacitor side surface 106 of the ceramic capacitor 101 using a dispenser device (manufactured by Asymtek). Product). Then, when heat processing are performed, the resin filling part 92 will harden | cure and the ceramic capacitor 101 will be fixed in the accommodation hole part 90 (refer FIG. 11). At this point, the adhesive tape 171 is peeled off.

  Thereafter, the surface of the copper plating layer 152 constituting the plain electrodes 111 and 112 and the surface of the protruding conductor 50 are roughened (see FIG. 4). In addition, since the surface of the copper plating layer 152 and the surface of the protruding conductor 50 are roughened at the same time, a part of the surface of the copper plating layer 152 (connection portion with the protruding conductor 50) is roughened. Absent.

  Next, the first buildup layer 31 is formed on the core main surface 12 and the second buildup layer 32 is formed on the core back surface 13 based on a conventionally known method. Specifically, first, a resin epoxy insulating layer 33 is formed by depositing a photosensitive epoxy resin on the core main surface 12 and the capacitor main surface 102 and performing exposure and development (see FIG. 12). At this time, each protruding conductor 50 of the ceramic capacitor 101 is engaged with the resin interlayer insulating layer 33, whereby the ceramic capacitor 101 is positioned. Further, a photosensitive epoxy resin is applied to the core back surface 13 and the capacitor back surface 103, and the resin interlayer insulating layer 34 is formed by performing exposure and development. In place of depositing the photosensitive epoxy resin, an insulating resin or a liquid crystal polymer (LCP) may be deposited.

  Further, laser drilling is performed using a YAG laser or a carbon dioxide laser to form a via hole at a position where the via conductor 47 is to be formed. Specifically, a via hole penetrating the resin interlayer insulating layer 34 is formed to expose the surface of the top portion 52 of the protruding conductor 50 protruding on the plane electrodes 121 and 122.

  Further, drilling is performed using a drill machine, and through holes (not shown) penetrating the resin core substrate 11 and the resin interlayer insulating layers 33 and 34 are formed in advance at predetermined positions. Then, after performing electroless copper plating on the surfaces of the resin interlayer insulating layers 33 and 34, the inner surfaces of the via holes, and the inner surfaces of the through holes, an etching resist is formed, and then electrolytic copper plating is performed. Further, the etching resist is removed and soft etching is performed. Thereby, the conductor layer 42 is formed on the resin interlayer insulating layer 33 and the conductor layer 42 is patterned on the resin interlayer insulating layer 34. At the same time, the through-hole conductor 16 is formed in the through hole, and the via conductor 47 is formed in each via hole. Thereafter, the cavity of the through-hole conductor 16 is filled with an insulating resin material (epoxy resin) to form the closing body 17.

  Next, a photosensitive epoxy resin is deposited on the resin interlayer insulation layers 33 and 34, and exposure and development are performed, whereby a resin interlayer insulation having via holes (not shown) at positions where the via conductors 43 are to be formed. Layers 35 and 36 are formed. Instead of depositing the photosensitive epoxy resin, an insulating resin or a liquid crystal polymer may be deposited. In this case, a via hole is formed at a position where the via conductor 43 is to be formed by a laser processing machine or the like. Next, electrolytic copper plating is performed in accordance with a conventionally known method to form a via conductor 43 inside the via hole, a terminal pad 44 is formed on the resin interlayer insulating layer 35, and a BGA is formed on the resin interlayer insulating layer 36. A pad 48 is formed.

  Next, solder resists 37 and 38 are formed by applying and curing a photosensitive epoxy resin on the resin interlayer insulation layers 35 and 36. Thereafter, exposure and development are performed with a predetermined mask placed, and the openings 40 and 46 are patterned in the solder resists 37 and 38. Further, solder bumps 45 are formed on the terminal pads 44 and solder bumps 49 are formed on the BGA pads 48. It can be understood that the product in this state is a multi-cavity wiring board in which a plurality of product regions to be the wiring board 10 are arranged vertically and horizontally along the plane direction. Furthermore, when the multi-cavity wiring board is divided, a large number of wiring boards 10 which are individual products can be obtained simultaneously.

  Therefore, according to the present embodiment, the following effects can be obtained.

  (1) In the ceramic capacitor 101 of the present embodiment, in the planar electrodes 111, 112, 121, 122, the maximum particle size of the copper particles 154 constituting the copper plating layer 152 is 1 μm or less and the metallized metal layer 151 Smaller than the maximum particle size of the nickel particles 155 constituting the. Specifically, the nickel particles 155 have a maximum particle size of about 10 μm, and one or more copper particles 154 are in contact with one nickel particle 155. As described above, when the plurality of copper particles 154 are in close contact with the nickel particles 155 of the metallized metal layer 151, the copper plating layer 152 having excellent peel resistance can be formed. Moreover, since the maximum particle diameter of the copper particle 154 which comprises the copper plating layer 152 is as small as 1 micrometer or less, the grain boundary area | region roughened becomes large, and the surface roughening of the copper plating layer 152 can be performed more reliably. . Thereby, sufficient adhesiveness with the resin interlayer insulation layer 33 in the wiring board 10 can be ensured.

  (2) In the ceramic capacitor 101 of the present embodiment, the protruding conductors 50 project from the respective planar electrodes 111, 112, 121, 122. Each protruding conductor 50 is a copper plating layer formed by electrolytic copper plating, and the maximum particle diameter of the copper particles constituting the protruding conductor 50 is 1 μm or less. In this way, the surface roughness of each protruding conductor 50 can be more reliably performed, and sufficient adhesion with the resin interlayer insulating layer 33 in the wiring board 10 can be ensured.

  (3) In the ceramic capacitor 101 of the present embodiment, in each of the planar electrodes 111, 112, 121, 122, the metallized metal layer 151 is mainly composed of nickel particles 155, and barium titanate 156 is used as the co-material particles. It has been added. Thus, by using nickel as the material for forming the metallized metal layer 151, the manufacturing cost of the ceramic sintered body 104 can be reduced as compared with the case of using relatively expensive palladium. Moreover, by adding barium titanate 156 as co-material particles to the metallized metal layer 151, the difference in thermal shrinkage of the metallized metal layer 151 in the ceramic sintered body 104 can be suppressed, and problems such as cracks and delamination are avoided. can do.

  (4) In the case of this embodiment, the maximum particle size of barium titanate 156 is about 5 μm, which is smaller than the maximum particle size of nickel particles 155 and larger than the copper particles 154 of the copper plating layer 152. . In this case, even if a gap is formed between the nickel particle 155 having a relatively large particle size and the barium titanate 156 at the interface between the metallized metal layer 151 and the copper plating layer 152, the copper particle 154 is formed in the gap. Can enter the nickel particles 155 without fail. Thereby, the adhesiveness of the metallized metal layer 151 and the copper plating layer 152 can be improved.

  (5) In the wiring board 10 of the present embodiment, the via array type ceramic capacitor 101 is housed in the housing hole 90 as the electronic component for wiring board built-in. In this ceramic capacitor 101, since the plurality of via conductors 131 and 132 are arranged in an array as a whole, the inductance of the ceramic capacitor 101 can be reduced, and high-speed power supply for noise absorption and power fluctuation smoothing can be achieved. Is possible. In addition, the entire ceramic capacitor 101 can be easily reduced in size, and as a result, the entire wiring board can be easily reduced in size. In addition, a high capacitance is easily achieved for a small amount, and more stable power supply to the IC chip 21 is possible.

  (6) In the wiring substrate 10 of the present embodiment, the ceramic capacitor 101 is disposed immediately below the IC chip 21 mounted in the IC chip mounting region 23, so that the wiring connecting the ceramic capacitor 101 and the IC chip 21 is short. Thus, an increase in the inductance component of the wiring is prevented. Therefore, the switching noise of the IC chip 21 due to the ceramic capacitor 101 can be reliably reduced, and the power supply voltage can be reliably stabilized. In addition, since noise entering between the IC chip 21 and the ceramic capacitor 101 can be suppressed to a very low level, high reliability can be obtained without causing malfunction such as malfunction.

  (7) In the wiring substrate 10 of the present embodiment, since the IC chip mounting area 23 is located in the area immediately above the ceramic capacitor 101, the IC chip 21 mounted in the IC chip mounting area 23 is highly rigid. And supported by a ceramic capacitor 101 having a low coefficient of thermal expansion. Therefore, in the IC chip mounting area 23, the first buildup layer 31 is not easily deformed, so that the IC chip 21 mounted in the IC chip mounting area 23 can be supported more stably. Therefore, it is possible to prevent the IC chip 21 from cracking and poor connection due to large thermal stress. Therefore, the IC chip 21 is considered to be a large IC chip of 10 mm square or more, which has a large stress (strain) due to a difference in thermal expansion and is greatly affected by thermal stress, and has a large calorific value and severe thermal shock during use. A low-k (low dielectric constant) IC chip can be used.

  In addition, you may change embodiment of this invention as follows.

  In the wiring substrate 10 of the above embodiment, the ceramic capacitor 101 is accommodated in the resin core substrate 11. However, a ceramic capacitor 303 (thickness 0.08 mm) thinner than the ceramic capacitor 101 of the above embodiment is formed, and the ceramic capacitor 303 is placed in the first buildup layer 310 of the wiring board 10A (see, for example, FIG. 13). May be accommodated. Also in the ceramic capacitor 303, similarly to the ceramic capacitor 101 described above, external electrodes (plane-like electrodes 111 and 112 on the capacitor main surface 102 and a plane on the capacitor back surface 103) composed of the metallized metal layer 151 and the copper plating layer 152. And the protruding conductor 50 is formed on the plain electrodes 111, 112, 121, 122. In addition, the maximum particle diameter of the copper particle which comprises the copper plating layer 152 of each electrode 111,112,121,122 is 1 micrometer or less, and the maximum particle diameter of the copper particle which comprises the protruding conductor 50 is also 1 micrometer or less. Then, after the surface of the copper plating layer 152 of each electrode 111, 112, 121, 122 and the surface of the protruding conductor 50 are roughened, the ceramic capacitor 303 is built in the resin core substrate 11.

  Specifically, a resin sheet (uncured resin interlayer insulating layer 30) is laminated on the core main surface 12 of the resin core substrate 11, and before the resin sheet is cured, a mounting device (manufactured by Yamaha Motor Co., Ltd.). ) To place the ceramic capacitor 303 on the resin sheet. At this time, a part of the ceramic capacitor 303 (the planar electrodes 121 and 122 and the protruding conductor 50 on the capacitor back surface 103 side) is made to enter the resin sheet while being pressurized. Thereby, since the protruding conductor 50 bites into the resin sheet, the ceramic capacitor 303 is positioned. Thereafter, the resin sheet is cured to form the resin interlayer insulating layer 30. Furthermore, if the resin interlayer insulation layer 30 and the conductor layer 42 are formed alternately, the first buildup layer 310 is completed.

  Also in this ceramic capacitor 303, since the maximum particle diameter of the copper particles constituting the copper plating layer 152 and the protruding conductor 50 of each electrode 111, 112, 121, 122 is as small as 1 μm or less, the grain boundary region to be roughened is small. As a result, the surface of the copper plating layer 152 and the protruding conductor 50 can be more reliably roughened. As a result, in the wiring board 10 </ b> A, the adhesion between the electrodes 111, 112, 121, 122 of the ceramic capacitor 303 and the protruding conductor 50 and the resin interlayer insulating layer 30 can be sufficiently ensured. Further, as compared with the case where the ceramic capacitor 101 is accommodated in the resin core substrate 11, a conduction path (capacitor connection wiring) for electrically connecting the IC chip 21 and the ceramic capacitor 303 is shortened. This prevents an increase in the inductance component of the wiring, so that the switching noise of the IC chip 21 can be reliably reduced by the ceramic capacitor 303 and the power supply voltage can be reliably stabilized. Furthermore, since noise entering between the IC chip 21 and the ceramic capacitor 303 can be suppressed to a very low level, high reliability can be obtained without causing malfunction such as malfunction. Even if the thin ceramic capacitor 303 is used, since the ceramic capacitor 303 itself is thick, in FIG. 13, the build-up layer is a first build-up layer made of the resin interlayer insulating layer 30 having a thickness greater than that of the above embodiment. It is embodied in 310. Further, the ceramic capacitor 101 of the above embodiment may be accommodated in the same first buildup layer 31 as that of the above embodiment.

  In the above embodiment, after the protruding conductors 50 are projected on the plain electrodes 111, 112, 121, 122, the surface of the copper plating layer 152 constituting the plane electrodes 111, 112, 121, 122 The surface of the protruding conductor 50 was roughened at the same time. However, after the planar electrodes 111, 112, 121, and 122 are formed, they may be roughened once and then roughened again when the protruding conductors 50 are formed. In this way, the connection portion between the copper plating layer 152 and the protruding conductor 50 is also roughened, so that the adhesion between the two is improved (see FIG. 14).

  In the above embodiment, the ceramic capacitors 101 and 303 having the protruding conductors 50 on the plain electrodes 111, 112, 121, and 122 are embodied, but the present invention is not limited to this. Specifically, for example, as shown in FIG. 15, a ceramic capacitor 101A in which no protruding conductor 50 is formed on each of the planar electrodes 111, 112, 121, 122 may be built in the wiring board 10B. . The ceramic capacitor 101A is a capacitor that has been completed without performing the process of forming the protruding conductors 50 in the above embodiment, and the rest of the configuration is the same as the ceramic capacitor 101. In the wiring substrate 10B, the plane electrodes 111 and 112 on the capacitor main surface 102 of the ceramic capacitor 101A are connected to the conductor layer 42 via via conductors 47 formed in the resin interlayer insulating layer 33. Furthermore, the planar electrodes 121 and 122 on the capacitor back surface 103 in the ceramic capacitor 101A are connected to the conductor layer 42 via via conductors 47 formed in the resin interlayer insulating layer 34. Also in this ceramic capacitor 101A, the maximum particle diameter of the copper particles 154 constituting the copper plating layer 152 of the plain electrodes 111, 112, 121, 122 is 1 μm or less. For this reason, it is possible to reliably roughen the surface of the copper plating layer 152, and to sufficiently secure the adhesion between the wiring substrate 10B and the resin interlayer insulating layers 33 and 34.

  In the ceramic capacitor 101 of the above embodiment, the planar electrodes 111, 112, 121, and 122 having a substantially rectangular shape in plan view are provided as external electrodes, but the external electrodes have a circular shape or the like You may change into a shape suitably. In the ceramic capacitor 101, the plain electrodes 111, 112, 121, 122 are provided on both the capacitor main surface 102 and the capacitor back surface 103, but may be provided on only one of them.

  In the above embodiment, the package form of the wiring board 10 is BGA (ball grid array). However, the package form is not limited to BGA. For example, PGA (pin grid array) or LGA (land grid array) may be used. Good.

  Next, the technical ideas grasped by the embodiment described above are listed below.

  (1) A ceramic sintered body having a main surface and a back surface, and an external electrode which is disposed on at least one of the main surface and the back surface of the ceramic sintered body and has a copper plating layer formed on the surface of the metallized metal layer And the copper particle constituting the copper plating layer has a maximum particle size of 5 μm or less, and the surface of the copper plating layer is roughened when embedded in the wiring substrate. Electronic components.

  (2) The wiring board built-in electronic component according to (1), wherein the copper plating layer is a copper post having a height of 150 μm or more.

1 is a schematic cross-sectional view showing a wiring board of an embodiment embodying the present invention. The schematic sectional drawing which shows a ceramic capacitor. The top view which shows a ceramic capacitor. The schematic sectional drawing which shows the principal part of a ceramic capacitor. The schematic expanded sectional view which showed notionally the mode of the interface of a metallization metal layer and a copper plating layer in a planar electrode. Explanatory drawing of the manufacturing method of a ceramic capacitor. Explanatory drawing of the manufacturing method of a ceramic capacitor. Explanatory drawing of the manufacturing method of a ceramic capacitor. Explanatory drawing of the manufacturing method of a wiring board. Explanatory drawing of the manufacturing method of a wiring board. Explanatory drawing of the manufacturing method of a wiring board. Explanatory drawing of the manufacturing method of a wiring board. The schematic sectional drawing which shows the wiring board in another embodiment. The schematic sectional drawing which shows the principal part of the ceramic capacitor in another embodiment. The schematic sectional drawing which shows the wiring board in another embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10, 10A, 10B ... Wiring board 11 ... Resin core board 12 ... Core main surface 13 ... Core back surface 31,310 ... 1st buildup layer as a wiring lamination part 32 ... 2nd buildup layer 30 as a wiring lamination part, 33, 34, 35, 36 ... resin interlayer insulation layer 42 ... conductor layer 101, 101A, 303 ... ceramic capacitor as electronic component 102 ... capacitor main surface as main surface 103 ... capacitor back surface as back surface 104 ... ceramic sintered body DESCRIPTION OF SYMBOLS 105 ... Ceramic dielectric layer 111 ... Main surface side power plane plain electrode as external electrode 112 ... Main surface side ground plane electrode as external electrode 121 ... Back side power plane electrode as external electrode 122 ... External Planar electrode for back side ground as electrode 131... For power supply as via conductor in capacitor In-capacitor via conductor 132... Capacitor via conductor for ground as a via conductor in capacitor 141... Internal electrode layer for power supply as an internal electrode 142... Internal electrode layer for ground as an internal electrode 151. 154 ... Copper particles 155 ... Nickel particles 156 ... Barium titanate as a perovskite oxide

Claims (7)

An electronic component built in a wiring board,
A ceramic sintered body having a main surface and a back surface, and an external electrode disposed on at least one of the main surface and the back surface of the ceramic sintered body and having a copper plating layer formed on the surface of the metallized metal layer ,
A wiring board built-in electronic component, wherein the maximum particle size of copper particles constituting the copper plating layer is 1 μm or less and smaller than the maximum particle size of conductive metal particles constituting the metallized metal layer . At the interface between the copper plating layer and the metallized metal layer, to one particle of the conductive metal particles constituting the metallized metal layer, to claim 1, wherein the copper particles are in contact two or more Electronic component for built-in wiring board as described. In the interface between the metallized metal layer and the copper plating layer, the copper particles are in contact with the conductive metal particles in a state of entering the gap between the conductive metal particles constituting the metallized metal layer. The electronic component for a wiring board according to claim 2 . The ceramic sintered body is mainly composed of a perovskite oxide, the metallized metal layer is mainly composed of nickel particles as conductive metal particles, and the perovskite oxide is added as co-material particles. The wiring board built-in electronic component according to any one of claims 1 to 3 . 5. The electronic component with a built-in wiring board according to claim 4 , wherein the maximum particle size of the co-material particles made of the perovskite oxide is larger than the maximum particle size of the copper particles. In the ceramic sintered body, a plurality of internal electrodes are laminated and disposed via a ceramic dielectric layer, and a plurality of via conductors in a capacitor connected to the plurality of internal electrodes are provided,
The external electrode is connected to at least one end of the main surface side and the back surface side of the plurality of via conductors in the capacitor,
The wiring board built-in electronic component according to any one of claims 1 to 5 , wherein the plurality of via conductors in the capacitor are arranged in an array as a whole. The wiring board built-in electronic component according to any one of claims 1 to 6 , wherein the surface of the external electrode has been roughened, is in a resin core substrate having a core main surface and a core back surface, or a resin. A wiring board which is housed in a wiring laminated portion having a structure in which an interlayer insulating layer and a conductor layer are laminated.

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