JP5045730B2 - Level conversion circuit - Google Patents

Description

The present invention relates to a level conversion circuit that shifts and outputs a voltage level of an input signal.
In a multi-power supply semiconductor integrated circuit device (LSI), a level conversion circuit is provided to connect circuits having different power supply voltages. A level conversion circuit that connects circuits of different power supply voltages, particularly a level conversion circuit (a level conversion circuit for boosting) that converts a signal of a circuit of a low power supply voltage into a signal of a circuit of a high power supply voltage has a high power supply voltage. Compared with a circuit (a step-down level conversion circuit) that converts a circuit signal of 1 into a circuit signal of a low power supply voltage, an amplification function is required, so that the delay time and power consumption tend to increase. Therefore, a level conversion circuit that can reduce delay time and power consumption is required.

  In recent years, with the progress of miniaturization of integrated circuits, the degree of integration of digital circuits has continued to improve in semiconductor integrated circuit devices. In order to improve the reliability and reduce power consumption associated with the miniaturization, The power supply voltage is decreasing. For example, the power supply voltage of an integrated circuit manufactured with a 0.35 um technology is about 3.3 V, and the power supply voltage of an integrated circuit manufactured with a 0.18 um technology is about 1.8 V. On the other hand, in semiconductor integrated circuit devices and the like used as control parts for automobiles, there is still a strong demand for using the conventional 5V power supply voltage as the power supply voltage for the interface unit. For this reason, the internal circuit power supply voltage is used as the power supply of the interface circuit in order to enjoy the benefits of increased integration due to miniaturization while leaving the interface circuit compatible with the conventional power supply voltage (for example, 5 V). Many LSIs have been manufactured in which the internal circuit is formed by a fine CMOS process with a voltage value lower than the voltage.

  Further, the external specification of LSI is not limited to the case where there are a plurality of power supply voltages, but a voltage higher than the power supply voltage supplied from the outside is generated by an internal booster circuit such as DRAM, flash EEPROM, etc. There are many LSIs that use a plurality of different power supply voltages, and an LSI that uses a plurality of different power supply voltages as a result of generating an internal voltage lower than the power supply voltage supplied from the outside by a so-called step-down circuit.

  These multi-power supply LSIs are provided with a level conversion circuit for connecting circuits having different power supply voltages. Conventional level conversion circuits are disclosed in Patent Documents 1 to 9 and the like. The level conversion circuit is also called a level shift circuit or a level shifter circuit.

  25 and 26 show typical circuit examples of these conventional level conversion circuits. Note that the level conversion circuit 1 in FIG. 25 is a circuit disclosed in Patent Document 1, and the level conversion circuit 2 in FIG. 26 is a circuit disclosed in Patent Document 2.

  First, the level conversion circuit 1 of FIG. 25 will be described. The level conversion circuit 1 includes high breakdown voltage PMOS transistors PH1, PH2, high breakdown voltage NMOS transistors NH1, NH2, low breakdown voltage PMOS transistors PL1, PL2, and low breakdown voltage NMOS transistors NL1, NL2. In FIG. 25, a high breakdown voltage MOS transistor is circled in order to distinguish it from a low breakdown voltage MOS transistor. Similarly, in other drawings in this specification, the symbols of the high voltage MOS transistors are circled.

  The high breakdown voltage NMOS transistor NH1 has a drain connected to the drain of the high breakdown voltage PMOS transistor PH1 and the gate of the PMOS transistor PH2, and a source connected to the ground. The high breakdown voltage NMOS transistor NH2 has a drain connected to the drain of the high breakdown voltage PMOS transistor PH2 and the gate of the PMOS transistor PH1, and a source connected to the ground. The source voltage Vpp of the high voltage circuit portion is supplied to the sources of the PMOS transistors PH1 and PH2.

  The input signal IN is supplied to an inverter circuit 3 composed of a low breakdown voltage PMOS transistor PL1 and a low breakdown voltage NMOS transistor NL1. The output node N10 of the inverter circuit 3 (the connection portion between the MOS transistors PL1 and PL2) is connected to the inverter circuit 4 (the gates of the MOS transistors PL2 and NL2) composed of the low breakdown voltage PMOS transistor PL2 and the low breakdown voltage NMOS transistor NL2. It is connected. Each of the inverter circuits 3 and 4 operates by being supplied with the power supply voltage Vdd of the digital circuit.

  The output node N10 of the inverter circuit 3 is connected to the gate of the high breakdown voltage NMOS transistor NH1, and the output node N11 of the inverter circuit 4 is connected to the gate of the high breakdown voltage NMOS transistor NH2. Then, an output signal OUT is output from a connection portion between the PMOS transistor PH2 and the NMOS transistor NH2.

  Here, for example, when the power supply voltage Vdd of the digital circuit is 1.8V and the power supply voltage Vpp of the high voltage circuit portion is 5V, the level conversion circuit 1 in FIG. The level of IN is converted to an output signal OUT of 5V.

  Specifically, when the input signal IN is at H level (1.8V potential level), the output node N10 of the inverter circuit 3 is at L level (0V potential level), and the output node N11 of the inverter circuit 4 is at H level. Become. Since the output node N10 of the inverter circuit 3 is at L level, the NMOS transistor NH1 is turned off, and since the output node N11 of the inverter circuit 4 is at H level, the NMOS transistor NH2 is turned on. When the NMOS transistor NH2 is turned on, the output signal OUT becomes L level. At this time, since the NMOS transistor NH2 is turned on and the PMOS transistor PH2 is turned off, no steady current flows in the circuit.

  When the input signal IN is at L level, the output node N10 of the inverter circuit 3 is at H level and the output node N11 of the inverter circuit 4 is at L level. Therefore, the NMOS transistor NH1 is turned on and the NMOS transistor NH2 is turned off. Since the NMOS transistor NH1 is turned on, the node N20 between the PMOS transistor PH1 and the NMOS transistor NH1 becomes L level, and the PMOS transistor PH2 is turned on. When the PMOS transistor PH2 is turned on and the NMOS transistor NH2 is turned off, the output signal OUT becomes H level. At this time, since the PMOS transistor PH2 is turned on and the NMOS transistor NH2 is turned off, no steady current flows in the circuit.

  The signal amplitude of the node N20 and the output signal OUT is as large as 5V determined by the power supply voltage Vpp. Since 5V of the power supply voltage Vpp is applied to each circuit element in this portion, each MOS transistor PH1, PH2, NH1, NH2 A high breakdown voltage transistor is used for this. In a general MOS transistor, the breakdown voltage is increased by increasing the thickness of the gate oxide film. Further, in order to suppress the short channel effect and increase the drain breakdown voltage associated with increasing the thickness of the gate oxide film, it is necessary to ensure a long channel length.

The conventional level conversion circuit 1 configured in this manner is widely put into practical use because it has a simple circuit configuration and no steady current flows.
Next, the level conversion circuit 2 of FIG. 26 will be described. In the figure, the same components as those of the level conversion circuit 1 in FIG. That is, the level conversion circuit 2 includes a bias circuit 6 in addition to the MOS transistors PH1, PH2, NH1, NH2, PL1, PL2, NL1 and NL2, and the bias potential NB generated by the bias circuit 6 has a high breakdown voltage. Are supplied to the gates of the NMOS transistors NH1 and NH2. The source of the high breakdown voltage NMOS transistor NH 1 is connected to the output node N 10 of the inverter circuit 3, and the source of the high breakdown voltage NMOS transistor NH 2 is connected to the output node N 11 of the inverter circuit 4.

  The bias circuit 6 includes a resistor R2 and a high breakdown voltage PMOS transistor PH5. The power supply voltage Vpp of the high voltage circuit portion is supplied to the source of the PMOS transistor PH5 via the resistor R2. The power supply voltage Vdd of the digital circuit is supplied to the gate of the PMOS transistor PH5, and the drain of the PMOS transistor PH5 is connected to the ground.

  Also in this level conversion circuit 2, when the power supply voltage Vdd of the digital circuit is 1.8 and the power supply voltage Vpp of the high voltage circuit portion is 5V, the input signal IN with the signal amplitude of 1.8V is converted to the output signal of 5V. Level conversion to OUT. The bias potential NB in the bias circuit 6 is a potential (Vdd + Vth) that is higher than the power supply voltage Vdd by about the threshold voltage Vth of the PMOS transistor PH5. The resistor R2 of the bias circuit 6 functions as a current source of the source follower circuit.

  Specifically, when the input signal IN is at the H level (1.8V), the output node N10 of the inverter circuit 3 is at the L level (0V), and the output node N11 of the inverter circuit 4 is at the H level (1.8V). . Here, the bias potential NB of the bias circuit 6 is set to a potential of 2.4 V (= 1.8 V + 0.6 V) higher than the power supply voltage Vdd by a threshold voltage (for example, 0.6 V). In this case, since the node N10 is at the L level (0 V) and the bias potential NB is 2.4 V, the NMOS transistor NH1 is turned on (conductive state). Further, since the node N11 is at the H level (1.8V) and the bias potential NB is 2.4V, only a voltage of 0.6V is applied between the gate and source of the NMOS transistor NH2. Therefore, the NMOS transistor NH2 is turned off (non-conducting state).

  At this time, when the NMOS transistor NH1 is turned on, the node N20 becomes L level and the PMOS transistor PH2 is turned on. When the PMOS transistor PH2 is turned on and the NMOS transistor NH2 is turned off, the output signal OUT becomes H level. At this time, since the PMOS transistor PH2 is turned on and the NMOS transistor NH2 is turned off, no steady current flows in the circuit.

  When the input signal IN is at L level, the output node N10 of the inverter circuit 3 is at H level and the output node N11 of the inverter circuit 4 is at L level. In this case, since the node N10 is at the H level (1.8V) and the bias potential NB is 2.4V, only a voltage of 0.6V is applied between the gate and source of the NMOS transistor NH1. Therefore, the NMOS transistor NH1 is turned off. Further, since the node N11 is at the L level (0 V) and the bias potential NB is 2.4 V, the NMOS transistor NH2 is turned on. Therefore, the output signal OUT becomes L level. At this time, the PMOS transistor PH1 is turned on and the NMOS transistor NH1 is turned off, so that the node N20 becomes H level (5 V). When the node N20 becomes H level, the PMOS transistor PH2 is turned off, so that no steady current flows through the circuit.

  In this level conversion circuit 2, since the signal amplitudes of the nodes N10 and N20 are limited to 0V to 1.8V, the low breakdown voltage MOS transistors PL1, PL2, NL1 and NL2 have a power supply voltage Vdd higher than the digital circuit. No voltage is applied. Further, by setting the bias potential to a potential (2.4V) that is higher than the power supply voltage Vdd by about the threshold voltage Vth, the gate-source voltage when the NMOS transistors NH1 and NH2 are turned on becomes the power supply voltage Vdd. The voltage value is increased by adding the value voltage Vth to achieve high-speed operation of the circuit.

  As described above, in the level conversion circuit 2, the bias circuit 6 is added to the level conversion circuit 1 of FIG. A non-flowing configuration is realized.

JP-A-6-204850 JP 2003-101405 A JP 2001-351393 A JP 2002-190731 A JP 2003-60496 A JP 2002-198800 A JP 2001-274675 A Japanese Patent Laid-Open No. 9-7371 JP-A-6-37624

  By the way, in the level conversion circuit 1 of FIG. 25, a level conversion function for converting the input signal IN of the low power supply voltage Vdd into the output signal OUT of the high power supply voltage Vpp can be realized with a simple circuit configuration. There is a problem of becoming larger. Further, if the voltage value of the low power supply voltage Vdd is reduced to about the threshold voltage Vth of the high breakdown voltage NMOS transistors NH1 and NH2, the delay time becomes long and the operation speed of the circuit is lowered. The problem that the occupied area becomes large is also pointed out in Patent Document 3.

  In the level conversion circuit 1 of FIG. 25, for example, consider a case where the output signal OUT is changed from H level to L level. When the output signal OUT is at the H level (5V), the node N20 having a complementary signal level is at the L level (0V), and the input signal IN is also at the L level. When the input signal IN changes to H level (1.8 V), the node N10 becomes L level and the node N11 becomes H level. At this time, in order for the output signal OUT to change from the H level to the L level, the NMOS transistor NH2 passes a current larger than the current supplied from the PMOS transistor PH2, so that the potential of the output terminal is changed from the H level to the L level. Need to be discharged. Here, while 5V is applied to the gate-source voltage of the PMOS transistor PH2, the gate-source voltage of the NMOS transistor NH2 is only 1.8V, which is higher than the drive current of the PMOS transistor PH2. In order to increase the drive current, the gate width of the transistor NH2 must be designed large.

  Further, assuming that the maximum value of the threshold voltage Vth of the NMOS transistor NH2 is 1.2V when the lower limit value of the low power supply voltage Vdd is 1.2V, how large the gate width of the transistor NH2 is. Even if designed, it becomes impossible to increase the drive current of the NMOS transistor NH2 more than the PMOS transistor PH2, and normal circuit operation cannot be realized.

  On the other hand, in the level conversion circuit 2 of FIG. 26, the above disadvantages are eliminated with a relatively simple configuration in which the bias circuit 6 is added and the circuit connection is changed. Circuit configurations similar to the level conversion circuit 2 are also disclosed in Patent Documents 3 and 4.

  In the level conversion circuit 1 of FIG. 25, the signal of the low power supply voltage Vdd is supplied to the gates of the high breakdown voltage NMOS transistors NH1 and NH2. On the other hand, in the level conversion circuit 2 in FIG. 26, the signal of the power supply voltage Vdd is supplied to the sources of the NMOS transistors NH1 and NH2, and the threshold of the NMOS transistor is higher than the power supply voltage Vdd at the gates of the NMOS transistors NH1 and NH2. A bias potential NB (= Vdd + Vth) having a value voltage Vth higher than that is supplied. As a result, almost no steady current flows in the level conversion circuit 2, and the level conversion function is realized. Further, the gate-source voltages of the NMOS transistors NH1 and NH2 are higher by about the threshold voltage Vth than the power supply voltage Vdd. Since the voltage is used, the circuit operation can be speeded up. Further, in this level conversion circuit 2, since the gate-source voltage of the NMOS transistors NH1 and NH2 becomes high, it becomes easy to design the drive current of the NMOS transistor NH2 larger than the drive current of the PMOS transistor PH2.

  However, in the level conversion circuit 2 of FIG. 26, the bias circuit 6 that generates the bias potential is always in operation, and current is consumed even when level conversion is not necessary. For example, when an LSI is manufactured and shipped, a test is performed to check whether the LSI satisfies desired characteristics. This test has an important item called IDDQ. This IDDQ is a measurement item of Quiescent Power Supply Current. In the case of a CMOS circuit, a current flows only at the moment when a signal changes, and hardly flows in a steady state where there is no signal change. In an LSI having a leak failure or a signal fixing failure, since a quiescent current increases due to a leak current or a through current flowing in the CMOS circuit, the presence or absence of the failure is determined by detecting it. Therefore, if the steady current in the bias circuit 6 cannot be stopped, the accuracy of IDDQ measurement, which is an important item as an LSI, is lowered.

  Further, for example, in an integrated circuit manufactured with a 0.18 um technology, in which each circuit of 1.8 V, 3.3 V, and 5 V power supply voltage is mixed, the power supply voltage of the digital circuit is 1.8 V, and the external interface A circuit configuration in which most of the power supply voltage of the circuit is 3.3V and only some of the power supply voltages of the analog circuits is 5V is conceivable. This LSI requires a level conversion circuit for converting the signal level between a circuit that operates with a power supply voltage of 1.8V and a circuit that operates with a power supply voltage of 5V. In some cases, the period of operation is limited to a small part.

  In such a case, it is desirable to activate and operate the circuit only during the period of use, and to minimize the current during the period of not using the circuit. However, in the level conversion circuit 2 of FIG. 26, since the circuit configuration for stopping the bias circuit 6 has not been studied, there is a problem that wasteful current is consumed as described above.

  Similarly, the level conversion circuit of Patent Document 3 supplies a circuit signal of a low power supply voltage to the source of a high voltage NMOS transistor, and the gate potential of the NMOS transistor is increased from a low power supply voltage to a threshold voltage of the NMOS transistor. High-speed operation is realized by biasing to the value. However, a specific circuit configuration of the bias circuit is not disclosed, and, of course, a circuit that stops the bias circuit at the time of testing or the like is not shown.

  On the other hand, the level conversion circuit of Patent Document 4 discloses a bias circuit that stops generation of a bias potential by a control signal. In this level conversion circuit, when the low power supply voltage is 1.8V and the high power supply voltage is 5V, the control signal has a signal amplitude of 5V in order to control the stop of the bias circuit. This is because it is necessary to form a bias circuit with a 5V breakdown voltage MOS transistor in order to generate a bias potential higher than a low power supply voltage.

  As described above, in a multi-power supply LSI, the power supply voltage of the digital circuit is 1.8V, the power supply voltage of most of the external interface circuits is 3.3V, and the power supply voltage of some analog circuits is 5V. An analog circuit that has a limited period during which the analog circuit is operating has also been put into practical use. In this LSI, it is desirable to activate and operate each circuit having a power supply voltage of 5 V only during the period of use, and to minimize the current consumption of the circuit during the period of nonuse. In this case, it is desirable that the level conversion circuit for converting the level of the signal from 1.8 V to 5 V includes the bias circuit and reduces the current to the minimum at the standby time when the signal does not change.

  Specifically, before using an analog circuit with a power supply voltage of 5 V, the bias circuit of the level conversion circuit is activated to stabilize the bias potential, and then the bias is applied when signal processing in the analog circuit is completed. The circuit current may be minimized. However, since a digital circuit is generally configured by a circuit block that operates at 1.8 V, a signal indicating the transition of the state is a 1.8 V signal. For example, when the MPU as a digital circuit is configured by a circuit block that operates at 1.8 V, and the AD conversion circuit as an analog circuit is a circuit that operates at 5 V, the MCU executes AD at a certain point in time by executing a program. It can be seen that a conversion circuit is used. Therefore, control is required to increase the current of the bias circuit of the level conversion circuit at that time, but since the control signal output from the MPU has a signal level of 1.8V, the control signal of 1.8V It must be possible to control the bias circuit stably.

  When the control signal is 5V as in the bias circuit of Patent Document 4, it is necessary to convert the 1.8V signal to 5V. To that end, the bias circuit of the level conversion circuit must be operating. Therefore, contradiction occurs when the bias circuit is controlled from a circuit operating at 1.8V. Therefore, in the LSI as described above, it has not been possible to obtain a guarantee that stable control can be performed.

  In the bias circuit of Patent Document 4, it is possible to input a control signal of 5V from the outside through a dedicated control terminal at the time of testing or the like, and stop the current of the bias circuit at the time of IDDQ measurement. No circuit configuration for stopping the current of the bias circuit is disclosed. In actual use, the power supply voltage varies with time, so the bias potential of the bias circuit must be able to follow the variation. Further, the bias potential varies depending on the coupling capacitance between the gate and the source of the MOS transistor in the level conversion circuit. Therefore, in an actual use state where the input / output signals of the level conversion circuit change frequently, it is desirable to reduce the impedance by passing a certain amount of current through the bias circuit. Therefore, if the bias circuit cannot be turned on / off by the control signal of 1.8V or the current value cannot be controlled, the maximum current is always supplied to the bias circuit, so that current consumption becomes a problem.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a level conversion circuit that can prevent a decrease in operating speed due to a decrease in power supply voltage and can perform level conversion appropriately. There is to do.

As shown in FIG. 2, the level conversion circuit 45 of the present invention includes first to fourth PMOS transistors PH1, PH2, PH40, PH41, first and second NMOS transistors NH1, NH2, and a bias circuit 46. The input signal IN having the signal level of the reference voltage GND and the first power supply voltage Vdd is converted into the output signal OUT having the signal level of the second power supply voltage Vpp higher than the reference voltage GND and the first power supply voltage Vdd. To do. In the level conversion circuit 45, the drain of the first NMOS transistor NH1 is connected to the drain of the first PMOS transistor PH1 and the gate of the second PMOS transistor PH2. The drain of the second NMOS transistor NH2 is connected to the drain of the second PMOS transistor PH2 and the gate of the first PMOS transistor PH1. Further, the drain of the third PMOS transistor PH40 is connected to the source of the first PMOS transistor PH1, and the drain of the fourth PMOS transistor PH41 is connected to the source of the second PMOS transistor PH2. Input signals are supplied to the gates of the first and second NMOS transistors NH1 and NH2. The bias circuit 46 includes a fifth PMOS transistor and a third NMOS transistor, and the gate of the fifth PMOS transistor is connected to the drain of the fifth PMOS transistor and the drain of the third NMOS transistor. The gate of the third NMOS transistor is supplied with a control signal output from an inverter circuit that operates by being supplied with the first power supply voltage Vdd. A bias potential PB is supplied from the gate of the fifth PMOS transistor to the gates of the third and fourth PMOS transistors PH40, PH41 by the bias circuit 46, and the third and fourth PMOS transistors PH40, PH40, PH are changed when the output signal OUT changes. The current flowing through the PH 41 is controlled to be proportional to the current flowing through the first and second NMOS transistors NH1 and NH2. As described above, since the PMOS transistors PH40 and PH41 for current limitation are provided in series with the cross-coupled PMOS transistors PH1 and PH2, for example, conditions necessary for changing the output signal OUT from the H level to the L level. Can be designed to satisfy That is, the condition that the current of the NMOS transistor NH2 is set larger than the current of the PMOS transistor PH2 can be satisfied without increasing the gate width W of the NMOS transistor NH2 as in the prior art.

Further, in the bias circuit 46 of FIG. 2, a sixth PMOS transistor whose drain is connected to the source of the fifth PMOS transistor, and a fourth NMOS transistor whose drain is connected to the gate of the fifth PMOS transistor. When the third NMOS transistor is off, the fifth PMOS transistor is turned off and the fourth NMOS transistor is turned on . In this case, since the third and fourth PMOS transistors PH40 and PH41 are turned on based on the bias potential PB, it is possible to prevent the output signal OUT from becoming indefinite during standby when the bias current is stopped.

  Since this level conversion circuit has a capacitor for stabilizing the bias potential, an accurate bias potential with little potential fluctuation can be supplied.

  According to the present invention, it is possible to provide a level conversion circuit that can prevent a decrease in operating speed and can appropriately perform level conversion.

It is a principle explanatory view of the present invention. It is a principle explanatory view of the present invention. It is a principle explanatory view of the present invention. FIG. 4 is an operation waveform diagram of the level conversion circuit of FIG. 3. It is a circuit diagram showing a level conversion circuit of a first embodiment. It is a circuit diagram which shows the AD converter circuit of 2nd Embodiment. It is a circuit diagram which shows a level conversion circuit. It is a circuit diagram which shows a switch circuit. It is explanatory drawing of the control timing of an AD converter circuit. It is a circuit diagram which shows the level conversion circuit of 3rd Embodiment. FIG. 11 is an operation waveform diagram of the level conversion circuit of FIG. 10. It is a circuit diagram which shows the level conversion circuit of 4th Embodiment. It is a circuit diagram which shows the level conversion circuit of 5th Embodiment. It is a circuit diagram which shows the level conversion circuit of 6th Embodiment. It is a circuit diagram which shows the level conversion circuit of 7th Embodiment. It is a principle explanatory view of an 8th embodiment. It is a circuit diagram which shows the level conversion circuit of 8th Embodiment. It is a circuit diagram which shows the level conversion circuit of 9th Embodiment. It is a circuit diagram which shows the level conversion circuit of 10th Embodiment. It is a circuit diagram which shows the level conversion circuit of 11th Embodiment. It is a circuit diagram which shows the level conversion circuit of 12th Embodiment. It is a circuit diagram which shows the level conversion circuit of 13th Embodiment. It is a circuit diagram which shows the level conversion circuit of 14th Embodiment. It is a circuit diagram which shows the level conversion circuit of 15th Embodiment. It is a circuit diagram which shows the level conversion circuit of a 1st prior art example. It is a circuit diagram which shows the level conversion circuit of a 2nd prior art example.

(First embodiment)
A first embodiment embodying the present invention will be described below.
FIG. 5 shows the level conversion circuit 10 of the present embodiment. The level conversion circuit 10 is different from the conventional example shown in FIG. 26 in the configuration of the bias circuit 11 for generating the bias potential NB. In FIG. 5, the same components as those of the conventional example of FIG. 26 (the MOS transistors PH1, PH2, NH1, NH2, inverter circuits 3, 4, etc.) are denoted by the same reference numerals.

  This level conversion circuit 10 converts an input signal IN having a signal level of 0V of the reference voltage and 1.8V of the power supply voltage Vdd into an output signal OUT having a signal level of 0V of the reference voltage and 5V of the power supply voltage Vpp. Level conversion. The bias circuit 11 generates a bias potential NB (= Vdd + Vth) that is higher than the power supply voltage Vdd (for example, 1.8 V) of the digital circuit by about the threshold voltage Vth of the high breakdown voltage NMOS transistor, and the bias potential NB is generated. This is supplied to the gates of the NMOS transistors NH1 and NH2.

  The operation of the level conversion circuit 10 when the bias circuit 11 generates a bias potential NB of Vdd + Vth will be described. Here, the threshold voltage Vth is 0.8 V, and the bias potential NB is 2.6 V (= 1.8 V + 0.8 V).

  When the input signal IN is at the H level (1.8V), the output node N10 of the inverter circuit 3 is at the L level (0V) and the bias potential NB is 2.6V, so the NMOS transistor NH1 is turned on. On the other hand, since the output node N11 of the inverter circuit 4 is at the H level (1.8V) and the bias potential NB is 2.6V, only a voltage of 0.8V is applied between the gate and source of the NMOS transistor NH2. Therefore, the NMOS transistor NH2 is turned off because the gate-source voltage is 0.8V and the threshold voltage Vth is 0.8V.

  When the NMOS transistor NH1 is turned on, the node N20 (connection portion between the PMOS transistor PH1 and the NMOS transistor NH1) becomes L level (0 V), and the PMOS transistor PH2 is turned on. When the PMOS transistor PH2 is turned on and the NMOS transistor NH2 is turned off, the output signal OUT becomes H level (5 V). Further, since the PMOS transistor PH2 is on and the NMOS transistor NH2 is off, no steady current flows in this part of the circuit.

  When the input signal IN is at L level, the output node N10 of the inverter circuit 3 is at H level and the output node N11 of the inverter circuit 4 is at L level. The output node N10 of the inverter circuit 3 is at H level (1.8V), the bias potential NB is 2.6V, and only a voltage of 0.8V is applied between the gate and source of the NMOS transistor NH1, so that the NMOS transistor NH1 Turn off. On the other hand, since the output node N11 of the inverter circuit 4 is at L level (0V) and the bias potential NB is 2.6V, the NMOS transistor NH2 is turned on.

  When the NMOS transistor NH2 is turned on, the output signal OUT becomes L level (0 V), and the PMOS transistor PH1 is turned on. When the PMOS transistor PH1 is turned on and the NMOS transistor NH1 is turned off, the node N20 becomes H level (5 V). Since the PMOS transistor PH2 is turned off when the node N20 becomes H level, no steady current flows through this portion of the circuit.

  Since the signal amplitude at each of the nodes N10 and N11 is limited to 0V to 1.8V, the MOS transistors PL1, PL2, NL1 and NL2 having a low withstand voltage have a power voltage vdd (= 1.8V) or higher in the digital portion. No voltage is applied. Further, by setting the bias potential NB generated in the bias circuit 11 to a voltage (2.6 V) that is about the threshold voltage Vth higher than the power supply voltage Vdd, the high-speed operation of the level conversion circuit 10 is achieved.

Next, the configuration of the bias circuit 11 in the present embodiment will be described in detail.
The bias circuit 11 includes high breakdown voltage PMOS transistors PH3 and PH4, high breakdown voltage NMOS transistors NH3 and NH4, a resistor R1, and capacitors C1 and CPOR. In the bias circuit 11, a power supply voltage Vpp (for example, 5V) is supplied to the sources of the high breakdown voltage PMOS transistors PH3 and PH4. The gate of the PMOS transistor PH3 and the gate of the PMOS transistor PH4 are connected to each other, and each gate is connected to the drain of the PMOS transistor PH4. That is, the PMOS transistors PH3 and PH4 form a current mirror circuit.

  The drain of the PMOS transistor PH4 is connected to the drain of the NMOS transistor NH4 through the resistor R1, and is connected to the ground through the capacitor CPOR. The source of the NMOS transistor NH4 is connected to the ground, and the enable control signal EN is supplied to its gate via the inverter circuit 12. This inverter circuit 12 is a CMOS inverter circuit composed of a low breakdown voltage PMOS transistor PL4 and an NMOS transistor NL4. The inverter circuit 12 operates by being supplied with a power supply voltage Vdd of 1.8 V, and outputs a control signal EN obtained by inverting the control signal ENX. To do.

  In the bias circuit 11, a high breakdown voltage NMOS transistor NH3 is connected in series to the high breakdown voltage PMOS transistor PH3, and a power supply voltage Vdd of 1.8 V is supplied to the source of the NMOS transistor NH3. The gate of the NMOS transistor NH3 is connected to the drain of the NMOS transistor NH3. That is, the NMOS transistor NH3 is diode-connected. A capacitor C1 is connected in parallel with the diode-connected NMOS transistor NH3. The bias potential NB generated at the connection portion of the drains of the MOS transistors PH3 and NH3 is supplied to the NMOS transistors NH1 and NH2.

The operation of the bias circuit 11 configured as described above will be described.
When the control signal ENX is at the L level (0 V) and the control signal EN at the H level (1.8 V) obtained by inverting the control signal ENX is supplied to the bias circuit 11, the NMOS transistor NH4 is turned on. At this time, a current flows through the resistor R1, and the current flows through the PMOS transistor PH4. Then, a current also flows through the PMOS transistor PH3 connected to the PMOS transistor PH4 as a current mirror, and the current flows into the power supply side of the low power supply voltage Vdd (digital circuit) via the diode-connected NMOS transistor NH3. As a result, the bias potential NB of the bias circuit 11 is higher than the power supply voltage Vdd by about the threshold voltage Vth of the high breakdown voltage NMOS transistor NH3. The value of the current flowing through the NMOS transistor NH3 is set by the resistor R1. The capacitor C1 functions as a stabilizing capacitor that suppresses fluctuations in the bias potential NB.

  When the control signal EN is at the L level, the NMOS transistor NH4 is turned off, so that no current flows through the resistor R1. Since no current flows through the resistor R1, no current flows through the PMOS transistor PH4 and the PMOS transistor PH3. Since no current flows through the PMOS transistor PH3, almost no current flows through the NMOS transistor NH3. In this case, the value of the bias potential NB is determined by the leak current flowing through the NMOS transistor NH3. The bias potential NB is smaller than the value when the control signal EN is at the H level, but is higher than the power supply voltage Vdd.

  The power supply voltage Vdd may vary with time, and the bias potential NB must be able to follow the variation. Further, since the bias potential NB fluctuates due to the gate-source coupling of the NMOS transistors NH1 and NH2, when the input / output signal of the level conversion circuit 10 changes frequently, a current is passed through the bias circuit 11 to some extent. It is desirable to reduce the impedance of the potential NB.

  By controlling on / off of the NMOS transistor NH4 by the control signal EN, the current flowing through the bias circuit 11 can be changed. That is, the NMOS transistor NH4 is turned on when the input / output signal of the level conversion circuit 10 changes frequently, and the NMOS transistor NH4 is turned off when the input / output signal does not change. This control allows a current to flow through the bias circuit 11 only during a period in which the impedance of the bias potential NB needs to be lowered.

  When the power supply voltage Vdd of the low voltage circuit (digital circuit) part is supplied as the gate potential of the NMOS transistor NH4 as in this embodiment, the on-resistance of the NMOS transistor NH4 is designed to be smaller than the value of the resistor R1. Thus, the bias circuit 11 can be turned on / off based on the control signal EN of the low power supply voltage Vdd.

  Here, when the control signal ENX is at the L level and the control signal EN is at the H level, the equivalent impedance of the bias potential NB is reduced by increasing the current of the bias circuit 11, so that the bias potential NB is equal to the power supply voltage Vdd. Follow the fluctuations of

  The capacitor CPOR functions as a power-on reset circuit that generates a power-on reset signal when the power supply voltage Vpp of 5V rises. That is, the capacitor CPOR is provided to speed up the rising of the bias potential NB when the power is turned on.

  Generally, in order to prevent the output of the level conversion circuit 10 from becoming indefinite, the power-on order is determined in advance. For example, when the power supply voltage Vpp of 5V rises first and the power supply voltage Vdd of 1.8V rises later, when the power supply voltage Vpp is 5V and the power supply voltage Vdd is 0V, the output nodes N10 and N11 Becomes 0V. In this case, since the output of the level conversion circuit 10 is not determined and becomes unstable, a current may flow through the NMOS transistors NH1 and NH2 depending on the value of the bias potential NB, which is not desirable.

  On the contrary, when the power supply voltage Vdd of 1.8V rises first and the power supply voltage Vpp of 5V rises later, the output is indefinite even when the power supply voltage Vpp is 0V and the power supply voltage Vdd is 1.8. (The output is fixed at 0V because the power supply voltage Vpp is 0V). In this case, it is desirable that the internal potential in the level conversion circuit 10 is determined immediately after the power supply voltage Vpp of 5 V rises, and the output is determined.

  Here, when the rising of the bias potential NB in the bias circuit 11 is delayed, the power supply voltage Vpp is 5 V, the power supply voltage Vdd is 1.8 V, and the bias potential NB is in a state where both the power supply voltage Vdd and the power supply voltage Vpp are rising. The potential becomes low (potential less than 2.6) that does not reach the final value. For this reason, even when the signal level of the nodes N10 and N11 is determined with the input of the L level or H level input signal IN, the bias potential NB is low, so that the transistors NH1 and NH2 are not sufficiently turned on. Does not work properly. As a result, the level of the output signal OUT becomes indefinite.

  In the bias circuit 11 of the present embodiment, a capacitor CPOR is provided in order to avoid such an undesirable state. That is, immediately after the 5V power supply voltage Vpp rises, the potential of the node N30 in the bias circuit 11 (the gate potentials of the PMOS transistors PH3 and PH4) is 0V by the capacitor CPOR. As a result, a large current flows through each of the PMOS transistors PH3 and PH4. As a large current flows through the PMOS transistor PH3, the bias potential NB quickly approaches the final value. At this time, the capacitor CPOR is charged, the potential of the node N30 rises, and the current flowing through the PMOS transistors PH3 and PH4 gradually decreases. Finally, since the potential of the node N30 becomes a value lower than the power supply voltage Vpp by about the threshold voltage Vth of the PMOS transistor PH4, only a slight current of about the leakage current flows through the transistor PH3.

  In this way, by providing the capacitor CPOR that functions as a power-on reset circuit, the bias potential NB is rapidly charged to the final design value, so that the output of the level conversion circuit 10 becomes unstable (the output cannot be predicted). The period can be minimized. In this embodiment, a circuit example in which the capacitor CPOR is provided has been described. In particular, even if the capacitor CPOR is not provided, if the rise of the bias potential NB is sufficiently fast due to the parasitic capacitance or the like, the parasitic capacitance is used. It may be configured.

  In the level conversion circuit 10 of the present embodiment, the power supply voltage Vpp is supplied to the sources of the PMOS transistors PH1 and PH2, the drain of the transistor PH1 and the gate of the transistor PH2 are at a common potential, and the drain of the transistor PH2 and the gate of the transistor PH1 are connected. An example of connection with a common potential is shown. In addition to this, as long as it works as a positive feedback circuit, a circuit configuration including other circuit elements in that portion may be used.

As described above, according to the present embodiment, the following effects can be obtained.
(1) In the bias circuit 11, the source of the diode-connected NMOS transistor NH3 is connected to the power supply of the power supply voltage Vdd, and a current is passed through the NMOS transistor NH3, whereby a voltage (2 .6V) bias potential NB is generated. By supplying the bias potential NB to the gates of the NMOS transistors NH1 and NH2, the circuit operation can be speeded up. In addition, the bias circuit 11 is configured by the NMOS transistor NH4 operating as a switch and the resistor R1 for determining the current, and the circuit is devised so that the NMOS transistor NH4 can be turned on / off. In the bias circuit 11, the value of the current flowing through the bias circuit 11 can be changed by controlling the NMOS transistor NH4 on / off by the control signal EN of the low power supply voltage Vdd. Thereby, the control of the impedance of the bias potential NB in the level conversion circuit 10 can be performed from the circuit side of the low power supply voltage Vdd. Specifically, for example, when a CPU is provided as a circuit block with a low power supply voltage Vdd, the CPU outputs a control signal EN by executing a program, and a period during which the impedance of the bias potential NB needs to be lowered ( A current can be passed through the bias circuit 11 only during a period in which the input / output signals of the level conversion circuit 10 change frequently.

  (2) Since the capacitor CPOR that functions as a power-on reset circuit is provided, the bias potential NB is rapidly charged to the final design value, so that the period during which the output of the level conversion circuit 10 is indefinite can be minimized. it can.

  (3) Since the capacitor C1 functioning as a stabilizing capacitor is provided in the bias circuit 11, an accurate bias potential with little potential fluctuation can be supplied to the NMOS transistors NH1 and NH2.

(Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.
FIG. 6 shows an AD conversion circuit 15 using the level conversion circuit 10 of the first embodiment.

  The AD conversion circuit 15 of the present embodiment is a successive approximation AD conversion circuit that converts an analog signal Vin into a 4-bit digital signal, and is used, for example, in a semiconductor integrated circuit device (LSI) for automobiles. In addition to the level conversion circuit 10, the AD conversion circuit 15 includes first and second switch circuits SW1 and SW2, sampling capacitors CS1, CS2, CS3, CS4 and CS5, a comparator 16, a level conversion circuit 17, and a successive approximation control circuit 18. including.

  The sampling capacitors CS1 to CS5 have their capacitance values set by weighting values of 2, and the ratio of the capacitance values is set to 1: 1: 2: 4: 8. That is, the capacitors CS1 and CS2 are composed of one unit capacitor Cx, the capacitor CS3 is composed of two unit capacitors Cx, the capacitor CS4 is composed of four unit capacitors Cx, and the capacitor CS5 is composed of eight unit capacitors Cx. Thus, it is composed of a total of 16 capacity groups.

  One terminal of each of the sampling capacitors CS1 to CS5 is connected to the comparator 16, and the other terminal is connected to the first switch circuit SW1. The first switch circuit SW1 is connected to the second switch circuit SW2. Based on the control signal output from the level conversion circuit 10, each of the switch circuits SW1 and SW2 applies the reference potential (reference potential) Vref, the reference potential Vref, and the level of the ground GND to the sampling capacitors CS1 to CS5, respectively. The level is switched so that one of the level of the analog signal Vin and the level of the ground GND are input.

  The comparator 16 includes high breakdown voltage PMOS transistors PH10, PH11, PH12, high breakdown voltage NMOS transistors NH10, NH11, NH12, NH13, NH14, NH15, and coupling capacitors CC1, CC2. In the comparator 16, a PMOS transistor PH10 and an NMOS transistor NH10 are connected in series to form a first-stage CMOS inverter circuit 19a, and an NMOS transistor NH13 is connected in parallel to the inverter circuit 19a. The PMOS transistor PH11 and the NMOS transistor NH11 are connected in series to form a second-stage CMOS inverter circuit 19b, and the NMOS transistor NH14 is connected in parallel to the inverter circuit 19b. Further, the PMOS transistor PH12 and the NMOS transistor NH12 are connected in series to form a third-stage CMOS inverter circuit 19c, and the NMOS transistor NH15 is connected in parallel to the inverter circuit 19c. The power supply voltage Vpp (= 5V) is supplied to the inverter circuits 19a to 19c at each stage. A sampling control signal SPL is supplied to the gates of the NMOS transistors NH13 to NH15, and on / off of the NMOS transistors NH13 to NH15 is controlled based on the control signal SPL.

  The input of the inverter circuit 19a (the gates of the MOS transistors PH10 and NH10) is connected to the sampling capacitors CS1 to CS5, and the output of the inverter circuit 19a (the drains of the MOS transistors PH10 and NH10) is connected to the inverter via the coupling capacitor CC1. It is connected to the input of the circuit 19b (the gates of the MOS transistors PH11 and NH11). The output of the inverter circuit 19b (the drains of the MOS transistors PH11 and NH11) is connected to the input of the inverter circuit 19c (the gates of the MOS transistors PH12 and NH12) via the coupling capacitor CC2, and is output from the inverter circuit 19c. The signal to be processed is supplied to the level conversion circuit 17.

  The level conversion circuit 17 is a step-down level conversion circuit that converts the signal amplitude from 5V to 1.8V, and supplies the converted signal to the successive approximation control circuit 18. A specific circuit example of the level conversion circuit 17 is shown in FIG. That is, the level conversion circuit 17 includes high breakdown voltage PMOS transistors PH16 and PH17, high breakdown voltage NMOS transistors NH16 to NH19, and low breakdown voltage PMOS transistors PL18 and PL19. Between the 1.8 V power supply and the ground, a PMOS transistor PL18 and an NMOS transistor NH18 are connected in series, and a PMOS transistor PL19 and an NMOS transistor NH19 are connected in series. The gate of the PMOS transistor PL18 is connected to the drain of the PMOS transistor PL19, and the gate of the PMOS transistor PL19 is connected to the drain of the PMOS transistor PL18.

  The input signal IN is inverted and input to the gate of the NMOS transistor NH18 via the inverter circuit 20a including the PMOS transistor PH16 and the NMOS transistor NH16. The output signal of the inverter circuit 20a is inverted and input to the gate of the NMOS transistor NH19 via the inverter circuit 20b including the PMOS transistor PH17 and the NMOS transistor NH17. The input signal IN is a signal having a signal amplitude of 5V, and a power supply voltage Vpp of 5V is supplied to each of the inverter circuits 20a and 20b.

  Accordingly, when the input signal IN is at the H level (5V), the output node of the inverter circuit 20a is at the L level (0V), and the output node of the inverter circuit 20b is at the H level (5V). The L level (0 V) output signal OUT is supplied to the successive approximation control circuit 18. On the other hand, when the input signal IN is at L level (0V), the output node of the inverter circuit 20a is at H level (5V) and the output node of the inverter circuit 20b is at L level (0V). The H level (1.8 V) output signal OUT is supplied to the successive approximation control circuit 18.

  The successive approximation control circuit 18 performs comparison control based on the output signal of the level conversion circuit 17 and supplies the level conversion circuit 10 with a control signal for controlling the comparator 16 and the switch circuits SW1 and SW2. The level conversion circuit 10 converts the 1.8V input signal IN into 5V, and controls the switch circuits SW1 and SW2 based on the converted 5V output signal.

The operation of the AD conversion circuit 15 configured as described above will be described.
Before starting the conversion, the NMOS transistors NH13 to NH15 are turned off by the L level control signal SPL. When the conversion is started, first, the successive approximation control circuit 18 sets the control signal SPL to H level to turn on the NMOS transistors NH13 to NH15 in order to sample the analog signal Vin. When the NMOS transistor NH13 is turned on, the potentials of the output node DACOUT and the node N50 of each capacitor become equal, and when the NMOS transistor NH14 is turned on, the potentials of the node N51 and the node N52 become equal. Further, when the NMOS transistor NH15 is turned on, the potentials of the node N53 and the node N54 become equal. The PMOS transistor PH10 and the NMOS transistor NH10 constitute the first stage of the comparator 16. When the NMOS transistor NH13 is turned on, the potentials of the output node DACOUT and the node N50 are the first stage logic threshold value (in the comparator 16). The threshold value of the inverter circuit 19a) VTL. Similarly, when the NMOS transistors NH14 and NH15 are turned on, the potentials of the nodes N51, N52, N53, and N54 also become the logic threshold value VTL.

  When the control signal SPL is set to the H level and the sampling operation is started, all of the capacitors CS1 to CS5 are connected to the analog input terminals via the switch circuits SW1 and SW2 while the output node DACOUT is kept at the potential VTL. As a result, the analog signal Vin is supplied and the capacitors CS1 to CS5 are charged to the potential of the analog signal Vin.

  After completion of the sampling operation, the comparison operation is started, and digital data is determined in order from the most significant bit (MSB). Specifically, for example, after the NMOS transistor NH15 is turned off by the L level control signal SPL, the capacitors CS1 to CS4 are grounded by controlling the switch circuits SW1 and SW2 for one node of the capacitors CS1 to CS5. Connected to the GND terminal, the capacitor CS5 is connected to the reference potential Vref terminal. At this time, the potential of the output node DACOUT determined by charge redistribution is Vref / 2−Vin + VTL, and the first stage of the comparator 16 determines whether the potential of the analog signal Vin is larger or smaller than ½ of the reference potential Vref. The determination is made by the circuits 19a, 19b, and 19c of the second stage (transistors PH11 and NH11) and the third stage (transistors PH12 and NH12) (transistors PH10 and NH10). Then, the MSB is determined based on the signal level output from the node N54 as the determination result.

  Similarly, by controlling the switch circuits SW1 and SW2, a potential of Vref / 4−Vin + VTL or 3Vref / 4−Vin + VTL is generated, and digital data is sequentially determined from the MSB side. For example, when the capacitors CS1, CS3 to CS5 are connected to the terminal of the ground GND and the capacitor CS2 is connected to the terminal of the reference potential Vref, the potential of the node DACOUT input to the comparator 16 is Vref / 16−Vin + VTL. That is, by connecting the capacitors CS1 to CS5 to the reference potential Vref or the ground GND by the switch circuits SW1 and SW2, the size is 1/16 of 16Cx which is the total capacitance value of the sampling capacitors CS1 to CS5. The potential of the output node DACOUT can be changed in increments of Vref / 16 in units of Cx. Thereby, 4-bit digital data is determined.

FIG. 8 shows a specific circuit example of the switch circuit controlled by the output signal of the level conversion circuit 10.
As shown in FIG. 8, the output signal OUT of the level conversion circuit 10 is supplied to the first input terminal of the NAND circuit NAND1 and to the first input terminal of the NOR circuit NOR1. Further, the control signal COMP for starting the comparison is supplied to the second input terminal of the NAND circuit NAND1, and is inverted through the inverter circuit INV1 and supplied to the second input terminal of the NOR circuit NOR1. The NAND circuit NAND1, the NOR circuit NOR1, and the inverter circuit INV1 are gate circuits that operate by being supplied with a power supply voltage of 5V.

  The output signal of the NAND circuit NAND1 is supplied to the gate of the high breakdown voltage PMOS transistor PH20, and the output signal of the NOR circuit NOR1 is supplied to the gate of the high breakdown voltage NMOS transistor NH20. The drains of the MOS transistors PH20 and NH20 are connected to each other, and the connection is connected to the sampling capacitor CS1. The reference potential Vref is supplied to the source of the PMOS transistor PH20, and the source of the NMOS transistor NH20 is connected to the ground GND. Further, a switch circuit SW3 is connected to a connection portion between each of the MOS transistors PH20 and NH20 and the capacitor CS1, and an analog signal (input voltage) Vin is supplied via the switch circuit SW3.

Here, the operation timing of the AD conversion circuit 15 will be described.
As shown in FIG. 9, at the same time or before the start of sampling, the control signal EN supplied to the level conversion circuit 10 is set to H level, and a current is supplied to the bias circuit 11 of the level conversion circuit 10 to activate it. The bias circuit 11 returns to the operating state at a sufficiently high speed for a sampling period of several hundred ns to several thousand ns because the bias potential NB reaches a steady state in several tens ns with the control signal EN at the H level. When a current flows through the bias circuit 11 and its output impedance is low, the input signal IN of the level conversion circuit 10 changes, and the output signal OUT is also converted in response thereto.

  During the sampling period of the AD conversion circuit 15 (period in which the sampling control signal SPL is at the H level), the L level control signal COMP is supplied, the PMOS transistor PH20 and the NMOS transistor NH20 are turned off, and the switch circuit SW3 is closed. Thus, the sampling capacitor CS1 is charged to the potential of the analog signal Vin.

  Further, during the comparison determination period, an H level control signal COMP is supplied, and one of the MOS transistors PH20 and NH20 is turned on according to the output signal OUT of the level conversion circuit 10, and the sampling capacitor CS1 is set to the potential Vref or Connected to ground.

When the comparison determination is completed, the signal of the AD conversion circuit 15 does not change, so the control signal EN is set to L level, and the current of the bias circuit 11 in the level conversion circuit 10 is stopped.
As described above, the level conversion circuit 10 of the first embodiment can be applied to the successive approximation AD conversion circuit 15. Further, when the level conversion circuit 10 is applied to the resources of the MCU such as the successive approximation AD conversion circuit 15 as in the present embodiment, since the MCU knows in advance the timing of using each resource, Thus, the bias current in the bias circuit 11 can be reduced when the bias circuit 11 is activated and the use of resources is completed.

(Third embodiment)
Hereinafter, a third embodiment of the present invention will be described.
FIG. 10 shows the level conversion circuit 22 of the present embodiment. The level conversion circuit 22 is different from the level conversion circuit 10 according to the first embodiment in that the circuit configuration of the bias circuit 23 is changed and an inverter circuit 24 including a low breakdown voltage PMOS transistor PL3 and an NMOS transistor NL3 is added. Is different. In FIG. 10, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is partially omitted. Hereinafter, the differences will be mainly described.

  The potential of the output node N10 of the inverter circuit 3 changes from the H level to the L level as the current flows through the NMOS transistors NH1 and NL1 exceeding the driving current of the PMOS transistor PH1 and is discharged. The fall of the output node N10 is delayed. Further, since the level conversion circuit 10 has a configuration in which the potential of the output node N10 of the inverter circuit 3 is inverted by the inverter circuit 4, the rise of the output node N11 of the inverter circuit 4 may be delayed depending on the circuit setting. On the other hand, in the level conversion circuit 22 of the present embodiment, the potential of the output node N11 of the inverter circuit 4 is not provided to be generated by inverting the logic level of the output node N10 of the inverter circuit 3, but provided separately. In this configuration, the logic level of the output node of the inverter circuit 24 is inverted. With this configuration, more reliable circuit design is possible.

Next, the configuration of the bias circuit 23 in the present embodiment will be described.
The bias circuit 23 includes high breakdown voltage PMOS transistors PH3 and PH4, high breakdown voltage NMOS transistors NH3, NH4 and NH5, resistors R1 and R3, and a capacitor CPOR. In the bias circuit 23, the connection configuration of the high breakdown voltage PMOS transistors PH3 and PH4, the high breakdown voltage NMOS transistors NH3 and NH4, the resistor R1, and the capacitor CPOR is the same as that of the bias circuit 11 in the first embodiment. Here, the description is omitted.

  In the bias circuit 23 of the present embodiment, unlike the first embodiment, the drain of the PMOS transistor PH4 (the connection node N30 of the gates of the PMOS transistors PH3 and PH4) is connected via the resistor R3 and the NMOS transistor NH5. Connected to ground. A control signal PDX obtained by inverting the control signal PD via an inverter circuit (CMOS inverter circuit composed of a PMOS transistor PL5 and an NMOS transistor NL5) 25 is supplied to the gate of the NMOS transistor NH5. Normally, the control signal PD is controlled to L level and the control signal PDX is controlled to H level.

  In the bias circuit 11, when the supplied control signal EN is at the L level, the NMOS transistor NH4 is turned off. Therefore, the current in the inversion region does not flow through the PMOS transistor PH3, and the leakage flows through the MOS transistors PH3 and NH3. The bias potential NB is determined by the current.

  Here, for example, a case is assumed where the level conversion circuit 10 of the first embodiment is manufactured by a P-type substrate and an nwell process. In that case, the drain junction of the PMOS transistor PH3 includes a reverse pn junction between the power supply voltage Vpp and the bias potential NB, and the drain junction of the NMOS transistor NH3 has a reverse pn junction between the bias potential NB and the ground GND. Including. Regarding the leak current flowing in the pn junction in the reverse direction, for example, the area of the drain junction of the PMOS transistor PH3 is increased, and the layout is devised so that the leak current from the transistor PH3 increases. Thereby, it is possible to design the bias potential NB to a potential (potential higher than or lower than the threshold voltage Vth of the high breakdown voltage NMOS transistor from the power supply voltage Vdd). In contrast, by using the bias circuit 23 shown in FIG. 10, the bias potential NB can be designed more reliably and easily.

  In the bias circuit 23, for example, the resistance value of the resistor R1 is 400 kilohms, and the resistance value of the resistor R3 is 4000 kilohms. Also, assuming that the power supply voltage Vpp is 5V and the threshold voltage Vth of the PMOS transistor PH4 is 1V, when the control signal EN is at the H level, a current of 4V / 400 kOhm = 10 uA flows through the resistor R1. When the gate width W of the PMOS transistor PH3 and the PMOS transistor PH4 constituting the current mirror circuit is equal, a current of 10 uA also flows in the PMOS transistor PH3 (when the control signal PD is at L level, the current flowing in the resistor R3 is Since it is added, a current of 11 uA flows accurately). When the gate width W of the NMOS transistor NH3 is designed to be 10 times that of the NMOS transistors NH1 and NH2, the leakage current flowing through the NMOS transistors NH1 and NH2 can be designed to be 1 uA.

  Further, when the control signal EN is at the L level and the control signal PD is at the L level, no current flows through the resistor R1, and a current flows only through the resistor R3. In this case, a current of 1 uA flows through the PMOS transistor PH3, and a leakage current flowing through the NMOS transistors NH1 and NH2 can be 0.1 uA.

  In this way, the bias circuit 23 has a resistor R1 for flowing a large current (the above-described 10 uA current) when the level conversion circuit 22 is operating, and a small current (when the output of the level conversion circuit 22 is not changed). The resistor R3 for supplying the above-described 1uA current) is provided. According to this configuration, the current flowing through the bias circuit 23 can be accurately designed even during standby when the output of the level conversion circuit 22 does not change. In the above description, the current value flowing through the resistor R3 has been described as 1 uA. However, the current value can be appropriately changed within a range that does not cause a problem during standby.

  Further, in the level conversion circuit 22, since the current flowing through the resistor R3 is stopped by setting the control signal PD to the H level (the control signal PDX is set to the L level), the standby bias current 1uA becomes a problem. For example, when measuring IDDQ, the control signal PD is set to H level.

  In the bias circuit 23 in the present embodiment, the stabilization capacitor C1 of the bias potential NB is omitted, but a capacitor C1 may be provided as necessary. Further, although the control signals PD and PDX are shown as 1.8V signals, the control signals PD and PDX may be changed to 5V signals when the current is stopped only during the test.

FIG. 11 is a waveform diagram showing the operation of the level conversion circuit 22 of FIG.
Here, the operation when the threshold voltage Vth of the high breakdown voltage NMOS transistor is about 1 V, the power supply voltage Vdd is 1.8 V, and the power supply voltage Vpp is 5 V is shown. Further, in the level conversion circuit 22, since the input signal IN and the output signal OUT are in-phase signals (the signal waveforms are overlapped and are difficult to understand), the signal waveform of the node N20 having the opposite phase to the input signal IN is shown.

  By changing the control signal EN to H level at time 0, a bias current flows through the bias circuit 23, and the bias potential NB increases. When the input signal IN is changed from the H level to the L level in the period from 30 ns to 40 ns, the output signal OUT (the potential of the node N20 in FIG. 11) changes accordingly. Then, by changing the control signal EN to the L level at time 50 ns, the bias potential NB returns to the standby state. At this time, the control signal PDX maintains a signal level (H level) of 1.8V.

  As shown in the figure, by setting the control signal EN to the H level, the bias potential NB increases to the value at the time of operation, and by setting the control signal EN to the L level, the bias potential NB slowly decreases. The threshold voltage Vth of the high breakdown voltage NMOS transistor is about 1 V, but the bias potential NB is about 3.5 V due to the substrate bias effect.

As described above, according to the present embodiment, the following effects can be obtained.
(1) Two resistors for determining the bias current in the bias circuit 23 are prepared, and the current values of the respective resistors R1 and R3 are designed to be appropriate current values required during standby and during operation. The bias current can be designed more easily. Also, the equivalent impedance of the bias potential NB can be lowered by increasing the current flowing through the bias circuit 23 only when necessary. The level conversion function itself is not adversely affected by this bias current control.

  (2) In the level conversion circuit 22, the potential of the output node N11 of the inverter circuit 4 is generated by inverting the output of the inverter circuit 24 provided separately from the inverter circuit 3, so that the circuit operation speed can be increased. Can do.

(Fourth embodiment)
Hereinafter, a fourth embodiment of the present invention will be described.
FIG. 12 shows the level conversion circuit 27 of the present embodiment. This level conversion circuit 27 is different from the level conversion circuit 22 in the third embodiment in that the PMOS transistors PL1 and PL2 of the inverter circuits 3 and 4 that receive the input signal IN are omitted. In FIG. 12, the same components as those of the third embodiment are denoted by the same reference numerals, and the description thereof is omitted. Hereinafter, the differences will be mainly described.

  That is, in the level conversion circuit 22 shown in FIG. 10, when the nodes N10 and N11 are at the H level, the PMOS transistors PL1 and PL2 are turned on to reach the level of the power supply voltage Vdd. Therefore, the level conversion circuit 22 can design the H level of the nodes N10 and N11 directly to the power supply voltage Vdd by providing the PMOS transistors PL1 and PL2. Further, when the input signal IN changes, either one of the nodes N10 and N11 is charged to the power supply voltage Vdd by the PMOS transistors PL1 and PL2, so that there is an advantage that the timing at which the NMOS transistors NH1 and NH2 are turned off is earlier. is there.

  In contrast, the level conversion circuit 27 of the present embodiment has a circuit configuration that does not use the PMOS transistors PL1 and PL2. Even without these PMOS transistors PL1 and PL2, the bias potential NB generated in the bias circuit 23 is Vdd + Vth, so that the drain potentials of the NMOS transistors NH1 and NH2 can be designed to be approximately Vdd. In the bias circuit 23 of FIG. 12, the capacitor CPOR is omitted, but a capacitor CPOR may be provided if necessary.

  The level conversion circuit 27 of the present embodiment operates in the same manner as the level conversion circuit 22 in the third embodiment. Further, the level conversion circuit 27 has an advantage that an unintended current does not flow when the bias potential NB is in a transient potential or in an unintended state (intermediate potential) and the power supply voltage Vpp is 0V. For example, when the bias potential NB is generated from a power supply voltage different from the power supply voltages Vdd and Vpp, the circuit configuration of the level conversion circuit 27 is essential. In other words, it is assumed that a bias voltage NB is generated from a power supply voltage of 3.3 V and a level conversion from 1.8 V to 5 V is performed in an LSI in which circuits of power supply voltages of 1.8 V, 5 V, and 3.3 V are mixed. . Further, when the power supply voltage Vpp of 5V is 0V, the power supply voltage Vdd is 1.8V, and the bias potential NB is Vdd + Vth, as shown in FIG. When IN is at the L level, the potential of the node N10 is 1.8V. When the power supply voltage Vpp becomes 0V, the potential of the back gate of the PMOS transistor PH1 also becomes 0V. Since the bias potential NB supplied as the gate potential of the NMOS transistor NH1 is Vdd + Vth, the NMOS transistor NH1 is turned on. At this time, a current flows through the path of the PMOS transistor PL1 and the NMOS transistor NH1 to the back gate of the PMOS transistor PH1.

  On the other hand, level conversion circuit 27 of the present embodiment has a circuit configuration that does not use PMOS transistors PL1 and PL2. Therefore, even when power supply voltage Vpp is 0 V and bias potential NB is Vdd + Vth, current is supplied from power supply voltage Vdd. Therefore, an unintended current (undesired current) flowing through the back gate of the PMOS transistor PH1 can be avoided.

  Thus, in the level conversion circuit 27 of the present embodiment, the power supply voltage Vpp and the power supply voltage Vdd can be easily separated regardless of the bias potential NB. That is, when the bias potential NB is generated from a power supply voltage other than the power supply voltage Vpp, the circuit configuration in which the PMOS transistors PL1 and PL2 are omitted as in the level conversion circuit 27 can reliably separate the power supplies. .

(Fifth embodiment)
The fifth embodiment of the present invention will be described below.
FIG. 13 shows the level conversion circuit 28 of the present embodiment. This level conversion circuit 28 is different from the first embodiment in that a plurality of stages of conversion units 29a, 29b,... Each including MOS transistors PH1, PH2, PL1, PL2, NH1, NH2, NL1, NL2 are provided. This is different from the level conversion circuit 10. In FIG. 12, the same components as those in the first embodiment are denoted by the same reference numerals.

  In the level conversion circuit 28, the connection configuration of the MOS transistors PH1, PH2, PL1, PL2, NH1, NH2, NL1, and NL2 constituting the conversion units 29a and 29b is the same as that in the first embodiment. In this level conversion circuit 28, 1.8V input signals IN1, IN2,... Are respectively supplied to the conversion units 29a, 29b,... At each stage, and a 5V output signal corresponding to these input signals. OUT1, OUT2,... Are output. Further, the bias potential NB generated in the bias circuit 11 is supplied to the NMOS transistors NH1 and NH2 in the conversion units 29a and 29b in the respective stages. In the bias circuit 11 of FIG. 13, the capacitors CPOR and C1 are omitted, but the capacitors CPOR and C1 may be provided if necessary.

  As described above, in the level conversion circuit 28 of the present embodiment, the bias circuit 11 is shared by the plurality of conversion units 29a, 29b,. Therefore, by designing the conversion units so that the operation periods are the same, it is possible to easily perform control such as reducing the bias current of the bias circuit 11 during a period in which the output of the level conversion circuit 28 does not change.

(Sixth embodiment)
The sixth embodiment of the present invention will be described below.
FIG. 14 shows the level conversion circuit 30 of the present embodiment. This level conversion circuit 30 is different from the level conversion circuit 27 in the fourth embodiment in the configuration of the bias circuits 31 and 32. In FIG. 14, the same components as those in the fourth embodiment are denoted by the same reference numerals, and the description thereof is omitted. Hereinafter, the differences will be mainly described.

  The bias circuit 23 of the fourth embodiment has a circuit configuration in which the bias current flowing through the NMOS transistor NH3 is determined by the resistor R1, but in this embodiment, the bias current is determined by a more complicated circuit configuration. Yes.

  Specifically, the bias circuit 31 includes a high breakdown voltage PMOS transistor PH3 and a high breakdown voltage NMOS transistor NH3. The PMOS transistor PH3 and the NMOS transistor NH3 are connected in series, and the power supply voltage Vpp of 5V is supplied to the source of the PMOS transistor PH3. The NMOS transistor NH3 is diode-connected, and a power supply voltage Vdd of 1.8V is supplied to its source. The gate of the PMOS transistor PH3 is connected to the bias circuit 32. Also, a bias potential NB is output from the drain connection portion of each of the MOS transistors PH3 and NH3, and the bias potential NB is supplied to the gates of the NMOS transistors NH1 and NH2.

  The bias circuit 32 includes high breakdown voltage PMOS transistors PH23, PH24, PH25, PH26, high breakdown voltage NMOS transistors NH25, NH26, NH27, and resistors R4, R5. The sources of the PMOS transistors PH23 to PH26 are connected to each other, and the power supply voltage Vpp is supplied to the sources. The drain of the PMOS transistor PH23 is connected to the gate of the PMOS transistor PH26 and to the drain of the NMOS transistor NH25 via the resistor R4. The source of the NMOS transistor NH25 is connected to the ground, and a control signal EN of 1.8V is supplied to the gate of the NMOS transistor NH25.

  The gates of the PMOS transistors PH23, PH24, and PH25 are connected to each other and also connected to the gate of the PMOS transistor PH3 of the bias circuit 31. The gates are connected to the drain of the PMOS transistor PH25 and the drain of the NMOS transistor NH27. The drains of the PMOS transistors PH24 and PH26 and the NMOS transistor NH26 are connected to each other, and the drains are connected to the gates of the NMOS transistors NH26 and NH27. The source of the NMOS transistor NH26 is connected to the ground, and the source of the NMOS transistor NH27 is connected to the ground via the resistor R5.

  The control signal EN is inverted by the inverter circuit 33 including the low breakdown voltage PMOS transistor PL22 and the NMOS transistor NL20, and the inverted control signal ENX is supplied to the gate of the low breakdown voltage NMOS transistor NL21. The NMOS transistor NL21 has a drain connected to the gates of the NMOS transistors NH26 and NH27 in the bias circuit 32, and a source connected to the ground.

  In the bias circuit 32, a current mirror loop including PMOS transistors PH24 and PH25, NMOS transistors NH26 and NH27, and a resistor R5 is a circuit part well known as a self-bias circuit. The bias current of the bias circuit 31 is determined by this current mirror loop. In this case, there is an advantage that the resistance value of the resistor R5 can be reduced. For example, when the NMOS transistors NH26 and NH27 are operating in the subthreshold region, the currents flowing through the MOS transistors PH24, PH25, NH26, NH27, and the resistor R5 are the thermal voltages (kT / q, k: Boltzmann constant, T : Absolute temperature, q: Electronic charge) is determined by dividing the voltage by the resistance value of the resistor R5.

  Then, by supplying the bias potential of the self-bias circuit (the potential of the node N30) to the gate of the PMOS transistor PH3 of the bias circuit 31, the current determined by the self-bias circuit can be supplied to the PMOS transistor PH3.

  In the bias circuit 32, the PMOS transistors PH23 and PH26, the NMOS transistor NH25, and the resistor R4 function as a startup circuit. When the control signal EN is at the H level, the NMOS transistor NH25 is turned on. At this time, if no current flows through the PMOS transistors PH24 and PH25, the gate potential of the PMOS transistor PH26 is 0V.

  When the gate potential of the PMOS transistor PH26 becomes 0V, a current starts to flow through the NMOS transistor NH26, and a current flows through the current mirror loop (each MOS transistor PH24, PH25, NH26, NH27, resistor R5) to reach a stable point. When a current flows through the PMOS transistors PH24 and PH25, a current also flows through the PMOS transistor PH23, the gate potential of the PMOS transistor PH26 becomes the power supply voltage Vpp, and the startup circuit is disconnected.

  When the H level control signal EN is supplied to the bias circuit 32, the startup circuit operates, so that the bias circuit 32 starts up, and accordingly, a bias current flows through the NMOS transistor NH3 of the bias circuit 31. On the other hand, when the L level control signal EN is supplied, no current flows through the startup circuit, and the startup circuit does not function. At this time, since the NMOS transistor NL21 is turned on by the H level control signal ENX, the NMOS transistors NH26 and NH27 are turned off, and the current flowing through the bias circuit 32 becomes zero.

  As described above, even when the bias circuit 32 having a complicated circuit configuration is used, the current flowing through the bias circuit 32 can be controlled on / off by the control signal EN of 1.8 V, as in the fourth embodiment. it can.

(Seventh embodiment)
The seventh embodiment of the present invention will be described below.
FIG. 15 shows the level conversion circuit 35 of the present embodiment.

  In the sixth embodiment, the current flowing through the bias circuit 32 is directly turned on / off by the control signal EN. However, in the level conversion circuit 35 according to the present embodiment, the current flowing through the bias circuit 32 is changed. On / off control is performed by another control signal PD, and a circuit portion that amplifies current by the current mirror ratio is controlled on / off by the control signal EN. The bias current flowing in the bias circuit 31 is controlled by the potential generated in the circuit portion. In FIG. 15, the same components as those of the sixth embodiment are denoted by the same reference numerals, and the description thereof is omitted. Hereinafter, the differences will be mainly described.

  In the bias circuit 32, the sources of the PMOS transistors PH26 and PH27 having high breakdown voltage are connected to the source of the PMOS transistor PH25, and the gate of the PMOS transistor PH26 is connected to the connection portion between the gate and drain of the PMOS transistor PH25. The drain of the PMOS transistor PH26 is connected to the ground via a diode-connected NMOS transistor NH28.

  The PMOS transistor PH27 has a gate and a drain connected to each other, and the connection is connected to the drain of the NMOS transistor NH29 and to the gate of the PMOS transistor PH3 in the bias circuit 31. The NMOS transistor NH29 has a source connected to the ground, and a gate connected to a connection portion (drain) between the PMOS transistor PH26 and the NMOS transistor NH28 via the NMOS transistor NL24. The gate of the NMOS transistor NH29 is connected to the ground via the NMOS transistor NL25.

  The control signal EN is supplied to the gate of the NMOS transistor NL24, is inverted through an inverter circuit including the PMOS transistor PL24 and the NMOS transistor NL26, and is supplied to the gate of the NMOS transistor NL25.

  In the level conversion circuit 35 of the present embodiment, the gate potential of the PMOS transistor PH25 generated by the bias circuit 32 is supplied to the gate of the PMOS transistor PH26 that forms a current mirror circuit with the PMOS transistor PH25, and the gate potential is A corresponding current flows through the NMOS transistor NH28. The gate potential of the NMOS transistor NH28 is transmitted to the gate of the NMOS transistor NH29 via the NMOS transistor NL24 turned on by the H level control signal EN. The current flowing through the NMOS transistor NH29 is converted into a voltage (the potential of the node 30) by the PMOS transistor PH27 and supplied to the gate of the PMOS transistor PH3 of the bias circuit 31. Thereby, a bias current is passed through the PMOS transistor PH3 and the NMOS transistor NH3 in the bias circuit 31.

  In this level conversion circuit 35, the current of the bias circuit 32 can be made sufficiently small in practice by appropriately designing the ratio of the MOS transistors PH25, PH26, NH28, NH29, and PH3. The current of the transistor PH3 can be designed to a required size.

  Further, since the level conversion circuit 35 is configured to transmit the gate potential of the NMOS transistor NH28 to the NMOS transistor NH29 through the NMOS transistor NL24, the NMOS transistor NL24 is turned on and the gate potential is changed only when the control signal EN is at the H level. The current flows through the NMOS transistor NH29. Further, when the control signal EN is at the L level, the transmission of the gate potential is interrupted, and the NMOS transistor NL25 is turned on and the gate of the NMOS transistor NH29 is connected to the ground, so that a current flows through the NMOS transistor NH29. Not flowing. With this configuration, the bias current of the bias circuit 31 can be controlled by the control signal EN having a signal amplitude of 1.8V.

  Note that a PMOS transistor that allows a current to flow when the control signal EN is at the L level may be provided in parallel with the PMOS transistor PH3 in the bias circuit 31. The gate potential of the PMOS transistor can be the gate potential of the PMOS transistor PH25.

(Eighth embodiment)
The eighth embodiment of the present invention will be described below.
FIG. 16 is an explanatory diagram of the principle of the present embodiment. The level conversion circuit 40 of the present embodiment performs on / off control of the bias current at the normal time in the bias circuit 41 with the control signal EN of the low power supply voltage Vdd (1.8 V). Further, on / off control of the bias current during standby is performed with a control signal PDH of a high power supply voltage Vpp (5 V).

FIG. 17 is a circuit diagram showing a circuit configuration of the level conversion circuit 40 in the present embodiment.
The level conversion circuit 40 replaces the control signal EN in the level conversion circuit 30 (see FIG. 14) in the sixth embodiment with a 5V control signal PDH. Further, a current to be turned on / off by the control signal EN of 1.8 V is generated in the resistor R1 as in the level conversion circuit 10 (see FIG. 5) in the first embodiment. In FIG. 17, the same components as those in the first and sixth embodiments are denoted with the same reference numerals.

  That is, the level conversion circuit 40 includes high-breakdown-voltage PMOS transistors PH28, PH29, PH30, PH31, PH32, high-breakdown-voltage NMOS transistors NH4, NH30, NH31, and resistors in addition to the circuit elements constituting the bias circuits 31 and 32. R1 is included.

  The control signal PDH of 5V is supplied to the inverter circuit 42 composed of the PMOS transistor PH28 and the NMOS transistor NH30, and the control signal PDHX inverted by the inverter circuit 42 is supplied to the gate of the NMOS transistor NH31. The NMOS transistor NH31 has a drain connected to the gates of the NMOS transistors NH26 and NH27, and a source connected to the ground.

  The 5V control signal PDH is supplied to the gates of the PMOS transistors PH29 and PH30 and the NMOS transistor NH25. In the PMOS transistor PH29, the power supply voltage Vpp is supplied to the source, and the drain is connected to the gate of the PMOS transistor PH26. In the PMOS transistor PH30, the power supply voltage Vpp is supplied to the source, and the drain is connected to the gates of the PMOS transistors PH3, PH23, PH24, and PH25.

  A source voltage Vpp of 5 V is supplied to the sources of the PMOS transistors PH31 and PH32, the gate of the PMOS transistor PH31 and the gate of the PMOS transistor PH32 are connected to each other, and each gate is connected to the drain of the PMOS transistor PH32. .

  The drain of the PMOS transistor PH32 is connected to the drain of the NMOS transistor NH4 via the resistor R1. The NMOS transistor NH4 has a source connected to the ground and a gate supplied with a control signal EN of 1.8V. The drain of the PMOS transistor PH31 is connected to a connection portion (drain) between the PMOS transistor PH3 and the NMOS transistor NH3.

Next, the operation of the level conversion circuit 40 in the present embodiment will be described.
During the operation of the level conversion circuit 40, the H level (1.8V) control signal EN is supplied, and the NMOS transistor NH4 is turned on. At this time, a current flows through the resistor R1, and the current flows through the PMOS transistor PH32. Then, a current also flows through the PMOS transistor PH31 that is current-mirror connected to the PMOS transistor PH32, and the current flows into the power supply side of the low power supply voltage Vdd via the diode-connected NMOS transistor NH3. As a result, the bias potential NB of the bias circuit 41 is higher than the power supply voltage Vdd by about the threshold voltage Vth of the high breakdown voltage NMOS transistor NH3.

  On the other hand, during standby, the control signal EN of L level (0V) is supplied and the NMOS transistor NH4 is turned off, so that the current flowing through the PMOS transistor PH31 is stopped. In this standby mode, the current flowing through the PMOS transistor PH3 is on / off controlled by the control signal PDH.

  Specifically, when the control signal PDH is at the H level (the control signal PDHX is at the L level), the NMOS transistor NH31 and the PMOS transistors PH29 and PH30 are turned off. Further, when the NMOS transistor NH25 is turned on, a current flows through a self-bias circuit composed of the PMOS transistors PH24 and PH25, the NMOS transistors NH26 and NH27, and the resistor R5, and the current determined by the self-bias circuit enters the PMOS transistor PH3. Flowing.

  On the other hand, when the control signal PDH is at L level (the control signal PDHX is at H level), the NMOS transistor NH31 is turned on and the NMOS transistors NH26 and NH27 are turned off. At this time, the PMOS transistors PH29 and PH30 are turned on, and the PMOS transistors PH23 to PH26 are turned off. As a result, the current flowing through the self-bias circuit is stopped, and the current of the PMOS transistor PH3 is also stopped.

In the present embodiment, on / off control of the bias current during standby may be changed from the 5V control signal PDX to the 1.8V control signal.
In this way, only when the input / output signal of the level conversion circuit 40 changes frequently, control such as lowering the impedance of the bias potential NB can be executed from the circuit (digital circuit) side of the low power supply voltage Vdd. Become. For example, in a semiconductor integrated circuit device provided with a CPU as a circuit that operates with the power supply voltage Vdd, the current of the bias circuit 41 can be controlled by the CPU executing a program. Further, when the circuit is not used completely, such as when measuring IDDQ during a test, the bias current during standby can be stopped by the control signal PDH.

(Ninth embodiment)
The ninth embodiment that embodies the present invention will be described below.
FIG. 18 shows the level conversion circuit 43 of the present embodiment. In the level conversion circuit 10 of the first embodiment, the power-on reset function is realized by the capacitor CPOR connected to the node N30. However, in the level conversion circuit 43 of the present embodiment, power is used to realize the function. An on-reset circuit 44 is separately provided. In FIG. 18, the same components as those in the first embodiment are denoted by the same reference numerals, and a description thereof is partially omitted. Hereinafter, the differences will be mainly described.

  That is, the power-on reset circuit 44 includes a PMOS transistor PH33, a resistor RPOR, and a capacitor CPOR. In the power-on reset circuit 44, the resistor RPOR and the capacitor CPOR are connected, and the gate of the PMOS transistor PH33 is connected to the connection portion. The source of the PMOS transistor PH33 is supplied with a power supply voltage Vpp of 5V, and the drain of the PMOS transistor PH33 is connected to a connection portion (drain) between the PMOS transistor PH3 and the NMOS transistor NH3.

  When the power supply voltage Vpp rises, the gate voltage of the PMOS transistor PH3 is 0 V due to the capacitor CPOR. As a result, the PMOS transistor PH3 is turned on, a current flows through the NMOS transistor NH3, and the bias potential NB is charged regardless of the gate potential of the PMOS transistor PH3 (the potential of the node 30). The gate of the PMOS transistor PH33 is charged by the time constant determined by the capacitor CPOR and the resistor RPOR, and finally the PMOS transistor PH33 is turned off.

  Here, as a procedure for starting up the power supply voltages Vpp and Vdd, the power supply voltage Vdd rises and then the power supply voltage Vpp rises (see FIG. 4). By charging the bias potential NB by the power-on reset circuit 44 when the power supply voltage Vpp rises, the period during which the output of the level conversion circuit 43 is indefinite can be minimized. The power-on procedure in FIG. 4 is a procedure for minimizing the period in which the output of the level conversion circuit 43 is indefinite. If this is not necessary (a measure is taken on the circuit receiving the output of the level conversion circuit 43). The power-up procedure may be changed as appropriate.

(Tenth embodiment)
The tenth embodiment embodying the present invention will be described below.
FIG. 19 shows a level conversion circuit 45 in the present embodiment.

  This level conversion circuit 45 is different from the conventional example shown in FIG. 25 in that it includes high breakdown voltage PMOS transistors PH40 and PH41 for current limitation and a bias circuit 46 for supplying a bias potential PB to each of the transistors PH40 and PH41. To do. In FIG. 19, the same reference numerals are assigned to configurations similar to those of the conventional example of FIG. 25 (each MOS transistor PH1, PH2, NH1, NH2, inverter circuits 3, 4, etc.).

  As described in the description of the level conversion circuit 1 in FIG. 25, in order to change the output signal OUT from the H level to the L level, it is necessary to make the current of the NMOS transistor NH2 larger than the current of the PMOS transistor PH2. Become. The gate-source of the PMOS transistor PH2 is 5V (power supply voltage Vpp), whereas the gate-source of the NMOS transistor NH2 is only 1.8V (power supply voltage Vdd). In order to make the current of the NMOS transistor NH2 larger than the current of the PMOS transistor PH2, the gate width W of the NMOS transistor NH2 must be designed larger (relative to the gate width of the transistor PH2), and the size of the NMOS transistor NH2 Will become bigger. Further, when the voltage value of the power supply voltage Vdd decreases to near the threshold voltage Vth of the NMOS transistors NH1 and NH2, the delay time becomes extremely large. This is because even if the gate width W of the NMOS transistors NH1 and NH2 is increased, the current difference between the PMOS transistor PH2 and the NMOS transistor NH2 contributing to the discharge of the output terminal of the output signal OUT is reduced.

  In order to solve this problem, in the level conversion circuit 45 of the present embodiment, PMOS transistors PH40 and PH41 for current limitation are provided in series with the cross-coupled high breakdown voltage PMOS transistors PH1 and PH2. A bias potential PB generated by the bias circuit 46 is supplied to the gates of the PMOS transistors PH40 and PH41 to control the current flowing through the PMOS transistors PH40 and PH41, that is, the PMOS transistors PH1 and PH2. The value of the current flowing through each PMOS transistor PH40, PH41, PH1, PH2 is set to be proportional to the current flowing when the power supply voltage Vdd is applied to the gates of the high breakdown voltage NMOS transistors NH1, NH2.

  Specifically, the bias circuit 46 includes a high voltage PMOS transistor PH42, an NMOS transistor NH40, and a capacitor C2. The source of the PMOS transistor PH42 is supplied with the power supply voltage Vpp, and the gate of the PMOS transistor PH42 is connected to the drains of the MOS transistors PH42 and NH40 and is connected to the power supply of the power supply voltage Vpp through the capacitor C2. . The capacitor C2 functions as a stabilization capacitor for the bias potential PB output from the bias circuit 46 (the gate of the PMOS transistor PH42).

  The source of the NMOS transistor NH40 is connected to the ground, and the control signal EN output from the inverter circuit 12 is supplied to the gate of the NMOS transistor NH40. The gate of the PMOS transistor PH42 is connected to the gates of the current limiting PMOS transistors PH40 and PH41.

  With such a circuit configuration, the value of the current flowing through each of the PMOS transistors PH40, PH41, PH1, and PH2 is proportional to the current that flows when the power supply voltage Vdd is applied to the gates of the high breakdown voltage NMOS transistors NH1 and NH2. That is, when the power supply voltage Vdd decreases and the currents of the NMOS transistors NH1 and NH2 decrease, the current flowing through the NMOS transistor NH40 of the bias circuit 46 also decreases. Since the current flowing through the NMOS transistor NH40 decreases, the current flowing through the PMOS transistor PH42 decreases. Therefore, the current flowing through the PMOS transistors PH40, PH41, PH1, and PH2 can have characteristics proportional to the currents of the NMOS transistors NH1 and NH2. With such circuit characteristics, even if the power supply voltage Vdd decreases, the current of the NMOS transistor NH2 can always be larger than the current of the PMOS transistor PH2.

  Further, when the control signal EN is set to the L level, the NMOS transistor NH40 is turned off and the current flowing through the bias circuit 46 can be stopped. At this time, since the PMOS transistors PH40 and PH41 are also turned off, the signal level of the output signal OUT may become unstable. Therefore, by providing a logic function with the control signal on the circuit side that receives the output signal OUT of the level conversion circuit 45, it is devised so that the output signal OUT is indefinite or no through current flows through the circuit even at an intermediate potential.

  In the present embodiment, the current limiting PMOS transistors PH40 and PH41 are inserted on the source side of the PMOS transistors PH1 and PH2. However, the current limiting PMOS transistors PH40 and PH41 are provided on the drain side of the PMOS transistors PH1 and PH2. You may comprise.

(Eleventh embodiment)
Hereinafter, an eleventh embodiment embodying the present invention will be described.
FIG. 20 shows the level conversion circuit 48 of the present embodiment. The level conversion circuit 48 is different from the level conversion circuit 45 in the tenth embodiment in the configuration of a bias circuit 49 and a circuit (a circuit including the level conversion circuit 50) that controls the bias circuit 49. In FIG. 20, the same components as those in the tenth embodiment are denoted by the same reference numerals, and description thereof is partially omitted. Hereinafter, the differences will be mainly described.

  In the tenth embodiment, when the NMOS transistor NH40 is turned off, the current flowing through the bias circuit 46 can be stopped, but at the same time, the PMOS transistors PH40 and PH41 are turned off and the output has a high impedance (output signal OUT). May be undefined). Therefore, the level conversion circuit 48 of the present embodiment is devised so that the output does not become high impedance even when the current of the bias circuit 49 is stopped.

  Specifically, the bias circuit 49 includes a PMOS transistor PH43 and an NMOS transistor NH41 in addition to the PMOS transistor PH42, the NMOS transistor NH40, and the capacitor C2 that constitute the bias circuit 46. The source of the PMOS transistor PH43 is supplied with a power supply voltage Vpp of 5V, and the drain of the PMOS transistor PH43 is connected to the source of the PMOS transistor PH42. The drain of the NMOS transistor NH41 is connected to the gate of the PMOS transistor PH42, and the source of the NMOS transistor NH41 is connected to the ground. The output signal (5V control signal) ENXH of the level conversion circuit 50 is supplied to the gates of the PMOS transistor PH43 and the NMOS transistor NH41. The level conversion circuit 50 includes PMOS transistors PH44 and PH45, NMOS transistors NH42 and NH43, and inverter circuits 51 and 52.

  When the control signal EN is at the H level (1.8V), the output node N12 of the inverter circuit 51 including the PMOS transistor PL40 and the NMOS transistor NL40 is at the L level (0V), and the inverter circuit including the PMOS transistor PL41 and the NMOS transistor NL41. The output node N13 of 52 becomes H level (1.8V). At this time, since the NMOS transistor NH43 and the PMOS transistor PH44 are turned on and the NMOS transistor NH42 and the PMOS transistor PH45 are turned off, the level conversion circuit 50 outputs the control signal ENXH of L level (0V).

  Since the control signal ENXH is at the L level, the NMOS transistor NH41 is turned off and the PMOS transistor PH43 is turned on. Therefore, when the control signal ENXH is at the L level, the operation is the same as that of the bias circuit 46 of FIG. In this case, since the node N13 is at the H level, a current flows through the NMOS transistor NH40, and the current flows when the power supply voltage Vdd is applied to the gates of the high breakdown voltage NMOS transistors NH1 and NH2 as in the bias circuit 46. It can be designed to be proportional to the current. Similarly, the currents flowing through the PMOS transistors PH40, PH41, PH1, and PH2 can be designed to be proportional to the currents of the NMOS transistors NH1 and NH2.

  On the other hand, when the control signal EN is at L level (0V), the output node N12 of the inverter circuit 51 is at H level (1.8V), and the output node N13 of the inverter circuit 52 is at L level (0V). At this time, since the NMOS transistor NH42 and the PMOS transistor PH45 are turned on and the NMOS transistor NH43 and the PMOS transistor PH44 are turned off, the level conversion circuit 50 outputs the control signal ENXH of H level (5V).

  Since the control signal ENXH is at the H level, the NMOS transistor NH41 is turned on and the PMOS transistor PH43 is turned off. When the PMOS transistor PH43 is turned off, no steady current flows through the bias circuit 49. At this time, when the NMOS transistor NH41 is turned on, the bias potential PB becomes 0 V of the ground potential, and the current limiting PMOS transistors PH40 and PH41 are turned on. When the bias potential PB supplied to the gates of the PMOS transistors PH40 and PH41 is 0 V, the current flowing through the PMOS transistors PH40 and PH41 does not become proportional to the current of the NMOS transistors NH1 and NH2 when the signal changes. If IN and output signal OUT do not change, the previous state can be maintained. Therefore, the current flowing through the bias circuit 49 can be stopped during standby when the input / output signal of the level conversion circuit 48 does not change.

  In this embodiment, the level conversion circuit 50 having the same configuration as that of the conventional example of FIG. 25 is used to generate the 5V control signal ENXH from the 1.8V control signal EN. When the power supply voltage Vdd decreases, the delay time of the control signal ENXH obtained by level conversion of the control signal EN increases. However, since the control signal is a control signal, there is no problem in circuit operation even if the delay time is somewhat increased. In such a case, in the level conversion circuit 50, the on-resistances of the PMOS transistors PH44 and PH45 are increased as much as possible to save the area, and the gate width W of the NMOS transistors NH42 and NH43 is increased to increase the operating voltage. What is necessary is just to design so that the lower limit of may be lowered as much as possible.

  By configuring the level conversion circuit 48 in this way, the current value flowing through the PMOS transistors PH40, PH41, PH1, and PH2 is changed to the current flowing when the power supply voltage Vdd is applied to the gates of the high breakdown voltage NMOS transistors NH1 and NH2. It is possible to stop the current of the bias circuit 49 that flows during standby while controlling to be proportional.

(Twelfth embodiment)
The twelfth embodiment embodying the present invention will be described below.
FIG. 21 shows the level conversion circuit 55 of the present embodiment. The level conversion circuit 55 has a circuit configuration in which the level conversion circuit 10 of the first embodiment (see FIG. 5) and the level conversion circuit 45 of the tenth embodiment (see FIG. 19) are combined. . In the level conversion circuit 55, the method of generating the bias potential PB in the bias circuit 46 is different by combining them. In FIG. 21, the same components as those in the first and tenth embodiments are denoted by the same reference numerals, and a description thereof is partially omitted. Hereinafter, differences will be mainly described.

  That is, in the level conversion circuit 55, the bias potential NB generated by the bias circuit 11 is supplied to the gate of the NMOS transistor NH40 of the bias circuit 46, and the source of the NMOS transistor NH40 is composed of the PMOS transistor PL42 and the NMOS transistor NL42. It is connected to the output node N40 of the inverter circuit 57. The inverter circuit 57 receives the control signal EN output from the inverter circuit 12, and the potential of the output node N40 becomes a level obtained by inverting the logic level of the control signal EN.

  In the level conversion circuit 45 of FIG. 19, the current flowing through the high breakdown voltage NMOS transistors NH1 and NH2 at the time of signal change is the current value flowing when the power supply voltage Vdd is applied to the gate. Therefore, in the level conversion circuit 45, the value of the current flowing through the PMOS transistors PH40, PH41, PH1, and PH2 is controlled to be proportional to the current flowing when the power supply voltage Vdd is applied to the gates of the NMOS transistors NH1 and NH2. It was.

  On the other hand, in the level conversion circuit 55 of the present embodiment shown in FIG. 21, the power supply voltage Vdd + threshold voltage Vth is applied to the gates of the NMOS transistors NH1 and NH2 when the signal changes, Current flows through the NMOS transistors NH1 and NH2. Therefore, it is desirable to control the value of the current flowing through the PMOS transistors PH40, PH41, PH1, and PH2 to be proportional to the current flowing when the power supply voltage Vdd + the threshold voltage Vth is applied to the gates of the NMOS transistors NH1 and NH2. .

  Therefore, in the bias circuit 46, the current flowing through the diode-connected PMOS transistor PH42 that generates the bias potential PB is the current that flows when the power supply voltage Vdd + threshold voltage Vth is applied to the gates of the NMOS transistors NH1 and NH2. The circuit is configured to be proportional.

  Specifically, in the level conversion circuit 45 of FIG. 19, the source of the NMOS transistor NH40 in the bias circuit 46 is the ground GND, and the gate potential of the NMOS transistor NH40 is the power supply voltage Vdd (during the operation of the bias circuit 46). In the level conversion circuit 55 of the present embodiment, the gate potential of the NMOS transistor NH40 is set to the bias potential NB, that is, the power supply voltage Vdd + the threshold voltage Vth. The source of the NMOS transistor NH40 is connected to the ground GND through the NMOS transistor NL42. This functions as a replica circuit of the NMOS transistors NH1 and NH2 and the NMOS transistors NL1 and NL2.

  In this level conversion circuit 55, when the control signal EN of H level is supplied, the potential of the output node N40 of the inverter circuit 57 becomes L level (approximately 0V), and therefore, between the gate and source of the NMOS transistor NH40, A voltage of approximately power supply voltage Vth + threshold voltage Vth is applied. At this time, in the bias circuit 46, the NMOS transistor NH40 is turned on, a current flows through the PMOS transistor PH42, and a bias potential PB is generated. Therefore, the values of the currents flowing through the PMOS transistors PH40, PH41, PH1, and PH2 are NMOS It becomes proportional to the current that flows when the power supply voltage Vdd + threshold voltage Vth is applied to the gates of the transistors NH1 and NH2.

  Thus, according to the present embodiment, as in the first embodiment, the bias potential NB generated in the bias circuit 11 is set to a voltage (2.6 V) that is higher than the power supply voltage Vdd by the threshold voltage Vth. As a result, high-speed circuit operation can be realized. Further, as in the tenth embodiment, even if the power supply voltage Vdd decreases, the current of the NMOS transistor NH2 can always be made larger than the current of the PMOS transistor PH2.

(Thirteenth embodiment)
A thirteenth embodiment embodying the present invention will be described below.
FIG. 22 shows the level conversion circuit 61 of the present embodiment. The level conversion circuit 61 has a circuit configuration in which the level conversion circuit 10 of the first embodiment (see FIG. 5) and the level conversion circuit 48 of the eleventh embodiment (see FIG. 20) are combined. . In FIG. 22, the same components as those in the first and eleventh embodiments are denoted by the same reference numerals.

  As in the eleventh embodiment, the level conversion circuit 61 is configured so that the output signal OUT does not become unstable even when the bias current of the bias circuit 49 is stopped. That is, in the level conversion circuit 61, the MOS transistors PH43 and NH41 of the bias circuit 49 and the level conversion circuit 50 are added to the level conversion circuit 55 in the twelfth embodiment.

  In this level conversion circuit 61, as in the twelfth embodiment, the current value flowing through the PMOS transistors PH40, PH41, PH1, and PH2 is supplied to the gates of the high-breakdown-voltage NMOS transistors NH1 and NH2, and the power supply voltage Vdd + threshold It is possible to stop the current of the bias circuit 49 that flows during standby while controlling to be proportional to the current that flows when the voltage Vth is applied.

(Fourteenth embodiment)
The fourteenth embodiment embodying the present invention will be described below.
As shown in FIG. 23, the present embodiment is different from the thirteenth embodiment in the configuration of a level conversion circuit 62 that generates a 5V control signal ENXH from a 1.8V control signal EN. In FIG. 23, the same components as those in the thirteenth embodiment are denoted by the same reference numerals, and description thereof is partially omitted. Hereinafter, differences will be mainly described.

  In the level conversion circuit 62, the bias potential (= Vdd + Vth) generated in the bias circuit 11 is supplied to the gates of the NMOS transistors NH42 and NH43. The source of the NMOS transistor NH42 is connected to the ground via the low breakdown voltage NMOS transistor NL42, and the source of the NMOS transistor NH43 is connected to the ground via the low breakdown voltage NMOS transistor NL43. The gate of the NMOS transistor NL42 is connected to the output node N12 of the inverter circuit 51, and a potential level obtained by inverting the control signal EN is supplied. Further, the gate of the NMOS transistor NL43 is connected to the output node N13 of the inverter circuit 52, and the same level as the control signal EN is supplied.

  After the current of the bias circuit 49 is stopped, if the power supply voltage Vdd decreases to a voltage value at which the level conversion circuit that generates the control signal ENXH does not operate, the bias circuit 49 cannot be restored by the control signal EN, so the bias current is stopped. become unable.

  As a countermeasure against this, in the level conversion circuit 62 of the present embodiment, the lower limit of the operating voltage is lowered by setting the gate potential of the NMOS transistors NH42 and NH43 to the bias potential (= Vdd + Vth). That is, even when the value of the low power supply voltage Vdd is reduced, the current reduction of the transistors NH42 and NH43 is smaller than that of the level conversion circuit 50 of FIG. For this reason, the level conversion circuit 62 operates to a lower voltage, and it becomes possible to reliably generate the control signal ENXH of 5V from the control signal EN which is a 1.8V signal, and the power supply voltage Vdd which can control the bias circuit 49 The voltage range is widened. In addition, since the voltage range in which the bias circuit 49 can be controlled by the control signal EN (the voltage range of the power supply voltage Vdd that can be restored by the control signal EN after the bias circuit 49 is stopped) is widened, the bias circuit 49 is stopped more frequently. It becomes possible.

  In the eleventh embodiment, in order to lower the lower limit of the operating voltage of the level conversion circuit 50 that outputs the 5V control signal ENXH from the 1.8V control signal EN, the on-resistances of the PMOS transistors PH44 and PH45 are reduced. The method has been described in which the gate width W of the NMOS transistors NH42 and NH43 is designed to be as large as possible while saving the area. In the level conversion circuit 62 of this embodiment, in addition to the design method, the bias potential NB (= Vdd + Vth) is supplied to the NMOS transistors NH42 and NH43, so that the lower limit of the operating voltage can be further lowered.

(Fifteenth embodiment)
The fifteenth embodiment embodying the present invention will be described below.
FIG. 24 shows the level conversion circuit 71 of the present embodiment. The configurations of the MOS transistors PH1, PH2, NH1, and NH2 and the inverter circuits 3 and 4 constituting the level conversion circuit 71 are the same as those in the first embodiment, and the configuration of the bias circuit 72 is different.

  The bias circuit 72 is controlled by a 5V control signal ENXH supplied from the level conversion circuit 62 (see FIG. 23). Specifically, the bias circuit 72 includes a PMOS transistor PH3, an NMOS transistor NH3, a resistor R6, and a capacitor C1. In the bias circuit 72, when the control signal ENXH of L level (0V) is supplied to the gate of the PMOS transistor PH3, the PMOS transistor PH3 is turned on, and a bias current flows through the NMOS transistor NH3 via the resistor R6. On the other hand, when the control signal ENXH at the H level (5 V) is supplied to the gate of the PMOS transistor PH3, the PMOS transistor PH3 is turned off and the bias current is stopped.

  The control signal ENXH of 5V can be generated based on the control signal EN of 1.8V in the level conversion circuit 62 of FIG. Therefore, also in the present embodiment, the same effect as in the first embodiment can be obtained.

In addition, you may implement each said embodiment in the following aspects.
The AD conversion circuit 15 according to the second embodiment uses the level conversion circuit 10 according to the first embodiment, but the level conversion circuit according to another embodiment is used instead of the level conversion circuit 10. May be used. Further, the level conversion circuit in each embodiment may be used in other semiconductor integrated circuit devices other than the AD conversion circuit.

  The power-on reset circuit 44 in the ninth embodiment may be provided in the level conversion circuit of another embodiment. The power-on reset circuit 44 is composed of a PMOS transistor PH31, a resistor RPOR, and a capacitor CPOR. However, the circuit configuration may be changed as appropriate.

The technical ideas that can be grasped from the above embodiments are described below.
(Appendix 1) A level conversion circuit for converting an input signal having a reference voltage and a first voltage as signal levels into a signal level of a second voltage higher than the reference voltage and the first voltage,
Including first and second PMOS transistors, first to fourth NMOS transistors, and a bias circuit for generating a bias potential;
The drain of the first NMOS transistor is connected to the drain of the first PMOS transistor and the gate of the second PMOS transistor, the source is connected to the drain of the third NMOS transistor, and the drain of the second NMOS transistor The drain of the second PMOS transistor and the gate of the first PMOS transistor are connected, the source is connected to the drain of the fourth NMOS transistor, the input signal is supplied to the gate of the third NMOS transistor, and the first The signal obtained by inverting the input signal is supplied to the gate of the NMOS transistor No. 4,
The bias circuit is a circuit that supplies a bias potential higher than a threshold voltage of the first and second NMOS transistors to the gates of the first and second NMOS transistors than the first voltage; A level conversion circuit for controlling a current for generating the bias potential based on a control signal having a signal level of a first voltage.
(Supplementary note 2) A level conversion circuit for converting an input signal having a signal level of a reference voltage and a first voltage into a signal level of a second voltage higher than the reference voltage and the first voltage,
Including first to fourth PMOS transistors, first and second NMOS transistors, and a bias circuit for generating a bias potential;
The drain of the first NMOS transistor is connected to the drain of the first PMOS transistor and the gate of the second PMOS transistor, and the drain of the second NMOS transistor is the drain of the second PMOS transistor and the first PMOS transistor. The drain of the third PMOS transistor is connected to the source of the first PMOS transistor, the drain of the fourth PMOS transistor is connected to the source of the second PMOS transistor,
The bias circuit supplies the bias potential to the gates of the third and fourth PMOS transistors, and a current flowing through the third and fourth PMOS transistors when the output signal changes changes to the first and second NMOS transistors. A level conversion circuit which is controlled so as to be proportional to a flowing current.
(Supplementary note 3) A level conversion circuit for converting an input signal having a reference voltage and a first voltage as signal levels into a signal level of a second voltage higher than the reference voltage and the first voltage,
First to fourth PMOS transistors, first to fourth NMOS transistors, a first bias circuit for generating a first bias potential, and a second bias circuit for generating a second bias potential Including
The drain of the first NMOS transistor is connected to the drain of the first PMOS transistor and the gate of the second PMOS transistor, the source is connected to the drain of the third NMOS transistor, and the drain of the second NMOS transistor The drain of the second PMOS transistor is connected to the gate of the first PMOS transistor, the source is connected to the drain of the fourth NMOS transistor, and the drain of the third PMOS transistor is connected to the source of the first PMOS transistor. The drain of the fourth PMOS transistor is connected to the source of the second PMOS transistor;
The input signal is supplied to the gate of the third NMOS transistor, and the signal obtained by inverting the input signal is supplied to the gate of the fourth NMOS transistor.
The first bias circuit is a circuit for supplying a first bias potential higher than a threshold voltage of the first and second NMOS transistors to the gates of the first and second NMOS transistors than the first voltage. And, based on a control signal having a signal level of the reference voltage and the first voltage, controlling a current for generating the first bias potential,
The second bias circuit supplies the second bias potential to the gates of the third and fourth PMOS transistors, and currents flowing through the third and fourth PMOS transistors when the output signal changes are the first and fourth PMOS transistors. A level conversion circuit, characterized in that the level conversion circuit is controlled so as to be proportional to a current flowing through the second NMOS transistor.
(Supplementary note 4) The level conversion according to Supplementary note 1, wherein the bias circuit includes a resistor for setting a bias current and a MOS transistor for controlling a current flowing through the resistor based on the control signal. circuit.
(Supplementary Note 5) The level conversion circuit according to Supplementary Note 4, wherein the bias circuit includes a plurality of resistors for setting the bias current.
(Appendix 6) A power-on reset circuit that detects a rising edge of the second voltage and supplies a reset signal to the bias circuit, wherein the bias circuit increases a bias current based on the reset signal. The level conversion circuit according to appendix 1.
(Supplementary note 7) The level conversion circuit according to supplementary note 2, wherein the bias circuit includes a MOS transistor for setting the bias potential to the potential level of the reference voltage when the bias current is stopped.
(Additional remark 8) The said bias circuit is provided with the capacity | capacitance for stabilizing the said bias potential, The level conversion circuit in any one of Additional remark 1-7 characterized by the above-mentioned.
(Supplementary note 9) The level conversion circuit according to supplementary note 1, wherein the bias circuit determines a bias current based on a bias potential output from a self-bias circuit composed of a plurality of MOS transistors.
(Supplementary Note 10) The bias circuit includes a pair of PMOS transistors that are connected to the power source of the second voltage to form a current mirror circuit, a drain and a gate are connected to the mirror circuit, and a source is the power source of the first voltage The level conversion circuit according to claim 1, further comprising an NMOS transistor connected to the first and second NMOS transistors.
(Additional remark 11) The said bias circuit is provided with the resistance for setting the bias current which flows into the said current mirror circuit, and the NMOS transistor which controls the electric current which flows into the said resistance based on the said control signal. The level conversion circuit according to 10.
(Supplementary note 12) The level conversion circuit according to supplementary note 1, wherein a plurality of conversion units each including the MOS transistors are provided, and a bias circuit for supplying a bias potential to the conversion units is commonly used.
(Supplementary note 13) A level conversion circuit for level-converting an input signal having a voltage level of a reference voltage and a first voltage into an output signal having a voltage level of the reference voltage and a second voltage higher than the first voltage. ,
Bias circuit for generating a bias potential, cross-coupled first and second PMOS transistors, and first and second NMOS transistors connected in series to each PMOS transistor and supplied with the bias potential at the gate And third and fourth NMOS transistors connected in series to each of the NMOS transistors and supplied with the input signal at the gate,
The bias potential is a potential higher than the first voltage by the threshold voltages of the first and second NMOS transistors, and the bias circuit uses a control signal having the reference voltage and the first voltage as signal levels. A level conversion circuit that controls a current for generating the bias potential based on the level conversion circuit.
(Supplementary note 14) A level conversion circuit for level-converting an input signal having a voltage level of a reference voltage and a first voltage into an output signal having a voltage level of the reference voltage and a second voltage higher than the first voltage. ,
A bias circuit for generating a bias potential, cross-coupled first and second PMOS transistors, and each PMOS transistor connected in series and flowing to each PMOS transistor based on the bias potential supplied to the gate Third and fourth PMOS transistors for limiting current; and first and second N-channel MOS transistors connected in series with the PMOS transistor and supplied with the input signal at a gate;
The bias circuit controls based on the bias potential so that a current flowing through the third and fourth PMOS transistors is proportional to a current flowing through the first and second NMOS transistors when the output signal changes. A characteristic level conversion circuit.
(Supplementary note 15) A semiconductor integrated circuit device including the level conversion circuit according to any one of Supplementary notes 1 to 14 and a control circuit for controlling the level conversion circuit.
(Supplementary note 16) The semiconductor integrated circuit device according to supplementary note 15, wherein AD conversion is performed to convert an analog signal into a digital signal.

10, 22, 27, 28, 30, 35, 40 Level conversion circuit 43, 45, 48, 55, 61, 71 Level conversion circuit 11, 23, 31, 41, 46, 49, 72 Bias circuit 15 Semiconductor integrated circuit device AD conversion circuit 18 as successive approximation control circuit 44 power on reset circuit C1, C2 capacitance IN, IN1, IN2 input signal EN, ENX, PD, PDX control signal NB bias potential NH1 first NMOS transistor NH2 second NMOS transistor NH4, NH41 MOS transistor NL1 Third NMOS transistor NL2 Fourth NMOS transistor OUT, OUT1, OUT2 Output signal PB Bias potential PH1 First PMOS transistor PH2 Second PMOS transistor PH40 Third PMOS transistor Motor PH41 fourth PMOS transistor R1, R3 resistor Vdd supply voltage Vin analog signal Vth the threshold voltage Vpp power supply voltage as the second voltage as the first voltage

Claims (4)

A level conversion circuit for converting an input signal having a reference voltage and a first voltage as signal levels into a signal level of a second voltage higher than the reference voltage and the first voltage,
First to fourth PMOS transistors, first and second NMOS transistors, a bias circuit that generates a bias potential, and an inverter circuit that operates by being supplied with the first voltage and outputs a control signal. ,
The drain of the first NMOS transistor is connected to the drain of the first PMOS transistor and the gate of the second PMOS transistor, and the drain of the second NMOS transistor is the drain of the second PMOS transistor and the first PMOS transistor. is connected to the gate, the drain of the third PMOS transistor is connected to said first source of the PMOS transistor, the drain of the fourth PMOS transistor is connected to a source of said second PMOS transistor, said first The input signals are supplied to the gates of the first and second NMOS transistors,
The bias circuit includes a fifth PMOS transistor and a third NMOS transistor, and a gate of the fifth PMOS transistor is connected to a drain of the fifth PMOS transistor and a drain of the third NMOS transistor, The control signal is supplied to the gate of the third NMOS transistor,
The bias circuit supplies the bias potential from the gate of the fifth PMOS transistor to the gates of the third and fourth PMOS transistors, and a current flowing through the third and fourth PMOS transistors when an output signal changes. A level conversion circuit, wherein the level conversion circuit is controlled so as to be proportional to a current flowing through the first and second NMOS transistors. The bias circuit includes a sixth PMOS transistor having a drain connected to the source of the fifth PMOS transistor, and a fourth NMOS transistor having a drain connected to the gate of the fifth PMOS transistor,
2. The level conversion circuit according to claim 1 , wherein when the third NMOS transistor is off, the fifth PMOS transistor is turned off and the fourth NMOS transistor is turned on .   3. The level conversion circuit according to claim 1, wherein the bias circuit includes a capacitor for stabilizing the bias potential. 4. A level conversion circuit for level-converting an input signal having a voltage level of a reference voltage and a first voltage into an output signal having a voltage level of the reference voltage and a second voltage higher than the first voltage;
A bias circuit that generates a bias potential; an inverter circuit that operates by being supplied with the first voltage and outputs a control signal; first and second PMOS transistors that are cross-coupled; and each PMOS transistor in series The third and fourth PMOS transistors that are connected and limit the current flowing to each PMOS transistor based on the bias potential supplied to the gate, and are connected in series with the PMOS transistor, and the input signal is supplied to the gate First and second N-channel MOS transistors,
The bias circuit includes a fifth PMOS transistor and a third NMOS transistor, and a gate of the fifth PMOS transistor is connected to a drain of the fifth PMOS transistor and a drain of the third NMOS transistor, The control signal is supplied to the gate of the third NMOS transistor,
In the bias circuit, a current flowing through the third and fourth PMOS transistors when the output signal changes is applied to the first and second NMOS transistors based on the bias potential output from the gate of the fifth PMOS transistor. A level conversion circuit which is controlled so as to be proportional to a flowing current.

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