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JP5000105B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP5000105B2
JP5000105B2 JP2005188806A JP2005188806A JP5000105B2 JP 5000105 B2 JP5000105 B2 JP 5000105B2 JP 2005188806 A JP2005188806 A JP 2005188806A JP 2005188806 A JP2005188806 A JP 2005188806A JP 5000105 B2 JP5000105 B2 JP 5000105B2
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Prior art keywords
semiconductor device
insulating substrate
layer
semiconductor chip
solder resist
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JP2005188806A
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JP2007012714A (en
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泰正 糟谷
洋一 木村
嘉聴 稲見
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Rohm Co Ltd
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Rohm Co Ltd
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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Description

この発明は、半導体装置に関する。 The present invention relates to a semiconductor device.

近年、プリント配線板等に半導体装置を実装する技術として、プリント配線板等に半導体装置を直接半田付けする表面実装技術が広く用いられていて、半導体装置やプリント配線板等の小型化、実装密度の向上等が図られている。表面実装技術に用いられる半導体装置としては、ＱＦＰ（Quad Flat Package）、ＢＧＡ（Ball Grid array）、ＬＧＡ（Land grid array）等の半導体装置が採用されているが、なかでも、ＢＧＡ型半導体装置やＬＧＡ型半導体装置によれば、半導体装置の表面に多数の外部端子（ランドや半田バンプ等）を配置することができるため、半導体装置やプリント配線板等のさらなる小型化、実装密度の向上等が可能になる。 In recent years, as a technology for mounting a semiconductor device on a printed wiring board or the like, surface mounting technology for directly soldering the semiconductor device to the printed wiring board or the like has been widely used. The improvement etc. are aimed at. As semiconductor devices used for surface mounting technology, semiconductor devices such as QFP (Quad Flat Package), BGA (Ball Grid Array), and LGA (Land Grid Array) are adopted. Among them, BGA type semiconductor devices and According to the LGA type semiconductor device, since a large number of external terminals (land, solder bumps, etc.) can be arranged on the surface of the semiconductor device, the semiconductor device, the printed wiring board, etc. can be further miniaturized and the mounting density can be improved. It becomes possible.

従来のＢＧＡ型半導体装置について図７を用いて説明する。
図７は、従来の半導体装置の一例を模式的に示す断面図である。
半導体装置８０が備える絶縁性基板９１の両面には、所定のパターンを有する導体層９３が形成されていて、絶縁性基板９１の両面に形成された導体層９３の一部が、絶縁性基板９１に形成されたビアホール９６によって接続されている。絶縁性基板９１の表面（上面）には、導体層９３の一部を露出させて残りの導体層９３及び絶縁性基板９１を覆うように、ソルダーレジスト層９５が形成されていて、その露出した導体層９３の表面には、複数のワイヤボンディングパッド９４が形成されている。 A conventional BGA type semiconductor device will be described with reference to FIG.
FIG. 7 is a cross-sectional view schematically showing an example of a conventional semiconductor device.
Conductive layers 93 having a predetermined pattern are formed on both surfaces of the insulating substrate 91 provided in the semiconductor device 80, and a part of the conductive layers 93 formed on both surfaces of the insulating substrate 91 is formed on the insulating substrate 91. The via holes 96 are connected to each other. A solder resist layer 95 is formed on the surface (upper surface) of the insulating substrate 91 so as to expose a part of the conductor layer 93 so as to cover the remaining conductor layer 93 and the insulating substrate 91. A plurality of wire bonding pads 94 are formed on the surface of the conductor layer 93.

また、絶縁性基板９１の裏面（下面）には、導体層９３の一部を露出させて残りの導体層９３及び絶縁性基板９１を覆うように、ソルダーレジスト層９９が形成されていて、その露出した導体層９３の表面には、複数のランド９７が形成されている。各ランド９７上には、半田バンプ９８が形成されている。半導体チップ８１は、接着材層８８を介して、ソルダーレジスト層９５の中央部分にダイボンディングされている。半導体チップ８１の上面に設けられた電極８６と、ワイヤボンディングパッド９４とがワイヤ８７によって電気的に接続されている。さらに、半導体装置８０には、絶縁性基板９１の表面（上面）全体を覆うように半導体チップ８１を封止する樹脂パッケージ部８９が形成されている。 Also, a solder resist layer 99 is formed on the back surface (lower surface) of the insulating substrate 91 so as to expose a part of the conductor layer 93 and cover the remaining conductor layer 93 and the insulating substrate 91. A plurality of lands 97 are formed on the exposed surface of the conductor layer 93. Solder bumps 98 are formed on each land 97. The semiconductor chip 81 is die-bonded to the central portion of the solder resist layer 95 via the adhesive layer 88. The electrode 86 provided on the upper surface of the semiconductor chip 81 and the wire bonding pad 94 are electrically connected by a wire 87. Further, the semiconductor device 80 is formed with a resin package part 89 for sealing the semiconductor chip 81 so as to cover the entire surface (upper surface) of the insulating substrate 91.

このような半導体装置８０において、絶縁性基板９１、ソルダーレジスト層９５、９９及び接着材層８８は、一般的に、有機系物質を含んでいて吸湿する性質を有するため、半導体装置８０をプリント配線板に実装するために加熱すると、吸湿された水分が加熱膨張する。その結果、接着材層８８とソルダーレジスト層９５との界面、ソルダーレジスト層９５と絶縁性基板９１との界面、絶縁性基板９１とソルダーレジスト層９９との界面等に、剥離が生じたり、膨れが生じたりする場合がある。このような現象は、一般的に、ポップコーン現象と呼ばれている。ポップコーン現象が生じると、半導体チップ８１に位置ズレや傾きが生じてワイヤ８７が断線したり、隣り合う半田バンプ９８が接触して電気的に短絡が発生したりするおそれがある。 In such a semiconductor device 80, the insulating substrate 91, the solder resist layers 95 and 99, and the adhesive layer 88 generally contain an organic substance and have a property of absorbing moisture. When heated for mounting on a board, the moisture absorbed is heated and expanded. As a result, peeling or swelling occurs at the interface between the adhesive layer 88 and the solder resist layer 95, the interface between the solder resist layer 95 and the insulating substrate 91, the interface between the insulating substrate 91 and the solder resist layer 99, or the like. May occur. Such a phenomenon is generally called a popcorn phenomenon. When the popcorn phenomenon occurs, the semiconductor chip 81 may be misaligned or tilted, and the wire 87 may be disconnected, or the adjacent solder bumps 98 may come into contact and an electrical short circuit may occur.

従来の半導体装置としては、例えば、絶縁性基板における半導体チップの直下にビアホールが形成された半導体装置が存在する（例えば、特許文献１〜３参照）。
このような半導体装置について、図８を用いて説明する。なお、図８では、図７に示した構成要素と対応する構成要素には同一の符号を付している。
図８に示す半導体装置８０では、半導体チップ８１の中央部分の下方に、絶縁性基板９１とソルダーレジスト層９５、９９とを連通するビアホール９２が形成されている。このビアホール９２は、貫通孔の内部に樹脂充填材が充填されているものである。図８に示した半導体装置８０によれば、ビアホール９２の側壁に沿って内部の水分を外部へ放出することが可能になる。 As a conventional semiconductor device, for example, there is a semiconductor device in which a via hole is formed immediately below a semiconductor chip in an insulating substrate (see, for example, Patent Documents 1 to 3).
Such a semiconductor device will be described with reference to FIG. In FIG. 8, the same reference numerals are given to the components corresponding to the components shown in FIG.
In the semiconductor device 80 shown in FIG. 8, a via hole 92 that connects the insulating substrate 91 and the solder resist layers 95 and 99 is formed below the central portion of the semiconductor chip 81. The via hole 92 has a through-hole filled with a resin filler. According to the semiconductor device 80 shown in FIG. 8, it becomes possible to release the moisture inside along the side wall of the via hole 92.

特開平１０−４１５１号公報Japanese Patent Laid-Open No. 10-4151 特開平１１−２６０９５４号公報Japanese Patent Application Laid-Open No. 11-260954 特開２０００−２１６２８１号公報JP 2000-216281 A

しかしながら、特許文献１〜３に記載の半導体装置によれば、図８に示したように、半導体チップ８１の中央部分の下方に、ビアホール９２が形成されているため、半導体チップ８１の中央部分の直下に溜まった水分をビアホール９２から放出することができるものの、半導体チップ８１の外周部分の下方に溜まった水分を放出することが困難であり、半導体チップ８１の外周部分の下方には局所的に膨れが生じてしまうおそれがあった。
半導体チップ８１の外周部分の下方に膨れが生じた場合、半導体チップ８１の中央部分の下方に膨れが生じた場合と比較すると、ソルダーレジスト層９５と接着材層８８との界面に剥離が生じ易く、また半導体チップ８１に傾きや位置ズレが生じ易いという問題がある。また、特許文献１〜３に記載の半導体装置によれば、図８に示したように、ビアホール９２は、樹脂充填材等が充填されているため、ビアホール９２から水分を効率よく放出することができないという問題があった。 However, according to the semiconductor devices described in Patent Documents 1 to 3, since the via hole 92 is formed below the central portion of the semiconductor chip 81 as shown in FIG. Although it is possible to release the moisture accumulated immediately below from the via hole 92, it is difficult to release the moisture accumulated below the outer peripheral portion of the semiconductor chip 81, and locally below the outer peripheral portion of the semiconductor chip 81. There was a risk of blistering.
When swelling occurs below the outer peripheral portion of the semiconductor chip 81, the interface between the solder resist layer 95 and the adhesive layer 88 is more likely to peel than when swelling occurs below the central portion of the semiconductor chip 81. In addition, there is a problem that the semiconductor chip 81 is likely to be inclined or misaligned. In addition, according to the semiconductor devices described in Patent Documents 1 to 3, since the via hole 92 is filled with a resin filler or the like as shown in FIG. 8, moisture can be efficiently discharged from the via hole 92. There was a problem that I could not.

本発明は、上述した課題に鑑みてなされたものであり、その目的は、絶縁性基板が吸湿した水分等の加熱膨張によって膨れや剥離が生じることを防止し得る半導体装置を提供することにある。 The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a semiconductor device that can prevent swelling and peeling due to thermal expansion of moisture or the like absorbed by an insulating substrate. .

上述した課題を解決するために、本発明は、以下のようなものを提供する。
請求項１記載の発明は、
半導体チップと、
前記半導体チップの真下に位置するダイボンディング領域を有し、当該ダイボンディング領域に接着材を介して前記半導体チップがダイボンディングされた絶縁性基板と
を備えた半導体装置であって、
前記絶縁性基板は、少なくとも前記ダイボンディング領域の隅に形成された中空の貫通孔と、前記ダイボンディング領域以外の領域にのみ形成された導体層とを有し、
前記貫通孔は、前記接着材を外部に露出させ、前記半導体チップ側の径が小さいテーパ形状を有することを特徴とする半導体装置である。 In order to solve the above-described problems, the present invention provides the following .
請 Motomeko 1 the described invention,
A semiconductor chip;
Before SL has a die bonding region located immediately below the semiconductor chip, the semiconductor chip through the adhesive material to the die bonding region is a semiconductor device including an insulating substrate which is die-bonded,
The insulating substrate has at least a hollow through hole formed at a corner of the die bonding region, and a conductor layer formed only in a region other than the die bonding region ,
The through hole is a semiconductor device characterized in that the adhesive is exposed to the outside and has a tapered shape with a small diameter on the semiconductor chip side .

請求項１の発明によれば、絶縁性基板が、少なくともダイボンディング領域の隅に形成された中空の貫通孔を有し、上記貫通孔が、外部に露出しているため、ダイボンディング領域の隅の近傍に溜まった水分を、上記貫通孔から効率良く放出することができる。従って、絶縁性基板が吸湿した水分等の加熱膨張によって膨れや剥離が生じることを防止することができる。
さらに、請求項１の発明によれば、貫通孔が、半導体チップ側の径が小さいテーパ形状を有していて、半導体チップ側の貫通孔の径が小さくなっている。
従って、例えば、絶縁性基板の表面に接着材によって半導体チップがダイボンディングされる場合、貫通孔に接着材が入り込むことを防止することができ、接着材層の上面に凹凸が生じて該接着材層と半導体チップとの接着強度が低下したり、両者の間に剥離が生じたりすることを防止することができる。
また、例えば、絶縁性基板の表面にソルダーレジスト層が形成される場合、未硬化のソルダーレジスト組成物が貫通孔に入り込むことを防止することができ、ソルダーレジスト層の上面に凹凸が生じてソルダーレジスト層と半導体チップとの接着強度が低下したり、両者の間に剥離が生じたりすることを防止することができる。 According to the invention of claim 1 , since the insulating substrate has hollow through holes formed at least in the corners of the die bonding area, and the through holes are exposed to the outside, the corners of the die bonding area are Moisture accumulated in the vicinity of can be efficiently discharged from the through hole. Therefore, it is possible to prevent the insulating substrate from being swollen or peeled off due to thermal expansion of moisture absorbed by the insulating substrate.
According to the first aspect of the present invention, the through hole has a tapered shape with a small diameter on the semiconductor chip side, and the diameter of the through hole on the semiconductor chip side is small.
Therefore, for example, when a semiconductor chip is die-bonded to the surface of the insulating substrate with an adhesive, it is possible to prevent the adhesive from entering the through hole, and unevenness is generated on the upper surface of the adhesive layer. It is possible to prevent the adhesive strength between the layer and the semiconductor chip from being lowered or peeling between the two.
Further, for example, when a solder resist layer is formed on the surface of the insulating substrate, it is possible to prevent the uncured solder resist composition from entering the through holes, and unevenness is generated on the upper surface of the solder resist layer. It is possible to prevent the adhesive strength between the resist layer and the semiconductor chip from being lowered or peeling between the two.

請求項２記載の発明は、前記貫通孔は、前記ダイボンディング領域の全域に、均等に形成されている請求項１に記載の半導体装置である。 A second aspect of the present invention is the semiconductor device according to the first aspect , wherein the through holes are formed uniformly over the entire area of the die bonding region.

請求項２の発明によれば、貫通孔が、ダイボンディング領域の全域に均等に形成されているため、ダイボンディング領域の全域から効率良く水分を放出することが可能であり、局所的に水分が溜まることを防止することができる。従って、絶縁性基板が吸湿した水分等の加熱膨張によって膨れや剥離が生じることをより確実に防止することができる。 According to the second aspect of the present invention, since the through holes are formed evenly over the entire area of the die bonding area, it is possible to efficiently release moisture from the entire area of the die bonding area, and the moisture is locally absorbed. Accumulation can be prevented. Therefore, it is possible to more reliably prevent the insulating substrate from being swollen or peeled off due to heat expansion of moisture absorbed by the insulating substrate.

請求項３記載の発明は、前記絶縁性基板と前記半導体チップとの間には、フィルム状の前記接着材が設けられている請求項１または２に記載の半導体装置である。 A third aspect of the present invention is the semiconductor device according to the first or second aspect , wherein the film-like adhesive is provided between the insulating substrate and the semiconductor chip.

請求項３の発明によれば、半導体チップが絶縁性基板にダイボンディングされるときに形成される接着材層が、フィルム状の樹脂組成物によって形成されているため、貫通孔への樹脂組成物の入り込みが生じることがない。
従って、絶縁性基板の表面にフィルム状の接着材によって半導体チップがダイボンディングされる場合、接着材が貫通孔に入り込まないので、接着材層の上面に凹凸が生じて該接着材層と半導体チップとの接着強度が低下したり、両者の間に剥離が生じたりすることを防止することができる。
請求項４記載の発明は、前記絶縁性基板は、ガラス繊維を含浸したエポキシ樹脂からなる、請求項１〜３のいずれか一項に記載の半導体装置である。
請求項５記載の発明は、前記絶縁性基板は、ビスマレイミド−トリアジン樹脂（ＢＴ樹脂）、エポキシ樹脂、ポリエステル樹脂、ポリイミド樹脂、もしくはフェノール樹脂、またはこれらの樹脂にガラス繊維等の補強材を含浸したものからなる、請求項１〜４のいずれか一項に記載の半導体装置である。
請求項６記載の発明は、前記導体層が、前記絶縁性基板の前記半導体チップ側の表面の外周部分と、前記絶縁性基板の前記半導体チップと反対側の裏面の外周部分とに所定のパターンを有しており、前記絶縁性基板の表面の外周部分に形成された導体層と、前記絶縁性基板の裏面の外周部分に形成された導体層とが、ビアホールによって接続されている、請求項１〜５のいずれか一項に記載の半導体装置である。
請求項７記載の発明は、前記ビアホールは、前記絶縁性基板に穿設された貫通孔の壁面に金属薄膜が形成され、さらに該貫通孔に充填材が充填されたものである、請求項６に記載の半導体装置である。
請求項８記載の発明は、前記絶縁性基板の表面には、前記絶縁性基板の外周部分に形成された導体層の一部を露出させて、残りの導体層及び前記絶縁性基板を覆う第１のソルダーレジスト層が形成されており、前記第１のソルダーレジスト層から露出した導体層の表面に、Ｎｉ層またはＡｕ層からなる複数のワイヤボンディングパッドが形成されており、前記半導体チップの表面に複数の電極が設けられており、各電極と前記ワイヤボンディングパッドとがワイヤによって電気的に接続されている、請求項６または７に記載の半導体装置である。
請求項９記載の発明は、前記第１のソルダーレジスト層は、フィルム状のソルダーレジスト組成物によって形成されている、請求項８に記載の半導体装置である。
請求項１０記載の発明は、前記半導体チップの下方における前記絶縁性基板及び前記第１のソルダーレジスト層に、前記絶縁性基板及び前記第１のソルダーレジスト層を連通する前記貫通孔が形成されている、請求項８または９に記載の半導体装置である。
請求項１１記載の発明は、前記第１のソルダーレジスト層には、前記接着材の層を介して前記半導体チップがダイボンディングされている、請求項８〜１０のいずれか一項に記載の半導体装置である。
請求項１２記載の発明は、前記絶縁性基板の裏面には、前記導体層の一部を露出させて残りの導体層及び前記絶縁性基板を覆う第２のソルダーレジスト層が形成されている、請求項６〜１１のいずれか一項に記載の半導体装置である。
請求項１３記載の発明は、前記第２のソルダーレジスト層は、フィルム状のソルダーレジスト組成物によって形成されている、請求項１２に記載の半導体装置である。
請求項１４記載の発明は、前記半導体チップの下方における前記絶縁性基板及び前記第２のソルダーレジスト層に、前記絶縁性基板及び前記第２のソルダーレジスト層を連通する前記貫通孔が形成されている、請求項１２または１３に記載の半導体装置である。
請求項１５記載の発明は、前記第２のソルダーレジスト層から露出した導体層の表面に、Ｎｉ層またはＡｕ層からなる複数のランドが形成されている、請求項１２〜１４のいずれか一項に記載の半導体装置である。
請求項１６記載の発明は、前記ランド上には、半田バンプが形成されている、請求項１５に記載の半導体装置である。
請求項１７記載の発明は、前記接着材は、エポキシ樹脂等の樹脂組成物によって形成されている、請求項１〜１６のいずれか一項に記載の半導体装置である。
請求項１８記載の発明は、前記絶縁性基板の前記半導体チップ側の表面全体を覆うように前記半導体チップを封止する樹脂パッケージ部が形成されている、請求項１〜１７のいずれか一項に記載の半導体装置である。
請求項１９記載の発明は、前記樹脂パッケージ部は、エポキシ樹脂等を含有する樹脂組成物からなる、請求項１８に記載の半導体装置である。
請求項２０記載の発明は、前記貫通孔の前記半導体チップ側の径は、１５０μｍ以下である、請求項１〜１９のいずれか一項に記載の半導体装置である。
請求項２１記載の発明は、前記ダイボンディング領域の隅は、前記ダイボンディング領域をマトリックス状に等分区画して得られる複数の領域のうち、当該ダイボンディング領域の隅に位置する４つの領域である、請求項１〜２０のいずれか一項に記載の半導体装置である。
請求項２２記載の発明は、複数の前記貫通孔がマトリックス状に配置されている、請求項１〜２１のいずれか一項に記載の半導体装置である。
請求項２３記載の発明は、径の異なる複数の前記貫通孔が配置されている、請求項１〜２２のいずれか一項に記載の半導体装置である。
請求項２４記載の発明は、前記貫通孔の平面視形状が円形である、請求項１〜２３のいずれか一項に記載の半導体装置である。
請求項２５記載の発明は、前記絶縁性基板は、複数の板状体が積層されたものである、請求項１〜２４のいずれか一項に記載の半導体装置である。
請求項２６記載の発明は、パッケージ方式がＢＧＡ（Ball Grid array）またはＬＧＡ（Land grid array）である、請求項１〜２５のいずれか一項に記載の半導体装置である。 According to the invention of claim 3 , since the adhesive layer formed when the semiconductor chip is die-bonded to the insulating substrate is formed of the film-like resin composition, the resin composition to the through hole No intrusion occurs.
Therefore, when the semiconductor chip is die-bonded to the surface of the insulating substrate with a film-like adhesive, the adhesive does not enter the through-hole, so that the upper surface of the adhesive layer is uneven and the adhesive layer and the semiconductor chip It is possible to prevent the adhesive strength from being lowered or peeling between the two.
A fourth aspect of the present invention is the semiconductor device according to any one of the first to third aspects, wherein the insulating substrate is made of an epoxy resin impregnated with glass fibers.
According to a fifth aspect of the present invention, the insulating substrate is formed by impregnating a bismaleimide-triazine resin (BT resin), an epoxy resin, a polyester resin, a polyimide resin, a phenol resin, or a reinforcing material such as glass fiber into these resins. It is a semiconductor device as described in any one of Claims 1-4 which consists of what was manufactured.
According to a sixth aspect of the present invention, the conductor layer has a predetermined pattern on the outer peripheral portion of the surface of the insulating substrate on the semiconductor chip side and the outer peripheral portion of the back surface of the insulating substrate opposite to the semiconductor chip. and have a, the conductor layer formed on the outer periphery portion of the surface of the insulating substrate, and the insulated conductor layer formed on the outer periphery portion of the back surface of the substrate are connected by via holes, claims It is a semiconductor device as described in any one of 1-5 .
According to a seventh aspect, the via hole, the metal thin film is formed on the wall surface of the drilled on an insulating substrate by through holes, in which further through holes in the filling material is filled, claim 6 It is a semiconductor device as described in above.
According to an eighth aspect of the present invention, a part of the conductor layer formed on the outer peripheral portion of the insulating substrate is exposed on the surface of the insulating substrate to cover the remaining conductor layer and the insulating substrate. 1 solder resist layer is formed, a plurality of wire bonding pads made of Ni layer or Au layer are formed on the surface of the conductor layer exposed from the first solder resist layer, and the surface of the semiconductor chip is provided with a plurality of electrodes, each electrode and the wire bonding pads are electrically connected by a wire, which is a semiconductor device according to claim 6 or 7.
The invention according to claim 9 is the semiconductor device according to claim 8 , wherein the first solder resist layer is formed of a film-like solder resist composition.
According to a tenth aspect of the present invention, the through-hole that communicates the insulating substrate and the first solder resist layer is formed in the insulating substrate and the first solder resist layer below the semiconductor chip. The semiconductor device according to claim 8 or 9 .
The invention according to claim 11 is the semiconductor according to any one of claims 8 to 10 , wherein the semiconductor chip is die-bonded to the first solder resist layer via the adhesive layer. Device.
In a twelfth aspect of the invention, a second solder resist layer is formed on the back surface of the insulating substrate to expose a part of the conductor layer and cover the remaining conductor layer and the insulating substrate. a semiconductor device according to any one of claims 6-11.
The invention according to claim 13 is the semiconductor device according to claim 12 , wherein the second solder resist layer is formed of a film-like solder resist composition.
According to a fourteenth aspect of the present invention, the through-hole that communicates the insulating substrate and the second solder resist layer is formed in the insulating substrate and the second solder resist layer below the semiconductor chip. The semiconductor device according to claim 12 or 13 .
The invention according to claim 15 is any one of claims 12 to 14, wherein a plurality of lands made of a Ni layer or an Au layer are formed on the surface of the conductor layer exposed from the second solder resist layer. It is a semiconductor device as described in above.
A sixteenth aspect of the present invention is the semiconductor device according to the fifteenth aspect , wherein solder bumps are formed on the lands.
The invention according to claim 17 is the semiconductor device according to any one of claims 1 to 16 , wherein the adhesive is formed of a resin composition such as an epoxy resin.
The invention according to claim 18 is any one of claims 1 to 17, wherein a resin package portion for sealing the semiconductor chip is formed so as to cover the entire surface of the insulating substrate on the semiconductor chip side. It is a semiconductor device as described in above.
The invention according to claim 19 is the semiconductor device according to claim 18 , wherein the resin package portion is made of a resin composition containing an epoxy resin or the like.
A twentieth aspect of the present invention is the semiconductor device according to any one of the first to nineteenth aspects, wherein a diameter of the through hole on the semiconductor chip side is 150 μm or less.
According to a twenty- first aspect of the present invention, the corners of the die bonding region are four regions located at the corners of the die bonding region among a plurality of regions obtained by equally dividing the die bonding region into a matrix. It is a semiconductor device as described in any one of Claims 1-20 .
The invention according to claim 22 is the semiconductor device according to any one of claims 1 to 21 , wherein the plurality of through holes are arranged in a matrix.
A twenty- third aspect of the invention is the semiconductor device according to any one of the first to twenty-second aspects, wherein a plurality of the through holes having different diameters are arranged.
The invention according to claim 24 is the semiconductor device according to any one of claims 1 to 23 , wherein the through hole has a circular shape in plan view.
The invention according to claim 25 is the semiconductor device according to any one of claims 1 to 24 , wherein the insulating substrate is formed by laminating a plurality of plate-like bodies.
The invention described in claim 26 is the semiconductor device according to any one of claims 1 to 25 , wherein the package system is BGA (Ball Grid Array) or LGA (Land Grid Array).

本発明の半導体装置によれば、絶縁性基板が吸湿した水分等の加熱膨張によって膨れや剥離が生じることを防止することができる。 According to the semiconductor device of the present invention, it is possible to prevent the insulating substrate from being swollen or peeled off due to thermal expansion of moisture absorbed by the insulating substrate.

図１は、参考例に係る半導体装置の一例を模式的に示す断面図である。 FIG. 1 is a cross-sectional view schematically showing an example of a semiconductor device according to a reference example .

半導体装置１０が備える絶縁性基板２１は、ガラス繊維を含浸したエポキシ樹脂からなるものである。なお、本発明において、絶縁性基板としては、絶縁性を有するものであれば、特に限定されるものではなく、ビスマレイミド−トリアジン樹脂（ＢＴ樹脂）、エポキシ樹脂、ポリエステル樹脂、ポリイミド樹脂、フェノール樹脂、これらの樹脂にガラス繊維等の補強材を含浸したもの等からなる基板を挙げることができる。 The insulating substrate 21 provided in the semiconductor device 10 is made of an epoxy resin impregnated with glass fibers. In the present invention, the insulating substrate is not particularly limited as long as it has insulating properties. Bismaleimide-triazine resin (BT resin), epoxy resin, polyester resin, polyimide resin, phenol resin And a substrate made of such a resin impregnated with a reinforcing material such as glass fiber.

絶縁性基板２１の両面には、所定のパターンを有する導体層（例えばＣｕ層）２３が形成されている。具体的に、導体層２３は、絶縁性基板２１の表面（上面）の外周部分と、絶縁性基板２１の裏面（下面）の外周部分とに形成されている。
絶縁性基板２１の表面の外周部分に形成された導体層２３と、絶縁性基板２１の裏面の外周部分に形成された導体層２３とは、ビアホール２６によって接続されている。ビアホール２６は、絶縁性基板２１に穿設された貫通孔の壁面に無電解メッキや電解メッキ等によって金属薄膜が形成され、さらに該貫通孔に充填材が充填されたものである。上記充填材としては、特に限定されるものではなく、例えば、樹脂充填材等の絶縁性充填材であってもよく、金属充填材等の導電性充填材であってもよい。 Conductive layers (for example, Cu layers) 23 having a predetermined pattern are formed on both surfaces of the insulating substrate 21. Specifically, the conductor layer 23 is formed on the outer peripheral portion of the surface (upper surface) of the insulating substrate 21 and the outer peripheral portion of the back surface (lower surface) of the insulating substrate 21.
The conductor layer 23 formed on the outer peripheral portion of the surface of the insulating substrate 21 and the conductor layer 23 formed on the outer peripheral portion of the back surface of the insulating substrate 21 are connected by a via hole 26. The via hole 26 is formed by forming a metal thin film on the wall surface of the through hole formed in the insulating substrate 21 by electroless plating or electrolytic plating, and further filling the through hole with a filler. The filler is not particularly limited, and may be, for example, an insulating filler such as a resin filler or a conductive filler such as a metal filler.

絶縁性基板２１の表面には、絶縁性基板２１の外周部分に形成された導体層２３の一部を露出させて、残りの導体層２３及び絶縁性基板２１を覆うように、ソルダーレジスト層２５が形成されていて、その露出した導体層２３の表面には、Ｎｉ層やＡｕ層からなる複数のワイヤボンディングパッド２４が形成されている。
また、絶縁性基板２１の裏面には、導体層２３の一部を露出させて残りの導体層２３及び絶縁性基板２１を覆うように、ソルダーレジスト層２９が形成されていて、その露出した導体層２３の表面には、Ｎｉ層やＡｕ層からなる複数のランド２７が形成されている。
各ランド２７上には、半田バンプ２８が形成されている。本実施形態では、予めランド２７上に半田バンプ２８が形成されている場合について説明するが、本発明はこの例に限定されず、例えば、実装時に半田ボールや半田ペースト等を用いて直接、プリント基板に実装することとしてもよい。 On the surface of the insulating substrate 21, a part of the conductor layer 23 formed on the outer peripheral portion of the insulating substrate 21 is exposed to cover the remaining conductor layer 23 and the insulating substrate 21. A plurality of wire bonding pads 24 made of a Ni layer or an Au layer are formed on the exposed surface of the conductor layer 23.
Further, a solder resist layer 29 is formed on the back surface of the insulating substrate 21 so as to expose a part of the conductor layer 23 and cover the remaining conductor layer 23 and the insulating substrate 21, and the exposed conductor A plurality of lands 27 made of a Ni layer or an Au layer are formed on the surface of the layer 23.
Solder bumps 28 are formed on each land 27. In the present embodiment, a case in which the solder bumps 28 are formed on the lands 27 in advance will be described. However, the present invention is not limited to this example. For example, printing can be performed directly using solder balls, solder paste, or the like during mounting. It is good also as mounting on a board | substrate.

絶縁性基板２１の上面に設けられたソルダーレジスト層２５には、接着材層１８を介して半導体チップ１１がダイボンディングされている。半導体チップ１１としては、種々のものを用いることが可能であり、その具体的な機能や内部の回路構成は、特に限定されるものではない。接着材層１８は、エポキシ樹脂等の樹脂組成物によって形成されたものである。半導体チップ１１の上面には、複数の電極１６が設けられていて、各電極１６とボンディングパッド２４とがワイヤ１７によって電気的に接続されている。
半導体装置１０には、絶縁性基板２１の表面（上面）全体を覆うように半導体チップ１１を封止する樹脂パッケージ部１９が形成されている。樹脂パッケージ部１９は、例えば、エポキシ樹脂等を含有する樹脂組成物からなるものである。 The semiconductor chip 11 is die-bonded to the solder resist layer 25 provided on the upper surface of the insulating substrate 21 through the adhesive layer 18. Various semiconductor chips 11 can be used, and specific functions and internal circuit configurations are not particularly limited. The adhesive layer 18 is formed of a resin composition such as an epoxy resin. A plurality of electrodes 16 are provided on the upper surface of the semiconductor chip 11, and each electrode 16 and the bonding pad 24 are electrically connected by wires 17.
In the semiconductor device 10, a resin package portion 19 that seals the semiconductor chip 11 is formed so as to cover the entire surface (upper surface) of the insulating substrate 21. The resin package part 19 consists of a resin composition containing an epoxy resin etc., for example.

半導体チップ１１の下方における絶縁性基板２１及びソルダーレジスト層２５、２９には、絶縁性基板２１及びソルダーレジスト層２５、２９を連通する貫通孔２２が形成されている。貫通孔２２は、中空であり、下側が外部に露出している。貫通孔２２の径としては、特に限定されるものではないが、１５０μｍ以下であることが望ましい。１５０μｍ以上であると、貫通孔２２の径が大き過ぎて、接着材層１８を形成するとき、未硬化の接着材が貫通孔２２に入り込んで接着材層１８の上面に凹凸が生じるおそれがあるからである。 The insulating substrate 21 and the solder resist layers 25 and 29 below the semiconductor chip 11 are formed with through holes 22 that communicate the insulating substrate 21 and the solder resist layers 25 and 29. The through hole 22 is hollow, and the lower side is exposed to the outside. Although it does not specifically limit as a diameter of the through-hole 22, It is desirable that it is 150 micrometers or less. When the thickness is 150 μm or more, the diameter of the through hole 22 is too large, and when the adhesive layer 18 is formed, the uncured adhesive may enter the through hole 22 to cause unevenness on the upper surface of the adhesive layer 18. Because.

次に、絶縁性基板２１における貫通孔２２の配置について、図２を用いて説明することにする。
図２は、図１に示した半導体装置１０が備える絶縁性基板２１の平面図である。図２は、絶縁性基板２１に形成された貫通孔２２の配置について説明するための図であるから、他の構成（導体層２３、ワイヤボンディングパッド２４、ソルダーレジスト層２５、２９、ビアホール２６、ランド２７及び半田バンプ２８）については記載を省略している。また、２１ａは、ダイボンディング領域を示している。 Next, the arrangement of the through holes 22 in the insulating substrate 21 will be described with reference to FIG.
FIG. 2 is a plan view of the insulating substrate 21 provided in the semiconductor device 10 shown in FIG. FIG. 2 is a diagram for explaining the arrangement of the through holes 22 formed in the insulating substrate 21, so that other configurations (conductor layer 23, wire bonding pad 24, solder resist layers 25 and 29, via holes 26, The description of the land 27 and the solder bump 28) is omitted. Reference numeral 21a denotes a die bonding area.

絶縁性基板２１のダイボンディング領域２１ａの全域には、９個の貫通孔２２（２２ａ〜２２ｉ）が均等に形成されている。具体的に、貫通孔２２は、ダイボンディング領域２１を縦３つ×横３つで９等分割した各領域に、１つずつ形成されている。
９個の貫通孔２２ａ〜２２ｉのうち、４つの貫通孔２２ａ、２２ｃ、２２ｇ、２２ｉが、ダイボンディング領域２１ａの隅に形成された貫通孔である。 Nine through holes 22 (22a to 22i) are uniformly formed in the entire area of the die bonding region 21a of the insulating substrate 21. Specifically, one through-hole 22 is formed in each of the regions obtained by dividing the die bonding region 21 into 9 equal sections of 3 × 3.
Of the nine through holes 22a to 22i, four through holes 22a, 22c, 22g, and 22i are through holes formed at the corners of the die bonding region 21a.

半導体装置１０によれば、絶縁性基板２１が、少なくともダイボンディング領域２１ａの隅に形成された中空の貫通孔２２を有し、貫通孔２１が、外部に露出しているため、ダイボンディング領域２１ａの隅の近傍に溜まった水分を、貫通孔２２から効率良く放出することができる。従って、絶縁性基板２２が吸湿した水分等の加熱膨張によって膨れや剥離が生じることを防止することができる。 According to the semiconductor device 10, the insulating substrate 21 has the hollow through holes 22 formed at least at the corners of the die bonding region 21a, and the through holes 21 are exposed to the outside. Moisture accumulated in the vicinity of the corners can be efficiently discharged from the through hole 22. Therefore, it is possible to prevent the insulating substrate 22 from being swollen or peeled off due to thermal expansion of moisture or the like absorbed by moisture.

本発明において「ダイボンディング領域」とは、絶縁性基板の表面のうち、平面視において半導体チップの真下に位置する領域をいい、このダイボンディング領域に半導体チップがダイボンディングされる。また、「ダイボンディング領域の隅」とは、ダイボンディング領域をマトリックス状に等分区画して得られる複数の領域のうち、ダイボンディング領域の隅に位置する４つの領域をいう。ここで、ダイボンディング領域の区画数としては、縦３つ×横３つの計９つ（図２参照）以上であれば、特に限定されるものではない。 In the present invention, the “die bonding region” refers to a region located directly below the semiconductor chip in plan view on the surface of the insulating substrate, and the semiconductor chip is die bonded to the die bonding region. The “corner of the die bonding region” refers to four regions located at the corners of the die bonding region among a plurality of regions obtained by equally dividing the die bonding region into a matrix. Here, the number of sections of the die bonding region is not particularly limited as long as it is 9 or more (see FIG. 2) of 3 in the vertical direction and 3 in the horizontal direction.

本発明においては、半導体装置１０のように、貫通孔２２が、ダイボンディング領域２１ａの全域に、均等に形成されていることが望ましい。
ダイボンディング領域２１ａの全域から効率良く水分を放出することが可能であり、局所的に水分が溜まることを防止することができ、絶縁性基板２１が吸湿した水分等の加熱膨張によって膨れや剥離が生じることをより確実に防止することができるからである。 In the present invention, like the semiconductor device 10, it is desirable that the through holes 22 are uniformly formed over the entire die bonding region 21 a.
It is possible to efficiently release moisture from the entire area of the die bonding region 21a, prevent the water from being locally accumulated, and the insulating substrate 21 may be swollen or peeled off due to heat expansion of moisture absorbed by the insulating substrate 21. It is because it can prevent more reliably.

本発明において「貫通孔がダイボンディング領域の全域に均等に形成される」とは、ダイボンディング領域をマトリックス状に等分区画して得られる複数の領域の全てに、貫通孔が形成されることをいう。ここで、ダイボンディング領域の区画数としては、縦３つ×横３つの計９つ（図２参照）以上であれば、特に限定されるものではなく、例えば、縦４つ×横４つの計１６個、縦６つ×横６つの計３６個、縦８つ×横８つの計６４個、縦１０個×横１０個の計１００個を挙げることができる。また、このようにダイボンディング領域を区画した場合において、各領域に形成される貫通孔の数は、必ずしも１個である必要はなく、複数であってもよい。 In the present invention, “through-holes are uniformly formed throughout the die bonding region” means that the through-holes are formed in all of a plurality of regions obtained by equally dividing the die bonding region into a matrix. Say. Here, the number of sections of the die bonding region is not particularly limited as long as it is 9 or more in total 3 in the vertical direction and 3 in the horizontal direction (see FIG. 2). There can be listed a total of 100 of 16 pieces, a total of 36 pieces, 16 pieces in a vertical direction and 6 pieces in a horizontal direction, 64 pieces in a vertical direction, 8 pieces in a horizontal direction, and 10 pieces in a vertical direction. Further, when the die bonding regions are partitioned in this way, the number of through holes formed in each region is not necessarily one, and may be plural.

本発明においては、半導体装置１０のように、貫通孔２２がマトリックス状に配置されていることが望ましい（図２参照）。ダイボンディング領域２１ａの全域から効率良く均一に水分を放出することができるため、局所的に水分が溜まることをより確実に防止することができるからである。 In the present invention, it is desirable that the through holes 22 are arranged in a matrix like the semiconductor device 10 (see FIG. 2). This is because moisture can be efficiently and uniformly released from the entire area of the die bonding region 21a, so that it is possible to more reliably prevent moisture from being locally accumulated.

なお、絶縁性基板のダイボンディング領域に導体層が形成されている場合、貫通孔は、導体層と近接しない位置に形成されていることが望ましい。貫通孔内の水分によって該貫通孔と近接する導体層が腐食されることを防止することができるからである。また、本発明において、貫通孔の径は、必ずしも、全て同一である必要はなく、絶縁性基板に形成された導体層の位置等に応じて、各貫通孔の径を適宜設定することとしてもよい。また、貫通孔の平面視形状としては、特に限定されるものではないが、円形であることが望ましい。貫通孔の壁面近傍に応力が集中して絶縁性基板にクラックが生じることを防止することができるからである。 In addition, when the conductor layer is formed in the die bonding area | region of an insulating board | substrate, it is desirable for the through-hole to be formed in the position which is not adjacent to a conductor layer. This is because it is possible to prevent the conductor layer adjacent to the through hole from being corroded by moisture in the through hole. In the present invention, the diameters of the through holes are not necessarily the same, and the diameters of the through holes may be appropriately set according to the position of the conductor layer formed on the insulating substrate. Good. Further, the shape of the through hole in plan view is not particularly limited, but is preferably circular. This is because it is possible to prevent stress from concentrating near the wall surface of the through hole and causing cracks in the insulating substrate.

図３は、本発明に係る半導体装置の一例を模式的に示す断面図である。
半導体装置３０が備える絶縁性基板４１の両面には、所定のパターンを有する導体層４３が形成されていて、夫々の導体層４３は、ビアホール４６によって接続されている。
絶縁性基板４１の表面には、絶縁性基板４１の外周部分に形成された導体層４３の一部を露出させて、残りの導体層４３及び絶縁性基板４１を覆うように、ソルダーレジスト層４５が形成されていて、その露出した導体層４３の表面には、複数のワイヤボンディングパッド４４が形成されている。また、絶縁性基板４１の裏面には、導体層４３の一部を露出させて残りの導体層４３及び絶縁性基板４１を覆うように、ソルダーレジスト層４９が形成されていて、その露出した導体層４３の表面には、複数のランド４７が形成されている。各ランド４７上には、半田バンプ４８が形成されている。 FIG. 3 is a cross-sectional view schematically showing an example of a semiconductor device according to the present invention.
Conductive layers 43 having a predetermined pattern are formed on both surfaces of the insulating substrate 41 included in the semiconductor device 30, and the respective conductive layers 43 are connected by via holes 46.
On the surface of the insulating substrate 41, a part of the conductor layer 43 formed on the outer peripheral portion of the insulating substrate 41 is exposed, and the solder resist layer 45 is formed so as to cover the remaining conductor layer 43 and the insulating substrate 41. A plurality of wire bonding pads 44 are formed on the exposed surface of the conductor layer 43. Further, a solder resist layer 49 is formed on the back surface of the insulating substrate 41 so as to expose a part of the conductor layer 43 and cover the remaining conductor layer 43 and the insulating substrate 41, and the exposed conductors. A plurality of lands 47 are formed on the surface of the layer 43. Solder bumps 48 are formed on each land 47.

絶縁性基板４１の上面に設けられたソルダーレジスト層４５には、フィルム状に成形されたエポキシ樹脂等の樹脂組成物からなる接着材によって形成された接着材層３８を介して、半導体チップ３１がダイボンディングされている。
半導体チップ３１の上面には、複数の電極３６が設けられていて、各電極３６とボンディングパッド４４とがワイヤ３７によって電気的に接続されている。
半導体装置３０には、絶縁性基板４１の表面（上面）全体を覆うように半導体チップ３１を封止する樹脂パッケージ部３９が形成されている。 The solder resist layer 45 provided on the upper surface of the insulating substrate 41 is provided with the semiconductor chip 31 via an adhesive layer 38 formed of an adhesive material made of a resin composition such as an epoxy resin formed into a film shape. Die bonded.
A plurality of electrodes 36 are provided on the upper surface of the semiconductor chip 31, and each electrode 36 and the bonding pad 44 are electrically connected by wires 37.
In the semiconductor device 30, a resin package portion 39 that seals the semiconductor chip 31 is formed so as to cover the entire surface (upper surface) of the insulating substrate 41.

半導体チップ３１の下方における絶縁性基板４１及びソルダーレジスト層４５、４９には、絶縁性基板４１及びソルダーレジスト層４５、４９を連通する貫通孔４２が形成されている。貫通孔４２は、中空であり、下側が外部に露出している。また、貫通孔４２は、半導体チップ３１側の径が小さいテーパ形状を有している。 The insulating substrate 41 and the solder resist layers 45 and 49 below the semiconductor chip 31 are formed with through holes 42 communicating with the insulating substrate 41 and the solder resist layers 45 and 49. The through hole 42 is hollow, and the lower side is exposed to the outside. The through hole 42 has a tapered shape with a small diameter on the semiconductor chip 31 side.

本発明においては、半導体装置３０のように、貫通孔４２は、半導体チップ３１側の径が小さいテーパ形状を有していることが望ましい。
半導体チップ３１側の貫通孔４２の径が小さいため、接着材層３８を形成する未硬化の接着材が貫通孔４２に入り込むことを防止することができ、接着材層３８の上面に凹凸が生じて接着材層３８と半導体チップ３１との接着強度が低下したり、両者の間に剥離が生じたりすることを防止することができるからである。 In the present invention, like the semiconductor device 30, the through hole 42 preferably has a tapered shape with a small diameter on the semiconductor chip 31 side.
Since the diameter of the through hole 42 on the semiconductor chip 31 side is small, it is possible to prevent the uncured adhesive forming the adhesive layer 38 from entering the through hole 42, and unevenness is generated on the upper surface of the adhesive layer 38. This is because it is possible to prevent the adhesive strength between the adhesive layer 38 and the semiconductor chip 31 from being lowered or peeling between the two.

また、本発明においては、半導体装置３０のように、接着材層３８は、フィルム状に成形された接着材によって形成されていることが望ましい。
フィルム状に成形された接着材を用いて接着材層３８を形成することによって、未硬化の接着材が貫通孔４２に入り込むことを防止することができ、接着材層３８の上面に凹凸が生じて接着材層３８と半導体チップ３１との接着強度が低下したり、両者の間に剥離が生じたりすることを防止することができるからである。 In the present invention, like the semiconductor device 30, the adhesive layer 38 is preferably formed of an adhesive formed into a film shape.
By forming the adhesive layer 38 using the adhesive formed into a film shape, it is possible to prevent the uncured adhesive from entering the through hole 42, and unevenness is generated on the upper surface of the adhesive layer 38. This is because it is possible to prevent the adhesive strength between the adhesive layer 38 and the semiconductor chip 31 from being lowered or peeling between the two.

図４は、参考例に係る半導体装置の他の一例を模式的に示す断面図である。
半導体装置５０が備える絶縁性基板６１の両面には、所定のパターンを有する導体層６３が形成されていて、夫々の導体層６３は、ビアホール６６によって接続されている。
絶縁性基板６１の表面には、絶縁性基板６１の外周部分に形成された導体層６３の一部を露出させて、残りの導体層６３及び絶縁性基板６１を覆うように、ソルダーレジスト層６５が形成されていて、その露出した導体層６３の表面には、複数のワイヤボンディングパッド６４が形成されている。また、絶縁性基板６１の裏面には、導体層６３の一部を露出させて残りの導体層６３及び絶縁性基板６１を覆うように、ソルダーレジスト層６９が形成されていて、その露出した導体層６３の表面には、複数のランド６７が形成されている。各ランド６７上には、半田バンプ６８が形成されている。 FIG. 4 is a cross-sectional view schematically showing another example of a semiconductor device according to a reference example .
Conductive layers 63 having a predetermined pattern are formed on both surfaces of an insulating substrate 61 provided in the semiconductor device 50, and the respective conductive layers 63 are connected by via holes 66.
On the surface of the insulating substrate 61, a part of the conductor layer 63 formed on the outer peripheral portion of the insulating substrate 61 is exposed, and the solder resist layer 65 is covered so as to cover the remaining conductor layer 63 and the insulating substrate 61. A plurality of wire bonding pads 64 are formed on the exposed surface of the conductor layer 63. Further, a solder resist layer 69 is formed on the back surface of the insulating substrate 61 so as to expose a part of the conductor layer 63 and cover the remaining conductor layer 63 and the insulating substrate 61, and the exposed conductor A plurality of lands 67 are formed on the surface of the layer 63. Solder bumps 68 are formed on each land 67.

絶縁性基板６１の上面に設けられたソルダーレジスト層６５には、エポキシ樹脂等の樹脂組成物からなる接着材によって形成された接着剤層５８を介して、半導体チップ５１がダイボンディングされている。
半導体チップ５１の上面には、複数の電極５６が設けられていて、各電極５６とボンディングパッド６４とがワイヤ５７によって電気的に接続されている。
半導体装置５０には、絶縁性基板６１の表面（上面）全体を覆うように半導体チップ５１を封止する樹脂パッケージ部５９が形成されている。 The semiconductor chip 51 is die-bonded to the solder resist layer 65 provided on the upper surface of the insulating substrate 61 via an adhesive layer 58 formed of an adhesive made of a resin composition such as an epoxy resin.
A plurality of electrodes 56 are provided on the upper surface of the semiconductor chip 51, and each electrode 56 and the bonding pad 64 are electrically connected by wires 57.
In the semiconductor device 50, a resin package part 59 for sealing the semiconductor chip 51 is formed so as to cover the entire surface (upper surface) of the insulating substrate 61.

半導体チップ５１の下方における絶縁性基板６１及びソルダーレジスト層６９には、絶縁性基板６１及びソルダーレジスト層６９を連通する貫通孔６２が形成されている。貫通孔６２は、絶縁性基板６１の上面に形成されたソルダーレジスト層６５には形成されていない。貫通孔６２は、中空であり、下側が外部に露出している。 A through hole 62 is formed in the insulating substrate 61 and the solder resist layer 69 below the semiconductor chip 51 so as to communicate with the insulating substrate 61 and the solder resist layer 69. The through hole 62 is not formed in the solder resist layer 65 formed on the upper surface of the insulating substrate 61. The through hole 62 is hollow, and the lower side is exposed to the outside.

半導体装置６０によれば、絶縁性基板６１とソルダーレジスト層６５との間の水分や、絶縁性基板６１とソルダーレジスト層６９との間の水分を、貫通孔６２から外部に放出することができる。 According to the semi-conductor device 60, moisture and between the insulating substrate 61 and the solder resist layer 65, the water between the insulating substrate 61 and the solder resist layer 69, may be discharged from the through hole 62 to the outside it can.

図４に示した半導体装置６０のように、絶縁性基板６１の表面（上面）にソルダーレジスト層６５が設けられる場合、ソルダーレジスト層６５は、フィルム状のソルダーレジスト組成物によって形成されていることが望ましい。
フィルム状に成形されたソルダーレジスト組成物を用いてソルダーレジスト層６５を形成することによって、ソルダーレジスト組成物が貫通孔６２に入り込むことを防止することができ、ソルダーレジスト層６５の上面に凹凸が生じてソルダーレジスト層６５と半導体チップ６１との接着強度が低下したり、両者の間に剥離が生じたりすることを防止することができるからである。 When the solder resist layer 65 is provided on the surface (upper surface) of the insulating substrate 61 as in the semiconductor device 60 shown in FIG. 4, the solder resist layer 65 is formed of a film-like solder resist composition. Is desirable.
By forming the solder resist layer 65 using the solder resist composition formed into a film shape, the solder resist composition can be prevented from entering the through holes 62, and the upper surface of the solder resist layer 65 is uneven. This is because it is possible to prevent the adhesive strength between the solder resist layer 65 and the semiconductor chip 61 from being lowered and peeling between the two.

次に、本発明の半導体装置の製造方法について説明する。
ここでは、図１及び図２に示した半導体装置の製造方法について説明することとする。また、先ず半導体装置の製造に用いられる基板（以下、半導体装置製造用基板という）の製造方法について説明し、その後、半導体装置製造用基板を用いた半導体装置の製造方法について説明することとする。
図５（ａ）〜（ｅ）、及び、図６（ａ）〜（ｃ）は、本発明の半導体装置の製造方法を模式的に示す断面図である。 Next, a method for manufacturing a semiconductor device of the present invention will be described.
Here, a manufacturing method of the semiconductor device shown in FIGS. 1 and 2 will be described. First, a manufacturing method of a substrate (hereinafter referred to as a semiconductor device manufacturing substrate) used for manufacturing a semiconductor device will be described, and then a manufacturing method of the semiconductor device using the semiconductor device manufacturing substrate will be described.
FIGS. 5A to 5E and FIGS. 6A to 6C are cross-sectional views schematically showing a method for manufacturing a semiconductor device of the present invention.

（Ａ）絶縁性基板２１を出発材料とし、まず、絶縁性基板２１の両面に、導体層２３を形成する。導体層２３は、絶縁性基板２１の両面に無電解メッキを施し、さらに電解メッキを施してベタの金属層を形成した後、エッチング処理を施すことにより形成することができる。また、銅張基板にエッチング処理を施すことにより形成してもよい。 (A) Using the insulating substrate 21 as a starting material, first, the conductor layer 23 is formed on both surfaces of the insulating substrate 21. The conductor layer 23 can be formed by performing electroless plating on both surfaces of the insulating substrate 21, further performing electrolytic plating to form a solid metal layer, and then performing an etching process. Moreover, you may form by performing an etching process to a copper clad board | substrate.

（Ｂ）次に、絶縁性基板２１に、ドリルやレーザ等により貫通孔を穿設する。続いて、無電解メッキを施し、さらに電解メッキを施すことにより、上記貫通孔の壁面に金属薄膜を形成し、該貫通孔に充填材を充填することにより、ビアホール２６を形成する。上記充填材としては、例えば、樹脂充填材や金属充填材等を挙げることができる。また、ビアホール２６には、蓋メッキを施してもよい。 (B) Next, a through hole is drilled in the insulating substrate 21 with a drill, a laser, or the like. Subsequently, electroless plating is performed, and further electroplating is performed to form a metal thin film on the wall surface of the through hole, and the via hole is formed by filling the through hole with a filler. Examples of the filler include a resin filler and a metal filler. The via hole 26 may be plated with a lid.

（Ｃ）次に、絶縁性基板２１の表面に、未硬化のソルダーレジスト組成物をロールコータやカーテンコータ等により塗布したり、フィルム状に成形したソルダーレジスト組成物を圧着したりした後、硬化処理を施すことにより、ソルダーレジスト層２５を形成する。絶縁性基板２１の裏面にも、同様にしてソルダーレジスト層２９を形成する。
続いて、ソルダーレジスト層２５の所定箇所にレーザ処理や露光現像処理により開口を形成し、露出した箇所にＮｉメッキやＡｕメッキを行うことにより、ボンディングパッド２４を形成する。また、ソルダーレジスト層２９に対しても同様の処理を行い、ランド２７を形成する。 (C) Next, an uncured solder resist composition is applied to the surface of the insulating substrate 21 by a roll coater, a curtain coater, or the like, or a solder resist composition formed into a film shape is pressure-bonded and then cured. By performing the treatment, the solder resist layer 25 is formed. Similarly, a solder resist layer 29 is formed on the back surface of the insulating substrate 21.
Subsequently, an opening is formed in a predetermined portion of the solder resist layer 25 by laser processing or exposure and development processing, and a bonding pad 24 is formed by performing Ni plating or Au plating on the exposed portion. The land 27 is formed by performing the same process on the solder resist layer 29.

（Ｄ）次に、ドリルやレーザ等により、絶縁性基板２１のダイボンディング領域２１ａ（図２参照）に、絶縁性基板２１及びダイボンディング領域２５、２９を連通する貫通孔２２を形成する。
上記（Ａ）〜（Ｄ）の工程を経ることにより、半導体装置製造用基板２０を製造することができる（図５（ａ）参照）。 (D) Next, a through hole 22 that communicates the insulating substrate 21 and the die bonding regions 25 and 29 is formed in the die bonding region 21a (see FIG. 2) of the insulating substrate 21 by a drill or a laser.
Through the steps (A) to (D), the semiconductor device manufacturing substrate 20 can be manufactured (see FIG. 5A).

なお、図３に示した半導体装置３０を製造する場合には、上記（Ｄ）の工程において、ドリルの先端形状を変更したり、レーザの強度を調整したりすることにより、テーパ形状を有する貫通孔４２を形成することができる。 In the case of manufacturing the semiconductor device 30 shown in FIG. 3, in the step (D), the drill tip shape is changed by changing the tip shape of the drill or adjusting the laser intensity. Holes 42 can be formed.

また、図４に示した半導体装置５０を製造する場合には、上記（Ｃ）の工程において、絶縁性基板６１の裏面に、ソルダーレジスト層６９を形成し、さらにランド６７を形成した後に、上記（Ｄ）の工程において、貫通孔６２を形成する。その後、絶縁性基板６１の表面に、ソルダーレジスト層６５を形成し、さらにワイヤボンディングパッド６４を形成する。ソルダーレジスト層６５を形成するときには、フィルム状に成形されたソルダーレジスト組成物を用いることが望ましい。ソルダーレジスト組成物が貫通孔６２に入り込むことを防止することができ、ソルダーレジスト層６５の上面に凹凸が生じてソルダーレジスト層６５と半導体チップ６１との接着強度が低下したり、両者の間に剥離が生じたりすることを防止することができるからである。 When the semiconductor device 50 shown in FIG. 4 is manufactured, after the solder resist layer 69 is formed on the back surface of the insulating substrate 61 and the land 67 is further formed in the step (C), the above-described process is performed. In the step (D), the through hole 62 is formed. Thereafter, a solder resist layer 65 is formed on the surface of the insulating substrate 61, and a wire bonding pad 64 is further formed. When forming the solder resist layer 65, it is desirable to use a solder resist composition formed into a film. The solder resist composition can be prevented from entering the through-holes 62, and unevenness is generated on the upper surface of the solder resist layer 65 to reduce the adhesive strength between the solder resist layer 65 and the semiconductor chip 61. This is because peeling can be prevented.

（Ｅ）次に、半導体装置製造用基板２０のソルダーレジスト層２５の中央部分（絶縁性基板２１のダイボンディング領域２１ａ（図２参照）に対応する部分）に、エポキシ樹脂等からなる接着材を塗布し、未硬化の接着材層１８′を形成する（図５（ｂ）参照）。
このとき、フィルム状に成形された接着材を用いて、未硬化の接着材層１８′を形成することが望ましい。フィルム状に成形された接着材を用いることによって、接着材が貫通孔２２に入り込むことを防止することができ、接着材層１８の上面に凹凸が生じて接着材層１８と半導体チップ１１との接着強度が低下したり、両者の間に剥離が生じたりすることを防止することができる。次に、半導体チップ１１を、未硬化の接着材層１８′に載置する。続いて、露光処理等を行い、接着材層１８を形成する（図５（ｃ）参照）。 (E) Next, an adhesive made of epoxy resin or the like is applied to the central portion of the solder resist layer 25 of the semiconductor device manufacturing substrate 20 (the portion corresponding to the die bonding region 21a (see FIG. 2) of the insulating substrate 21). Application is performed to form an uncured adhesive layer 18 '(see FIG. 5B).
At this time, it is desirable to form the uncured adhesive layer 18 ′ using an adhesive formed in a film shape. By using the adhesive formed into a film shape, it is possible to prevent the adhesive from entering the through hole 22, and unevenness is generated on the upper surface of the adhesive layer 18, so that the adhesive layer 18 and the semiconductor chip 11 It can prevent that adhesive strength falls or peeling arises between both. Next, the semiconductor chip 11 is placed on the uncured adhesive layer 18 ′. Subsequently, an exposure process or the like is performed to form the adhesive layer 18 (see FIG. 5C).

（Ｆ）続いて、半導体チップ１１の上面に設けられた電極１６と、ボンディングパッド２４とをワイヤ１７を用いてワイヤボンディングする（図５（ｄ）参照）。次に、絶縁性基板２１の上面全体を覆うように、エポキシ樹脂等を含有する樹脂組成物で樹脂パッケージ部１９を形成する（図５（ｅ）参照）。次に、ランド２７上に半田ボールを載置し、上記半田ボールをリフローすることにより、ランド２７上に半田バンプ２８を形成する（図６（ａ）参照）。続いて、樹脂パッケージ部１９に粘着テープ９を貼着し（図６（ｂ）参照）、その状態で、ダイシングを行うことにより、半導体装置１０を製造することができる（図６（ｃ）参照）。 (F) Subsequently, the electrode 16 provided on the upper surface of the semiconductor chip 11 and the bonding pad 24 are wire-bonded using the wire 17 (see FIG. 5D). Next, the resin package part 19 is formed with a resin composition containing an epoxy resin or the like so as to cover the entire top surface of the insulating substrate 21 (see FIG. 5E). Next, a solder ball is placed on the land 27, and the solder ball 28 is formed on the land 27 by reflowing the solder ball (see FIG. 6A). Subsequently, the adhesive tape 9 is attached to the resin package portion 19 (see FIG. 6B), and the semiconductor device 10 can be manufactured by performing dicing in that state (see FIG. 6C). ).

以上、本発明の実施形態に係る半導体装置について説明したが、本発明は、この例に限定されるものではない。本実施形態においては、絶縁性基板が１層からなるものである場合について説明したが、本発明において、上記絶縁性基板は、複数の板状体が積層されたものであってもよい。また、本実施形態では、半導体装置のパッケージ方式がＢＧＡである場合について説明したが、本発明はこの例に限定されず、例えば、ＬＧＡであってもよい。 The semiconductor device according to the embodiment of the present invention has been described above, but the present invention is not limited to this example. In the present embodiment, the case where the insulating substrate is composed of one layer has been described, but in the present invention, the insulating substrate may be a laminate of a plurality of plate-like bodies. In the present embodiment, the case where the package system of the semiconductor device is BGA has been described. However, the present invention is not limited to this example, and may be LGA, for example.

参考例係る半導体装置の一例を模式的に示す断面図である。It is sectional drawing which shows typically an example of the semiconductor device which concerns on a reference example . 図１に示した半導体装置が備える絶縁性基板の平面図である。FIG. 2 is a plan view of an insulating substrate provided in the semiconductor device shown in FIG. 1. 本発明に係る半導体装置の一例を模式的に示す断面図である。It is sectional drawing which shows typically an example of the semiconductor device which concerns on this invention. 参考例に係る半導体装置の他の一例を模式的に示す断面図である。It is sectional drawing which shows typically another example of the semiconductor device which concerns on a reference example . （ａ）〜（ｅ）は、本発明の半導体装置の製造方法を模式的に示す断面図である。(A)-(e) is sectional drawing which shows the manufacturing method of the semiconductor device of this invention typically. （ａ）〜（ｃ）は、本発明の半導体装置の製造方法を模式的に示す断面図である。(A)-(c) is sectional drawing which shows typically the manufacturing method of the semiconductor device of this invention. 従来の半導体装置の一例を模式的に示す断面図である。It is sectional drawing which shows an example of the conventional semiconductor device typically. 従来の半導体装置の他の一例を模式的に示す断面図である。It is sectional drawing which shows typically another example of the conventional semiconductor device.

符号の説明Explanation of symbols

１０、３０、５０ 半導体装置
１１、３１、５１ 半導体チップ
１６、３６、５６ 電極
１７、３７、５７ ワイヤ
１８、３８、５８ 接着材層
１９、３９、５９ 樹脂パッケージ部
２０ 半導体装置製造用基板
２１、４１、６１ 絶縁性基板
２１ａ ワイヤボンディング領域
２２（２２ａ〜２２ｉ）、４２、６２ 貫通孔
２３、４３、６３ 導体層
２４、４４、６４ ワイヤボンディングパッド
２５、２９、４５、４９、６５、６９ ソルダーレジスト層
２６、４６、６６ ビアホール
２７、４７、６７ ランド
２８、４８、６８ 半田バンプ 10, 30, 50 Semiconductor devices 11, 31, 51 Semiconductor chips 16, 36, 56 Electrodes 17, 37, 57 Wires 18, 38, 58 Adhesive layers 19, 39, 59 Resin package part 20 Semiconductor device manufacturing substrate 21, 41, 61 Insulating substrate 21a Wire bonding region 22 (22a-22i), 42, 62 Through holes 23, 43, 63 Conductor layers 24, 44, 64 Wire bonding pads 25, 29, 45, 49, 65, 69 Solder resist Layer 26, 46, 66 Via hole 27, 47, 67 Land 28, 48, 68 Solder bump

Claims (26)

半導体チップと、
前記半導体チップの真下に位置するダイボンディング領域を有し、当該ダイボンディング領域に接着材を介して前記半導体チップがダイボンディングされた絶縁性基板と
を備えた半導体装置であって、
前記絶縁性基板は、少なくとも前記ダイボンディング領域の隅に形成された中空の貫通孔と、前記ダイボンディング領域以外の領域にのみ形成された導体層とを有し、
前記貫通孔は、前記接着材を外部に露出させ、前記半導体チップ側の径が小さいテーパ形状を有することを特徴とする半導体装置。 A semiconductor chip;
Before SL has a die bonding region located immediately below the semiconductor chip, the semiconductor chip through the adhesive material to the die bonding region is a semiconductor device including an insulating substrate which is die-bonded,
The insulating substrate has at least a hollow through hole formed at a corner of the die bonding region, and a conductor layer formed only in a region other than the die bonding region ,
The semiconductor device according to claim 1, wherein the through hole has a tapered shape in which the adhesive is exposed to the outside and the diameter on the semiconductor chip side is small. 前記貫通孔は、前記ダイボンディング領域の全域に、均等に形成されている請求項１に記載の半導体装置。 The semiconductor device according to claim 1 , wherein the through holes are formed uniformly over the entire area of the die bonding region. 前記絶縁性基板と前記半導体チップとの間には、フィルム状の前記接着材が設けられている請求項１または２に記載の半導体装置。 Wherein between the insulating substrate and the semiconductor chip, the semiconductor device according to claim 1 or 2 film form of the adhesive material is provided. 前記絶縁性基板は、ガラス繊維を含浸したエポキシ樹脂からなる、請求項１〜３のいずれか一項に記載の半導体装置。 The insulating substrate is made of an epoxy resin impregnated with glass fiber, a semiconductor device according to any one of claims 1-3. 前記絶縁性基板は、ビスマレイミド−トリアジン樹脂（ＢＴ樹脂）、エポキシ樹脂、ポリエステル樹脂、ポリイミド樹脂、もしくはフェノール樹脂、またはこれらの樹脂にガラス繊維等の補強材を含浸したものからなる、請求項１〜４のいずれか一項に記載の半導体装置。 The insulating substrate is made of bismaleimide-triazine resin (BT resin), epoxy resin, polyester resin, polyimide resin, phenol resin, or a resin in which a reinforcing material such as glass fiber is impregnated. the semiconductor device according to any one of 1-4. 前記導体層が、前記絶縁性基板の前記半導体チップ側の表面の外周部分と、前記絶縁性基板の前記半導体チップと反対側の裏面の外周部分とに所定のパターンを有しており、前記絶縁性基板の表面の外周部分に形成された導体層と、前記絶縁性基板の裏面の外周部分に形成された導体層とが、ビアホールによって接続されている、請求項１〜５のいずれか一項に記載の半導体装置。 The conductor layer, and the outer peripheral portion of the semiconductor chip side surface of the insulating substrate, and have a predetermined pattern wherein the semiconductor chip opposite the rear surface outer peripheral portion of the insulating substrate, the insulating a conductor layer formed on the outer periphery portion of the surface of sexual substrate, wherein an insulating back conductor layer formed on the outer periphery portion of the substrate are connected by via holes, any one of claims 1 to 5 A semiconductor device according to 1. 前記ビアホールは、前記絶縁性基板に穿設された貫通孔の壁面に金属薄膜が形成され、さらに該貫通孔に充填材が充填されたものである、請求項６に記載の半導体装置。 The semiconductor device according to claim 6 , wherein the via hole is formed by forming a metal thin film on a wall surface of a through hole formed in the insulating substrate and further filling the through hole with a filler. 前記絶縁性基板の表面には、前記絶縁性基板の外周部分に形成された導体層の一部を露出させて、残りの導体層及び前記絶縁性基板を覆う第１のソルダーレジスト層が形成されており、前記第１のソルダーレジスト層から露出した導体層の表面に、Ｎｉ層またはＡｕ層からなる複数のワイヤボンディングパッドが形成されており、
前記半導体チップの表面に複数の電極が設けられており、各電極と前記ワイヤボンディングパッドとがワイヤによって電気的に接続されている、請求項６または７に記載の半導体装置。 A first solder resist layer is formed on the surface of the insulating substrate to expose a part of the conductor layer formed on the outer peripheral portion of the insulating substrate and cover the remaining conductor layer and the insulating substrate. A plurality of wire bonding pads made of a Ni layer or an Au layer are formed on the surface of the conductor layer exposed from the first solder resist layer;
The semiconductor device according to claim 6 or 7 , wherein a plurality of electrodes are provided on a surface of the semiconductor chip, and each electrode and the wire bonding pad are electrically connected by a wire. 前記第１のソルダーレジスト層は、フィルム状のソルダーレジスト組成物によって形成されている、請求項８に記載の半導体装置。 The semiconductor device according to claim 8 , wherein the first solder resist layer is formed of a film-like solder resist composition. 前記半導体チップの下方における前記絶縁性基板及び前記第１のソルダーレジスト層に、前記絶縁性基板及び前記第１のソルダーレジスト層を連通する前記貫通孔が形成されている、請求項８または９に記載の半導体装置。 The said through-hole which connects the said insulating substrate and the said 1st soldering resist layer is formed in the said insulating substrate and the said 1st soldering resist layer under the said semiconductor chip, The Claim 8 or 9 The semiconductor device described. 前記第１のソルダーレジスト層には、前記接着材の層を介して前記半導体チップがダイボンディングされている、請求項８〜１０のいずれか一項に記載の半導体装置。 The semiconductor device according to any one of claims 8 to 10 , wherein the semiconductor chip is die-bonded to the first solder resist layer via the adhesive layer. 前記絶縁性基板の裏面には、前記導体層の一部を露出させて残りの導体層及び前記絶縁性基板を覆う第２のソルダーレジスト層が形成されている、請求項６〜１１のいずれか一項に記載の半導体装置。 Wherein the back surface of the insulating substrate to expose a portion of the conductive layer and the second solder resist layer covering the remainder of the conductor layer and the insulating substrate is formed, any one of claims 6-11 The semiconductor device according to one item. 前記第２のソルダーレジスト層は、フィルム状のソルダーレジスト組成物によって形成されている、請求項１２に記載の半導体装置。 The semiconductor device according to claim 12 , wherein the second solder resist layer is formed of a film-like solder resist composition. 前記半導体チップの下方における前記絶縁性基板及び前記第２のソルダーレジスト層に、前記絶縁性基板及び前記第２のソルダーレジスト層を連通する前記貫通孔が形成されている、請求項１２または１３に記載の半導体装置。 The said through-hole which connects the said insulating substrate and the said 2nd soldering resist layer is formed in the said insulating substrate and the said 2nd soldering resist layer under the said semiconductor chip, The Claim 12 or 13 The semiconductor device described. 前記第２のソルダーレジスト層から露出した導体層の表面に、Ｎｉ層またはＡｕ層からなる複数のランドが形成されている、請求項１２〜１４のいずれか一項に記載の半導体装置。 The semiconductor device according to any one of claims 12 to 14, wherein a plurality of lands made of a Ni layer or an Au layer are formed on a surface of the conductor layer exposed from the second solder resist layer. 前記ランド上には、半田バンプが形成されている、請求項１５に記載の半導体装置。 The semiconductor device according to claim 15 , wherein solder bumps are formed on the lands. 前記接着材は、エポキシ樹脂等の樹脂組成物によって形成されている、請求項１〜１６のいずれか一項に記載の半導体装置。 The adhesive material is formed of a resin composition such as epoxy resin, the semiconductor device according to any one of claims 1-16. 前記絶縁性基板の前記半導体チップ側の表面全体を覆うように前記半導体チップを封止する樹脂パッケージ部が形成されている、請求項１〜１７のいずれか一項に記載の半導体装置。The semiconductor device according to claim 1, wherein a resin package portion that seals the semiconductor chip is formed so as to cover the entire surface of the insulating substrate on the semiconductor chip side. 前記樹脂パッケージ部は、エポキシ樹脂等を含有する樹脂組成物からなる、請求項１８に記載の半導体装置。 The semiconductor device according to claim 18 , wherein the resin package part is made of a resin composition containing an epoxy resin or the like. 前記貫通孔の前記半導体チップ側の径は、１５０μｍ以下である、請求項１〜１９のいずれか一項に記載の半導体装置。 The diameter of the semiconductor chip side of the through hole is 150μm or less, the semiconductor device according to any one of claims 1 to 19. 前記ダイボンディング領域の隅は、前記ダイボンディング領域をマトリックス状に等分区画して得られる複数の領域のうち、当該ダイボンディング領域の隅に位置する４つの領域である、請求項１〜２０のいずれか一項に記載の半導体装置。 Corners of the die bonding area, among the plurality of regions obtained by the die bonding area aliquoted partitioned in a matrix, a four areas located in the corners of the die bonding area, according to claim 1 to 20 The semiconductor device as described in any one. 複数の前記貫通孔がマトリックス状に配置されている、請求項１〜２１のいずれか一項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 21 , wherein the plurality of through holes are arranged in a matrix. 径の異なる複数の前記貫通孔が配置されている、請求項１〜２２のいずれか一項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 22 , wherein a plurality of the through holes having different diameters are arranged. 前記貫通孔の平面視形状が円形である、請求項１〜２３のいずれか一項に記載の半導体装置。 The plan view shape of the through hole is circular, the semiconductor device according to any one of claims 1 to 23. 前記絶縁性基板は、複数の板状体が積層されたものである、請求項１〜２４のいずれか一項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 24 , wherein the insulating substrate is a laminate of a plurality of plate-like bodies. パッケージ方式がＢＧＡ（Ball Grid array）またはＬＧＡ（Land grid array）である、請求項１〜２５のいずれか一項に記載の半導体装置。 Packaging method is BGA (Ball Grid array) or LGA (Land grid array), the semiconductor device according to any one of claims 1 to 25.
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