JP4995503B2 - Method for manufacturing micro electromechanical device - Google Patents

Description

  The present invention relates to a microelectromechanical device having a microstructure and a semiconductor element on the same surface and a manufacturing method thereof.

  In recent years, research on micro mechanical systems called MEMS has been actively conducted. MEMS (Micro Electro Mechanical System) is an abbreviation for a micro electro mechanical system and is called a micro machine (a semiconductor device including a micro machine). Currently, there is no clear definition of a micromachine, but in general, it refers to a microdevice that integrates a "movable microstructure having a three-dimensional structure" and an "electronic circuit having a semiconductor element" using semiconductor microfabrication technology. . Unlike a semiconductor element, a microstructure has a movable portion having a three-dimensional structure, and a space for operating the movable portion is provided.

  A micromachine can control a microstructure by an electronic circuit. Therefore, it is not a central processing control type as in the case of a conventional computer-based device, but an autonomous decentralized type in which a series of operations are performed in which information obtained by a sensor is processed by an electronic circuit and actions are taken via an actuator or the like. It is thought that a system can be constructed.

  A lot of research has been done on micromachines. For example, an improved MEMS wafer level package has been proposed with a problem that the manufacturing process cannot be compatible with facilities for wafer manufacturing and plastic assembly (see Patent Document 1).

  In addition, there is a document related to an electromechanical device called MEMS (see Patent Document 2). Patent Document 2 includes amorphous materials, nanocrystalline materials, microcrystalline materials, and polycrystalline materials as thin film starting materials, which include silicon, germanium, silicon germanium, anisotropic dielectric materials, and anisotropic materials. Piezoelectric materials, copper, aluminum, tantalum, and titanium are described. A thin film amorphous silicon layer is formed on the surface of the glass substrate and crystallized. Crystallization is performed by controlling laser irradiation so as to have good mechanical properties.

Further, as a technique related to a process of etching a sacrificial layer for forming a space, for example, a method of manufacturing a micro electro mechanical device in which a first sacrificial layer member and a second sacrificial layer member are made of different resist materials. There is literature (see Patent Literature 3). In Patent Document 3, by using different resist materials, a difference in baking temperature is caused, and sacrificial layer members having different etching rates are formed.
JP 2001-144117 A Japanese Patent Application Laid-Open No. 2004-1201 JP 2004-133281 A

  As described in Patent Document 1, a microstructure which is a component of a micromachine is formed by a process for manufacturing a semiconductor element using a silicon wafer. In particular, in order to obtain a material having a thickness and strength sufficient to form a microstructure, a micromachine that has been put into practical use mainly uses a silicon wafer.

  In addition, in order to mass-produce micromachines having a minute structure, it is necessary to reduce manufacturing costs. As one of the means, a method of forming a microstructure and a semiconductor element for controlling the microstructure on the same substrate can be considered. However, in the case where the microstructure and the semiconductor element are formed over the same substrate, a process different from the process for manufacturing the semiconductor element, such as etching of the sacrificial layer, is necessary, and thus the process is complicated. As described above, a manufacturing process is different between a microstructure and a semiconductor element for controlling the microstructure, and as a result, the microstructure or the semiconductor element may be destroyed and may not function. Therefore, in manufacturing a micromachine that is currently in practical use, a microstructure and a semiconductor element are often formed by different processes.

  Therefore, in the present invention, a microstructure and a semiconductor element are formed over the same surface over the same substrate, and a micromachine including these (hereinafter referred to as a semiconductor device or a microelectromechanical device) is manufactured. In particular, a method for simplifying a step of removing a sacrificial layer when a microstructure and a semiconductor element are formed over the same surface is provided.

  In view of the above problems, the present invention provides a region for forming a semiconductor element by forming a sacrificial layer using the same material as a mask material in an etching process when forming a pattern of a semiconductor element portion and a microstructure structure portion. The mask removal in the region where the microstructure is formed and the sacrificial layer removal in the region where the microstructure is formed are performed in the same step.

  The process of removing such a sacrificial layer is determined by the structure and operation method when a microstructure is formed. When the sacrificial layer is removed, a space is generated, and a part of the microstructure becomes a movable portion.

  Below, the concrete structure of this invention is shown.

  In one embodiment of the present invention, a sacrificial layer is selectively formed over an insulating substrate (insulating substrate), a semiconductor layer is formed to cover the sacrificial layer, a mask is formed over the semiconductor layer, and the mask is formed. A method for manufacturing a microelectromechanical device is characterized in that the semiconductor layer is etched and the mask and the sacrificial layer are removed in the same step.

  In another embodiment of the present invention, a sacrificial layer is formed in a first region over an insulating substrate, a semiconductor layer is formed in the first region and the second region so as to cover the sacrificial layer, and the first over the semiconductor layer is formed. A first mask is formed in the region, a second mask is formed in the second region, the semiconductor layer is etched using the first and second masks, and the structure layer of the microstructure and the active layer of the semiconductor element And a part of the sacrificial layer is exposed, and the first mask, the second mask, and the sacrificial layer are removed in the same step.

  In any one of the above forms, a semiconductor layer is formed over the sacrificial layer, the semiconductor layer is etched, a conductive layer is formed over the etched semiconductor layer, the conductive layer is etched, and the microstructure is formed. A second sacrificial layer and a gate electrode of the semiconductor element are formed.

  In another embodiment of the present invention, a semiconductor layer is formed over an insulating substrate, an insulating layer is formed to cover the semiconductor layer, a sacrificial layer is selectively formed through the insulating layer, and a conductive layer is formed over the sacrificial layer. Forming a mask over the conductive layer, etching the conductive layer using the mask, exposing part of the sacrificial layer, and removing the mask and the sacrificial layer in the same step This is a method for manufacturing an electromechanical device.

  In another embodiment of the present invention, a semiconductor layer is formed in a first region and a second region on an insulating substrate, an insulating layer is formed to cover the semiconductor layer, and the first region is sacrificed through the insulating layer. Forming a layer, forming a conductive layer over the sacrificial layer and the second region, forming a mask over the conductive layer, etching the conductive layer using the mask, and exposing a portion of the sacrificial layer; And the sacrificial layer are removed in the same step.

  In another embodiment of the present invention, a semiconductor layer is formed in a first region and a second region on an insulating substrate, an insulating layer is formed to cover the semiconductor layer, and the first region is sacrificed through the insulating layer. Forming a layer, forming a conductive layer on the sacrificial layer and the second region, forming first and second masks on the conductive layer, and etching the conductive layer using the first and second masks; Then, the structure layer of the microstructure and the gate electrode of the semiconductor element are formed, a part of the sacrifice layer is exposed, the conductive layer is etched using the mask, and the first mask, the second mask, and the sacrifice A method for manufacturing a microelectromechanical device, wherein a layer is removed in the same step.

  In any one of the above forms, the semiconductor layer includes a silicon layer crystallized using a metal. In addition, silicide including metal may be formed in the semiconductor layer.

  In the present invention, the semiconductor layer may have a stacked structure of a silicon layer crystallized using a metal and an amorphous silicon layer.

  In the present invention, the insulating substrate may be peeled off. By peeling the substrate, the thickness and weight can be reduced.

  According to the present invention, a microstructure and a semiconductor element can be formed over the same surface of the same substrate, so that the process can be simplified. As a result, the production tact of the micro electromechanical device can be improved, the cost can be reduced, and the damage to the microstructure during the manufacturing process can be reduced.

  By forming the microstructure and the semiconductor element over the same surface in this manner, a microelectromechanical device that does not require assembly and packaging can be provided at low cost.

  Further, according to the present invention, polycrystalline silicon crystallized using a metal such as nickel can be used for a structure layer of a microstructure and an active layer of a semiconductor element. A microelectromechanical device in which semiconductor elements having excellent characteristics are formed on the same surface can be provided.

  Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description. It will be readily understood by those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the present invention. Therefore, the present invention is not construed as being limited to the following embodiments and the description of the embodiments. Note that in describing the structure of the present invention with reference to the drawings, the same portions are denoted by the same reference numerals in different drawings.

(Embodiment 1)
In this embodiment, a method for forming a microstructure and a semiconductor element over the same surface is described with reference to drawings. In the drawing, a top view and a cross-sectional view at OP or QR are shown.

  The microstructure and the semiconductor element of the present invention can be formed over the same surface and on an insulating substrate. Examples of the insulating substrate include a glass substrate, a quartz substrate, and a plastic substrate. For example, by forming a microstructure and a semiconductor element over a plastic substrate, a highly flexible and lightweight microelectromechanical device can be manufactured. In addition, by thinning the glass substrate by polishing or the like, a thin micro electro mechanical device can be manufactured. Furthermore, a substrate in which an insulating film (insulating layer) is formed over a conductive substrate such as metal or a semiconductor substrate such as silicon can be used as the insulating substrate.

First, the base layer 102 is formed over the insulating substrate 101 (see FIGS. 1A-1 and 1A-2). For the base layer 102, an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide can be formed with a single-layer structure or a stacked structure. In this embodiment mode, the base layer 102 is formed with a stacked structure. As the first layer of the base layer 102, silicon oxynitride formed by using a plasma CVD method and using SiH ₄ , NH ₃ , N ₂ O, and H ₂ as a reactive gas has a thickness of 10 to 200 nm (preferably 50 to 100 nm). It can be formed to have a film thickness. In this embodiment, silicon oxynitride with a thickness of 50 nm is formed as the first layer of the base layer 102. As the second layer of the base layer 102, a plasma CVD method is used, SiH ₄ and N ₂ O are used as reaction gases, and silicon oxynitride is stacked to a thickness of 50 to 200 nm (preferably 100 to 150 nm). Can be formed. In this embodiment, silicon oxynitride with a thickness of 100 nm is formed as the second layer of the base layer 102.

  Next, a first sacrificial layer 103 is formed over the base layer 102 and etched into a predetermined shape (see FIGS. 1A-1 and A-2). For the first sacrificial layer 103, a resin material such as an epoxy resin, an acrylic resin, a phenol resin, a novolac resin, a melamine resin, or a urethane resin is used. Also, a composition comprising an organic material such as benzocyclobutene, parylene, fluorinated arylene ether, translucent polyimide, a compound material obtained by polymerization of a siloxane polymer, a water-soluble homopolymer and a water-soluble copolymer A material or the like may be used. Note that siloxane corresponds to a resin including a Si—O—Si bond and is a resin having a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) may be used, and a fluoro group may be used as the substituent. Further, as a substituent, an organic group containing at least hydrogen and a fluoro group may be used.

  For the first sacrificial layer 103, a resist material containing a photosensitizer may be used. For example, a novolak resin that is a typical positive resist, a naphthoquinone diazide compound that is a photosensitizer, a base resin that is a negative resist, A photosensitive resin having diphenylsilanediol and an acid generator may be used.

  Regardless of which material is used, the surface tension and viscosity are determined by adjusting the concentration of the solvent mixed with the material or adding a surfactant or the like. For example, the surface tension of the solvent can be reduced by adding a surfactant.

  The first sacrificial layer 103 can be formed by forming the film using the above materials and then etching the film to have a predetermined shape. For the etching, a photolithography method can be used. Alternatively, a mask may be drawn using a droplet discharge device such as an inkjet, and the first sacrificial layer 103 may be etched using the mask. By drawing a mask using such a droplet discharge device, it is possible to eliminate the steps of exposure and development necessary for photolithography and waste of mask material.

  The thickness of the first sacrificial layer 103 is determined in consideration of the material of the first sacrificial layer 103, the structure and operation method of the structure, the sacrificial layer etching method, and the like. For example, if the first sacrificial layer 103 is too thin, the etching agent does not diffuse, so that a phenomenon occurs in which the etching is not performed or the structural layer is buckled after the etching.

  Further, when the structure is operated with electrostatic attraction (hereinafter referred to as electrostatic force), the structure cannot be driven if the first sacrificial layer is too thick. For example, in the case where the structure is driven by an electrostatic force generated between the lower conductive layer and the structure layer, the first sacrificial layer 103 has a thickness of 0.5 μm to 3 μm, and preferably 1 μm to 2.5 μm. Good.

  Next, the semiconductor layer 104 is formed over the base layer 102 and the first sacrificial layer 103. The semiconductor layer 104 serves as an active layer constituting a semiconductor element and a structural layer constituting a microstructure. Note that the active layer includes a channel formation region, a source region, and a drain region. The semiconductor layer 104 can be formed using a material containing silicon such as a material containing silicon as a main component or a silicon germanium material containing about 0.01 to 4.5 atomic% of germanium. As the semiconductor layer 104, a semiconductor layer having a crystalline structure or an amorphous structure is used.

  Then, a mask 105 is formed in a predetermined region over the semiconductor layer 104 (see FIGS. 1B-1 and B-2). The mask 105 is formed into a predetermined shape by, for example, exposing and developing the active layer and the structural layer after applying a resist agent.

  In the present invention, the mask 105 is made of the same material as that of the first sacrificial layer 103 or a material that can be processed at the same time in a subsequent mask removing process.

  The semiconductor layer 104 is etched using the mask 105, so that the active layer 107 and the structural layer 108 are formed (see FIGS. 1C-1 and C-2). At this time, a part of the first sacrificial layer 103 is exposed.

  Then, the first sacrificial layer 103 and the mask 105 are removed at the same time (see FIGS. 2A-1 and 2A-2). In the present invention, the first sacrificial layer 103 and the mask 105 are formed of the same material or a material that can be processed in the same process. The treatment time is adjusted as appropriate so that the first sacrificial layer 103 and the mask 105 can be removed in the same step. Therefore, the first sacrificial layer 103 and the mask 105 can be removed in the same process. A space is formed by removing the first sacrificial layer 103. Due to the existence of this space, a part of the microstructure becomes a movable part.

  Note that the sacrificial layer refers to a layer that is removed in order to form a space necessary for the microstructure, and may be a conductive layer or an insulating layer.

  As described above, the present invention is characterized in that the removal of the mask 105 and the removal of the first sacrificial layer 103 are performed in the same step. Thus, a process only for removing the sacrificial layer can be omitted, and damage to the structural layer 108 and the active layer 107 can be reduced.

  The material and thickness of the structural layer 108 can be determined in consideration of various factors such as the thickness and material of the first sacrificial layer 103, the structure of the structure, or the sacrificial layer etching method. For example, when a material having a large internal stress distribution difference is used for the structural layer 108, the structural layer 108 may be warped. Conversely, a structure can be formed by utilizing the warp of the structural layer 108. Further, when the structural layer 108 is formed thick, the internal stress is distributed, which causes warping and buckling. In view of the above, when the structural layer 108 is formed, the film thickness is preferably 0.5 μm or more and 10 μm or less.

  In this embodiment mode, the semiconductor layer to be the active layer 107 and the structural layer 108 is formed over the first sacrificial layer 103, but an insulating layer is formed over the first sacrificial layer 103 and then the semiconductor A layer may be formed. By using such a step, the structural layer 108 can be protected by the insulating layer when the first sacrifice layer 103 is removed, and damage to the structural layer 108 can be reduced.

  Next, the insulating layer 109 which covers the upper surface of the structural layer 108 is formed over the active layer 107 and the structural layer 108 (see FIGS. 2A-1 and 2A-2). The insulating layer 109 functions as a gate insulating layer of the semiconductor element. The insulating layer 109 can be formed by a plasma CVD method, a sputtering method, or the like using a material containing silicon such as silicon oxide or silicon nitride, like the base layer 102. Either a single layer structure or a laminated structure may be used. In this embodiment, a silicon oxynitride film (composition ratio: Si = 32%, O = 59%, N = 7%, H = 2%) is formed as the insulating layer 109 with a thickness of 115 nm by a plasma CVD method. .

  Further, as the material of the insulating layer 109, a metal oxide having a high dielectric constant, for example, hafnium (Hf) oxide can be used. By forming the gate insulating layer using such a high dielectric constant material, the semiconductor element can be driven at a low voltage, and a micro electro mechanical device with low power consumption can be provided.

The insulating layer 109 is formed by high density plasma treatment. The high density plasma treatment means that the plasma density is 1 × 10 ¹¹ cm ⁻³ or more, preferably 1 × 10 ¹¹ cm ⁻³ or more and 9 × 10 ¹⁵ cm ⁻³ or less, and is a microwave (for example, frequency 2.45 GHz). This is a plasma treatment using such a high frequency. When plasma is generated under such conditions, the low electron temperature is changed from 0.2 eV to 2 eV. In this way, since the high-density plasma having a low electron temperature has low kinetic energy of active species, a film with little plasma damage and few defects can be formed.

  A substrate on which an active layer 107 and a structural layer 108 are formed is placed in a deposition chamber capable of performing plasma treatment, and a distance between an electrode for plasma generation, that is, a so-called antenna and an object to be formed is 20 mm to 80 mm, preferably Processing is performed from 20 mm to 60 mm. By using such high-density plasma treatment, a low-temperature process with a substrate temperature of 400 ° C. or lower is possible. Therefore, glass or plastic with low heat resistance can be used as the insulating substrate 101.

  The atmosphere for film formation using such high-density plasma can be a nitrogen atmosphere or an oxygen atmosphere. The nitrogen atmosphere is typically a mixed atmosphere of nitrogen and a rare gas, or a mixed atmosphere of nitrogen, hydrogen, and a rare gas. As the rare gas, at least one of helium, neon, argon, krypton, and xenon is used. The oxygen atmosphere is typically a mixed atmosphere of oxygen and a rare gas, a mixed atmosphere of oxygen, hydrogen, and a rare gas, or a mixed atmosphere of dinitrogen monoxide and a rare gas. As the rare gas, at least one of helium, neon, argon, krypton, and xenon is used.

  The insulating layer formed by such a high-density plasma treatment is dense with little damage to other films during film formation. In addition, the interface state in contact with the insulating layer can be improved. For example, when the gate insulating layer is formed by high-density plasma treatment, the interface state with the semiconductor layer can be improved. As a result, the electrical characteristics of the semiconductor element can be improved. Furthermore, by forming the insulating layer on the structural layer in this way, damage to the structural layer during formation can be reduced, and deterioration of the mechanical strength of the structural layer 108 can be prevented.

  Although the case where high-density plasma treatment is used for forming the insulating layer 109 is described here, high-density plasma treatment may be performed on the semiconductor layer. The semiconductor layer surface can be modified by high-density plasma treatment. As a result, the interface state can be improved and the electrical characteristics of the semiconductor element can be improved.

  Further, not only the formation of the insulating layer 109 but also the formation of the base layer 102 or another insulating layer can use high-density plasma treatment.

  Next, a first conductive layer 110 which functions as a gate electrode of a semiconductor element and a second sacrificial layer 111 of a microstructure are formed over the insulating layer 109 (FIGS. 2B-1 and 2B-2). )reference). The first conductive layer 110 can be formed by a CVD method, a sputtering method, or the like, and is etched so as to have a predetermined shape. Alternatively, the conductive film can be formed by a droplet discharge method using a composition containing a conductive material. Examples of conductive materials include Ag, Au, Cu, Ni, Pt, Pd, Ir, Rh, W, Al, Ta, Mo, Cd, Zn, Fe, Ti, Zr, Ba, and other metals, Si, Ge, and the like. It is preferable to use semiconductor, ITO (indium tin oxide), ITSO having silicon oxide as a composition, IZO which is indium zinc oxide, organic indium, organic tin, zinc oxide (ZnO), titanium nitride (TiN), or the like. it can. Note that indium zinc oxide (IZO) is a transparent conductive material formed by sputtering using a target in which 2 to 20 wt% zinc oxide (ZnO) is mixed with indium tin oxide (ITO). . In the case of forming by a droplet discharge method, a solvent mixed with these metals, dispersible nanoparticles, silver halide fine particles, or the like can be used. By using the droplet discharge method, the development and exposure steps necessary for the photolithography method can be omitted, so that the process is simplified.

  End surfaces of the first conductive layer 110 and the second sacrificial layer 111 may be tapered. By forming the end face in a tapered shape, a film formed in a subsequent process can be satisfactorily covered. The first conductive layer 110 and the second sacrificial layer 111 can have a single-layer structure or a stacked structure.

Next, an impurity element is added to the active layer 107 included in the semiconductor element to form an N-type impurity region 113 and a P-type impurity region 112 (see FIGS. 2C-1 and 2C-2). Such an impurity region can be selectively formed by forming a mask by a photolithography method and adding an impurity element. The impurity element can be added by a thermal diffusion method or an ion implantation method. Typically, phosphorus (P) or arsenic (As) is used as the impurity element imparting N-type, and boron (B) can be used as the impurity element imparting P-type. An impurity element is preferably added to the N-type impurity region 113 and the P-type impurity region 112 in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ³ .

  Next, an insulating layer made of a nitrogen compound such as silicon nitride or an oxide such as silicon oxide is formed by a plasma CVD method or the like, and the insulating layer is anisotropically etched in the vertical direction, whereby the first conductive layer 110 is formed. A sidewall 114 functioning as an insulating layer is formed in contact with the side surface of the substrate (see FIGS. 2C-1 and 2C-2). At this time, the sidewall 114 is also formed on the side surface of the second sacrificial layer 111. When the sidewall 114 is not desired to be formed, a mask that covers the second sacrificial layer 111 is formed in advance before the sidewall 114 is formed.

  Next, an impurity element is added to the active layer 107 having the N-type impurity region 113 to form a high-concentration N-type impurity region 117 having an impurity concentration higher than that of the N-type impurity region 113 provided below the sidewall 114. To do.

The reason why the two impurity regions having different concentrations are formed is to prevent the short channel effect. The short channel effect is a phenomenon in which a leakage current flows between a source and a drain without applying a voltage to the gate due to a shortened gate length. Here, two regions having different concentrations are formed only in the N-type semiconductor element, because the N-type semiconductor element is easily affected by the short channel effect. Of course, a sidewall may be formed in a P-type semiconductor element to form a high concentration P-type impurity region.

  In addition, when the first conductive layer 110 has a stacked structure of different conductive materials and has a tapered shape, the N-type impurity region 113 and the high-concentration N-type can be added by adding an impurity element once without providing a sidewall. The impurity region 117 can also be formed.

  After the impurity region is formed, heat treatment, infrared light irradiation, or laser light irradiation may be performed in order to activate the impurity element. Simultaneously with activation, damage to the insulating layer 109 due to plasma and damage to the interface between the insulating layer 109 and the active layer 107 can be recovered. In particular, when an impurity element is activated from the front surface or the back surface using an excimer laser in an atmosphere of room temperature to 300 ° C., the activation can be effectively performed. Further, it may be activated by irradiating a harmonic such as the second harmonic of the YAG laser. A YAG laser is preferred as an activation means because it requires less maintenance.

  Further, after a passivation film made of an insulator such as silicon oxynitride or silicon oxide is formed so as to cover the first conductive layer 110 or the semiconductor layer, heat treatment, infrared light irradiation, or laser light irradiation is performed. It is also possible to carry out hydrogenation. For example, as a passivation film, a silicon oxynitride film can be formed using a plasma CVD method, and then heated at 300 to 550 ° C. for 1 to 12 hours using a clean oven to hydrogenate the semiconductor layer. . By performing this step, dangling bonds in the semiconductor layer generated by the addition of the impurity element can be terminated by hydrogen contained in the passivation film. At the same time, the activation process of the impurity region can be performed.

  Through the above steps, an N-type semiconductor element 115 and a P-type semiconductor element 116 are formed (see FIGS. 2C-1 and 2C-2). At this time, an impurity region is formed in a region not covered with the second sacrificial layer 111 in the structural layer 108 included in the microstructure.

  Subsequently, an interlayer insulating layer 118 is formed so as to cover the whole (see FIGS. 3A-1 and 3A-2). The interlayer insulating layer 118 can be formed using an insulating material. It may be an inorganic material or an organic material. As the inorganic material, silicon oxide, silicon nitride, or the like can be used. As the organic material, polyimide, acrylic, polyamide, polyimide amide, resist, benzocyclobutene, siloxane, or polysilazane can be used. Polysilazane is formed using a polymer material having a bond of silicon (Si) and nitrogen (N) as a raw material.

  Next, the interlayer insulating layer 118 and the insulating layer 109 are sequentially etched and opened to form contact holes 119 (see FIGS. 3A-1 and 3A-2). For the etching, a dry etching method or a wet etching method can be used. In this embodiment mode, the contact hole 119 is formed by a dry etching method.

  Next, a second conductive layer 120 which functions as a source electrode and a drain electrode is formed over the interlayer insulating layer 118 and the contact hole 119 (see FIGS. 3A-1 and 3A-2). At this time, a wiring constituting the electric circuit can be formed.

  The conductive layer may be formed of a film of an aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), or silicon (Si) film or a conductive material made of an alloy using these elements. it can. The second conductive layer 120 can be formed by discharging a composition mixed with these conductive materials by a droplet discharge method. In addition, the second conductive layer 120 can be formed by forming a film of the above-described conductive material by a sputtering method or a CVD method and then etching into a predetermined shape.

  In the case where the second conductive layer 120 has a pattern with a corner when viewed from above, it is preferable to perform etching so that the corner is rounded. Thereby, generation | occurrence | production and accumulation | storage of refuse can be suppressed and a yield can be improved. The same applies to etching of a conductive layer such as the first conductive layer 110.

  Next, the interlayer insulating layer 118 is etched to form the opening 121. As a result, the second sacrificial layer 111 is exposed (see FIGS. 3B-1 and B-2). For the etching, a dry etching method or a wet etching method can be used. Note that FIGS. 3B-1 and 3B-2 illustrate only a microstructure.

  In this embodiment mode, the opening 121 is formed by a dry etching method. The opening 121 is opened to etch away the second sacrificial layer 111. Therefore, it is necessary to appropriately determine the diameter of the opening 121 so that the etching agent flows. For example, the diameter of the opening 121 is preferably 2 μm or more.

  Further, the opening 121 can be opened to be large so that the second sacrifice layer 111 can be easily etched. That is, it is not necessary to make the opening small as described above, and the opening 121 is formed so that the entire portion of the second sacrificial layer 111 is exposed, leaving a portion where the interlayer insulating layer 118 is necessary (for example, on a semiconductor element). That's fine. Further, by forming a plurality of openings 121, the second sacrificial layer 111 can be removed in a short time.

  Next, the second sacrificial layer 111 is removed by etching (see FIGS. 4A and 4B). Note that FIGS. 4A and 4B illustrate only a microstructure, and each illustrates a microstructure having an OP cross section and a microstructure having a QR cross section. For the etching, a wet etching method or a dry etching method can be applied depending on the material of the second sacrifice layer 111. By introducing an etchant or an etching gas into the opening 121, the second sacrificial layer 111 can be removed by etching.

For example, when the second sacrificial layer 111 is tungsten (W), it can be removed by immersing it in a solution in which 28% by weight of ammonia and 31% by weight of hydrogen peroxide are mixed in a ratio of 1: 2. The treatment time may be appropriately adjusted depending on the film thickness and the like. When the second sacrificial layer 111 is silicon dioxide, it can be removed by using buffered hydrofluoric acid in which ammonium fluoride is mixed at a ratio of 7 to the 49 wt% hydrofluoric acid aqueous solution 1. In the case where the second sacrificial layer 111 is silicon, alkali metal hydroxide such as phosphoric acid, KOH, NaOH, CsOH, NH ₄ OH, hydrazine, EPD (a mixture of ethylenediamine, pyrocatechol, water), TMAH, IPA , NMD3 solution or the like. When drying after wet etching, in order to prevent buckling of the structure due to capillarity, rinse with a low-viscosity organic solvent (for example, cyclohexane), or dry under low temperature and low pressure conditions, or both It can be performed by the combination of.

The second sacrificial layer 111 can also be removed by dry etching using F ₂ or XeF ₂ under a high pressure condition such as atmospheric pressure. In order to prevent buckling of the structure due to capillary action, plasma treatment may be performed to impart water repellency to the surface of the structure.

  By etching away the second sacrificial layer 111 through such a process, a space is generated and the microstructure 122 is formed. Then, the microstructure 122, the N-type semiconductor element 115, and the P-type semiconductor element 116 can be formed over the same surface (see FIG. 4C). By forming a microstructure and a semiconductor element over the same surface of the same substrate, assembly and packaging are unnecessary, and a microelectromechanical device can be manufactured at a lower cost than in the past.

  In the method for forming the microstructure 122 described above, an appropriate combination of the material of the structural layer 108, the material of the first sacrificial layer 103, the material of the second sacrificial layer 111, and the etchant for removing the sacrificial layer is used. Must be selected. For example, when a specific etching agent is determined, the first sacrificial layer 103 and the second sacrificial layer 111 may be formed using a material having an etching rate larger than that of the material of the structural layer 108.

(Embodiment 2)
In the present invention, as the semiconductor layer applied to the structural layer, a semiconductor layer having a crystalline structure or an amorphous structure can be used. Therefore, in this embodiment, a case where the structural layer is a crystalline silicon layer will be described.

  First, an amorphous silicon layer is formed on the surface where the structural layer is formed. Then, the amorphous silicon layer is crystallized by heat treatment, and a crystalline silicon layer can be obtained. For the heat treatment, a heating furnace, laser irradiation, irradiation of light emitted from a lamp instead of laser light (hereinafter referred to as lamp annealing), or a combination thereof can be used.

For laser irradiation, a continuous wave laser beam (hereinafter referred to as a CW laser beam) or a pulsed laser beam (hereinafter referred to as a pulsed laser beam) can be used. As the laser beam, Ar laser, Kr laser, excimer laser, YAG laser, Y ₂ O ₃ laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, glass laser, ruby laser, alexandrite laser, Ti: sapphire laser, copper vapor Lasers oscillated from one or a plurality of lasers or gold vapor lasers can be used. By irradiating the fundamental wave of such a laser beam and the second to fourth harmonics of the fundamental wave, a crystal having a large grain size can be obtained. For example, a second harmonic (532 nm) or a third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm) can be used. At this time, the energy density of the laser about 0.01 to 100 MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. The scanning speed is controlled to about 10 to 2000 cm / sec. Note that in this specification, a laser beam includes laser light.

  The continuous wave type fundamental wave laser beam and the continuous wave type harmonic laser beam may be irradiated, or the continuous wave type fundamental wave laser beam and the pulse wave form harmonic laser beam may be irradiated. You may make it irradiate. By irradiating a plurality of laser beams, energy can be supplemented.

  Further, a pulse oscillation type laser that oscillates at an oscillation frequency that can be irradiated with the laser beam of the next pulse after the silicon layer is melted by the laser beam and solidified can also be used. By oscillating the laser at such a frequency, crystal grains continuously grown in the scanning direction can be obtained. A specific oscillation frequency of the laser beam is 10 MHz or more, and a frequency band that is significantly higher than a frequency band of several tens to several hundreds Hz that is normally used is used.

  When a heating furnace is used as other heat treatment, the amorphous silicon layer is heated at 400 to 550 ° C. for 2 to 20 hours. At this time, the temperature may be set stepwise in the range of 400 to 550 ° C. so that the temperature gradually increases. In the first low-temperature heating process at about 400 ° C., hydrogen and the like of the amorphous silicon layer are generated, so that film roughness during crystallization can be reduced. Furthermore, it is preferable to form a metal element that promotes crystallization, such as nickel (Ni), on the amorphous silicon layer because the heating temperature can be reduced. As the metal element, Fe, Ru, Rh, Pd, Os, Ir, Pt, Cu, Au, or the like can be used.

  Further, in addition to the heat treatment, the crystalline silicon layer may be formed by irradiation with the laser beam as described above.

  Polycrystalline silicon crystallized using such a metal has almost the same crystal structure as that of a single crystal, and has higher toughness than polycrystalline silicon formed by crystallization without using a metal. can do. This is because crystal grain boundaries of polycrystalline silicon are continuous by crystallization using a metal. Unlike polycrystalline silicon obtained by crystallization without using a metal, polycrystalline silicon in which crystal grain boundaries are continuous does not break a covalent bond at the crystal grain boundary. Therefore, the stress concentration that causes defects in the crystal grain boundaries, which occurs in polycrystalline silicon obtained by crystallization without using metal, does not occur, and as a result, the fracture stress is higher than that of polycrystalline silicon formed without using metal. Get higher.

  Polycrystalline silicon with continuous crystal grain boundaries has high electron mobility, and is therefore suitable as a material for controlling a microstructure with electrostatic force. Furthermore, since the structural layer includes a metal element that promotes crystallization and has conductivity, it is suitable for the microelectromechanical device of the present invention that controls the structure with electrostatic force. Needless to say, a polycrystalline silicon layer formed without using metal may be applied to the structural layer in the case where the microstructure is controlled by electromagnetic force.

  When nickel is used as the metal, nickel silicide can be formed in the silicon layer. Silicon alloys such as nickel silicide are generally known to have high mechanical strength. Therefore, by selectively leaving the metal used in the heat treatment in the whole or a part of the silicon layer and performing an appropriate heat treatment, a microstructure that is harder and has higher conductivity can be formed.

  By laminating the layer having nickel silicide (nickel silicide layer) leaving the metal used for crystallization as described above and the polycrystalline silicon layer, a flexible structure layer having excellent conductivity can be obtained. Further, by stacking an amorphous silicon layer and a nickel silicide layer, a hard layer having excellent conductivity can be obtained.

  Such a silicide layer can be formed of tungsten, titanium, molybdenum, tantalum, cobalt, or platinum in addition to nickel. A tungsten silicide layer, a titanium silicide layer, a molybdenum silicide layer, a tantalum silicide layer, a cobalt silicide layer, and a platinum silicide layer are formed. Among these, cobalt and platinum can also be used as a metal for lowering the heating temperature.

  The structural layer 108 formed by such a process can be used in a state having a metal.

  However, since the metal used for promoting crystallization becomes a contamination source of the microelectromechanical device, it is better to remove it after crystallization. In this case, after crystallization by heat treatment or laser irradiation, a layer serving as a gettering sink is formed over the silicon layer and heated, whereby the metal element can be moved to the gettering sink. As the gettering sink, a polycrystalline semiconductor layer or a semiconductor layer to which an impurity is added can be used. For example, a polycrystalline semiconductor layer to which an inert element such as argon is added can be formed over the semiconductor layer, and this can be used as a gettering sink. By adding an inert element, the polycrystalline semiconductor layer can be strained, and the metal element can be efficiently captured by the strain. In addition, a metal can be captured by forming a semiconductor layer to which an element such as phosphorus (P) is added.

  When the structure layer needs to be conductive, an impurity element such as phosphorus (P), arsenic (As), or boron (B) can be added after removing the metal. The structure having conductivity is suitable for the microelectromechanical device of the present invention controlled by electrostatic force.

  The structural layer may have a laminated structure in order to obtain a necessary thickness. For example, a polycrystalline silicon layer can be formed by stacking by repeating formation of an amorphous silicon layer and crystallization by heat treatment. By this heat treatment, stress in the previously formed polycrystalline silicon layer can be relieved, and film peeling and substrate deformation can be prevented. In order to further relieve the stress in the film, the process can be repeated including the etching of the silicon layer. Such a formation method including etching in the process is suitable when a material having a large internal stress is used for the structural layer.

  As described above, when crystallization is performed using a metal, crystallization can be performed at a lower temperature than crystallization performed without using a metal, so that a selection range of a substrate over which a microstructure is formed is widened. For example, when the semiconductor layer is crystallized only by heating, it is necessary to perform heating for about 1 hour at a temperature of about 1000 ° C. In this case, a glass substrate cannot be used. However, it is possible to use a glass substrate having a strain point of 593 ° C. by crystallization using the above metal as in this embodiment mode.

(Embodiment 3)
In the case where the microstructure 122 is moved by an electrostatic force, a lower electrode that can be used as a common electrode, a control electrode, or the like is preferably formed below the base layer. Therefore, in this embodiment mode, a microelectromechanical device having a lower electrode will be described.

  In the case where the microstructure 122 is moved by an electrostatic force, a conductive layer 123 that can be used as a common electrode, a control electrode, or the like is preferably formed below the base layer 102 (see FIG. 9). In the case where the base layer 102 has a stacked structure, the conductive layer 123 can be formed between the base layers 102. The conductive layer 123 is formed by a CVD method or the like using a metal such as tungsten or a conductive substance as a material. Further, the conductive layer 123 may be etched into a predetermined shape as necessary to form a pattern.

  This embodiment mode can be freely combined with Embodiment Mode 1 and Embodiment Mode 2.

(Embodiment 4)
In the present invention, silicon and silicon compounds having various properties can be stacked on the microstructure. The silicon layers having various properties have different properties such as strength by selecting any one of amorphous, microcrystalline, and polycrystalline crystal structures. Furthermore, even if it is polycrystalline, it becomes a silicon layer having a difference in properties depending on the crystal direction. Thus, in this embodiment, a structural example of a semiconductor layer used for the structural layer is described.

  As shown in FIG. 5, silicon or silicon compounds having different crystal structures can be stacked. FIG. 5A shows the case where an amorphous silicon layer 150, a polycrystalline silicon layer 151, and a layer 152 having nickel silicide are stacked over an insulating substrate 101. In the present invention, the layers constituting the structure can be selected and stacked. In addition, since the stacked structure can be easily formed, it is easy to form the structural layer 108 having desired properties.

  Silicon alloys such as nickel silicide are generally known to have high mechanical strength. By selectively leaving the metal used for crystallization of the semiconductor layer entirely or partially in the semiconductor layer and applying an appropriate heat treatment, a structure having high mechanical strength and high conductivity can be formed. it can.

  Crystallization using a metal as described above can also be partially performed by selectively applying a metal. For example, the metal can be applied and crystallized only in the portion of the structural layer 108 where the first sacrificial layer 103 is present.

  The crystallization as described above can be partially performed by selectively irradiating a laser beam. For example, only the portion 154 of the structural layer 108 under which the first sacrificial layer 103 is located can be crystallized. Further, as shown in FIG. 5B, by changing the laser beam irradiation conditions, it is possible to leave the amorphous silicon only in the column portion 155 of the beam structure and to crystallize the beam portion. .

  By partially crystallizing as described above, various materials can be combined. For example, only the portion to be driven can be crystallized to increase toughness.

  As the other structural layers, a layer having polycrystalline silicon as described in Embodiment Mode 2 and a layer having amorphous silicon can be stacked.

  Further, by laminating a layer in which metal is left in polycrystalline silicon and a layer having polycrystalline silicon, a flexible material with excellent conductivity can be obtained.

  Alternatively, a layer including amorphous silicon and a layer including silicide may be stacked. As a result, it is excellent in conductivity and can be hardened.

  The balance between flexibility and hardness can be determined by the ratio of the thicknesses of the layers to be stacked. This is because even if breakdown occurs due to crystal defects in the amorphous silicon layer, the breakdown does not easily propagate to the polycrystalline silicon layer having high crystallinity, and it is considered that the breakdown stops there.

  Further, when laser crystallization is performed using metal, the crystal growth direction of silicon proceeds in a direction perpendicular to the substrate, and when laser crystallization is performed without using metal, the crystal growth direction proceeds in a direction parallel to the substrate. . By laminating these two or more layers, a material having further excellent toughness can be obtained. Since films with different crystal directions are stacked, even if a crack or the like occurs in one layer, the crack does not easily propagate to the other layer with a different crystal direction, resulting in the formation of a high-strength structural layer 108 can do.

  The amorphous silicon layer, the polycrystalline silicon layer, or the layer having nickel silicide as described above can be stacked by repeatedly forming a film in order to obtain a necessary thickness. For example, formation of a layer containing amorphous silicon and heating may be repeated. Further, in order to relieve the stress in the film, it may be repeated including etching. The combination of film formation and crystallization can be freely selected from the above examples and combined.

  By stacking the semiconductor layers in this manner, a structural layer having both flexibility and hardness can be obtained.

  This embodiment mode can be freely combined with Embodiment Modes 1 to 3.

(Embodiment 5)
In this embodiment, a method for forming a microstructure and a semiconductor element over the same surface will be described with reference to drawings, which is different from that in Embodiment 1. In the drawing, a top view is shown on the upper side, and a sectional view in the top view OP or QR is shown on the lower side.

  First, as in Embodiment Mode 1, the base layer 202 is formed over the insulating substrate 201 (see FIGS. 6A-1 and 6A-2).

  Next, a semiconductor layer 203 included in the microstructure and an active layer 204 included in the semiconductor element are formed and etched into a predetermined shape (see FIGS. 6A-1 and 6A-2). The semiconductor layer 203 and the active layer 204 can be formed similarly to Embodiment Mode 1. For the semiconductor layer 203 and the active layer 204, amorphous silicon or crystalline silicon can be used.

  Next, as in Embodiment Mode 1, an insulating layer 205 is formed over the semiconductor layer 203 and the active layer 204 (see FIGS. 6A-1 and 6A-2). The insulating layer 205 functions as a gate insulating layer of the semiconductor element. Further, as in Embodiment Mode 1, the insulating layer and the like can be formed by high density plasma.

  Next, a first sacrificial layer 206 is formed over the semiconductor layer 203 included in the microstructure and etched into a predetermined shape (see FIGS. 6B-1 and 6B-2). For the first sacrificial layer 206, a resin material such as an epoxy resin, an acrylic resin, a phenol resin, a novolac resin, a melamine resin, or a urethane resin can be used. Also, benzocyclobutene, parylene, fluorinated arylene ether, organic materials such as permeable polyimide, compound materials made by polymerization of siloxane polymers, composition materials containing water-soluble homopolymers and water-soluble copolymers You may form using.

  For the first sacrificial layer 206, a commercially available resist material containing a photosensitizer may be used. For example, a novolak resin that is a typical positive resist, a naphthoquinone diazide compound that is a photosensitizer, and a base resin that is a negative resist. Diphenylsilanediol and acid generators may be used.

  Regardless of which material is used, the surface tension and viscosity are adjusted by adjusting the concentration of the solvent mixed with the material or adding a surfactant or the like. For example, the surface tension of the solvent can be lowered by adding a surfactant.

  After the material as described above is formed, the first sacrificial layer 206 can be formed by etching to have a predetermined shape. For the etching, a photolithography method can be used. Alternatively, a mask may be drawn using a droplet discharge device such as an inkjet, and the first sacrificial layer 206 may be etched using the mask. By drawing a mask using such a droplet discharge device, it is possible to eliminate exposure and development steps and mask material that are necessary in the photolithography method.

  The thickness of the first sacrificial layer 206 is determined in consideration of the material of the first sacrificial layer 206, the structure and operation method of the structure, the sacrificial layer etching method, and the like. For example, if the first sacrificial layer 206 is too thin, a phenomenon occurs in which the etching agent does not diffuse and is not etched, or the structural layer is buckled after etching.

  When the structure is operated with an electrostatic force, if the first sacrificial layer 206 is too thick, the structure cannot be driven. For example, when the structure is driven by an electrostatic force generated between the lower conductive layer and the structure layer, the thickness of the first sacrificial layer 206 is 0.5 μm to 3 μm, preferably 1 μm to 2.5 μm. The following is recommended.

  Next, a first conductive layer 207 is formed over the first sacrificial layer 206 and the insulating layer 205, and a second conductive layer 208 is formed thereover (FIGS. 6C-1 and 6C). -2)). The conductive layer can be sequentially formed by a sputtering method, a CVD method, or the like.

  The first conductive layer 207 and the second conductive layer 208 are formed using a metal element selected from Ta, W, Ti, Mo, Al, and Cu, or an alloy material or compound material containing the metal element as a main component. The thickness may be about 50 nm to 2 μm. Alternatively, a semiconductor layer typified by a polycrystalline silicon layer doped with an impurity element such as phosphorus, or an AgPdCu alloy may be used as the conductive layer.

  Next, a mask 209 is formed in a predetermined shape (see FIGS. 6C-1 and C-2). The mask 209 is formed using the same material as the first sacrificial layer 206 or a material that can be processed in the same process.

The first conductive layer 207 and the second conductive layer 208 are etched using the mask 209. Specifically, the second sacrificial layer 211 and the second conductive layer 208 are formed by using an ICP (Inductively Coupled Plasma) etching method. At this time, the cross section may be processed to be vertical by anisotropic etching, or may be processed to have a tapered shape. The structural layer 210 and the first conductive layer 207 are desired by determining the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the substrate-side electrode, the electrode temperature on the substrate side, etc.) Can be etched (see FIGS. 7A-1 and 7A-2). As an etching _gas, it is possible to use Cl _2, BCl 3, a chlorine-based _gas, a fluorine-based gas typified by CF 4, SF ₆ or NF ₃ typified like SiCl ₄ or CCl _4. Alternatively, ashing may be performed using O ₂ . Further, a rare gas may be mixed.

  Next, the first sacrificial layer 206 and the mask 209 are peeled off at the same time to form the structural layer 210, the second sacrificial layer 211, and the gate electrode layer 212 (FIGS. 7A-1 and 7A-2). reference). The gate electrode layer 212 includes a first conductive layer 207 and a second conductive layer 208.

  As described above, the first sacrificial layer 206 is etched during the removal process of the mask 209. This makes it possible to omit the process only for the etching of the sacrificial layer, simplify the process, and reduce the damage to the structural layer 210 and the semiconductor element. It is the same.

  The conductive layer having a stacked structure is not limited to a two-layer structure, and may have a three-layer structure. For example, tungsten, tungsten nitride, or the like is used for the first layer, an alloy of aluminum and silicon (Al—Si), an alloy of aluminum and titanium (Al—Ti) is used for the second layer, and titanium nitride or titanium is used for the third layer. Or the like, and a three-layer structure in which layers are sequentially stacked may be used. In this case, the first layer and the second layer can be the structure layer of the microstructure, and the third layer can be the second sacrificial layer. Alternatively, the first layer can be a structural layer, and the second and third layers can be sacrificial layers. Of course, the conductive layer may have a single layer structure.

  Next, as in the first embodiment, an impurity element is added to the active layer 204 constituting the semiconductor element to form an N-type impurity region and a P-type impurity region. Thereafter, heat treatment such as activation of the impurity regions and dehydrogenation may be performed.

  Similarly to Embodiment 1, when the gate electrode layer 212 is formed using a single-layer structure conductive layer or when the stacked structure conductive layer is not etched into a tapered shape, an insulating layer is formed over the gate electrode layer 212. A sidewall in contact with the side surface of the gate electrode layer 212 can be formed by forming and anisotropically etching the insulating layer.

  Through the above steps, an N-type semiconductor element 213 and a P-type semiconductor element 214 are formed (see FIGS. 7B-1 and 7B-2). At this time, an impurity region is formed in a region not covered with the structural layer 210 and the second sacrificial layer 211 in the semiconductor layer 203 included in the microstructure.

  Subsequently, an interlayer insulating layer 215 is formed so as to cover the whole (see FIGS. 7B-1 and 7B-2). The interlayer insulating layer 215 can be formed using an insulating inorganic material or organic material. The inorganic material or the organic material is the same as that in the first embodiment.

  Next, as in Embodiment Mode 1, the interlayer insulating layer 215 and the insulating layer 205 are sequentially etched to form a contact hole 216 for connecting a wiring to the semiconductor layer 203, the active layer 204, and the structural layer 210. The contact hole 216 is filled with a material for forming a conductive layer, a third conductive layer 217 is formed so as to cover the interlayer insulating layer 215, and etched into a predetermined shape, whereby a source electrode, a drain electrode, and an electric circuit Are formed (see FIGS. 7B-1 and 7B-2).

  In the case where the third conductive layer 217 forms a pattern having corners, the corner portions are preferably etched into a rounded shape.

  Next, the interlayer insulating layer 215 is etched to form an opening 218. The opening 218 is formed to expose the second sacrificial layer 211 (see FIGS. 8A-1 and 8A-2). For the etching process, a dry etching method or a wet etching method is used.

  In this embodiment mode, the opening 218 is formed by a dry etching method. The opening 218 is opened to remove the second sacrificial layer 211 by etching. Accordingly, the diameter of the opening 218 is determined so that the etchant flows and diffuses.

  The opening 218 can be formed to have a large diameter so that the second sacrifice layer 211 can be easily etched. That is, it is not necessary to form a small hole as described above, and the opening 218 is formed so that the entire sacrificial layer is exposed leaving a portion where the interlayer insulating layer 215 is necessary (for example, on the semiconductor layer 203 and the active layer 204). Can be formed.

  Next, the second sacrifice layer 211 is removed by etching (see FIGS. 8B-1 and 8B-2). Note that FIGS. 8B-1 and 8B-2 illustrate only a microstructure. The sacrificial layer is etched away through the opening 218 with an etching solution or etching gas suitable for the material of the sacrificial layer.

For example, when the second sacrificial layer 211 is tungsten (W), it is immersed in a solution in which 28% by weight of ammonia and 31% by weight of hydrogen peroxide are mixed at a ratio of 1: 2 for about 20 minutes. When the second sacrificial layer 211 is silicon dioxide, buffered hydrofluoric acid in which ammonium fluoride is mixed at a ratio of 7 to the 49 wt% hydrofluoric acid aqueous solution 1 is used. When the second sacrificial layer 211 is silicon, alkali metal hydroxide such as phosphoric acid, KOH, NaOH, CsOH, NH ₄ OH, hydrazine, EPD (a mixture of ethylenediamine, pyrocatechol, water), TMAH, IPA NMD3 solution or the like is used. When drying after wet etching, in order to prevent the microstructure from buckling due to capillary action, rinse with a low-viscosity organic solvent (for example, cyclohexane), or dry under conditions of low temperature and low pressure. It is done by a combination of both.

Further, the second sacrificial layer 211 can be dry-etched using F ₂ or XeF ₂ under a high pressure condition such as atmospheric pressure. In order to prevent buckling of the microstructure due to capillary action, plasma treatment can be performed so that the surface of the microstructure has water repellency. With the use of such a process, the second sacrifice layer 211 can be removed and the microstructure 219 can be formed.

  As in this embodiment mode, by forming a structure layer of a microstructure body using a conductive layer that forms a gate electrode, a microstructure body with high mechanical strength and a flexible movable portion can be formed.

(Embodiment 6)
In the present invention, a microstructure and a semiconductor element having various structures can be formed by changing part of the process or adding another process.

  For example, in the fifth embodiment, the second sacrificial layer 211 is removed by etching and only the conductive layer constituting the first conductive layer 207 is used as the structural layer 210. However, the second sacrificial layer 211 is not removed by etching. It is also possible to form a microstructure. In this case, for example, in Embodiment 5, the opening 218 formed to etch away the second sacrificial layer 211 is unnecessary.

  Thus, the present invention can be applied to many processes. That is, the present invention is not limited to other configurations as long as the sacrificial layer can be removed in the mask removing step.

  Note that this embodiment mode can be freely combined with Embodiment Modes 1 to 5.

(Embodiment 7)
In this embodiment, a mode in which the counter substrate 221 is attached to a microelectromechanical device formed over the insulating substrate 101 in order to protect the microstructure 219 is described.

  As shown in FIG. 10, in the case where the counter substrate 221 is attached, after the third conductive layer 217 is formed, the second insulating layer 222 is formed over the insulating substrate 101 and etched into a predetermined shape. (In this embodiment, the interlayer insulating layer 215 is a first insulating layer.) At this time, the second insulating layer is etched so that the sacrificial layer and the structural layer to be a microstructure are exposed. Thereafter, the sacrificial layer is removed to form a microstructure.

  Next, the counter substrate 221 for bonding is described. In the step of attaching the counter substrate 221, a third insulating layer 223 is formed in a portion facing the second insulating layer 222 formed over the insulating substrate 101 in order to prevent the microstructure from being destroyed ( (See FIG. 10A). Since the third insulating layer 223 is not formed in the portion facing the microstructure formed over the insulating substrate 101 and a space is formed between the substrates, the insulating substrate 101 and the counter substrate 221 are bonded to each other. The microstructures are not destroyed.

  In addition, the counter substrate 221 can be formed with a fourth conductive layer 224 etched into a predetermined shape, an antenna, or the like, which forms a circuit of a microelectromechanical device (see FIG. 10B). In this case, on the second insulating layer 222 formed on the insulating substrate 101, a second wiring (fifth conductive layer 225) for connecting to the first wiring (third conductive layer 217) is provided. ). Then, the insulating substrate 101 and the counter substrate 221 can be attached so that the fifth conductive layer 225 and the fourth conductive layer 224 are electrically connected.

  At this time, as described above, in order to protect the microstructure 219 formed over the insulating substrate 101, the portion that does not face the microstructure and the connection between the second conductive layer and the third conductive layer are used. The portion preferably forms a third insulating layer 223 so that the counter substrate 221 does not come into contact with the microstructure 219. In addition, the fourth conductive layer 224 may be formed only on the third insulating layer 223, or may be formed on the upper and lower portions of the third insulating layer 223 so that they are electrically connected. (Refer to FIG. 10B).

  Note that this embodiment mode can be freely combined with Embodiment Modes 1 to 6.

(Embodiment 8)
In this embodiment, a method of peeling the insulating substrate 101 and attaching it to another substrate or an object will be described.

  In the case where the microelectromechanical device is peeled from the insulating substrate 101, the peeling layer 226 is formed when the base layer 102 is formed (see FIG. 11A). The release layer 226 can be formed below or between the stacked base layers. Then, after the third conductive layer 217 is formed as described above, the micro electro mechanical device is peeled from the substrate before the opening 218 for etching the sacrifice layer is formed.

  There are various methods for peeling, and an example is shown here. First, an opening 227 is formed so that the peeling layer 226 is exposed, an etchant is introduced into the opening 227, and the peeling layer 226 is partially removed (see FIG. 11A). Next, a substrate 228 for separation is bonded from the upper surface direction of the insulating substrate 101, and the semiconductor element and the microstructure are separated from the insulating substrate 101 with the separation layer 226 as a boundary, and transferred to the substrate for separation ( (See FIG. 11B). Next, the flexible substrate 229 is bonded to the side where the semiconductor element and the microstructure are in contact with the insulating substrate 101. Then, the substrate can be transferred by peeling off the substrate 228 for separation attached from the upper surface direction (see FIG. 11C). In this manner, a microelectromechanical device can be manufactured on a glass substrate, and then bonded to a flexible substrate such as plastic that is thinner and softer than glass.

  Then, an opening is formed so that the second sacrificial layer 211 is exposed, and the second sacrificial layer 211 is removed by etching, whereby a microstructure is formed. In addition, a protective film may be formed over the wiring in order to protect the third conductive layer 217 and the like at the time of peeling.

  Further, when it is necessary to protect the microstructure, the counter substrate 221 described in Embodiment 7 can be used as a substrate for separation.

  In this embodiment mode, the method for transferring the semiconductor element and the microstructure to the flexible substrate 229 after etching the separation layer 226 from the opening 227 is described; however, the present invention is not limited to this. For example, after the separation layer 226 is removed only by an etching process, the substrate 228 is transferred to the flexible substrate 229, or the substrate 228 for separation is attached from the upper surface of the insulating substrate 101 without providing the opening 227. In addition, there is a method of peeling the microstructure from the insulating substrate 101. Further, there is a method of polishing the insulating substrate 101 from the back surface to obtain a semiconductor element and a microstructure, and these methods can be appropriately combined. If the process of transferring to the flexible substrate 229 is used, the insulating substrate 101 can be reused. However, the case where the insulating substrate 101 is polished from the back surface is excluded.

  As described above, the semiconductor element and the microstructure formed over the insulating substrate 101 are peeled off and attached to the flexible substrate 229, whereby a thin, soft, and small microelectromechanical device can be manufactured. .

  Note that this embodiment can be freely combined with the other embodiments described above.

(Embodiment 9)
In this embodiment mode, a structural example of a micro electro mechanical device of the present invention will be described with reference to the drawings.

  FIG. 12 shows a conceptual diagram of the microelectromechanical device of the present invention. The microelectromechanical device 11 of the present invention has an electric circuit portion 12 having a semiconductor element and a structure portion 13 constituted by a microstructure. The electric circuit unit 12 includes a control circuit 14 that controls the microstructure, an interface 15 that communicates with the external control device 10, and the like. In addition, the structure body portion 13 includes a sensor 16, an actuator 17, a switch, and the like by a microstructure.

  An actuator is a component that converts a signal (mainly an electrical signal) into a physical quantity.

  The electric circuit unit 12 can also include a central processing unit for processing information obtained by the structure unit 13.

  The external control device 10 transmits a signal for controlling the microelectromechanical device 11, receives information obtained by the microelectromechanical device 11, supplies drive power to the microelectromechanical device 11, and the like.

  The present invention is not limited to the above configuration. That is, the present invention is characterized in that a micro electromechanical device has an electric circuit that has a semiconductor element and controls the micro structure, and a micro structure that is controlled by the electric circuit.

  Conventionally, when handling minute objects such as millimeters or less, first the structure of a minute object is enlarged, and a person or computer obtains the information to determine information processing and operation, and then reduces the operation. It needed a process of communicating to minute objects.

  However, the microelectromechanical device of the present invention described above can be operated only by a human or computer transmitting a high-level conceptual command. That is, when a person or a computer determines a purpose and transmits a command, the microelectromechanical device can operate by obtaining information on the object using a sensor or the like to perform information processing.

  In the above example, it is assumed that the object is very small. This includes, for example, a case where the object itself has a size of a meter unit, but a signal emitted from the object is minute (for example, a minute change in light or pressure).

  The microelectromechanical device of the present invention belongs to the field of micromachines and has a size of micrometer to millimeter. Further, when manufactured to be incorporated as a part of a certain mechanical device, it may have a metric size so that it can be easily handled during assembly.

(Embodiment 10)
In this embodiment, an example of the microelectromechanical device described in the above embodiment will be described. The microelectromechanical device of the present invention can include a sensor device in which a detection element is formed using a microstructure.

  FIG. 13A illustrates a structure of a sensor device 301 which is an embodiment of the microelectromechanical device of the present invention. The sensor device 301 of this embodiment includes an electric circuit portion 302 having a semiconductor element and a structure portion 303 which is formed using a microstructure.

  The structure body 303 includes a detection element 304 configured by a microstructure that detects external pressure, substance concentration, gas or liquid flow rate, and the like.

  The electric circuit unit 302 includes an A / D conversion circuit 305, a control circuit 306, an interface 307, a memory 308, and the like.

  The A / D conversion circuit 305 converts information transmitted from the detection element 304 into a digital signal. The control circuit 306 controls the A / D conversion circuit such as storing the digital signal in a memory. The interface 307 receives drive power from the external control device 310, receives a control signal, transmits sensing information to the external control device 310, and the like. The memory 308 stores sensing information, information unique to the sensor device, and the like.

  In addition, the electric circuit unit 302 may include an amplifier circuit that amplifies a signal received from the structure unit 303, a central processing circuit for processing information obtained by the structure unit 303, and the like.

  The external control device 310 performs operations such as transmission of a signal for controlling the sensor device 301, reception of information obtained by the sensor device 301, or supply of driving power to the sensor device 301.

  The sensor device 301 having the above-described configuration can detect external pressure, substance concentration, gas or liquid flow rate, temperature, and the like. In addition, since this sensor device has a central processing arithmetic circuit, it is possible to realize a sensor device that processes detected information in the sensor device and generates and outputs a control signal for controlling other devices. It is.

  FIG. 13B illustrates an example of a structure of the detection element 304 with a cross-sectional view. A sensing element 304 illustrated in FIG. 13 includes a second conductive layer 321 under a base layer, and has a capacitor whose structural layer becomes the first conductive layer 320. Further, since the first conductive layer 320 is moved by receiving an electrostatic force, pressure, or the like, the sensing element 304 is a variable capacitor in which the distance between the first conductive layer and the second conductive layer changes. .

  By using this structure, the detection element 304 can be used as a pressure detection element in which the first conductive layer 320 is moved by pressure.

  In the detection element 304 illustrated in FIG. 13B, the first conductive layer 320 can be formed by stacking two kinds of substances having different coefficients of thermal expansion. In this case, since the first conductive layer 320 moves due to a temperature change, the detection element 304 can be used as a temperature detection element.

  The present invention is not limited to the above configuration. In other words, in this embodiment, the sensor device includes an electric circuit that has a semiconductor element and controls the microstructure, and a detection element that detects some physical quantity, the microstructure being controlled by the electric circuit. It is characterized by having. Further, this sensor device is manufactured using the method described in the above embodiment.

  Note that this embodiment mode can be freely combined with the other embodiment modes described above.

(Embodiment 11)
In this embodiment, a specific example of the microelectromechanical device described in the above embodiment will be described. The microelectromechanical device of the present invention can constitute a memory device having a microstructure in a memory element. In this embodiment, an example of a memory device in which a peripheral circuit such as a decoder is formed using a semiconductor element and the inside of a memory cell is formed using a microstructure.

  FIG. 14 illustrates a configuration of a memory device 401 which is an embodiment of the microelectromechanical device of the present invention.

  The storage device 401 includes a memory cell array 402, a decoder 403, a selector 404, and a read / write circuit 405. The decoder 403 and the selector 404 may be configured using a known technique.

  The memory cell 409 includes, for example, a switch element 407 and a storage element 408 that control the storage element 408. A memory device 401 described in this embodiment is characterized in that the switch element 407 and the memory element 408 are formed of a microstructure.

  FIG. 15 shows a configuration example of the memory cell 409. 15A is a circuit diagram of the memory cell 409, and FIG. 15B is a cross-sectional view of the structure.

  As shown in FIG. 15A, the memory cell 409 includes a switch element 407 including a transistor 410 and a memory element 408 including a microstructure.

  As shown in FIG. 15B, the memory element 408 is a microstructure formed using the method described in Embodiment 1 or 2. The memory element 408 is a capacitor having a first conductive layer under a base layer and a structural layer serving as a second conductive layer. The second conductive layer is connected to one of the two high concentration impurity regions of the transistor 410.

  The first conductive layer is connected in common to the memory elements 408 of all the memory cells 409 included in the memory device 401. The first conductive layer applies a common potential to all the memory elements at the time of reading and writing of the memory device, and may be referred to as a common electrode 411 in this specification.

  FIG. 16 illustrates an example of a memory cell 409 including a switch element 407 and a memory element 408 which are formed using a microstructure. FIG. 16 is a perspective view showing the structure of the memory cell 409.

  The switch element 407 and the memory element 408 are formed using the method described in Embodiment Mode 1 or Embodiment Mode 2. The switch element 407 is a microstructure that functions as a switch having a structure in which cantilever beams are combined, and the memory element 408 is a microstructure that functions as a capacitor having a beam structure.

  Here, the structure of the switch element 407 will be described. In the switch element 407, the sacrificial layer 420 and the structural layer 421 are stacked on the substrate, and the bottom of the movable cantilever 422 may be etched.

  The switch element 407 controls whether or not the cantilever beam 422 and the conductive layer 424 are electrically connected by the control electrode 423. A specific operation will be described. The control electrode 423 is always charged with a positive voltage. When a positive voltage is input to the cantilever beam 422, the control electrode 423 and the cantilever beam 422 are repelled by electrostatic force, and switching is performed by the cantilever beam 422 being in contact with the conductive layer 424.

  A switch formed using a microstructure has an advantage that a signal transmission path (here, the cantilever beam 422 and the conductive layer 424) through the switch is completely insulated when the switch is off. Furthermore, there is an advantage that a control system (here, the control electrode 423) for controlling on / off of the switch and a signal transmission path (here, the cantilever 422 and the conductive layer 424) can be insulated.

  The storage device having the above structure can be used as a volatile memory, typically a DRAM (Dynamic Random Access Memory). For the peripheral circuit configuration and driving method, a known technique may be used.

  Since the scaling law is applied to the microstructure constituting the memory cell by forming it in a minute size (for example, in units of μm), there is an advantage that the response speed of the switch is fast and a large force is not required for driving. . Further, by forming the switch element 407 with a microstructure, it is possible to completely insulate the memory element 408 that is not selected, and the memory device 401 with low power consumption can be realized.

  Note that this embodiment can be freely combined with the other embodiments described above.

(Embodiment 12)
In this embodiment, an example of the microelectromechanical device described in the above embodiment will be described.

  The microelectromechanical device of the present invention can be configured as, for example, a separation device that separates a specific substance from a mixture. This will be described below.

  FIG. 17 shows a basic configuration example of the sorting apparatus according to the present embodiment. Here, as an example of the separation apparatus, a separation apparatus that separates a gas of a specific substance from a mixed gas of two or more kinds of substances will be described.

  The sorting device 501 is roughly divided into an electric circuit portion 502 and a structure portion 503, and the structure portion 503 includes a detection element 504 and a plurality of opening / closing means 505. The electric circuit unit 502 includes a signal processing unit 506, an opening / closing control unit 507, an information storage unit 508, and a communication unit 509.

  Here, the detection element 504 and the opening / closing means 505 are constituted by a micro structure having a size of about a gas molecule to be sorted. One detection element 504 is provided adjacent to one opening / closing means 505, and detects what kind of substance exists near the opening / closing means 505. The opening / closing means 505 has a passage opening, receives a control signal from the opening / closing control means 507, and opens the passage opening and allows it to pass only when a specific substance exists nearby.

  The signal processing unit 506 processes the signal transmitted from the detection element 504 by amplification, A / D conversion, and the like, and transmits the processed signal to the opening / closing control unit 507. The opening / closing control means 507 controls the opening / closing means 505 based on the signal transmitted from the detection element 504. The information storage unit 508 stores a program file for operating the sorting device 501, information unique to the sorting device 501, and the like. A communication unit 509 communicates with an external control device 510.

  The external control device 510 includes a communication unit 511, an information processing unit 512, a display unit 513, an input unit 514, and the like.

  The communication unit 511 transmits a signal for controlling the sorting device 501, receives information obtained by the sorting device 501, supplies driving power to the sorting device 501, and the like. The information processing unit 512 performs processing of information received from the sorting device 501, processing for transmitting information input from the input unit to the sorting device 501, and the like. The display unit 513 displays information obtained from the sorting device 501, the operation status of the sorting device 501, and the like. The input means 514 provides a means for inputting information.

  FIG. 17B shows an example of a form in which the sorting device 501 is used. The separation device 501 having the above configuration is installed between the mixture system 520 and the specific product system 521. When the sorting device 501 receives information such as which material is to be sorted from the external control device 510, the sensing device 504 detects what kind of material is present in the vicinity of the opening / closing means 505. Next, the signal processing means 506 processes the detection signal and transmits it to the open / close control means 507. The opening / closing control means 507 controls the opening / closing means 505 so that the passage opening is opened only when there is a substance to be separated in the immediate vicinity of the opening / closing means 505. The opening / closing means 505 allows only the substances to be separated to pass through the passage port under the control of the opening / closing control means 507.

  By the above operation, the separation device 501 can separate the gas of the specific substance from two or more kinds of mixed gases. Further, the separation device 501 is not limited to only gas separation. By using the above configuration, for example, it is possible to configure as a device for sorting specific cells. As an example, control can be performed so that only cells that fluoresce when irradiated with ultraviolet light are separated. Furthermore, it is possible to realize an apparatus having functions such as separation of only minute grain boundaries, for example, particles containing radioactive substances, and separation of only magnetic ore particles.

  The present invention can provide a separation system that includes a separation device 501, a mixture system 520, a specific product system 521, and an external control device 510, and separates a specific substance from the mixture.

  Note that this embodiment can be freely combined with the other embodiments described above.

4A and 4B illustrate a method for manufacturing a microelectromechanical device of the present invention. 4A and 4B illustrate a method for manufacturing a microelectromechanical device of the present invention. 4A and 4B illustrate a method for manufacturing a microelectromechanical device of the present invention. 4A and 4B illustrate a method for manufacturing a microelectromechanical device of the present invention. 4A and 4B illustrate a method for manufacturing a microelectromechanical device of the present invention. 4A and 4B illustrate a method for manufacturing a microelectromechanical device of the present invention. 4A and 4B illustrate a method for manufacturing a microelectromechanical device of the present invention. 4A and 4B illustrate a method for manufacturing a microelectromechanical device of the present invention. FIG. 6 illustrates one embodiment of a microelectromechanical device of the present invention. 4A and 4B illustrate a method for manufacturing a microelectromechanical device of the present invention. 4A and 4B illustrate a method for manufacturing a microelectromechanical device of the present invention. 1A and 1B illustrate a microelectromechanical device of the present invention. FIG. 6 illustrates one embodiment of a microelectromechanical device of the present invention. FIG. 6 illustrates one embodiment of a microelectromechanical device of the present invention. FIG. 9 illustrates a structure of a memory cell. FIG. 9 illustrates a structure of a memory cell. FIG. 6 illustrates one embodiment of a microelectromechanical device of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Control apparatus 11 Microelectromechanical apparatus 12 Electrical circuit part 13 Structure part 14 Control circuit 15 Interface 16 Sensor 17 Actuator 101 Insulating substrate 102 Underlayer 103 First sacrificial layer 104 Semiconductor layer 105 Mask 107 Active layer 108 Structural layer 109 Insulating layer 110 First conductive layer 111 Second sacrificial layer 112 P-type impurity region 113 N-type impurity region 114 Side wall 115 N-type semiconductor element 116 P-type semiconductor element 117 High-concentration N-type impurity region 118 Interlayer insulating layer 119 Contact hole 120 Second conductive layer 121 Opening portion 122 Microstructure 123 Conductive layer 150 Amorphous silicon layer 151 Polycrystalline silicon layer 152 Layer 154 having nickel silicide The portion 155 with the first sacrificial layer 103 155 Column portion 201 Insulating substrate 202 Underlayer 203 Semiconductor layer 204 Active layer 205 Insulating layer 206 First sacrificial layer 207 First conductive layer 208 Second conductive layer 209 Mask 210 Structure layer 211 Second sacrificial layer 212 Gate electrode layer 213 N-type semiconductor element 214 P-type Semiconductor element 215 Interlayer insulating layer 216 Contact hole 217 Third conductive layer 218 Opening 219 Microstructure 221 Counter substrate 222 Second insulating layer 223 Third insulating layer 224 Fourth conductive layer 225 Fifth conductive layer 226 Release layer 227 Opening 228 Substrate 229 for peeling Flexible substrate 301 Sensor device 302 Electric circuit portion 303 Structure portion 304 Detection element 305 A / D conversion circuit 306 Control circuit 307 Interface 308 Memory 310 Control device 320 First Conductive layer 321 Second conductive layer 401 Memory device 402 Memory cell array 4 3 Decoder 404 Selector 405 Read / write circuit 407 Switch element 408 Memory element 409 Memory cell 410 Transistor 411 Common electrode 420 Sacrificial layer 421 Structure layer 422 Cantilever 423 Control electrode 424 Conductive layer 501 Sorting device 502 Electric circuit section 503 Structure section 504 Detection element 505 Opening / closing means 506 Signal processing means 507 Opening / closing control means 508 Information storage means 509 Communication means 510 Control device 511 Communication means 512 Information processing means 513 Display means 514 Input means 520 Mixture system 521 Specific object system

Claims (9)

A method for manufacturing a microelectromechanical device in which an active layer constituting a semiconductor element and a structural layer constituting a microstructure are respectively provided on the same substrate,
Selectively forming a sacrificial layer on the substrate,
On the substrate, a sacrificial layer and a semiconductor layer covering a portion constituting the semiconductor element are formed,
Wherein the semiconductor layer, selectively forming a second mask overlapping with the sacrificial layer and the first mask having no heavy Naru portion, and the sacrificial layer through the semiconductor layer,
The semiconductor layer is etched using the first mask and the second mask to form the active layer overlapping the first mask, and the structural layer overlapping the second mask is the sacrificial layer form shape over and to expose the part of the previous SL sacrificial layer,
A method for manufacturing a microelectromechanical device, wherein the first mask, the second mask , and the sacrificial layer are removed at the same time. A method for manufacturing a microelectromechanical device in which an active layer constituting a semiconductor element and a structural layer constituting a microstructure are respectively provided on the same substrate,
Selectively forming a first sacrificial layer on the substrate,
Forming a semiconductor layer covering the first sacrificial layer and a portion constituting the semiconductor element on the substrate;
Wherein the semiconductor layer, and selectively forming a second mask overlapping with the first mask, and the first sacrificial layer through the semiconductor layer without the first sacrificial layer and the heavy Naru portion,
The semiconductor layer is etched using the first mask and the second mask to form the active layer that overlaps the first mask, and the structural layer that overlaps the second mask is the first layer . form forms on the sacrificial layer, and to expose a part of the pre-Symbol first sacrificial layer,
Removing the first mask , the second mask , and the first sacrificial layer simultaneously;
Forming a second sacrificial layer on the structural layer;
Forming an insulating layer having an opening provided to expose the second sacrificial layer on the second sacrificial layer;
A method of manufacturing a microelectromechanical device, wherein the second sacrificial layer is removed using the opening. A method for manufacturing a microelectromechanical device in which an active layer constituting a semiconductor element and a structural layer constituting a microstructure are respectively provided on the same substrate,
To form an active layer constituting the semiconductor layer and the semiconductor element on the substrate,
Forming a sacrificial layer selectively on the semiconductor layer;
Forming a first conductive layer on the sacrificial layer , the semiconductor layer , and the active layer;
Selectively forming a first mask overlapping the sacrificial layer via the first conductive layer and a second mask overlapping the active layer via the first conductive layer;
The first mask and by etching the first conductive layer using the second mask, the structure layer is formed on the sacrificial layer, a second conductive layer formed on the active layer and, exposing a portion of the pre-Symbol sacrificial layer,
A method for manufacturing a microelectromechanical device, wherein the first mask, the second mask, and the sacrificial layer are simultaneously removed. In claim 2 ,
The method for manufacturing a microelectromechanical device, wherein the first mask, the second mask, and the first sacrificial layer are formed using the same material. In claim 1 or claim 3 ,
The method for manufacturing a microelectromechanical device, wherein the first mask, the second mask, and the sacrificial layer are formed using the same material. In claim 2 ,
A method of manufacturing a microelectromechanical device, wherein a plurality of the openings are formed in the insulating layer. In any one of Claims 1 thru | or 6 ,
A method for manufacturing a microelectromechanical device, wherein a silicon layer crystallized using a metal is used as the semiconductor layer. In any one of Claims 1 thru | or 6 ,
As the semiconductor layer, a silicon layer crystallized using a metal is used,
The method for manufacturing a microelectromechanical device, wherein the silicon layer includes a silicide including the metal. In any one of Claims 1 thru | or 6 ,
A method for manufacturing a microelectromechanical device, wherein a silicon layer crystallized using a metal and an amorphous silicon layer are used as the semiconductor layer.

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