JP4964430B2 - Semiconductor element forming substrate, epitaxial wafer, and semiconductor element and semiconductor device using them - Google Patents

Description

  The present invention relates to a semiconductor element forming substrate and an epitaxial wafer, and a semiconductor element and a semiconductor device using them.

In recent years, in order to achieve both the characteristics and productivity of a semiconductor epitaxial wafer, an epitaxial wafer in which a working layer such as InGaAs having a different lattice constant is formed on an inexpensive substrate such as a silicon substrate is manufactured. The need is increasing. For semiconductor epitaxial wafers, for example, electronic devices such as field effect transistors (FETs) and heterobipolar transistors (HBT), or optical devices such as light emitting diodes (LEDs), laser diodes (LDs), and light receiving elements are created. There are uses to do.
Below, the prior art regarding LED is mentioned as an example, and is demonstrated.
A lighting device using a light emitting diode (LED) having an advantage of small size and long life is expected, and since the use in the outdoors is increasing, further enhancement of brightness of the LED is desired.
FIG. 5 shows an example of a cross-sectional structure of a typical lattice-matching light emitting diode that has been conventionally used.
This light-emitting diode 30 uses a GaAs substrate 1 and has InAlGaP-based semiconductor layers 3 to 5 lattice-matched on the GaAs substrate 1. On the substrate 1 made of n-type GaAs having a lattice constant of 0.5653 nm, an In _0.5 Al _0.5 P crystal having a lattice constant of 0.5666 nm is first formed as the buffer layer 2 to a thickness of 1 μm, and the lower cladding layer N-type In _0.5 Al _0.5 P crystal having a thickness of 1 μm and a lattice constant of 0.5666 nm, and In _0.5 Al ₀ having a thickness of 1 μm and a lattice constant of 0.5663 nm as the light-emitting layer 4 _.25 Ga _0.25 P crystal and a double heterostructure consisting of three layers formed with a p-type In _0.5 Al _0.5 P crystal having a thickness of 1 μm and a lattice constant of 0.5666 nm as the upper cladding layer 5 The light-emitting structure 9 is mounted, and an In _0.5 Al _0.5 P crystal having a thickness of 10 μm and a lattice constant of 0.5666 nm is formed as the current diffusion layer 6 on the uppermost portion, and each includes a metal layer on the top surface and the bottom surface. n-type electrode 3 It is constructed by forming the p-type electrode 37 and. In this light emitting diode, red light emission with a wavelength of 610 nm is obtained.
Further, in this light emitting diode, since the lattice constant of each layer of the double heterostructure light emitting structure portion which is an active region is coincident with the lattice constant of GaAs which is a substrate, crystal defects in the light emitting structure portion are etched pit density ( It is said that a high-performance light-emitting diode can be obtained because a high-quality crystal having a low Etch Pit Density (EPD) of about 1 × 10 ⁵ cm ⁻² can be formed.
However, in the conventional light emitting diode, since light emission is absorbed by the GaAs substrate, the light that can be extracted to the outside is extremely reduced with respect to the light emitted inside.

Therefore, attempts have been made to improve the external quantum efficiency by laminating an InAlGaP-based semiconductor layer on a GaP substrate that is transparent to the emission wavelength of InAlGaP. In this case, a GaP substrate having a lattice constant of 0.5451 nm and an InAlGaP crystal having a 0.5663 nm have a lattice constant mismatch degree of 3.9% or more. Therefore, in an InAlGaP-based semiconductor layer grown on a GaP substrate, Many threading dislocations extending from 10 to the upper layer are present at 10 ⁸ / cm ² or more. The existence of such a large number of dislocations causes a decrease in crystallinity of the light emitting layer, and the light emission characteristics represented by luminance are reduced to 1 or less in the case of a lattice matching light emitting semiconductor element.

  Therefore, as a method of reducing the propagation of dislocations to the upper layer in the InAlGaP-based semiconductor layer as described above, a lattice relaxation buffer layer (linear graded buffer layer, hereinafter referred to as an LG buffer) in which the composition is gradually changed, or a step. In particular, it has been proposed to use a lattice relaxation buffer layer (step graded buffer layer, hereinafter referred to as an SG buffer) or the like whose composition is changed (see, for example, Patent Document 1 and Patent Document 2).

FIG. 6 shows an example of a cross-sectional structure of a light-emitting diode in which the lattice constant is changed stepwise by the SG buffer layer so that the uppermost layer of the SG buffer layer matches the lattice constant of the operating region. This light-emitting diode 40 uses a substrate 1 made of GaP, and forms five layers of buffer layers 2-1 to 2-5 whose lattice constants are changed in stages on the substrate 1 made of GaP, and the buffer layer thereon. The InAlGaP-based semiconductor layers 3 to 5 that are lattice-matched with the layer 2-5 are formed.
In this light emitting diode 40, a lattice mismatch between the substrate 1 made of GaP having a lattice constant of 0.5451 nm and the light emitting layer 4 made of In _0.5 Al _0.25 Ga _0.25 P having a lattice constant of 0.5663 nm. Although the degree is (0.5663-0.5451) /0.5451=0.039, that is, 3.9%, the uppermost buffer layer 2-5 and the light emitting layer 4 are almost lattice matched. . For this reason, the EPD of the light emitting layer is reduced to 5 × 10 ⁶ / cm ² , and the luminance is about one tenth when the substrate and the light emitting layer are lattice-matched.

When growing these buffer layers, first, an n-InAlP buffer layer is grown on an n-GaP substrate. At this time, it is preferable to use a substrate whose plane orientation is the (100) plane or a 0-15 ° off substrate. For example, the Al mixed crystal ratio is set to 0.9 immediately after the start of growth, and the Al mixed crystal ratio is continuously changed in the case of the LG buffer layer as the growth of the buffer layer proceeds. In the case of the SG buffer layer, means for decreasing the Al mixed crystal ratio stepwise in a discontinuous manner to match the lattice constant of the lower cladding layer of the light emitting structure is taken. That is, in the case of the SG buffer layer, on the substrate 1 made of n-type GaP having a lattice constant of 0.5451 nm, first, In _0.1 Al _{0. 5} having a lattice constant of 0.5503 nm as the first buffer layer 2-1 _{. 9} P crystal is formed to a thickness of 0.1 μm, then an In _0.2 Al _0.8 P crystal having a lattice constant of 0.5544 nm is formed as the second buffer layer 2-2 to a thickness of 0.1 μm, As a buffer layer 2-3, an In _0.3 Al _0.7 P crystal having a lattice constant of 0.5584 nm is formed to a thickness of 0.1 μm, and as a fourth buffer layer 2-4, the lattice constant is 0.5625 nm. In _0.4 Al _0.6 P crystal having a thickness of 0.1 μm was formed, and then an In _0.5 Al _0.5 P crystal having a lattice constant of 0.5666 nm was formed as the fifth buffer layer 2-5. Formed to 1 μm. Furthermore, an n-type In _0.5 Al _0.5 P crystal having a thickness of 1 μm and a lattice constant of 0.5666 nm as the lower cladding layer 3 and a lattice constant of 0.5663 nm and a thickness of 1 μm as the light emitting layer 4 are formed. Three layers of In _0.5 Al _0.25 Ga _0.25 P crystal and p-type In _0.5 Al _0.5 P crystal having a thickness of 1 μm and a lattice constant of 0.5666 nm as the upper cladding layer 5 The p-type In _0.5 Al _0.5 P crystal having a thickness of 10 μm and a lattice constant of 0.5666 nm is formed as the current diffusion layer 6 on the top, and the top and bottom surfaces are mounted. Are formed by forming an n-type electrode 8 and a p-type electrode 7 each made of a metal layer. The light emitting diode 40 formed in such a structure can emit red light having a wavelength of 610 nm.
JP 59-84417 A Japanese Patent Laid-Open No. 04-257276

However, in the conventional lattice constant difference relaxation buffer layer, threading dislocations cannot be sufficiently reduced, and the EPD of the light emitting layer is about 5 × (10 ⁶ to 10 ⁷ ) cm ^−2. As a result, the luminance characteristics of the light-emitting element are reduced to about one-hundred to one-hundred compared with the case where the luminance characteristics of the light-emitting element are lattice-matched due to the generation of leakage current flowing along threading dislocations.
Accordingly, an object of the present invention is to provide a good semiconductor device by reducing threading dislocations propagating to an active layer in order to solve the above problem.

In order to solve the above-described problems, the present invention includes (1) a plurality of convex semiconductor working regions having a thick central portion and a thin peripheral portion, and a surface having a mirror surface. is polished, the semiconductor active area is surrounded by the lattice-shaped grooves, the semiconductor element formation substrate said convex surface Ru curved der,
(2) The substrate for forming a semiconductor element according to (1), wherein the height difference of the surface is 1 μm or more and 100 μm or less,
(3) The substrate for forming a semiconductor element according to (1) or (2), wherein the substrate is any one of GaP, GaAs, InP, AlP, AlAs, and Si,
(4) An epitaxial wafer having an operation region made of a semiconductor crystal having a lattice constant different from that of the substrate crystal, wherein the operation region is the semiconductor element formation substrate according to any one of (1) to (3) An epitaxial wafer formed thereon,
(5) The epitaxial wafer according to (4), wherein the difference in lattice constant between the substrate crystal and the semiconductor crystal in the operation region is 0.15% or more,
(6) The epitaxial wafer according to (4) or (5), wherein the semiconductor crystal in the operation region includes at least one element selected from Al, Ga, In, P, As, Sb, Si, Ge, and C. ,

( 7 ) A semiconductor device using the epitaxial wafer according to any one of ( 4 ) to ( 6 ),
(8) The semiconductor element is a light-emitting element, a semiconductor device according to either of the laser element or an electronic device element (7),
( 9 ) A semiconductor device using the semiconductor element according to ( 8 ),
(10) The semiconductor device is an illumination device, a display device, a communication device, a semiconductor device according to either of the radar device (9),
Each invention is provided.

  As described above, according to the present invention, the following excellent effects can be obtained. That is, the substrate used in the present invention is a mirror-polished surface, but still has a difference in height, so that crystal defects in the substrate are concentrated in the low part, and the lattice constant is different from that of the substrate. In the case of forming a compound semiconductor epitaxial wafer having a region, the number of threading dislocations passing through the operation region can be reduced. Therefore, the semiconductor element using the epitaxial wafer of the present invention becomes a high-performance semiconductor element, and a high-performance semiconductor device can be created. Further, according to the present invention, the density distribution of threading dislocations can be provided, and the threading dislocation density in the operation region that is close to the electrode and contributes more to the operation can be reduced. Semiconductor devices can be created.

As a substrate for forming a semiconductor element, various materials such as sapphire and diamond are used in addition to a semiconductor substrate such as GaAs, GaP, InP, AlP, AlAs, and silicon.
Semiconductor substrates such as silicon, GaAs, GaP, and InP are roughly divided into (a) a grinding step for adjusting the orientation and outer shape of a single crystal ingot in order to make the surface as flat as possible and further reduce damage caused by polishing, (b ) A slicing step for thinly cutting a single crystal ingot, (c) a wrapping step for making the sliced wafer an equal thickness and an equal slice damage depth, (d) a beveling step for grinding the outer periphery of the wrapped wafer, e) Etching process for etching a wafer that has been leveled; (f) Polishing process for polishing an etched wafer; (g) Cleaning process for cleaning a polished wafer; (h) Inspection / packaging for inspecting and packing the cleaned wafer Processed through the process.
In order to solve the problem of reducing threading dislocations, the substrate for forming a semiconductor element of the present invention is a substrate whose surface is mirror-polished but is not flat and has a height difference.

A substrate whose surface is mirror-polished but is not flat but has a height difference is that the thickness of the central portion of a portion forming one semiconductor operating region is thick, and the portion forming one semiconductor operating region is It means a substrate having a thin peripheral part. In general, since a large number of elements are formed on a single substrate, the substrate of the present invention has a large number of concavo-convex portions having minute height differences on the surface.
FIG. 1 shows an example of a cross-sectional structure of a semiconductor element which is one of the present invention. In the following drawings, the scale is not necessarily drawn accurately in order to make the explanation easy to understand.
The semiconductor element 10 shown in FIG. 1 has a double heterostructure InAlGaP-based light emission through a buffer layer for lattice matching with the surface of a semiconductor substrate having a mirror-polished surface but not flat and having a height difference. A semiconductor light emitting device having a structure.
In FIG. 1, 1 is a substrate made of GaP having a lattice constant of 5.451 nm, 2-1 to 2-5 are buffer layers made of In _1-x Al _x P, the lattice constant of which changes stepwise, and the substrate 1 The buffer layer 2-1 in contact with the electrode is made of In _0.1 Al _0.9 P crystal having a lattice constant of 5.503 nm. The lattice constants of the buffer layers 2-1 to 2-5 gradually increase, and the compositions of the buffer layers 2-2 to 2-4 are In _0.2 Al _0.8 P and In _0.3 Al _0.7 , respectively. P and In _0.4 Al _0.6 P, respectively, and the lattice constants are 0.5544, 0.5584, and 0.5625, respectively.
The uppermost buffer layer 2-5 is made of In _0.5 Al _0.5 P crystal having a lattice constant of 5.666 nm and lattice-matched with the lower cladding layer 3 of the double hetero light-emitting structure portion. Therefore, the light emitting layer 4 lattice-matched with the lower cladding layer 3 can obtain a high quality crystal with few crystal defects such as dislocations.

The double hetero light emitting structure 9 has a lower cladding layer 3 made of an n-type In _0.5 Al _0.5 P crystal having a thickness of 1 μm and a lattice constant of 0.5666 nm, a thickness of 1 μm and a lattice constant of 5. From the light-emitting layer 4 made of 663 nm In _0.5 Al _0.25 Ga _0.25 P crystal and the p-type In _0.5 Al _0.5 P crystal having a thickness of 0.1 μm and a lattice constant of 5.666 nm The upper clad layer 5 is composed of three layers. Here, the lattice constant of GaP of the substrate 1 is 5.451 nm, and the lattice constant of the light emitting layer 4 made of In _0.5 Al _0.25 Ga _0.25 P crystal is 5.663 nm. The degree of lattice constant mismatch with the light-emitting layer 4 is (5.663-5.451) /5.451=0.039, that is, 3.9%.

In the semiconductor light emitting device having the above structure, the surface of the substrate 1 made of GaP is mirror-polished but is not flat. As shown in FIG. 1, the thickness h ₁ at the central portion is greater than the thickness h ₂ at the peripheral portion. Is slightly larger and has a difference in height (h ₁ −h ₂ ) in the portion forming the operation region. This height difference (h ₁ -h ₂ ) is suitably about 1 μm or more and 100 μm or less for a substrate having a thickness of 0.6 mm.

Usually, a semiconductor element forms a large number of working areas on the surface of a single substrate, and performs a necessary process on a large number of working areas on a single substrate simultaneously to form a large number of semiconductor elements. Finally, it is common to use each semiconductor element separately.
FIG. 2 shows a part of a cross-sectional structure of the epitaxial wafer 20 before a large number of semiconductor light emitting elements having the structure shown in FIG. FIG. 2 shows a state where four semiconductor light emitting elements 10 having the structure shown in FIG. 1 are connected. In plan view, a large number of semiconductor light emitting elements are formed in a lattice pattern.
In the epitaxial wafer 20, the region for forming the working region of the substrate 1 is raised upward and becomes thicker. If the surface shape of the substrate is arranged in this way, crystal defects are concentrated on the thin part, and threading dislocations extending from the substrate to the upper layer are less in the thick part. The semiconductor crystal formed in this way provides a high-quality crystal with few crystal defects such as dislocations, and a semiconductor element having high-performance operating characteristics.

Here, a method for manufacturing a non-flat substrate having a polished surface but having a height difference will be described by taking a semiconductor substrate as an example.
First, a smooth semiconductor substrate is prepared. Here, there is no problem even if the surface dermage depth of the smooth semiconductor substrate remains up to a depth that can be removed by subsequent polishing. In a normal semiconductor substrate manufacturing process, a base material obtained from a single crystal ingot through a slicing process, a lapping process, a beveling process and the like can be used.
An etching mask made of, for example, a chemical resistant resist is formed on a predetermined portion of the smooth semiconductor substrate surface by a photolithography technique. For example, if an element to be manufactured has an interval of 0.3 mm, the etching mask has a lattice shape with an interval of 0.3 mm, and a negative or positive type photoresist that is generally available on the market can be used as the resist. Here, when the resist is used as an etching mask, it is desirable that the resist has high stability with respect to the etching method used for etching.
When a silicon oxide thin film is used as an etching mask, a silicon oxide thin film is formed on a substrate by a method such as plasma CVD, and a resist is patterned by using a photolithography technique, and the silicon oxide thin film is formed into hydrogen fluoride. By etching with an acid-based etchant to remove the resist, a silicon oxide etching mask can be formed.

  Next, as shown in FIGS. 3 and 4, one surface of the base material 11 with a lattice-like etching mask (not shown) on the front and back surfaces is chemically etched, for example, etching with acid, alkali, or other chemicals. Alternatively, the predetermined lattice-shaped grooves 12 are formed by physical etching such as plasma dry etching or etching with hydrogen chloride gas. FIG. 3 shows a part of a plan view of the base material 11 forming the grid-like grooves 12, and FIG. In the figure, reference numeral 13 denotes a portion that forms individual operating regions. The grooves 12 are formed in a lattice shape so as to surround the portion 13 that forms the operating region. In many cases, the size of the portion 13 forming the operating region is a square having a side W of about 0.3 mm. In this case, the width L of the groove 12 is preferably about 0.3 mm. The depth D of the groove 12, that is, the etching amount, which depends on the polishing conditions in the subsequent process, is generally about 1 to 100 μm.

A representative example of the chemical etching chemical solution for the GaP substrate is a mixed solution of hydrochloric acid, nitric acid and pure water. In order to increase the etching rate, methods such as increasing the concentration or increasing the temperature can be used.
Typical examples of chemical etching chemicals for GaAs substrates include a mixture of hydrofluoric acid, hydrogen peroxide and pure water, a mixture of sulfuric acid, hydrogen peroxide and pure water, and phosphoric acid and hydrogen peroxide. Examples of the etchant that are usually used in the semiconductor processing field according to the material of the substrate, such as a mixed solution of pure water.
As a typical example of the chemical etching chemical solution for the InP substrate, hydrochloric acid or a mixed solution of hydrochloric acid, hydrogen peroxide water and pure water can be given.
A typical example of the chemical etching chemical solution for the Si substrate is a mixed solution of hydrofluoric acid and pure water.

In the case of chemical etching, the back surface is often etched in the same manner. When etching on the back surface is not required, it is necessary to create an etching mask on the back surface.
In dry etching, etching can be performed mainly using a silicon oxide thin film as an etching mask and using hydrogen chloride or the like as a reactive gas. In order to protect the back surface, there is also a method of attaching an etching mask to the back surface.
After the etching, the resist and silicon oxide used as the etching mask are removed by cleaning with an organic solvent such as acetone or acid cleaning.

Next, polishing by chemical-mechanical polishing (CMP) is performed to finish the surface to be a smooth curved surface. That is, chemical-mechanical polishing (CMP) is performed on the surface of the base material 11 on which the grooves 12 are formed as shown in FIG. 4, and polishing is performed until the surface S of the base material 11 becomes S ′ indicated by a broken line in a cross-sectional shape. A height difference of height D (= h ₁ −h ₂ ) is formed on the substrate surface. Here, when the ratio of mechanical polishing is high, the flatness is improved, but there is a problem that damage due to polishing tends to remain. On the other hand, when the rate of chemical polishing is high, the degree of improvement in flatness is inferior to mechanical polishing, but there is a feature that polishing damage is small.
In chemical-mechanical polishing (CMP), a polishing liquid (slurry) in which fine abrasive grains are suspended is flowed to the surface of the substrate, and the substrate attached to the spindle is pressed against the polishing pad on the surface of the rotary table for polishing. A technology that preferentially removes protrusions on the substrate using both a chemical mechanism that oxidizes the surface of the substrate to be polished with the slurry and a mechanical mechanism that mechanically scrapes the oxide layer. It is. As the slurry, silica fine particles or alumina fine particles suspended in an alkaline solution or an oxidizing agent aqueous solution are used. Moreover, as a polishing pad, a nonwoven fabric is used as a base material, and the fiber entangled body is impregnated with various resins to form a foam structure. A large number of polishing pads with various improvements added according to the type of the target substrate and the purpose of polishing are employed.

As an example of conditions where the ratio of chemical polishing is high, a nonwoven fabric type soft polishing pad, such as POLYPAS # 27 manufactured by Fuji Boseki Co., Ltd., is used as the polishing cloth, and 40% silica, such as Fujimi Incorporated Compol, is used as the polishing agent. An aqueous solution in which 5 vol% sodium hypochlorite is added as an oxidizing agent to 80 is used, and polishing conditions with a polishing pressure of 2 N / cm ² can be mentioned.
As an example of conditions with a high ratio of mechanical polishing, a non-woven fabric type hard polishing pad, for example, POLYPAS # 194 manufactured by Fuji Boseki Co., Ltd., and an aqueous alkaline solution in which 40% silica is suspended in an abrasive, For example, a polishing condition with a polishing pressure of 3 N / cm ² using a Fujimi Incorporated Compol 80 is used. In this case, no oxidizing agent is used.
In the present invention, if polishing is continued under a condition where the ratio of chemical polishing is large, the polishing of the peripheral portion of the groove provided on the substrate surface proceeds and becomes low, and the portion away from the groove becomes high, so that a large number as a whole. A substrate having a concavo-convex portion having a minute height difference is obtained.

When polishing is carried out under polishing conditions with a high ratio of chemical polishing, the corners near the grooves are gradually removed, and the entire substrate surface has irregularities and is not flat, but is microscopically polished to a mirror surface state. Substrate can be manufactured. As an amount of polishing, an amount of about 20 to 100% of a groove formed by etching is appropriate.
In this way, a mirror-polished semiconductor substrate is manufactured which has a slight difference in height at a necessary depth at a necessary interval for a base material to be used and has sufficiently reduced polishing damage as an epitaxial growth substrate. be able to.

Next, the substrate is epitaxially grown on this substrate by MOCVD or MBE, and the LG buffer layer or SG buffer layer, and the target semiconductor device (for example, field effect transistor (FET), heterobipolar transistor (HBT), light emission) A diode (LED), a laser diode (LD), a light receiving element), and the like are formed. Then, an electrode formation, element isolation, wiring connection, etc. are performed and an electronic device and an optical device are produced. There are no particular limitations on the semiconductor layer of the working area, known _{In 1-x-y Ga x} Al y As 1-a-b Sb a P b based semiconductor (although depending on the purpose, 0 ≦ x, y, a , B ≦ 1) and SiGeC based semiconductor crystals can be used if necessary.
The manufacturing method of these semiconductor crystals is not particularly limited, and various known methods used in the semiconductor manufacturing field can be used.
The epitaxial wafer of the present invention can be obtained by epitaxially growing a working region comprising a target semiconductor crystal layer on a substrate.
In the epitaxial wafer of the present invention, strain is generated due to lattice mismatch when the buffer layer is grown, and dislocations generated by this strain are concentrated on the surface recess having a large surface shape change. Using this characteristic, an operating region with few crystal defects such as threading dislocations is formed, and an element having excellent characteristics can be formed.

The semiconductor element of the present invention is formed using the above epitaxial wafer of the present invention. Representative examples of the semiconductor element of the present invention include a field effect transistor, a heterobipolar transistor, a light emitting element, a laser element, and the like. Since the operation region of these semiconductor elements is formed in a region with few crystal defects such as threading dislocations in the substrate, it becomes a semiconductor crystal with few crystal defects and can exhibit a high-performance element function.
The semiconductor device of the present invention is formed using the conductor element of the present invention. Representative examples of the semiconductor device of the present invention include a lighting device, a display device, a communication device, a radar device, and the like. Since the semiconductor device of the present invention uses a semiconductor element having a semiconductor operation region with excellent crystallinity, it can exhibit high performance and stable operation.

A semiconductor light emitting device having a cross-sectional structure shown in FIG. 1 was formed on the GaP substrate by epitaxial growth.
A Si-doped n-type GaP substrate having a lattice constant of 0.5451 nm and a plane orientation (100) was used as the substrate, and a chemical-resistant etching mask was formed on the substrate by photolithography. As the etching mask, a lattice pattern having a pitch of 0.3 mm and a width of 0.05 mm, which is the same as the element interval, was used. Since the back surface does not require etching, an etching mask was formed on the entire surface. After forming the etching mask, the exposed portion of the GaP substrate surface was etched to a thickness of about 10 μm with an etchant composed of a mixture of hydrochloric acid, nitric acid, and pure water.
Thereafter, the etching mask was removed using acetone as a remover.
Next, it was polished to a thickness of 5 μm by chemical-mechanical polishing. At this time, Compil 80 manufactured by Fujimi Incorporated, which is an aqueous solution in which 40% by mass of silica fine particles were suspended in an abrasive, was used. And 5 vol% sodium hypochlorite was added as an oxidizing agent in order to strengthen the ratio of chemical polishing. As the polishing pad, a soft polishing pad of POLYPAS # 27 manufactured by Fuji Boseki Co., Ltd. was used. The polishing pressure was 2 N / cm ² . As a result, an n-type GaP substrate having periodic lattice-like depressions with a gap of 0.3 mm and a depth of 5 μm on the surface of the GaP substrate and having no polishing damage was obtained.

Next, an InAlGaP lattice mismatched LED was formed on this substrate via an SG buffer structure made of InAlP crystal. Each crystal layer is grown by MOCVD using trimethylgallium (TMG), trimethylaluminum (TMAl), tolmethylindium (TMI), arsine (AsH ₃ ), and phosphine (PH ₃ ) as the organic metal (MO) raw material. It was. The growth temperature was 700 ° C.
The Al mixed crystal ratio of the SG buffer was set to 0.9 immediately after the start of growth, and the Al mixed crystal ratio was decreased stepwise discontinuously as the growth of the buffer layer progressed. That is, the composition of the five buffer layers is In _0.1 Al _0.9 P, In _0.2 Al _0.8 P, In _0.3 Al _0.7 P, In _0.4 Al _0.6 P sequentially. In _0.5 Al _0.5 P, and the lattice constants were 0.5503 nm, 0.5544 nm, 0.5584 nm, 0.5625 nm, and 0.5666 nm, respectively. Next, a lower cladding layer made of n-type In _0.5 Al _0.5 P lattice-matched with the uppermost portion of the buffer layer was grown by 1.0 μm. Next, a light emitting layer made of undoped-In _0.5 Ga _0.25 Al _0.25 P lattice-matched with the lower cladding layer was grown on the lower cladding layer to a thickness of 1.0 μm.
Next, an upper clad layer made of p-type-In _0.5 Al _0.5 P having the same Al mixed crystal ratio as that of the lower clad layer was grown on the light emitting layer by a thickness of 1.0 μm. Further, after forming a p-type In _0.5 Al _0.5 P layer having a thickness of 10 μm and a lattice constant of 0.5666 as a current diffusion layer, a transparent electrode and a metal electrode were formed to produce an LED.

The lattice mismatched LED had an EPD of 1 × 10 ⁵ cm ⁻² and an LED brightness of 500 (arbitrary unit).
According to the present invention, the luminance, which is the most important characteristic of the LED, has been confirmed to be greatly improved as compared with the lattice matching LED and the lattice mismatching LED using the conventional SG buffer layer not using this method.

It is a figure which shows an example of the cross-section of the semiconductor element of this invention. It is a figure which shows a part of cross-sectional structure of the epitaxial wafer of this invention. It is a figure explaining the manufacturing method of the board | substrate of this invention. FIG. 4 is a sectional view taken along line A-A ′ of FIG. 3. It is a figure which shows an example of the cross-sectional structure of the conventional semiconductor element. It is a figure which shows the other example of the cross-section of the conventional semiconductor element.

Explanation of symbols

1 .... substrate, 2 .... buffer layer, 3 .... lower cladding layer, 4 .... light emitting layer, 5 .... upper cladding layer , 6... Current spreading layer, 7... P-type electrode, 8... N-type electrode, 9. 40... Light emitting element, 11... Base material, 12.

Claims (10)

It has a plurality of convex semiconductor working regions with a thick central part and a thin peripheral part, and the surface is mirror-polished , and the semiconductor working region is surrounded by a lattice-shaped groove. the semiconductor device substrate for forming said convex surface and said curved der Rukoto.   The semiconductor element forming substrate according to claim 1, wherein a difference in height of the surface is 1 μm or more and 100 μm or less.   3. The semiconductor element forming substrate according to claim 1, wherein the substrate is one of GaP, GaAs, InP, AlP, AlAs, and Si. 4.   An epitaxial wafer having an operating region made of a semiconductor crystal having a lattice constant different from that of the substrate crystal, wherein the operating region is formed on the substrate for forming a semiconductor element according to any one of claims 1 to 3. An epitaxial wafer characterized by comprising:   5. The epitaxial wafer according to claim 4, wherein a difference between a lattice constant of the substrate crystal and a semiconductor crystal in an operation region is 0.15% or more.   6. The semiconductor crystal according to claim 4 or 5, wherein the semiconductor crystal in the working region contains at least one element selected from Al, Ga, In, P, As, Sb, Si, Ge, and C. Epitaxial wafer.   A semiconductor device comprising the epitaxial wafer according to any one of claims 4 to 6.   The semiconductor element according to claim 7, wherein the semiconductor element is any one of a light emitting element, a laser element, and an electronic device element.   A semiconductor device using the semiconductor element according to claim 8.   The semiconductor device according to claim 9, wherein the semiconductor device is any one of a lighting device, a display device, a communication device, and a radar device.

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