JP4964406B2 - Formation of narrow shape using edge of self-assembled monolayer - Google Patents

Description

  The present invention generally relates to a structure and a method of manufacturing the structure, and more specifically, to a method of manufacturing a structure by using a disassembler of a self-assembled monolayer (SAM). .

There is great interest in developing cost-effective methods for producing nanostructures (structures with a minimum dimension of about 100 nm or less) for use in nanoelectronics, information storage devices and optical instruments. Several methods for making such structures have been proposed to replace optical lithography processes, each with its limitations. For example, electron beam drawing is a serial process and does not endure mass production. Both X-ray and extreme ultraviolet lithography are limited due to the complexity of the procedures that use them. Microcontact printing uses an elastomeric stamp to transfer a pattern of alkanethiol molecules, but this pattern itself is formed in a structured monolayer that binds to a metal such as silver or gold, thereby Acts as an etching resist. However, diffusion of alkanethiol during the printing stage limits its minimum lateral dimension to about 100 nm. In addition, defects are found on the etched surface coated with alkanethiol. There were also problems with previous attempts to develop a chemical lithography process for patterning using self-assembled monolayers (SAMs). For example, such a method can only be used to form grooves on a non-planar metal surface, such as a structure with silver on silver. Such a method is also limited to forming grooves in metals having different etch resistances for SAMs of various chain lengths.
Orlov O. A. et al. Science 277: 926-30 (1997). M.M. L. Steigerwald et al. Ann. Rev. Mat. Sci 19: 471-495 (1989) “Dielectric Properties of Polyelectrolyte Multilayers”, Durstock M. et al. F. And Rubner M. et al. F. Langmuir, 17: 7865-72 (2001).

  Accordingly, it is an object of the present invention to form a suitable structure on a wide variety of metal and non-metal surfaces, such that the surface becomes flat when the method is finished.

  In order to address the above-described problems, one embodiment of the present invention provides a method for making a groove in a base layer. The method includes forming the patterned layer over a portion of the base layer such that the patterned layer forms a target region disposed adjacent to the edge thereof. The method also includes the step of aligning a self-assembled monolayer (SAM) with the patterned layer, but chemically bonding to the base layer except for the patterned layer. The SAM includes an unorganized region within the target region. The method further includes etching the base layer in the target area.

  Another embodiment of the present invention is a method of making a wiring disposed on a base layer. The method includes forming the patterned layer over a portion of the base layer such that the patterned layer forms a target region disposed adjacent to the edge thereof. The method further includes aligning a first self-assembled monolayer (SAM) with the patterned layer, but chemically bonding to the base layer except for the patterned layer. The SAM includes an unorganized region within the target region. The method also includes exchanging the first SAM with a second SAM within the target area.

  Yet another embodiment of the invention is a method of making a field effect transistor. The method includes disposing an insulating layer on a base substrate and depositing a base layer on the insulating layer. The method also includes the step of forming a trench in the base layer as described above to expose the insulating layer, thereby forming a source and drain. The method further includes forming a gate dielectric in the trench, removing the patterned layer, and forming a semiconductor structure on the gate dielectric and the source and drain.

  The invention is best understood from the following detailed description when read with the accompanying drawing figures. The various shapes are not shown in certain dimensional ratios and can be arbitrarily expanded or reduced for clarity of explanation. The following description is referred to in conjunction with the accompanying drawings.

  The present invention recognizes that it is advantageous to utilize the deposition of a patterned layer on the base layer to facilitate the formation of narrow structures in or on the planar surface of the base layer. Because it is not protected by SAM, the patterned layer can be easily removed by subsequent processing, thereby leaving the planar surface of the base layer with the structure formed therein or thereon. Forming such a structure in or on a flat surface is desirable because it simplifies subsequent processing steps to form active or passive device structures. In addition, forming a SAM on the base layer alongside but not on the patterned layer results in a narrower unstructured region of the SAM at the edge interface between the base layer and the patterned layer. . This is advantageous because a narrow structure can be more precisely formed by various base layers.

  1A-1H show cross-sectional views of an intermediate structure according to one embodiment of a method for making a groove 101. FIG. The groove 101 is in the base layer 105 disposed on the base substrate 110. In some embodiments, the base substrate 110 is a semiconductor substrate 110, but those skilled in the art will appreciate that many other materials such as gallium arsenide or germanium can be suitable base substrates 110. The base layer 105 is formed on the base substrate 110 by an ordinary technique such as vapor deposition (FIG. 1A). The base layer 105 is made of a metal or a nonmetal that can be bonded to the SAM 107 (FIG. 1E). Exemplary base material 105 includes gold, silver, copper, platinum, palladium, aluminum, or mixtures thereof, or silicon. It is advantageous to use the above method to make the groove 101 in a base layer such as palladium that is compatible with normal complementary metal oxide semiconductor processes. This method can also be advantageously applied to manufacturing the groove 101 in the base layer of palladium or the like when there is no difference in etching resistance between the plurality of SAMs 107 having different chain lengths.

  As shown in FIGS. 1B-1D, the method includes forming a patterned layer 115 on a portion 117 of the base layer 105. The patterned layer 115 is formed such that the target region 120 is formed adjacent to the edge 125 thereof. The patterned layer 115 is formed by performing a normal deposition of a photoresist 130 on the base layer 105 and then patterning with photolithography. In one preferred embodiment, a patterned layer 115 is deposited on the photoresist 130 and the base layer 105, as shown in FIG. 1C. As shown in FIG. 1D, after normal lift-off of the photoresist 130, the patterned layer 115 remains on the portion 117 of the base layer 105. In an alternative embodiment, the patterned layer 115 is formed on the base layer 105 by conventional deposition of the patterned layer 115 through a stencil mask.

  The patterned layer 115 is a compound that is inert to the etchant of the base layer 105 and can be chemically bonded to the base layer 105 but not chemically bonded to the SAM 107. In some embodiments, the patterned layer 115 is a metal different from the base layer 105, such as chromium or titanium. In other embodiments, patterned layer 115 is an organic compound such as photoresist 130. Using an organic compound for the patterned layer 115 avoids the need to use a corrosive etchant to remove the patterned layer 115. Corrosive etchants, such as hydrogen fluoride, can damage other components. Use of the photoresist 130 is particularly advantageous because the patterned layer 115 can be formed using conventional optical lithography techniques. Examples of suitable photoresist compounds that do not chemically bond to the SAM 107 include diazo-based photoactive photoresists that contain a fluorinated aliphatic polymer ester. In one preferred embodiment, the patterned layer 115 comprises the product number Shipley 1805 (Shipley Corporation, Moorboro, Mass.).

  As shown in FIG. 1E, the method also includes chemically bonding the SAM 107 to the base layer 105 alongside the patterned layer 115. Chemically bonding the SAM 107 to the base layer 105 includes exposing the base layer 105 to a solution or vapor containing SAM 107 molecules. The exposure is performed for a time sufficient to allow the molecules to self-assemble into the SAM 107 and to chemically bond or adhere to the base layer 105.

  The SAM 107 is removed from the patterned layer 115. The patterned layer 115 is left uncoated because the molecules of the SAM 107 do not chemically bond or adhere to the patterned layer 115. Of course, it should be understood that a small amount of the SAM 107 may be slightly adhered to the patterned layer 115 due to weak non-covalent bonding force such as electrostatic force. However, such a small amount of SAM107 molecules on the patterned layer 115 does not interfere with the removal of the patterned layer with an etchant, as will be described later. Thus, the uncoated patterned layer 115 can be removed with an etchant as described below.

  As shown in FIG. 1F, the method also includes etching to remove the base layer 105 in the target region 120. The target area 120 is located below the approximate portion because the unorganized portion of the SAM 107 is close to the edge 125. The etchant for the base layer 105 diffuses more easily through the unstructured region of the SAM, thereby selectively removing portions of the base layer 105 that are within the target region 120. Suitable base layer etchants include various aqueous solutions including ferrocyanide, ferricyanide, thiosulfate, and hydroxide, and phosphoric acid, nitric acid, acetic acid, sulfuric acid, or combinations thereof, as exemplified below. There are various acidic aqueous solutions.

  The width 140 of the groove portion 101 can be enlarged or reduced according to the exposure time to the base layer etchant. As an example, SAM 107 is formed by exposing base layer 105 for at least 2 hours to a 0.01 M solution of n-hexadecanethiol in ethanol, wherein base layer 105 is gold and patterned layer 115 is titanium. Consider one preferred embodiment. Substrate 105 is exposed at different times to an etchant comprising an aqueous solution consisting of 10 mM potassium ferrocyanide, 1 mM potassium ferricyanide, 100 mM sodium thiosulfate, and 1 M sodium hydroxide. Etching produces a trench having a width 140 of about 50 nm after about 6 to about 12 minutes of exposure, and after about 16 minutes of exposure, produces a trench having a width 140 of about 70 nm, after about 60 minutes of exposure. Produces a groove having a width 140 of about 240 to about 250 nm.

  Those skilled in the art will appreciate that the edge of the groove 142 (FIG. 1F) formed by the method can be used to generate other target regions for forming the second groove. By applying the method repeatedly with varying etch times, various complex groove structures can be created in the base layer, such as a dual damascene structure. Such a structure will facilitate the fabrication of active and passive components within the integrated circuit.

  As shown in FIG. 1G, the method further includes removing the patterned layer 115 after etching the groove 101 in the base layer 105. Those skilled in the art will appreciate that the composition of the etchant of the patterned layer 115 depends on the composition of the patterned layer 115. For example, when the patterned layer 115 is titanium, the etchant preferably contains hydrogen fluoride, for example, a 1% aqueous solution of hydrogen fluoride. Alternatively, if the patterned layer 115 is a photoresist 130, the etchant is acetone or a similar organic solvent.

  As shown in FIG. 1H, the method also includes removing the SAM 107 after etching the groove 101 in the base layer 105. Again, those skilled in the art will similarly understand that the composition of the SAM etchant depends on the composition of the SAM 107. When the SAM 107 contains an alkanethiol, the etchant includes a reactive ion etchant (RIE) that uses oxygen plasma as the active etchant. In one preferred embodiment, the RIE includes 40 mTorr of oxygen and about 80 W of RF power in about 10 seconds.

The SAM 107 includes an organic molecule having a functional group that chemically bonds the organic molecule to the base layer 105. In embodiments where the base layer 105 is a metal, the organic molecule is preferably an unbranched alkane chain and the functional group is preferably a thiol. _{Examples, HS- (CH 2) n -X} ( where, n is between 2 and 20, X is -CH ₃ or _-CO 2 H) include organic molecules having made formula. When the base layer 105 is an Al ₂ O ₃ layer on Al, preferably the organic molecule is an unbranched alkane chain and the functional group is a phosphone group. _{Examples, PO (OH) 2 - (} CH 2) n -CH 3 ( where, n is 2 and between 20) include organic molecules having made formula. When the base layer 105 is a SiO ₂ layer on Si, preferably the organic molecule is an unbranched alkane chain and the functional group is silane. Examples include organic molecules having the chemical formula Si (Cl) ₃ — (CH ₂ ) _n —CH ₃ , where n is between 2 and 20.

  2A to 2H show a configuration of an embodiment of a method for producing the wiring 201 on the base substrate 210. FIG. Similar reference numbers are used to indicate similar structures shown in FIGS. Any of the procedures and embodiments described above can be applied to the method shown in FIGS.

  FIG. 2A shows forming the patterned layer 215 on the portion 217 of the base layer 205 such that the patterned layer 215 forms a target region 220 located adjacent to its edge 225. A base layer 205 is formed on the base substrate 210, and a patterned layer 215 is formed thereon using the same process described above and shown in FIGS. 2B uses a process similar to that described above and illustrated in FIG. 1E to align the first SAM 207 with the patterned layer 215 relative to the base layer 205, but not to overlie the patterned layer 215. It is shown to be combined.

FIG. 2C illustrates exchanging the first SAM 207 with the second SAM 245 within the target area 220. The first SAM 207 is more unorganized near the edge 225 than the flat region 235. Accordingly, the first SAM 207 can be selectively exchanged with the second SAM 245 within the target area 220. When the base layer 205 is a metal layer, the first SAM 207 has a chemical formula of HS— (CH ₂ ) _n —X (where n is between 2 and 10, and X is —CH ₃ or —CO ₂ H). It is a short chain alkanethiol. In such an embodiment, the second SAM 245 is a long chain having the chemical formula HS— (CH ₂ ) _n —X, where n is between 11 and 20, and X is —CH ₃ or —CO ₂ H. Alkanethiol. By way of example, in a preferred embodiment, the first SAM 207 comprises a gold substrate 205 by exposing the substrate 205 to a solution of 10 mM HS— (CH ₂ ) ₂ —CO ₂ H in ethanol for 10 hours at room temperature. Combined with The first SAM 207 then exposes the first SAM 207 to the second SAM 245 in the target region 220 by exposing the first SAM 207 to a solution containing 10 mM HS— (CH ₂ ) ₁₅ —CO ₂ H in ethanol for 1 hour at room temperature. Selectively exchanged.

  2D and 2E show a first embodiment of a method for producing the wiring 201. The method includes etching the base layer 205 disposed outside the target area 220. As shown in FIG. 2D, etching the base layer 205 further exposes the patterned layer 215 to the patterned layer etchant as described above to remove the patterned layer 215, thereby providing a portion 217 of the base layer 205. Remove the coating. FIG. 2E shows that etching the base layer 205 disposed outside the target region 220 further includes exposing the base layer 205 to a base layer etchant. The base layer etchant diffuses more easily through the first SAM 207 than the second SAM 245, thus selectively removing the base layer 205 outside the target region 220, thereby forming the interconnect 201. For example, after removal of the patterned titanium layer 215 and exposure to hydrogen fluoride as described above, the gold base layer 205 can be a base layer etchant (eg, 10 mM potassium ferrocyanide, 1 mM potassium ferricyanide, 100 mM sodium thiosulfate). And an aqueous solution of 1M sodium hydroxide) for about 40 seconds.

FIG. 2F shows a second embodiment of a method for forming the wiring 201. This method includes nucleation of the conductive metal crystal 201 in the target region 220. In such an embodiment, the base layer 205 preferably includes a non-conductive material such as SiO ₂ on Si. In a preferred embodiment, the organic molecule constituting the first SAM 207 has the chemical formula Si (Cl) ₃ — (CH ₂ ) _n —CH ₃ (where n is between 2 and 20), 2 SAM245 _{is, Si (Cl) 3 - (} CH 2) n -CO 2 H ( where, n is 2 and between 20) having become formula.

As shown in FIG. 2D of the first embodiment, the nucleation of the conductive metal crystal constituting the wiring 201 is performed by exposing the patterned layer 215 to the etchant and removing the patterned layer 215, thereby Removing the coating of portion 217 may be included. FIG. 2F further includes nucleating conductive metal crystals of the interconnect 201 in the target region 220 further comprising exposing the base layer 220 to a solution containing a metal salt such as cadmium sulfide to form the interconnect 201. Show.
After performing the first or second steps described above, the second SAM 245 may be removed by exposure to a SAM etchant, such as the RIE procedure described above, if necessary.

  Those skilled in the art will appreciate that the method of making the wiring 201 can also be used to form a linear structure or a non-linear structure on the base layer 205 or the base substrate 210. In some embodiments, for example, the wiring 201 forms a circular structure known as a quantum dot. Circular structures can be advantageously used in the fabrication of logic circuits with quantum dots to facilitate the encoding of logic states by locating individual electrons on interconnected quantum dots. This is described, for example, in Orlov O.D. A. et al. Science 277: 926-30 (1997); L. Steigerwald et al. Ann. Rev. Mat. Sci 19: 471-495 (1989), which are incorporated herein by reference.

  Another embodiment is a method of making a field effect transistor 300. The method shown in FIGS. 3A to 3E incorporates the method (FIG. 3C) for forming the groove 301 described above. Any of the above-described methods for fabricating the groove 301 can be used to fabricate the field effect transistor 300. Those skilled in the art will appreciate that many alternative transistor structures in addition to the embodiment shown in FIG. 3 can advantageously incorporate the structure of the present invention.

  Using reference numerals indicating structures similar to those shown in FIGS. 1 and 2, the method for making the transistor 300 includes placing an insulating layer 350 over the semiconductor substrate 310 (FIG. 3A). In one preferred embodiment, the base substrate 310 comprises a semiconductor substrate such as polysilicon and the insulating layer 350 comprises silicon dioxide. In such an embodiment, a portion of base substrate 310 serves as the gate of transistor 300.

  As shown in FIG. 3B, a base layer 305 made of a conductive material such as gold is deposited on the insulating layer 350. FIG. 3C shows forming a groove 301 in the base layer 305 to expose the insulating layer 350, thereby forming source and drain electrodes 355, 360 separately from the base layer 305. In a preferred embodiment, the groove 301 has a width 340 of less than about 100 nm, and more preferably has a width 340 of about 50 nm. The narrow width of the groove 301 is advantageous because the entire channel length of the transistor 300 is reduced as described later. In one preferred embodiment, the groove 301 has a depth 365 between about 10 nm and 20 nm, and more preferably has a depth of about 15 nm. Such a shallow trench depth 365 is preferred because it facilitates formation of the gate dielectric 370 (FIG. 3D).

  As shown in FIG. 3D, the gate dielectric 370 is formed using a normal process of filling the trench 301 with a dielectric material such as silicon dioxide. Alternatively, in certain preferred embodiments, filling of the groove 301 includes negatively charging the insulating layer 350, eg, treating with a solution of sulfuric acid and hydrogen peroxide, and then with ammonium hydroxide and hydrogen peroxide. It is facilitated by processing. In a preferred embodiment, the base layer 305 is then immersed in an alkyl-terminated thiol solution, which selectively binds only to the Au electrodes 355 and 360, with a polyelectrolyte on top of the Au electrodes 355, 360. Prevents adhesion. This is followed by a multilayer deposition of gate dielectric material 370 containing one or more charged polyelectrolytes. For example, in certain preferred embodiments, the charged polyelectrolyte is polyallylamine, polyacrylic acid, or a mixture thereof. When placed in the trench 301, the polyelectrolyte becomes charge neutral, thereby neutralizing the gate dielectric material and thus insulating. Those skilled in the art will appreciate that various layer-by-layer depositions as described above are available. For example, “Dielectric Properties of Polyelectrolyte Multilayers”, Durstock M. F. And Rubner M. et al. F. See Langmuir, 17: 7865-72 (2001), which is incorporated herein by reference in its entirety.

As shown in FIG. 3E, a semiconductor structure 375 is then formed over the gate dielectric 370 and the gates and drains 355,360. For example, in some embodiments, the semiconductor structure 375 is deposited through a patterned mask. The semiconductor structure 375 is made of a material with low electron mobility, so that it is non-conductive except when a voltage is applied to the gate 310. Such materials are well known to those skilled in the art and include pentacene or tetracene. The width of the trench 301 defines the dimension of the channel 380 disposed at the interface between the gate dielectric 370 and the semiconductor 375.
Although the invention has been described in detail, those skilled in the art will appreciate that various changes, substitutions and modifications can be made without departing from the scope of the invention.

It is sectional drawing of the intermediate structure formed by the method of producing a groove part in a base layer. It is sectional drawing of the intermediate structure formed by the method of producing a groove part in a base layer. It is sectional drawing of the intermediate structure formed by the method of producing a groove part in a base layer. It is sectional drawing of the intermediate structure formed by the method of producing a groove part in a base layer. It is sectional drawing of the intermediate structure formed by the method of producing a groove part in a base layer. It is sectional drawing of the intermediate structure formed by the method of producing a groove part in a base layer. It is sectional drawing of the intermediate structure formed by the method of producing a groove part in a base layer. It is sectional drawing of the intermediate structure formed by the method of producing a groove part in a base layer. It is sectional drawing which shows the process of producing the wiring arrange | positioned on the base layer in the various intermediate stage of manufacture. It is sectional drawing which shows the process of producing the wiring arrange | positioned on the base layer in the various intermediate stage of manufacture. It is sectional drawing which shows the process of producing the wiring arrange | positioned on the base layer in the various intermediate stage of manufacture. It is sectional drawing which shows the process of producing the wiring arrange | positioned on the base layer in the various intermediate stage of manufacture. It is sectional drawing which shows the process of producing the wiring arrange | positioned on the base layer in the various intermediate stage of manufacture. It is sectional drawing which shows the process of producing the wiring arrange | positioned on the base layer in the various intermediate stage of manufacture. It is sectional drawing which shows the manufacturing process of a field effect transistor in the various intermediate stage of manufacture. It is sectional drawing which shows the manufacturing process of a field effect transistor in the various intermediate stage of manufacture. It is sectional drawing which shows the manufacturing process of a field effect transistor in the various intermediate stage of manufacture. It is sectional drawing which shows the manufacturing process of a field effect transistor in the various intermediate stage of manufacture. It is sectional drawing which shows the manufacturing process of a field effect transistor in the various intermediate stage of manufacture.

Claims (11)

The patterned layer (115) is formed on a portion of the base layer (105) such that the patterned layer (115) forms a target region (120) disposed adjacent to its edge (125). Process,
Aligning a self-assembled monolayer (SAM) (107) with the patterned layer, but excluding the patterned layer (115) and chemically bonding to the base layer (105) , A self-assembled monolayer (SAM) (107) comprising an unorganized region within the target region (120) ;
Etching the base layer (105 ) in the target region (120) . The etching step further exposes the base layer (105) to an etchant that is diffusible via the self-assembled monolayer (SAM) (107) disposed on the edge (125) , thereby within the target region. The apparatus of claim 1, comprising selectively removing portions of the base layer (105) of the substrate. The method of claim 2, further comprising removing the patterned layer (115) after removing the portion of the base layer (105) from the target region. 3. The method of claim 2, further comprising removing the self-assembled monolayer (SAM) (107) after removing the portion of the base layer from the target region. The self-assembled monolayer (SAM) (107) includes one or more organic molecules having a functional group capable of chemically bonding organic molecules to the base layer (105) . The method of claim 1. A method for producing a wiring arranged on a base substrate (210), the method comprising:
As patterned layer (215) forms a target area (220) located adjacent an edge thereof, said on portion of the prior SL-formed substrate on the base substrate (210) (205) Forming a patterned layer (215) ;
Aligning a first self-assembled monolayer (SAM) (207) with the patterned layer, but excluding the patterned layer and chemically bonding to the base layer (205) , A first self-assembled monolayer (SAM) (207) comprising an unorganized region within the target region;
Replacing the first self-assembled monolayer (SAM) with a second self-assembled monolayer (SAM) (245) within the target region ;
Removing the base layer (205) located outside the target area . The method of claim 6, further comprising etching the base layer (205) disposed outside the target area (220) . Etching the base layer (205) comprises exposing the patterned layer (215) to an etchant of the patterned layer, thereby removing the patterned layer (215) and the portion of the base layer (205) . 8. The method of claim 7, comprising the step of removing the coating. The removal step, the exposed base layer (205) to the base layer etchant such as an etchant of the substrate (205) can be spread through the first SAM (207), whereby said first SAM ( 9. The method of claim 8, comprising removing the base layer (205) in the vicinity below 207) . A method for producing a wiring arranged on a base layer (205), the method comprising:
Forming the patterned layer on a portion of the base layer (205) such that the patterned layer (215) forms a target region (220) disposed adjacent to its edge;
Aligning a first self-assembled monolayer (SAM) (207) with the patterned layer, wherein the first layer is chemically bonded to the base layer (205) except for the patterned layer, A first self-assembled monolayer (SAM) (207) comprising an unorganized region within the target region;
Replacing the first self-assembled monolayer (SAM) with a second self-assembled monolayer (SAM) (245) within the target region;
And nucleating a conductive metal crystal in the target region. Disposing an insulating layer (350 ) on the base substrate (310) ; depositing a base layer (305) on the insulating layer (350) ;
Forming a groove (301) in the base layer (305) ,
Forming the patterned layer on a portion of the base layer (305) such that a patterned layer forms a target region disposed adjacent to an edge thereof;
A self-assembled monolayer (SAM) is aligned with the patterned layer, but is chemically bonded to the base layer except for the patterned layer, and the SAM includes an unorganized region within the target region. Process, and
Etching the base layer (305) in the target region to expose the insulating layer, thereby forming a source and drain (355, 360) ;
Forming a gate dielectric (370) in the trench;
Removing the patterned layer;
Forming a semiconductor structure (375) on the gate dielectric (370) and the source and drain (355, 360) .

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