JP4941254B2 - Image compression apparatus, printer, and multifunction machine - Google Patents

Description

  The present invention relates to an image compression apparatus, a printer, and a multifunction peripheral.

  As a technique for compressing data in a printer or the like, a run length compression method or a Huffman coding method is known. In the run-length compression method, original data is converted into information of a data value and the number of consecutive times (length) to reduce the data amount. The Huffman coding method is a method of shortening the average code length by changing the code length according to the establishment of the appearance of the data value. Specifically, the entire compression code amount is reduced by assigning a short code to a data value having a high occurrence probability and assigning a long code to a data value having a low occurrence probability.

For example, when the one-dimensional raster image is “AAABBBBCCDD...”, “A” is counted 3 times, “B” is 4 times, “C” is 2 times, “D” is 2 times,
“Code corresponding to pixel density A” + “Code corresponding to number of times 3”,
“Code corresponding to pixel density B” + “code corresponding to number of times 4”,
“Code corresponding to pixel density C” + “code corresponding to number of times 2”,
“Code corresponding to pixel density D” + “Code corresponding to number of times 2”,...
, And then combined in bit units by a bit combination shift register, compressed data can be obtained.

  In the image compression apparatus, data indicating pixel density (pixel density data) and data indicating the number of times (number of times data) are written and held in separate FIFO circuits. Then, when data is held in each FIFO circuit, an encoding request is sent, the data is read, encoded, and output. Here, the reading of the pixel density data and the reading of the frequency data are read in two clocks.

JP-A-8-195681

  In the conventional method, a problem occurs when non-continuous pixel density appears in the raster image, such as “AAABBBBCDDE” “C”.

  Specifically, as described above, the reading of the pixel density data from the FIFO circuit and the reading of the number of times data are not performed at the same time. Therefore, when the number of times is “1”, before the data is read from the FIFO circuit. Then, the next data is input, and the data overflows. Therefore, the control circuit prohibits data supply to the data supply unit, and as a result, the processing performance decreases.

  Further, according to Huffman coding, the number of bits after coding of 8-bit data is 13 bits at maximum. Therefore, when the code of the pixel density data and the code of the frequency data are combined, there is a possibility that a code of a maximum of 26 bits is generated. On the other hand, the number of bits that can be input to the bit combination shift register is the same as the output bus width, for example, 16 bits. Since the bit combination shift register cannot process a code having a number of bits exceeding the output bus width, data exceeding 16 bits overflows. As a solution, a method of widening the output bus width can be considered, but applicable systems are limited.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a versatile technique that does not reduce processing performance in data compression using a run-length compression method.

To achieve the above object, a first aspect of the present invention, by using the pixel density data of a pixel density, the number of times data indicating the number of continuous pixels of the same concentration, the one-dimensional raster image is compressed that an image compression apparatus, the pixel density data holding circuit in which the pixel density data is held, the number of times the data holding circuit in which the number of data is held, the pixel density data held in the pixel density data holding circuit A first encoding circuit in which the number of times data held in the number of times data holding circuit is encoded, a second encoding circuit in which the number of times data held in the number of times data holding circuit is encoded, the encoded pixel density data and the encoding based on the number of times data, and an output circuit for compressing data of said one-dimensional raster image is generated, when the pixels of the same concentration is not continuous, in the encoded pixel density data, the pressure The number of bits of data and a data unions circuit predetermined coded count data are combined so that the output becomes the bus width following said output circuit.

  According to a second aspect of the present invention, there is provided an image compression apparatus that compresses a one-dimensional raster image by using pixel density data indicating pixel density and frequency data indicating the number of consecutive pixels having the same density. A pixel density data holding circuit for writing and holding the pixel density data; a frequency data holding circuit for writing and holding the number of times data; and the pixel density data when the pixel density data is held in the pixel density data holding circuit. A first encoding circuit that reads and encodes data, and outputs encoded pixel density data; and when the number of times data is held in the number of times data holding circuit, reads and encodes the number of times data, A second encoding circuit that outputs encoded number data, the encoded pixel density data, and the encoded number data are combined, And an output circuit which generates compressed data of the dimensional raster image output, a. The encoded number data indicating that the continuous number of pixels having the same density is 1, the number of bits is the maximum of the number of bits of the encoded pixel density data from the output bus width of the output circuit. It is determined to be less than the number of bits obtained by subtracting the value.

  According to a third aspect of the present invention, there is provided an image compression apparatus for compressing a one-dimensional raster image using pixel density data indicating pixel density and frequency data indicating the number of consecutive pixels having the same density. A pixel density data holding circuit for writing and holding the pixel density data; a number data holding circuit for writing and holding the number of times data; a first encoding circuit for encoding the pixel density data; and encoding the number of times data And a data combination circuit for combining the encoded pixel density data output from the first encoding circuit with the encoded number data indicating that the number of consecutive times is one A selection circuit for inputting, selecting and outputting data output from the first encoding circuit, the second encoding circuit, and the data combination circuit, and the pixel density data holding Comprising road, the number of data holding circuits, and a control circuit for controlling the data selection circuit, an output circuit having a predetermined output bus width for outputting the data output from the selecting circuit. The encoded number data indicating that the continuous number is 1 is obtained by subtracting the maximum value of the number of bits of the encoded pixel density data from the output bus width of the output circuit. It is determined to be less than the number of bits to be obtained. In addition, when the pixel density data is held in the pixel density data holding circuit, the control circuit outputs the pixel density data to the first encoding circuit to the pixel density data holding circuit. When the number data is held in the number data holding circuit, the number data holding circuit is controlled to output the number data to the second encoding circuit. When the count data of the holding circuit indicates other than 1, the encoded pixel density data output from the first encoding circuit and the second encoding circuit are output to the selection circuit. If the number of times data stored in the number of times data holding circuit indicates 1 when the number of times data stored in the number of times data holding circuit is 1, the control is performed so that the input data among the encoded number of times data is output to the output circuit. The data output from the serial data combinational circuit controls so as to output to the output circuit.

  ADVANTAGE OF THE INVENTION According to this invention, in the data compression using a run length compression system, a versatile technique can be provided without deteriorating processing performance.

  Hereinafter, an embodiment of the present invention will be described. First, for easy understanding of the present invention, problems of the prior art will be described in detail.

  FIG. 4 is a diagram showing a schematic configuration of an image compression apparatus 200 in a conventional printer.

  As illustrated, the image compression apparatus 200 includes a first FF (flip-flop) circuit 101, a second FF circuit 102, a third FF circuit 103, a first comparator 111, and a second comparator. A comparator 112, a pixel density data FIFO (first-in first-out) circuit 121, a frequency data FIFO circuit 122, a counter 130, a first encoding circuit 141, a second encoding circuit 142, a control circuit 150, A multiplexer 160 and a bit combination shift register 170 are provided.

  The first FF circuit 101 sequentially inputs data for one pixel of one-dimensional raster image data output from a data supply unit (not shown) in synchronization with the clock, and the first comparator 111, Sequentially output to the second FF circuit 102.

  The second FF circuit 102 sequentially inputs the data output from the first FF circuit 101 one pixel at a time in synchronization with the clock and sequentially outputs the data to the pixel density data FIFO 121 and the third FF circuit 103. .

  The third FF circuit 103 sequentially inputs the data output from the second FF circuit 102 pixel by pixel in synchronization with the clock, and sequentially outputs the data to the second comparator 112.

  In this way, by configuring a three-stage pipeline including the three FF circuits 101, 102, and 103, the image compression apparatus 200 can know the left and right pixel states in the one-dimensional raster image.

  The first comparator 111 compares the data output from the first FF circuit 101 with the data output from the second FF circuit 102. If they are not equal, the first comparator 111 counts the count data FIFO 122 with a counter. A counter value write signal (write request signal) output from 130 is output. In such a case, the write signal is also output to the counter 130 as a counter reset signal.

  The second comparator 112 compares the data output from the second FF circuit 102 with the data output from the third FF circuit 103, and if not equal to the pixel density data FIFO 121, A write signal (write request signal) of data output from the second FF circuit 102 is output.

  The pixel density data FIFO 121 writes and holds the pixel density data output from the second FF circuit 102 in accordance with the write signal output from the second comparator 112. Further, in accordance with a read signal (read request signal) from the control circuit 150, the held pixel density data is output to the first encoding circuit 141.

  The count data FIFO 122 writes and holds the counter value output from the counter 130 as the count data in accordance with the write signal output from the first comparator 111. Further, in accordance with the read signal (read request signal) from the control circuit 150, the held number of times data is output to the second encoding circuit 142.

  The first encoding circuit 141 performs Huffman encoding on the pixel density data output from the pixel density data FIFO 121, generates encoded pixel density data (pixel density data code), and outputs the encoded pixel density data to the multiplexer 160. The first encoding circuit 141 holds a table in which pixel density data values and code values are associated with each other in advance in the register, and the input pixel density data values are converted using the table. Convert to the corresponding code value and perform Huffman coding.

  The second encoding circuit 142 performs Huffman coding on the frequency data output from the frequency data FIFO 122, generates encoded frequency data (code of the frequency data), and outputs the generated data to the multiplexer 160. The second encoding circuit 142 holds a table in which the number data value and the code value are associated in advance in the register, and the input number data value is associated with the table using the table. Convert to code value and perform Huffman coding.

  The control circuit 150 is a circuit that controls the image compression apparatus 200. Specifically, the control circuit 150 monitors the input of data to the pixel density data FIFO 121 and, when detecting that data has been input, sends a read signal (read request signal) to the pixel density data FIFO 121. In addition, the control circuit 150 monitors the input of data to the number-of-times data FIFO 122 and, when detecting that data has been input, sends a read signal (read request signal) to the number-of-times data FIFO 122.

  In addition, the control circuit 150 outputs a selection control signal to cause the multiplexer 160 to select data to be output to the bit combination shift register 170. Specifically, when the control circuit 150 outputs a read signal to the pixel density data FIFO 121, the control circuit 150 outputs data (pixel density data code) output from the first encoding circuit 141 to the multiplexer 160. ) Is output to the bit combination shift register 170. On the other hand, when the control circuit 150 outputs a read signal to the number-of-times data FIFO 122, the data (number-of-times data code) output from the second encoding circuit 142 is bit-coupled to the multiplexer 160. A selection control signal is output so as to be output to the register 170.

  The multiplexer 160 transfers either the data from the first encoding circuit 141 or the data from the second encoding circuit 142 to the bit combination shift register 170 in accordance with the selection control command from the control circuit 150. Output.

  The bit combination shift register 170 is a circuit that outputs compressed data of a one-dimensional raster image to the outside of the image compression apparatus 200. The bit combination shift register 170 sequentially combines the data output from the multiplexer 160 and outputs the combined data to an external device (for example, an image memory).

  The pixel density data and the number of times data are 8 bits at maximum. Further, the maximum number of bits of the code of the Huffman-encoded data by the first encoding circuit 141 or the second encoding circuit 142 is 13 bits.

  The maximum number of bits that can be input to the bit combination shift register 170 is 16 bits, which is the same as the output bus width.

  FIG. 5 is a timing chart when a one-dimensional raster image “AAABBCCDDD...” Is input to the image compression apparatus 200 having such a configuration.

  As shown in the figure, the pixel density data value of the second FF circuit (Pipe1) 102 and the pixel density data value of the second FF circuit (Pipe2) 103 are compared, and if they are not equal, a write signal is output. Then, the pixel density data value of the second FF circuit (Pipe1) 102 is input to the pixel density data FIFO circuit 121.

  Also, the pixel density data value of the first FF circuit (Pipe0) 101 and the pixel density data value of the second FF circuit (Pipe1) 102 are compared, and if they are not equal, a write signal is output and the counter A counter value of 130 is input to the count data FIFO circuit 122.

  By this operation, the pixel density and the continuous number of times of the same pixel density are sequentially specified from the input one-dimensional raster image data.

  Thus, when the one-dimensional raster image does not have a portion where the number of consecutive times is “1” such as “AAABBBBCCD...”, No problem occurs. However, a problem occurs when a portion where the number of times is “1”, such as “C” of “AAABBBBBCDDE.

  FIG. 6 is a timing chart when a one-dimensional raster image “AAABBBBCDDE...” Is input.

  As shown in the figure, when the data value “C” having the number of times “1” is input to the second FF circuit (Pipe1) 102, each of the pixel density data FIFO 141 and the number of times data FIFO 142 is set in one clock. Data will be entered. Then, two encoding requests are generated. On the other hand, since the control circuit 150 controls the pixel density data and the frequency data to be read out in two clocks in order, when data with discontinuous pixel density such as “ABCDE” continues, data is sent to the FIFO circuit. Overflows. In order to avoid this, the control circuit 150 sends a data supply prohibition request to the data supply source before the data overflows. As a result, processing performance decreases.

  Further, even when data is read simultaneously from the FIFO circuit, the maximum number of bits of the encoded data code is 13 bits, so the pixel density data code (maximum 13 bits) and the number data code (maximum) 13 bits) may exceed the number of bits (maximum 16 bits) that can be input to the bit combination shift register. However, increasing the output bus width is not desirable because it limits the applicable systems.

  The present invention has been made in consideration of such circumstances. Hereinafter, an embodiment of the present invention will be described in detail.

  FIG. 1 is a diagram showing a schematic configuration of an image compression apparatus 100 to which an embodiment of the present invention is applied. Such an image compression apparatus 100 is mounted inside a printer. Note that description of other components constituting the printer is omitted. Also, the same or similar components as those of the image compression apparatus 200 in FIG. 4 are denoted by the same reference numerals.

  As illustrated, the image compression apparatus 100 includes a first FF (flip-flop) circuit 101, a second FF circuit 102, a third FF circuit 103, a first comparator 111, and a second comparator. Comparator 112, pixel density data FIFO (first-in first-out) circuit 121, number-of-times data FIFO circuit 122, counter 130, first encoding circuit 141, second encoding circuit 142, and data combination circuit 143 A control circuit 150, a multiplexer 160, and a bit combination shift register 150.

  The first FF circuit 101 sequentially inputs data for one pixel of one-dimensional raster image data output from a data supply unit (not shown) in synchronization with the clock, and the first comparator 111, Sequentially output to the second FF circuit 102.

  The second FF circuit 102 sequentially inputs the data output from the first FF circuit 101 one pixel at a time in synchronization with the clock and sequentially outputs the data to the pixel density data FIFO 121 and the third FF circuit 103. .

  The third FF circuit 103 sequentially inputs the data output from the second FF circuit 102 pixel by pixel in synchronization with the clock, and sequentially outputs the data to the second comparator 112.

  In this way, by configuring a three-stage pipeline including the three FF circuits 101, 102, and 103, the image compression apparatus 200 can know the left and right pixel states in the one-dimensional raster image.

  The first comparator 111 compares the data output from the first FF circuit 101 with the data output from the second FF circuit 102. If they are not equal, the counter value write signal (write request signal) output from the counter 130 is output to the count data FIFO 122. At the same time, a counter reset signal is output to the counter 130.

  The second comparator 112 compares the data output from the second FF circuit 102 with the data output from the third FF circuit 103, and if not equal to the pixel density data FIFO 121, A write signal (write request signal) of data output from the second FF circuit 102 is output.

  The pixel density data FIFO 121 writes and holds the pixel density data output from the second FF circuit 102 in accordance with the write signal output from the second comparator 112. Further, in accordance with a read signal (read request signal) from the control circuit 150, the held pixel density data is output to the first encoding circuit 141.

  The count data FIFO 122 writes and holds the counter value output from the counter 130 as the count data in accordance with the write signal output from the first comparator 111. Further, in accordance with the read signal (read request signal) from the control circuit 150, the held number of times data is output to the second encoding circuit 142.

  The first encoding circuit 141 performs Huffman encoding on the pixel density data output from the pixel density data FIFO 121, generates encoded pixel density data (pixel density data code), and outputs the encoded pixel density data to the multiplexer 160. Note that the first encoding circuit 141 holds a table (density data conversion table) in which pixel density data values and code values are associated with each other in advance, and is input using the table. The pixel density data value is converted into a corresponding code value, and Huffman coding is performed.

  FIG. 2A is a diagram showing the configuration of the density data conversion table 210. The density data conversion table 210 stores Huffman encoded data (code) 212 corresponding to the pixel density data value (density value) 211 in consideration of appearance establishment. In the Huffman encoded data 212, a short code is assigned to a data value having a high probability of occurrence, and a long code is assigned to a data value having a low probability of occurrence.

  The Huffman encoded data 212 may be obtained from a statistical value of the appearance frequency of the pixel density of a general image. Prior to the image compression process, the Huffman encoded data 212 is read once to process the image data. It may be generated in advance from the appearance frequency of the concentration.

  The second encoding circuit 142 performs Huffman coding on the frequency data output from the frequency data FIFO 122, generates encoded frequency data (code of the frequency data), and outputs the generated data to the multiplexer 160. The second encoding circuit 142 holds a table (number data conversion table) in which the number data value and the code value are associated with each other in advance in the register, and the number of times input by using this table. The data value is converted into a corresponding code value and Huffman coding is performed.

  FIG. 2B is a diagram showing the configuration of the number data conversion table 220. The number-of-times data conversion table 220 stores Huffman encoded data (code) 222 corresponding to the number-of-times data value (the number of consecutive pixels having the same density) 221 in consideration of appearance establishment. In the Huffman encoded data 222, a short code is assigned to a data value having a high occurrence probability, and a long code is assigned to a data value having a low occurrence probability.

  The Huffman encoded data 222 may be obtained from a statistical value of the appearance frequency of the “continuous number” of pixels having the same density in a general image, or the image to be processed prior to the image compression process. Data may be read once and generated in advance from the appearance frequency of “continuous number of times”.

  The data combination circuit 143 adds a code indicating the number of times “1” to the code of the pixel density data output from the first encoding circuit 141 and outputs the code to the multiplexer 160. Here, the sum of the number of bits of the pixel density data code and the number of bits of the code indicating the number of times “1” needs to be equal to or less than the number of bits that can be input to the bit combination shift register 170. That is, the number of bits of the code indicating the number of times “1” is equal to or less than a value obtained by subtracting the maximum number of bits of the pixel density data code from the number of bits that can be input to the bit combination shift register 170 (same as the output bus width). .

  Since the maximum bit number of Huffman encoded data of 8-bit pixel density data is 13 bits and the output bus width of the bit combination shift register 170 is 16 bits, the code indicating the number of times “1” is, for example, “ 101 "is defined by 3 bits.

  The control circuit 150 is a circuit that controls the image compression apparatus 100. Specifically, the control circuit 150 monitors the input of data to the pixel density data FIFO 121 and, when detecting that data has been input, sends a read signal (read request signal) to the pixel density data FIFO 121. In addition, the control circuit 150 monitors the input of data to the number-of-times data FIFO 122 and, when detecting that data has been input, sends a read signal (read request signal) to the number-of-times data FIFO 122.

  In addition, the control circuit 150 outputs a selection control signal to cause the multiplexer 160 to select data to be output to the bit combination shift register 170. Specifically, when the control circuit 150 outputs a read signal to the pixel density data FIFO 121, the control circuit 150 outputs data (pixel density data code) output from the first encoding circuit 141 to the multiplexer 160. ) Is output to the bit combination shift register 170. On the other hand, when the control circuit 150 outputs a read signal to the number-of-times data FIFO 122, the data (number-of-times data code) output from the second encoding circuit 142 is bit-coupled to the multiplexer 160. A selection control signal is output so as to be output to the register 170.

  However, when the count data input to the count data FIFO circuit 122 indicates “1”, the control circuit 150 simultaneously sends a read signal to the pixel density data FIFO 121 and the count data FIFO 122. At the same time, the selection control signal is output so that the data output from the data combination circuit 143 (the code of the pixel density data + the code indicating “once”) is output to the bit combination shift register 170 to the multiplexer 160. Is output.

  The multiplexer 160 transfers either the data from the first encoding circuit 141 or the data from the second encoding circuit 142 to the bit combination shift register 170 in accordance with the selection control command from the control circuit 150. Output.

  The bit combination shift register 170 is a circuit that outputs compressed data of a one-dimensional raster image to the outside of the image compression apparatus 200. The bit combination shift register 170 sequentially combines the data output from the multiplexer 160 and outputs the combined data to an external device (for example, an image memory).

  The schematic configuration of the image compression apparatus 100 has been described above.

  FIG. 3 is a flowchart showing an operation flow of the image compression apparatus 100.

  The control circuit 150 monitors whether there is data in the pixel density data FIFO 121 (S11). If there is data (Y in S11), the control circuit 150 determines whether there is data indicating the number of times “1” in the number of times data FIFO 122. (S12).

  When there is no data indicating the number of times “1” (N in S12), the control circuit 150 sends a read signal to the pixel density data FIFO 121, and the multiplexer 160 receives the pixel density data output from the first encoding circuit 141. A selection control signal is sent to output a code (S13). As a result, the multiplexer 160 selects the code of the pixel density data and outputs it to the bit combination shift register 170. Thereafter, the control circuit 150 waits for the count data to be stored in the count data FIFO 122 (S14). When the data is stored (Y in S14), the control circuit 150 sends a read signal to the count data FIFO 121 to the multiplexer 160. The selection control signal is sent so as to output the code of the number-of-times data output from the second encoding circuit 142 (S15). As a result, the multiplexer 160 selects the code of the number data and outputs it to the bit combination shift register 170. Thereafter, the control circuit 150 returns to S11 and continues control.

  On the other hand, when there is data indicating the number of times “1” (Y in S12), the control circuit 150 simultaneously sends a read signal to both the pixel density data FIFO 121 and the number of times data FIFO 122. At the same time, the multiplexer 160 selects the code output from the data combination circuit 143 (the pixel density data code + the code indicating the number of times “1”) and outputs a selection control signal to the bit combination shift register 170. Send (S16). As a result, data is read from the pixel density data FIFO 121 and the number-of-times data FIFO 122, and the multiplexer 160 selects the code from the data combination circuit 143 and outputs it to the bit combination shift register 170. Thereafter, the control circuit 150 returns to S11 and continues control.

  According to the above embodiment, when the same pixel is not continuous, the data of the pixel density data FIFO 121 and the number-of-times data FIFO 122 are read at the same time, so that the data does not overflow.

  In addition, since the code indicating that “the pixel of the same density is once” is within 3 bits, even if the code of the image density data is the maximum number of bits (13 bits), the bit combination shift register 170 The number of inputtable bits (13 bits) is not exceeded. Therefore, the problem that occurs in the above-described conventional image compression apparatus 200 does not occur.

  The image compression apparatus of the present invention is not limited to the above embodiment. Various modifications are possible within the scope of the technical idea of the present invention.

  Further, the present invention can be applied as an image compression circuit of a multifunction machine having at least two functions such as a printer function, a scanner function, a copy function, and a facsimile function as well as a printer.

1 is a block diagram illustrating a configuration of an image compression device. The figure which shows the structural example of a data conversion table. The flowchart of operation | movement of an image compression apparatus. The block diagram which shows the structure of the conventional image compression apparatus. The figure for demonstrating the problem of the conventional image compression apparatus. The figure for demonstrating the problem of the conventional image compression apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Image compression apparatus, 101 ... 1st FF circuit, 102 ... 2nd FF circuit, 103 ... 3rd FF circuit, 111 ... 1st comparator, 112 ... 2nd comparator, 121 ... Image density Data FIFO circuit, 122 ... Count data FIFO circuit, 130 ... Counter, 140 ... Control circuit, 141 ... First encoding circuit, 142 ... Second encoding circuit, 143 ... Data combination circuit, 150 ... Control circuit, 160 ... Multiplexer, 170 ... Bit combination shift register, 200 ... Image compression apparatus

Claims (6)

By using the pixel density data of a pixel density, the number of times data indicating the number of continuous pixels of the same density, and an image compression apparatus one-dimensional raster image is compressed,
And pixel density data holding circuit the pixel density data is held,
The number of times the data holding circuit the number of times data is held,
A first encoding circuit in which the pixel density data held in the pixel density data holding circuit is encoded,
A second encoding circuit in which the number of times data held in the count data holding circuit is encoded,
An output circuit for generating compressed data of the one-dimensional raster image based on the encoded pixel density data and the encoded number of times data;
When the pixels having the same density are not consecutive , the encoded number of times data that is determined in advance so that the number of bits of the compressed data is less than or equal to the output bus width of the output circuit is included in the encoded pixel density data. And a data combination circuit combined with each other . The image compression apparatus according to claim 1,
The encoded number data indicating that the number of consecutive pixels of the same density is 1, the number of bits is the maximum value of the number of bits of the encoded pixel density data from the output bus width of the output circuit. An image compression apparatus characterized by being set to be equal to or less than the number of bits obtained by subtracting.
An image compression apparatus that compresses a one-dimensional raster image using pixel density data indicating pixel density and frequency data indicating the number of consecutive times of pixels having the same density,
A pixel density data holding circuit for writing and holding the pixel density data;
A frequency data holding circuit for writing and holding the frequency data;
A first encoding circuit for encoding the pixel density data;
A second encoding circuit for encoding the count data;
A data combination circuit that combines encoded pixel density data output from the first encoding circuit with encoded number data indicating that the number of consecutive times is one;
A selection circuit for inputting, selecting and outputting data output from the first encoding circuit, the second encoding circuit, and the data combination circuit;
A control circuit for controlling the pixel density data holding circuit, the number-of-times data holding circuit, and the data selection circuit;
An output circuit having a predetermined output bus width for outputting data output from the selection circuit;
With
The encoded number data indicating that the continuous number is 1,
The number of bits is determined to be equal to or less than the number of bits obtained by subtracting the maximum value of the number of bits of the encoded pixel density data from the output bus width of the output circuit,
The control circuit includes:
When the pixel density data is held in the pixel density data holding circuit, the pixel density data holding circuit is controlled to output the pixel density data to the first encoding circuit,
When the number data holding circuit holds the number data, the number data holding circuit is controlled to output the number data to the second encoding circuit,
When the number data of the number data holding circuit indicates other than 1, the encoded pixel density data output from the first encoding circuit and the second encoding circuit are output to the selection circuit. Control the input data out of the encoded number of times output to be output to the output circuit,
When the number data of the number data holding circuit indicates 1, the selection circuit is controlled to output the data output from the data combination circuit to the output circuit.
An image compression apparatus. The image compression apparatus according to any one of claims 1 to 3,
A first flip-flop circuit that inputs and outputs the pixel density data in a predetermined cycle in order;
A second flip-flop circuit that inputs pixel density data output from the first flip-flop circuit at the predetermined cycle and sequentially outputs the pixel density data;
A third flip-flop circuit that inputs pixel density data output from the second flip-flop circuit at the predetermined cycle and sequentially outputs the pixel density data;
The pixel density data output from the first flip-flop circuit and the pixel density data output from the second flip-flop circuit are compared. If they are not equal, a first data write signal is output. A comparison circuit of
The pixel density data output from the second flip-flop circuit and the pixel density data output from the third flip-flop circuit are compared. If they are not equal, a second pixel density data write signal is output. A comparison circuit of
A counter circuit that increments the count value at the predetermined period and resets the counter value when the count data write signal is output,
The pixel density data holding circuit includes:
It consists of a FIFO circuit,
When the pixel density data write signal is output, the pixel density data output from the second flip-flop circuit is written and held,
The number of times data holding circuit is
It consists of a FIFO circuit,
When the count data write signal is output, the counter value output from the counter circuit is written and held as count data.
An image compression apparatus.   The printer provided with the image compression apparatus as described in any one of Claims 1-4. Comprising the image compression apparatus according to any one of claims 1 to 5, and
A multifunction machine having at least two functions of a printer function, a scanner function, a copy function, and a facsimile function.

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