JP4461859B2 - Run-length code decoding apparatus - Google Patents

Description

  The present invention relates to a run-length code decoding apparatus, and more particularly to speeding up decoding processing.

  Conventionally, MPEG2 is known as a standard for image data compression and decompression. In MPEG2, image data is processed in units of blocks of 8 pixels × 8 pixels (or macro blocks of 16 pixels × 16 pixels). Specifically, DCT (Discrete Cosine Transform), quantization, and run length coding are performed. The data is compressed by variable length coding. Each process is known, but in brief, DCT converts spatial domain image data into frequency domain data. In a general image, energy concentrates in a low frequency region and energy in a high frequency region is small. Therefore, non-zero and relatively large coefficients can be concentrated in the low frequency region. When DCT conversion is performed on a block of 8 pixels × 8 pixels, one DC coefficient and 63 AC coefficients are generated. In the quantization, the number of data is compressed by roughly quantizing the coefficient in the high frequency region than in the low frequency region. As a result, the small value coefficient in the high frequency region is converted to almost zero. Run-length encoding is a zero-run-length data word that indicates the number of zero components preceding the non-zero component while scanning the quantization result in a zigzag pattern so that the zero components are likely to be continuous, and a non-zero value. A data stream composed of level data words is generated. In variable-length coding, a Huffman code is used to encode a data stream by assigning a short code to high-frequency data and assigning a long code to low-frequency data. A similar technique is used in JPEG.

  When decoding the image data compressed in this way, reverse processing at the time of compression is performed. That is, variable length decoding, run length code decoding, inverse quantization, and inverse DCT are sequentially performed to restore the original image data.

  FIG. 6 shows a conventional run-length code decoding apparatus described in the following patent document.

  The variable length code decoder (VLD) 201 outputs a block start signal indicating the start of one block to the signal line 205 when the variable length code of the DC coefficient is supplied to the data input terminal 200. When a variable-length code of an AC coefficient is applied to the data input terminal 200, a run-length data word representing the number of zero components preceding the non-zero component is sent to the signal line 207 to represent the absolute value of the non-zero component. The level data word is supplied to the signal line 208, and 1-bit information specifying whether the non-zero component is positive or negative is supplied to the signal line 209. The decoding result of the DC coefficient is supplied to the signal lines 208 and 209 as level data. When a variable length code of EOB (end of block) is applied to the data input terminal 200, an EOB detection signal is supplied to the signal line 206.

  The address counter 223 to which the block start signal is input sequentially counts up the count value from the initial value in synchronization with the clock signal 202 and supplies the count value to the signal line 224 as an address. When the count value reaches 63, a pulse signal indicating the end of the block is supplied as a block end signal to the signal line 225 (one block is composed of 8 pixels × 8 pixels = 64 pixels). In the initial state, the RS flip-flop 228 sets the signal line 229 to the L level, sets the signal line 229 to the H level when the EOB detection signal of the signal line 206 is input, and sets the signal line 229 to the L level when the block end signal is input. Reset.

  The lookup table 226 has an address conversion table corresponding to the zigzag scan, converts the address of the signal line 224 into a zigzag scan address corresponding to the address, and supplies it to the signal line 227. The zigzag scan address is given to the scan conversion RAM 232 as a write address.

  The zero-length data word is stored in the down counter 212, the level data word is stored in the first data latch 211, and the 1-bit information is stored in the 1-bit latch 210 in synchronization with the clock signal 202, respectively. The down counter 212 counts down the preset zero-length data word until it becomes zero. The level word data stored in the first data latch 211 is supplied to the positive / negative value switching unit 216 via the signal line 215, and the 1-bit information stored in the 1-bit latch 210 is supplied to the positive / negative value switching unit 216 via the signal line 214. . The positive / negative value switching unit 216 calculates a signed level data word and supplies it to the signal line 218.

  During the counting operation of the down counter 212, the NOR circuit 230 fixes the selection signal of the signal line 231 to the H level. The multiplexer 219 to which the H level selection signal is input supplies the fixed data word 0 to the signal line 220. When the count value of the down counter 212 becomes 0, the signal line 213 and the signal line 217 become L level, and the multiplexer 219 supplies the signed level data word on the signal line 218 to the signal line 220. The fixed data word 0 and the signed level data word supplied onto the signal line 220 are stored in the second data latch 221 in synchronization with the clock signal 202. The data words sequentially stored in the second data latch 221 are given as write data to the scan conversion RAM 232 via the signal line 222. Therefore, a series of data words is written at a position specified by the zigzag scan address in the scan conversion RAM 232, and one block composed of 8 × 8 components is restored in the scan conversion RAM 232. The 64 data restored in the scan conversion RAM 232 are sequentially supplied from the data output terminal 234 to the next-stage inverse quantizer.

JP-A-8-167856

  However, in the above prior art, only one data can be output to the next-stage quantizer, and the write side of the scan conversion RAM 232 must be in a standby state before outputting all the data. There is a problem that the throughput of processing as a whole is suppressed.

  In addition, since an initialization circuit and initialization control are required to write and initialize zero before writing a non-zero coefficient into the scan conversion RAM 232, there is a problem that the circuit is increased and the control is complicated. is there.

  An object of the present invention is to provide a decoding apparatus that can improve the overall throughput with a simple configuration without requiring an initialization circuit and initialization control separately.

  The present invention is an apparatus for decoding a discrete cosine transform and run-length encoded data stream, the DC register storing data corresponding to a DC component in the discrete cosine transform of the data stream, and the data stream And an AC register for storing data corresponding to the AC component in the discrete cosine transform, and the AC register at a timing of writing data corresponding to the DC component in the discrete cosine transform of the data stream to the DC register. Control means for writing zero data to the register.

  An apparatus for decoding a discrete cosine transform (DCT) and run-length encoded data stream includes run-length decoding and inverse DCT. Although DCT is converted into frequency domain data in units of blocks, the decoding apparatus of the present invention includes a DC register for storing data corresponding to a DC (direct current) component in DCT and data corresponding to an AC (alternating current) component. The decoded data is stored using an AC register for storing. When writing data corresponding to the DC component to the DC register, there is no data to be written to the AC register. However, in the present invention, the AC register is not put into a standby state, and the DC component data is stored in the DC register. The zero register is written to the AC register at the timing of writing the data to initialize the AC register. This eliminates the need to separately initialize the AC register before writing to the AC register. After the AC register is initialized at the timing of writing data to the DC register, the data is written to the AC register. However, since zero data is already stored in the AC register and initialized, the AC component data Of these, it is not necessary to write zero data again to the AC register, and only non-zero data needs to be written to the AC register, thereby realizing an efficient writing process.

  More specifically, the data stream to be decoded may have been subjected to DCT, quantization, zigzag scan, run-length encoding, and variable-length encoding processing steps. In this case, the decoding apparatus performs variable-length decoding, run-length encoding. Decoding, zigzag scanning, inverse quantization, and inverse DCT processes are executed. The DC register and AC register according to the present invention store run-length decoded data, and supply data necessary for subsequent inverse quantization or inverse DCT.

  In one embodiment of the present invention, among the AC registers, a register that does not need to write zero data based on zero run length data indicating the number of zero components preceding the non-zero component included in the data stream. Specify the register to which the non-zero component is to be written, and write the non-zero data.

  In another embodiment of the present invention, a plurality of sets of DC registers and AC registers are provided, and decoding data is written and read alternately in these sets. Processing throughput is further improved by so-called ping-pong control in which writing and reading are alternately performed.

  According to the present invention, since the data corresponding to the DC component of the data stream is stored in the DC register, zero data is written into the AC register and the AC register is initialized, thereby improving the processing throughput. it can.

  Further, the throughput of processing can be further improved by outputting the data stored in the DC register and AC register simultaneously or in an appropriate order within the range allowed by the subsequent processing.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 shows the configuration of a run-length code decoding apparatus according to this embodiment. The decoding apparatus shown in FIG. 6 does not have the scan conversion RAM 232, but instead has the DC coefficient register 14 and the AC coefficient register 16.

  The variable length code decoder (VLD) 10 receives the run-length encoded data stream and performs variable length decoding similarly to the variable length code decoder (VLD) 201 shown in FIG. At this time, when a variable length code of DC coefficient in DCT is input, the decoding result is output, and when a variable length code of AC coefficient in DCT is input, it represents the number of zero components preceding non-zero components. A run-length data word and a level data word representing the absolute value of the non-zero component are output. Also, 1-bit information designating whether the non-zero component is positive or negative is output. In the figure, a data word that is a DC coefficient decoding result and a signed level data word of an AC coefficient are collectively shown as “data”, and a run-length data word is simply shown as “run-length”. The variable length code decoder 10 outputs an identification signal indicating whether the input coefficient is a DC coefficient or an AC coefficient. Since the DC coefficient is located at the head of the block, it is easy to identify the DC coefficient / AC coefficient. In the figure, the identification signal is simply indicated as “DC / AC”. “Data” from the variable-length code decoder 10 is supplied to the DC coefficient register 14 and the AC coefficient register 16 via the signal line 100. The “run length” and “DC / AC” identification signals from the variable length code decoder 10 are supplied to the cumulative decoder 12 via the signal line 102. The “DC / AC” identification signal is also supplied to all the words in the DC coefficient register 14 and the AC coefficient register 16 described later.

  The progressive decoder 12 corresponds to the address counter 223 in FIG. 6, but its function is different. That is, when the DC / AC identification signal from the variable-length code decoder 10 indicates a DC coefficient, a selection signal is output to the DC coefficient register 14 via the signal line 106. A selection signal is output to the coefficient register 16 via the signal line 106. When a selection signal is output to the AC coefficient register 16, the run-length word data from the variable length code decoder 10 is referred to, and the selection signal is output to a register corresponding to a non-zero coefficient. In other words, the cumulative decoder 12 jumps over the AC coefficient registers by the number of zero components, and outputs a selection signal to the register corresponding to the coefficient that is non-zero. Specifically, the selection signal is transmitted by setting the signal line 106 from L level to H level. The selection signal functions as an enable signal for writing data to the register.

  The DC coefficient register 14 and the AC coefficient register 16 are provided separately. The DC coefficient register stores one word data of the DC coefficient, and the AC coefficient register 16 stores 63 word data of the AC coefficient.

  The DC coefficient register 14 is supplied with the data from the variable-length code decoder 10, that is, the DC coefficient decoding result via the signal line 100, and the selection signal from the cumulative decoder 12 is supplied via the signal line 106. Is done. The DC coefficient register 14 stores the decoding result of the DC coefficient when the selection signal is supplied (when the signal line 106 becomes H level).

  The AC coefficient register 16 is supplied with the data from the variable-length code decoder 10, that is, the decoding result of the non-zero component through the signal line 100, and the selection signal from the cumulative decoder 12 through the signal line 106. The DC / AC identification signal from the variable length code decoder 10 is also supplied. The AC coefficient register 16 writes zero in all the registers when the DC / AC identification signal designates a DC coefficient. That is, zero is written in the AC coefficient register 16 at the timing when the DC coefficient is written in the DC coefficient register 14. On the other hand, when the DC / AC identification signal specifies an AC coefficient, the AC coefficient register 16 writes data in the register in accordance with the selection signal supplied via the signal line 106. The selection signal is set according to the number of zeros. For example, when the number of zeros is 3, the selection signal is output to the fourth highest register among the AC coefficient registers 16. Write data to the 4th register. In this case, no data is written to the first to third registers, but in the DC coefficient writing process prior to the writing of the AC coefficient, all the registers of the AC coefficient register 16 are simultaneously set to zero. Is written, the first to third registers are maintained at zero.

  The 64 pieces of data stored in the DC coefficient register 14 and the AC coefficient register 16 are supplied to the subsequent selector 18 via the signal line 108.

  After the selector 18, it is output to the inverse quantizer and further to the inverse DCT (in the figure, both are collectively shown as the inverse DCT 20). A selection signal is supplied from the inverse DCT unit 20 to the selector 18 via the signal line 110. The selector 18 collects a plurality of data out of the 64 data at the timing specified by the selection signal, or simultaneously passes the 64 data via the signal line 112 if the configuration and function of the inverse DCT device 20 allow. To the inverse DCT device 20.

  FIG. 2 shows a processing flowchart of the DC coefficient register 14 and the AC coefficient register 16 in the present embodiment.

  First, based on the DC / AC identification signal from the variable length code decoder 10, it is determined whether the input data is a DC coefficient or an AC coefficient (S101). If there is word data indicating the head of the block, it is a DC coefficient, and otherwise, it is an AC coefficient. Therefore, it may be determined whether or not it is the head data of the block.

  When the input data is a DC coefficient, a selection signal is supplied to the DC coefficient register 14, so the DC coefficient register 14 stores the DC coefficient decoded data from the variable length code decoder 10 (S102). Since the DC / AC identification signal is also supplied to the DC coefficient register, the DC coefficient decoded data may be stored based on this identification signal instead of the selection signal. When the input data is a DC coefficient, the AC coefficient register 16 writes zero data in all the registers (S103). Specifically, a selector is provided in front of the AC coefficient register 16, zero data and a DC / AC identification signal are supplied to this selector, and if the coefficient is a DC coefficient, zero data is sent from the selector to all the AC coefficient registers 16. It is sufficient to supply to the register and write. This process of writing zero to the AC coefficient register 16 at the timing of writing the DC coefficient can be called a zero data pre-writing process in the next AC coefficient writing together with the initialization process of the AC coefficient register 16.

  On the other hand, when the input data is an AC coefficient, only the register corresponding to the non-zero component specified by the run-length data is selected from the AC coefficient register 16 having a 63 word register and selected by the selection signal. (S104). For example, 0, 1, 2, 3,... Are sequentially added to the word data from the beginning of the block (number 0 corresponds to a DC coefficient), the zero run length of code number 1 is 1, and code number 2 When the zero run length is 3 and the zero run length of code 3 is 0, a selection signal is output to the second, sixth, and seventh registers of the AC coefficient register 16 (selection signal). , Becomes the active state at the H level), the selection signal is not output to the first, third to fifth registers (the selection signal becomes the L level and the inactive state). After selecting the register to be written, the AC coefficient decoded data from the variable-length code decoder 10 is written into the selected register (S105). This data is signed level data.

  The above process is repeated for all coefficient data (S106), and a total of 64 data is stored in the registers 14 and 16. The stored data is simultaneously supplied to the inverse DCT unit 20 via the selector 18 as described above (for example, eight data or more data in parallel).

  FIG. 3 shows the configuration of the DC coefficient register 14. A selector 13 is provided in front of the DC coefficient register 14, and data (decoded data) is supplied to the selector 13 via the signal line 100, and a DC / AC identification signal is supplied to the selector 13 via the signal line 104. A selection signal is supplied via 106.

  The selector 13 supplies the data supplied via the signal line 100 to the DC coefficient register 14 when the DC / AC identification signal specifies DC or when the selection signal is at the H level. The DC coefficient register 14 stores the DC coefficient decoded data in synchronization with the clock signal CLK. When the DC / AC identification signal specifies AC, or when the selection signal is at the L level, the selector 13 does not output data from the signal line 100 and holds the value of the DC coefficient register 14.

  FIG. 4 shows the configuration of the AC coefficient register 16. A selector 15 is provided in front of all the registers of the AC coefficient register 16, data (decoded data) is supplied to the selector 15 via the signal line 100, and a DC / AC identification signal is supplied via the signal line 104. Then, a selection signal is supplied via the signal line 106. The selector 15 is also supplied with zero data.

  When the DC / AC identification signal specifies DC, the selector 15 selects zero data and supplies it to the AC coefficient register 16. The AC coefficient register 16 stores zero data in synchronization with the clock signal CLK regardless of the selection signal. In the cumulative decoder 12, when the DC / AC identification signal designates DC, all selection signals supplied to the DC coefficient register 14 and the AC coefficient register 16 are set to H level (active state) and writing to all the registers is performed. It is good also as a structure to permit. When the DC / AC identification signal specifies AC, the selector 15 selects the data from the signal line 100 and supplies it to the AC coefficient register 16 only when the selection signal is at the H level. When the selection signal is at the L level, the selector 15 does not output data from the signal line 100 and the zero data stored in the AC coefficient register 16 is maintained as it is.

  As described above, in this embodiment, at the timing of writing the DC coefficient decoded data to the DC coefficient register 14, zero data is simultaneously written to all the registers (63 registers in total) of the AC coefficient register 16 to be initialized. Therefore, a separate process for initializing the register is not required. Also, when writing AC coefficient decoded data, only one block of decoded data can be stored in the register by writing the decoded data only to the register corresponding to the non-zero component in the AC coefficient register 16. In this embodiment, since all 64-word registers are used instead of RAM, a plurality of pieces of data required for subsequent processing such as inverse quantization and inverse DCT are simultaneously processed and appropriately sequential (zigzag scan). Can be output sequentially).

  As mentioned above, although embodiment of this invention was described, this invention is not restricted to this, A various deformation | transformation is possible.

  For example, in the present embodiment, one DC coefficient register 14 and one AC coefficient register 16 are provided. However, two register sets each including the DC coefficient register 14 and the AC coefficient register 16 are provided, and these registers are written. The overall throughput can be further improved by alternately switching and executing reading.

  FIG. 5 shows a configuration of a double (or dual) register system in which two register sets are provided as described above.

  The first register set includes a DC coefficient register 14a and an AC coefficient register 16a, and the second register set includes a DC coefficient register 14b and an AC coefficient register 16b.

  When a data stream of a certain block is supplied to the decoding device, the progressive decoder 12 selects the DC coefficient register 14a and the AC coefficient register 16a, and writes the decoded data of the DC coefficient and the AC coefficient by the above-described processing. Specifically, in the case of a DC coefficient, the selection signal of the DC coefficient register 14a and the AC coefficient register 16a is set to the H level, the selection signal of the DC coefficient register 14b and the AC coefficient register 16b is set to the L level, and the DC coefficient is selected. Coefficient decoded data is written into the DC coefficient register 14a, and zero data is written into the AC coefficient register 16a. Next, in the case of an AC coefficient, only the register corresponding to the non-zero component specified by the run length data in the AC coefficient register 16a is set to the H level and the decoded data of the AC coefficient is written.

  When the data stream of the next block is supplied to the decoding device, the progressive decoder 12 selects the DC coefficient register 14b and the AC coefficient register 16b, and writes the decoded data of the DC coefficient and the AC coefficient by the above-described processing. Specifically, in the case of a DC coefficient, the selection signal of the DC coefficient register 14b and the AC coefficient register 16b is set to the H level, the selection signal of the DC coefficient register 14a and the AC coefficient register 16a is set to the L level, and the DC coefficient is selected. Coefficient decoded data is written into the DC coefficient register 14b, and zero data is written into the AC coefficient register 16b. Next, in the case of an AC coefficient, only the register corresponding to the non-zero component specified by the run length data in the AC coefficient register 16b is set to the H level and the decoded data of the AC coefficient is written. Further, at the timing when the decoded data of this block is written to the DC coefficient register 14b and the AC coefficient register 16b, the decoded data from the DC coefficient register 14a and the AC coefficient register 16a in which the decoded data of the previous block has already been stored. Is output.

  When the data stream of the next block is supplied to the decoding device, the cumulative decoder 12 selects the DC coefficient register 14a and the AC coefficient register 16a, and writes the decoded data of the DC coefficient and the AC coefficient. Specifically, in the case of a DC coefficient, the selection signal of the DC coefficient register 14a and the AC coefficient register 16a is set to the H level, the selection signal of the DC coefficient register 14b and the AC coefficient register 16b is set to the L level, and the DC coefficient is selected. Coefficient decoded data is written into the DC coefficient register 14a, and zero data is written into the AC coefficient register 16a. Next, in the case of an AC coefficient, only the register corresponding to the non-zero component specified by the run length data in the AC coefficient register 16a is set to the H level and the decoded data of the AC coefficient is written. Also, at the timing of writing the decoded data of this block to the DC coefficient register 14a and the AC coefficient register 16a, the decoded data from the DC coefficient register 14b and the AC coefficient register 16b in which the decoded data of the previous block has already been stored. Is output.

  As described above, the decoding process can be speeded up by alternately writing / reading the two register sets.

  The decoding apparatus of this embodiment can be applied to any device that decodes compressed image data that has been subjected to DCT and run-length encoding and outputs original image data. An example of such a device is multifunctional It is a copier.

It is a block diagram of the decoding apparatus which concerns on embodiment. It is a processing flowchart of an embodiment. FIG. 2 is a configuration diagram of a DC coefficient register in FIG. 1. FIG. 2 is a configuration diagram of an AC coefficient register in FIG. 1. It is a block diagram of the decoding apparatus which concerns on other embodiment. It is a block diagram of a conventional apparatus.

Explanation of symbols

  10 variable length code decoder (VLD), 12 accumulative decoder, 14 DC coefficient register, 16 AC coefficient register, 18 selector, 20 inverse DCT unit.

Claims (3)

An apparatus for decoding a data stream that has been subjected to discrete cosine transform, run length encoding, and variable length encoding for each predetermined block,
A variable length decoder that performs variable length decoding of the data stream and outputs decoded data, zero run length data, and DC component and AC component identification data of the discrete cosine transform;
A DC register for storing decoded data corresponding to the DC component of the discrete cosine transform which is the head data of the block;
AC registers for storing decoded data corresponding to AC components of discrete cosine transform, which is non-leading data of the block,
Based on the identification data, when the data of the data stream is decoded data corresponding to a DC component, the decoded data is written to the DC register and zero data is written to all of the AC registers, and the data stream Means for selecting the register corresponding to the non-zero component indicated by the run-length data and writing the decoded data out of the AC register when the data is decoded data corresponding to the AC component;
Selection output means for simultaneously outputting a plurality of data stored in the DC register and the AC register at a predetermined timing;
A run-length code decoding apparatus comprising: The apparatus of claim 1.
The AC registers are provided by the number of AC components included in the data stream,
When the data of the data stream is decoded data corresponding to an AC component, the writing means corresponds to the number of zero components preceding the non-zero component indicated by the run-length data in the AC register. An apparatus for decoding a run-length code , wherein the decoded data is written to a register corresponding to the non-zero component without writing to a register . The apparatus of claim 1.
A run-length code decoding apparatus , wherein a plurality of sets of the DC register and the AC register are provided .

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