JP4935139B2 - 多層プリント配線板 - Google Patents
多層プリント配線板 Download PDFInfo
- Publication number
- JP4935139B2 JP4935139B2 JP2006087566A JP2006087566A JP4935139B2 JP 4935139 B2 JP4935139 B2 JP 4935139B2 JP 2006087566 A JP2006087566 A JP 2006087566A JP 2006087566 A JP2006087566 A JP 2006087566A JP 4935139 B2 JP4935139 B2 JP 4935139B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- cavity
- printed wiring
- conductor
- side wall
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
- H01L2924/19103—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
図19〜図22は、本発明の実施形態に係る多層プリント配線板のキャビティ1内部に電子部品70を実装した様々な例を模式的に示した断面図である。
Claims (6)
- 電子部品実装用のキャビティとなる貫通穴をあけた上側プリント配線板と、前記キャビティの底面を構成する下側プリント配線板とが一体化されるように絶縁層を介して積層されている多層プリント配線板であって、
前記キャビティの前記底面上から、前記絶縁層と前記下側プリント配線板との間の一部まで延在するように、絶縁膜がさらに設けられていること
を特徴とする多層プリント配線板。 - 前記絶縁膜が、前記キャビティの前記底面上において、間隙を有して隔てられた部位を有することを特徴とする請求項1記載の多層プリント配線板。
- 前記絶縁膜が、前記絶縁層と前記下側プリント配線板との間に延在させた部分よりも前記キャビティの前記底面上に設けた部分において、高い位置まで形成されていること特徴とする請求項1または2記載の多層プリント配線板。
- 電子部品実装用のキャビティとなる貫通穴をあけた上側プリント配線板と、前記キャビティの底部を構成する下側プリント配線板とが一体化されるように絶縁層を介して積層されている多層プリント配線板であって、
前記キャビティの前記底面の近傍において、前記絶縁層に没入されるように前記下側プリント配線板上に突設された導体バンプをさらに有すること
を特徴とする多層プリント配線板。 - 前記上側プリント配線板と前記下側プリント配線板とを電気的に導通させるように前記絶縁層を貫通して設けられた層間接続導体をさらに具備し、
前記層間接続導体が、前記導体バンプと同じ材質であること
を特徴とする請求項4記載の多層プリント配線板。 - 前記導体バンプおよび前記層間接続導体が、導電性組成物の固化物からなることを特徴とする請求項5記載の多層プリント配線板。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006087566A JP4935139B2 (ja) | 2006-03-28 | 2006-03-28 | 多層プリント配線板 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006087566A JP4935139B2 (ja) | 2006-03-28 | 2006-03-28 | 多層プリント配線板 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007266196A JP2007266196A (ja) | 2007-10-11 |
JP4935139B2 true JP4935139B2 (ja) | 2012-05-23 |
Family
ID=38638909
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006087566A Expired - Fee Related JP4935139B2 (ja) | 2006-03-28 | 2006-03-28 | 多層プリント配線板 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4935139B2 (ja) |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8350388B2 (en) | 2007-11-01 | 2013-01-08 | Dai Nippon Printing Co., Ltd. | Component built-in wiring board and manufacturing method of component built-in wiring board |
JP2009111307A (ja) * | 2007-11-01 | 2009-05-21 | Dainippon Printing Co Ltd | 部品内蔵配線板 |
JP5176500B2 (ja) * | 2007-11-22 | 2013-04-03 | 大日本印刷株式会社 | 部品内蔵配線板、部品内蔵配線板の製造方法 |
JP5186927B2 (ja) * | 2008-01-18 | 2013-04-24 | パナソニック株式会社 | 立体プリント配線板 |
JP5251212B2 (ja) * | 2008-03-31 | 2013-07-31 | パナソニック株式会社 | 立体プリント配線板 |
TWI392404B (zh) * | 2009-04-02 | 2013-04-01 | Unimicron Technology Corp | 線路板及其製作方法 |
EP2405727A1 (en) * | 2009-04-02 | 2012-01-11 | Panasonic Corporation | Manufacturing method for circuit board, and circuit board |
JP2010267845A (ja) * | 2009-05-15 | 2010-11-25 | Dainippon Printing Co Ltd | 部品内蔵配線板、部品内蔵配線板の製造方法 |
TWI399140B (zh) | 2009-06-12 | 2013-06-11 | Unimicron Technology Corp | 內埋式封裝結構的製作方法 |
CN102860144B (zh) * | 2010-02-12 | 2016-03-02 | Lg伊诺特有限公司 | 具有腔的pcb及其制造方法 |
US8519270B2 (en) | 2010-05-19 | 2013-08-27 | Unimicron Technology Corp. | Circuit board and manufacturing method thereof |
KR101775150B1 (ko) | 2010-07-30 | 2017-09-05 | 삼성전자주식회사 | 다층 라미네이트 패키지 및 그 제조방법 |
JP2012089568A (ja) * | 2010-10-15 | 2012-05-10 | Murata Mfg Co Ltd | 有機多層基板及びその製造方法 |
US8735739B2 (en) | 2011-01-13 | 2014-05-27 | Ibiden Co., Ltd. | Wiring board and method for manufacturing the same |
JP6118170B2 (ja) * | 2013-05-10 | 2017-04-19 | 日本特殊陶業株式会社 | 多層セラミック基板およびその製造方法 |
JP2015138957A (ja) * | 2014-01-24 | 2015-07-30 | クローバー電子工業株式会社 | 多層プリント配線基板の製造方法 |
KR102123813B1 (ko) * | 2017-08-23 | 2020-06-18 | 스템코 주식회사 | 연성 회로 기판 및 그 제조 방법 |
KR102501905B1 (ko) * | 2017-11-09 | 2023-02-21 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조방법 |
JP7066603B2 (ja) * | 2018-12-20 | 2022-05-13 | 京セラ株式会社 | 配線基板および実装構造体 |
CN113747661B (zh) * | 2020-05-29 | 2023-01-17 | 庆鼎精密电子(淮安)有限公司 | 具有内埋电子元件的线路板及其制作方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05259646A (ja) * | 1992-03-10 | 1993-10-08 | Toshiba Corp | プリント配線板の製造方法 |
JPH08130372A (ja) * | 1994-10-31 | 1996-05-21 | Matsushita Electric Works Ltd | 多層プリント配線板の製造方法 |
JPH0982837A (ja) * | 1995-09-20 | 1997-03-28 | Shinko Electric Ind Co Ltd | 半導体パッケージの製造方法 |
JP3985782B2 (ja) * | 2003-12-10 | 2007-10-03 | 松下電器産業株式会社 | 多層プリント配線板とその製造方法 |
JP4304117B2 (ja) * | 2004-04-21 | 2009-07-29 | 日本メクトロン株式会社 | 多層回路基板およびその製造方法 |
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2006
- 2006-03-28 JP JP2006087566A patent/JP4935139B2/ja not_active Expired - Fee Related
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Publication number | Publication date |
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JP2007266196A (ja) | 2007-10-11 |
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