JP4901241B2 - Semiconductor light emitting device and manufacturing method thereof - Google Patents

Description

The present invention relates to a semiconductor light emitting device and a manufacturing method thereof, and more particularly to a semiconductor light emitting device in which a pair of electrodes are formed on one surface of a support substrate and a manufacturing method thereof.

  FIG. 4 is a cross-sectional view of the semiconductor light emitting device disclosed in Patent Document 1. On the sapphire substrate 100, a GaN buffer layer 101, an n-type GaN layer 102, an n-type AlGaN layer 103, an InGaN layer 104, a p-type AlGaN layer 105, and a p-type GaN layer 106 are laminated in this order. The stack from the n-type AlGaN layer 103 to the p-type GaN layer 106 is mesa-shaped, and the n-type GaN layer is exposed around the mesa. An n-side electrode 107 is formed on the upper surface of the n-type GaN layer 102 around the mesa, and a p-side electrode 108 is formed on the upper surface of the p-type GaN layer 106.

  The semiconductor light emitting device is mounted on the submount substrate with the electrodes 107 and 108 facing the submount substrate. At this time, the electrodes 107 and 108 are connected to the bonding pads of the submount substrate. Light emitted from the InGaN layer 104 is emitted to the outside through the sapphire substrate 100.

JP 2003-31851 A

  In the semiconductor light emitting device shown in FIG. 4, the p-side electrode 108 is formed on the upper surface of the mesa, and the n-side electrode 107 is disposed around the mesa. For this reason, the heights of the upper surface of the p-side electrode 108 and the upper surface of the n-side electrode 107 are not uniform. In order to flip-chip bond the semiconductor light emitting device to the submount substrate, a structure that absorbs the difference in height between the two electrodes must be employed on the submount substrate side.

An object of the present invention is to provide a semiconductor light emitting device having a structure capable of easily aligning the height of a pair of electrodes and a method for manufacturing the same.

According to one aspect of the invention,
A support substrate;
A first semiconductor layer formed on the support substrate and made of a first conductivity type semiconductor;
A second semiconductor layer formed on the first semiconductor layer and made of a semiconductor of a second conductivity type opposite to the first conductivity type;
A groove that reaches the bottom surface of the second semiconductor layer and divides the second semiconductor layer into a first region and a second region separated from each other;
A first electrode formed on a first region of the second semiconductor layer;
A second electrode that continuously covers from the second region of the second semiconductor layer to the surface of the first semiconductor layer that appears on the bottom surface of the groove, and the first semiconductor layer And the second semiconductor layer is formed of a III-V group compound semiconductor containing nitrogen as a group V element, the surface of the first electrode in contact with the second semiconductor layer, and the second electrode, The surfaces in contact with the first semiconductor layer and the second semiconductor layer are formed of the same metal material, and the heights of the first electrode and the second electrode are aligned,
A region of the first electrode and the second electrode in contact with the first semiconductor layer and the second semiconductor layer, a region made of a metal in ohmic contact with the first semiconductor layer, and the second electrode There is provided a semiconductor light emitting device including a region made of another metal in ohmic contact with a semiconductor layer .

According to another aspect of the invention,
Forming a first semiconductor layer of a first conductivity type on a support substrate;
Forming a second semiconductor layer of a second conductivity type opposite to the first conductivity type on the first semiconductor layer;
A groove reaching at least the bottom surface of the second semiconductor layer is formed in the second semiconductor layer, and the second semiconductor layer is divided into a first region and a second region separated from each other. Process,
A first electrode is formed on a first region of the second semiconductor layer, and continuous from the upper surface of the second region to the surface of the first semiconductor layer exposed on the bottom surface of the groove. Forming a second electrode that covers the first electrode, and forming the first electrode and the second electrode in the step of forming the first electrode and the second electrode. A method of manufacturing a semiconductor light emitting device with a uniform height ,
Forming the first electrode and the second electrode;
Depositing a metal in ohmic contact with one of the first semiconductor layer and the second semiconductor layer to a thickness that does not cover the entire exposed surface;
Thereafter, a method of manufacturing a semiconductor light emitting device is provided , including a step of depositing another metal that is in ohmic contact with the other of the first semiconductor layer and the second semiconductor layer .

  Since the second semiconductor layer is disposed under both the first electrode and the second electrode, the heights of the upper surfaces of the two electrodes can be easily aligned.

FIG. 1 is a sectional view of a semiconductor light emitting device according to an embodiment. An n-type semiconductor layer 2 is formed on the surface of the support substrate 1 where the C-plane of sapphire is exposed. A p-type semiconductor layer 3 is formed on the n-type semiconductor layer 2. The n-type semiconductor layer 2 and the p-type semiconductor layer 3 are formed of a III-V group compound semiconductor containing nitrogen as a group V element. For example, it is made of In _y Al _1-xy Ga _x N (x + y ≦ 1, 0 ≦ x ≦ 1, 0 ≦ y ≦ 1). The n-type semiconductor layer 2 and the p-type semiconductor layer 3 are formed by metal organic chemical vapor deposition (MOCVD).

  A groove 8 reaching at least the bottom surface is formed in the p-type semiconductor layer 3. The trench 8 divides the p-type semiconductor layer 3 into a first region 3a and a second region 3b that are separated from each other. The first area 3a is larger than the second area 3b. A recess 9 is formed in a part of the n-type semiconductor layer 2 exposed on the bottom surface of the groove 8. The groove 8 and the recess 9 are formed by photolithography and reactive ion etching (RIE) using chlorine gas.

  A p-side electrode 4 is formed on the first region 3 a of the p-type semiconductor layer 3. The n-side electrode 5 covers from the upper surface of the second region 3b to the surface of the n-type semiconductor layer 2 exposed at the bottom surface of the groove 8 via its end surface. The n-side electrode 5 is in contact with the inner surface of the recess 9. The p-side electrode 4 is in ohmic contact with the first region 3 a of the p-type semiconductor layer 3, and the n-side electrode 5 is in ohmic contact with the n-type semiconductor layer 2 on the bottom surface of the groove 8 and the inner surface of the recess 9.

  A p-side bonding pad 6 is formed on the p-side electrode 4, and an n-side bonding pad 7 is formed on the n-side electrode 5. The bonding pads 6 and 7 are made of Au or the like. The p-side electrode 4, the n-side electrode 5, the p-side bonding pad 6 and the n-side bonding pad 7 are formed by vacuum deposition using a lift-off method.

  Next, with reference to FIG. 2A and FIG. 2B, the structure and formation method of the p-side electrode 4 and the n-side electrode 5 will be described.

FIG. 2A shows a first configuration example of the p-side electrode 4. The p-side electrode 4 has an eight-layer structure in which four Rh layers 4R and four Al layers 4A are alternately stacked in order from the first region 3a side. The bonding pad 5 has a three-layer structure in which a Ti layer 5T, a Pt layer 5P, and an Au layer 5A are stacked. The thickness of each of the four layers from the first Rh layer 4R to the fourth Al layer 4A is 0.3 nm. The thickness of each of the fifth Rh layer 4R and the sixth Al layer 4A is 0.5 nm. The thickness of the seventh Rh layer 4R is 2 nm, and the thickness of the eighth Al layer 4A is 98 nm. The eighth Al layer 4A functions as a reflective electrode that reflects light generated at the interface between the first semiconductor layer 2 and the first region 3a shown in FIG.

  Each of the Ti layer 5T and the Pt layer 5P has a thickness of 50 nm, and the Au layer 5A has a thickness of 200 nm. The n-side electrode 5 has the same stacked structure as the p-side electrode 4. These layers are formed by vacuum deposition.

  Generally, Rh is used as a p-side electrode material in ohmic contact with a p-type III-V compound semiconductor containing N as a V-group element, and Al is used as an n-side electrode material in ohmic contact with an n-type III-V compound semiconductor. Used.

  In the first configuration example shown in FIG. 2A, the first Rh layer 4 </ b> R is in contact with the first region 3 a of the p-type semiconductor layer 3. For this reason, the p-side electrode 4 can be brought into ohmic contact with the p-type first region 3a.

  In the first configuration example, the thickness of each of the six layers from the first Rh layer 4R to the sixth Al layer 4A is about 0.3 nm to 0.5 nm. thin. Therefore, in actuality, the first layer Rh4R does not cover the upper surfaces of the first region 3a and the second region 3b shown in FIG. When the first Rh layer 4R is deposited, it is considered that there are mottled regions where these surfaces are exposed. When the second Al layer 4A is deposited thereon, the second Al layer 4A comes into contact with the mottled surface in a part of the region. Since the second Al layer 4A is in contact with the n-type semiconductor layer 2 exposed on the inner surfaces of the groove 8 and the recess 9, the n-side electrode 5 can be in ohmic contact with the n-type semiconductor layer 2.

  As described above, the surfaces of the p-side electrode 4 and the n-side electrode 5 that are in contact with the p-type semiconductor layer 3 and the n-type semiconductor layer 2 are made of the metal Rh that is in ohmic contact with the p-type semiconductor layer 3 and the n-type electrode. And a region made of other metal Al in ohmic contact with the semiconductor layer 2. Thereby, even if the same electrode structure is employed, it is possible to make ohmic contact with both the p-type and n-type semiconductor layers.

Actually, the contact resistance between the p-type semiconductor layer 3 and the p-side electrode 4 is about 9.4 × 10 ⁻³ Ωcm ² , and the contact resistance between the n-type semiconductor layer 2 and the n-side electrode 5 is about 8.6. × 10 ⁻⁵ Ωcm ² . As a result, a blue light emitting diode with an operating voltage of 3.4 V was realized. This operating voltage is comparable to the conventional element shown in FIG. Pt, Ir, Pd, or the like may be used instead of Rh as a material that can be brought into ohmic contact with the p-type first region 3a.

  FIG. 2B shows a second configuration example of the p-side electrode 4. The p-side electrode 4 has a two-layer structure in which an Rh layer 4R having a thickness of 1 nm and an Al layer 4A having a thickness of 500 nm are stacked in order from the first region 3a side. The bonding pad 5 has the same laminated structure as that of the first configuration example. These layers are formed by vacuum deposition. The n-side electrode 5 has a similar laminated structure.

The Rh layer 4R of the p-side electrode 4 is in contact with the p-type first region 3a. For this reason, after forming the p-side electrode 4, good ohmic contact between the p-side electrode 4 and the first region 3a was obtained without annealing. The contact resistance was 5 × 10 ⁻³ Ωcm ² . Since Rh is exposed in almost the entire region of the p-side electrode 4 in contact with the first region 3a, lower contact resistance is obtained compared to the first configuration example.

However, in this state, the n-side electrode 5 and the n-type semiconductor layer 2 are in Schottky contact, and good ohmic contact cannot be obtained. After the n-side electrode 5 is formed, ohmic contact can be obtained by annealing under predetermined conditions. This is presumably because Al atoms in the Al layer 42 diffuse into the Rh layer 4R and reach the n-type semiconductor layer 2. For example, when the annealing time was 20 seconds, the Schottky contact was maintained when the annealing-free temperature was 100 ° C., 200 ° C., and 300 ° C. When the annealing temperature was 400 ° C. or higher, ohmic contact was obtained. The contact resistance when the annealing temperature is 400 ° C., 500 ° C., and 600 ° C. is 4.0 × 10 ⁻⁵ Ωcm ² , 0.63 × 10 ⁻⁵ Ωcm ² , and 1.8 × 10 ⁻⁵ Ωcm ^{2, respectively.} Met.

When annealing is performed at a temperature of 400 ° C. or higher, the n-side electrode 5 can be brought into ohmic contact with the n-type semiconductor layer 2. Conversely, by performing annealing, the p-side electrode 4 and the p-type first region are formed. There is a tendency that ohmic contact with 3a becomes poor and Schottky contact occurs. Therefore, after forming the p-side electrode 4 and the n-side electrode 5, it is necessary to locally anneal only the region where the n-side electrode 5 and the n-type semiconductor layer 2 are in contact. As the local annealing, laser annealing using a laser having a wavelength region absorbed by an electrode material or a semiconductor material can be employed. For example, an Nd: YAG laser, a CO ₂ laser, an Ar ⁺ laser, an excimer laser, or the like can be used.

  In the above embodiment, the upper surface of the first region 3a of the p-type semiconductor layer 3 where the p-side electrode 4 is disposed and the upper surface of the second region 3b where the n-side electrode 5 is disposed are aligned. Yes. For this reason, the height of the upper surface of the p-side electrode 4 and the upper surface of the n-side electrode 5 and the height of the upper surface of the p-side bonding pad 6 and the upper surface of the n-side bonding pad 7 can be easily aligned.

  Further, since the n-side electrode 5 is in contact with the inner surface of the recess 9 formed on the surface of the n-type semiconductor layer 2, the contact area between the n-side electrode 5 and the n-type semiconductor layer 2 can be increased. For this reason, it becomes possible to reduce both contact resistance.

  The p-side electrode 4 and the p-side bonding pad 6, and the n-side electrode 5 and the n-side bonding pad 7 are patterned only by lift-off based on one photolithography process. For this reason, a photolithography process can be reduced.

  FIG. 3 shows a cross-sectional view of the semiconductor light emitting device shown in FIG. 1 mounted on a submount substrate. The structure of the submount substrate shown in FIG. 3 will be described. A silicon oxide film 21 is formed on the surface of the silicon substrate 20. A p-side electrode layer 22 is formed on a partial region of the silicon oxide film 21, and an n-side electrode layer 23 is formed on another region. The p-side electrode layer 22 and the n-side electrode layer 23 are made of, for example, aluminum (Al).

  A p-side bonding electrode 24 is formed on the p-side electrode layer 22, and an n-side bonding electrode 25 is formed on the n-side electrode layer 23. The bonding electrodes 24 and 25 have a laminated structure in which Au layers and Sn layers are alternately laminated. Note that the bonding electrodes 24 and 25 may be formed of an AuSn alloy.

  The p-side bonding pad 6 of the semiconductor light emitting device is in contact with the p-side bonding electrode 24, and the n-side bonding pad 7 is in contact with the n-side bonding electrode 25. Eutectic is formed at the contact portion, and both are electrically and mechanically bonded. Since the heights of the upper surface of the p-side bonding pad 6 and the upper surface of the n-side bonding pad 7 are equal, it is not necessary to perform fine height adjustment of the bonding electrodes 24 and 25 on the submount substrate side.

  When Rh and Al are used as the p-side electrode 4, a higher reflectance can be obtained as compared with the case where Ni that is put into practical use as the p-side electrode is used. When the semiconductor light emitting device is mounted on the submount substrate by flip chip bonding and light is extracted to the outside through the transparent support substrate 1, the extraction efficiency can be increased.

  When a current is passed through the semiconductor light emitting device, light emission occurs in the pn junction region between the first region 3 a of the p-type semiconductor layer 3 and the n-type semiconductor layer 2. The support substrate 1 made of sapphire is transparent to light having a wavelength corresponding to the band gap of the semiconductor layers 2 and 3. For this reason, the generated light is emitted to the outside through the support substrate 1.

  In the above embodiment, the p-side electrode 4 and the n-side electrode 5 shown in FIG. 1 are formed simultaneously, but may be formed separately. In this case, after forming one electrode by vacuum deposition using the lift-off method, the other electrode is formed by vacuum deposition using the lift-off method. When formed separately, the number of photolithography and film formation steps increases, but an optimal material that can easily make ohmic contact with each of the p-type semiconductor and the n-type semiconductor can be selected.

  A reflective layer may be inserted between the p-side electrode 4 and the p-side bonding pad 6 and between the n-side electrode 5 and the n-side bonding pad 7 shown in FIG. The reflective layer reflects the light emitted at the pn junction portion toward the support substrate 1 side, and improves the emission efficiency. As the material of the reflective layer, for example, Al, Ag, Rh, Ir, Pt, or the like can be used.

  Although the case where the semiconductor light emitting device is mounted on the submount substrate has been described as an example in the above embodiment, the configuration of the above embodiment can also be applied to the case where another semiconductor device is mounted on the submount substrate.

  Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

It is sectional drawing of the semiconductor light-emitting device by an Example. (2A) and (2B) are sectional views showing a first configuration example and a second configuration example of the p-side electrode, respectively. It is sectional drawing of the state which mounted the semiconductor light-emitting device by the Example in the submount board | substrate. It is sectional drawing of the conventional semiconductor light-emitting device.

Explanation of symbols

1 support substrate 2 n-type semiconductor layer 3 p-type semiconductor layer 4 p-side electrode 5 n-side electrode 6 p-side bonding pad 7 n-side bonding pad 8 groove 9 recess 20 silicon substrate 21 silicon oxide film 22 p-side electrode layer 23 n-side Electrode layer 24 p-side bonding electrode 25 n-side bonding electrode

Claims (6)

A support substrate;
A first semiconductor layer formed on the support substrate and made of a first conductivity type semiconductor;
A second semiconductor layer formed on the first semiconductor layer and made of a semiconductor of a second conductivity type opposite to the first conductivity type;
A groove that reaches the bottom surface of the second semiconductor layer and divides the second semiconductor layer into a first region and a second region separated from each other;
A first electrode formed on a first region of the second semiconductor layer;
A second electrode that continuously covers from the second region of the second semiconductor layer to the surface of the first semiconductor layer that appears on the bottom surface of the groove, and the first semiconductor layer And the second semiconductor layer is formed of a III-V group compound semiconductor containing nitrogen as a group V element, the surface of the first electrode in contact with the second semiconductor layer, and the second electrode, The surfaces in contact with the first semiconductor layer and the second semiconductor layer are formed of the same metal material, and the heights of the first electrode and the second electrode are aligned,
A region of the first electrode and the second electrode in contact with the first semiconductor layer and the second semiconductor layer, a region made of a metal in ohmic contact with the first semiconductor layer, and the second electrode A semiconductor light emitting element including a region made of another metal that is in ohmic contact with the semiconductor layer . Furthermore, it has a recess formed in the bottom surface of the groove, the second electrode covers the inner surface of the recess, and the support substrate has a band gap between the first semiconductor layer and the second semiconductor layer. The semiconductor light emitting device according to claim 1, which is transparent to light of a corresponding wavelength. A metal material that forms a surface of the first electrode in contact with the second semiconductor layer and a surface of the second electrode in contact with the first semiconductor layer and the second semiconductor layer is Rh and the device according to claim 1 or 2 including al. Forming a first semiconductor layer of a first conductivity type on a support substrate;
Forming a second semiconductor layer of a second conductivity type opposite to the first conductivity type on the first semiconductor layer;
A groove reaching at least the bottom surface of the second semiconductor layer is formed in the second semiconductor layer, and the second semiconductor layer is divided into a first region and a second region separated from each other. Process,
A first electrode is formed on a first region of the second semiconductor layer, and continuous from the upper surface of the second region to the surface of the first semiconductor layer exposed on the bottom surface of the groove. Forming a second electrode that covers the first electrode, and forming the first electrode and the second electrode in the step of forming the first electrode and the second electrode. A method of manufacturing a semiconductor light emitting device with a uniform height ,
Forming the first electrode and the second electrode;
Depositing a metal in ohmic contact with one of the first semiconductor layer and the second semiconductor layer to a thickness that does not cover the entire exposed surface;
And subsequently depositing another metal in ohmic contact with the other of the first semiconductor layer and the second semiconductor layer . Forming a first semiconductor layer of a first conductivity type on a support substrate;
Forming a second semiconductor layer of a second conductivity type opposite to the first conductivity type on the first semiconductor layer;
A groove reaching at least the bottom surface of the second semiconductor layer is formed in the second semiconductor layer, and the second semiconductor layer is divided into a first region and a second region separated from each other. Process,
A first electrode is formed on a first region of the second semiconductor layer, and continuous from the upper surface of the second region to the surface of the first semiconductor layer exposed on the bottom surface of the groove. Forming a second electrode to be covered
In the step of forming the first electrode and the second electrode, a semiconductor light emitting device in which both are formed simultaneously and the heights of the first electrode and the second electrode are made uniform is manufactured. A method,
The first semiconductor layer and the second semiconductor layer are formed of a III-V group compound semiconductor containing nitrogen as a group V element;
Forming the first electrode and the second electrode;
Depositing an Rh layer;
Depositing an Al layer on the Rh layer;
When the first semiconductor layer is n-type, the contact portion between the second electrode and the first semiconductor layer is locally annealed, and when the second semiconductor layer is n-type wherein by locally annealing the contact portion between the first electrode and the second semiconductor layer, the manufacturing method of the process and the including semiconductors light emitting elements to obtain an ohmic contact. The method further includes the step of forming a recess in the bottom surface of the groove, wherein in the step of forming the second electrode, the second electrode is formed so as to cover the inner surface of the recess. 6. A method for producing a semiconductor light emitting device according to 4 or 5 .

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