JP4880340B2 - Motor drive circuit and method, and disk device using the same - Google Patents

Description

  The present invention relates to a technique for controlling rotation of a rotor, and more particularly to a motor drive circuit that controls rotation of a motor including a stator having a plurality of coils and a magnetic rotor.

  In an electronic device using a disk-type medium such as a portable CD (Compact Disc) device or a DVD (Digital Versatile Disc), a brushless DC motor is used to rotate the disk. Brushless direct current (DC) motors generally include a rotor with a permanent magnet and a stator with a plurality of star-connected coils of a phase, and the coil is excited by controlling the current supplied to the coil. The rotor is driven by rotating relative to the stator. In order to detect the rotational position of the rotor, the brushless DC motor generally includes a sensor such as a Hall element or an optical encoder, and switches the current supplied to the coil of each phase according to the position detected by the sensor. And apply an appropriate torque to the rotor.

  In order to further reduce the size of the motor, a sensorless motor that detects the rotational position of the rotor without using a sensor such as a Hall element has also been proposed (for example, see Patent Documents 1 and 2). For example, a sensorless motor monitors the counter electromotive voltage (inductive voltage) generated in the coil by measuring the potential of the midpoint wiring of the motor (hereinafter referred to as the midpoint voltage). By detecting, position information is obtained.

  In driving such a sensorless motor, in order to monitor the back electromotive voltage of a certain phase coil, it is necessary to set the non-driving state in accordance with the timing at which the zero cross point occurs. In this non-driving state, the driver connected to the phase coil stops switching driving and is set to a high impedance state. In particular, in driving by a 180-degree energization method or the like, since current always flows through the phase coil, it is necessary to predict the timing at which the zero cross point occurs and set the high impedance state according to the prediction result. For example, Patent Document 4 discloses a method for realizing the timing for setting a high impedance state by a PLL (Phase Locked Loop) method.

JP-A-3-207250 Japanese Patent Laid-Open No. 10-243865 JP 11-341870 A Japanese Patent Laid-Open No. 2001-190085

  Here, if the non-driving period for setting the high impedance state is set to be long, the zero cross can be reliably detected, but the current flowing in the motor coil is discontinuous, leading to an increase in noise generated from the motor. Therefore, it is desirable that the non-driving period is as short as possible. However, if the non-driving period is too short, a situation may occur in which the timing of the zero cross point and the non-driving period do not match. When such a situation occurs, problems such as uneven rotation of the motor and, in the worst case, stop of the motor are caused. Therefore, the setting of the non-driving period needs to be adaptively performed in accordance with the number of rotations of the motor and the fluctuation of the load.

  The present invention has been made in view of such circumstances, and an object thereof is to provide a motor drive circuit capable of adaptively setting the length and timing of a non-drive period according to the rotation state of the motor.

  One embodiment of the present invention relates to a motor drive circuit that drives a multiphase motor by supplying a drive current. This drive circuit is provided for each coil of the multiphase motor, and is generated in at least one coil of the multiphase motor and a plurality of switching circuits for applying a high level or low level voltage to one end of the connected coil. The counter electromotive voltage is compared with the midpoint voltage of the coil to detect the zero cross point, and a counter electromotive detection circuit that outputs a counter electromotive detection signal and a counter electromotive detection signal output from the counter electromotive detection circuit Prior to the detection of the zero cross point by the back electromotive force detection circuit, the switching control circuit for controlling the switching state of the switching circuit and adjusting the current flowing through the coil of the multiphase motor, the back electromotive force detection signal output from the back electromotive force detection circuit A window generation circuit that outputs a window signal having a predetermined level for a period obtained by multiplying the period by a predetermined coefficient. The switching control circuit stops switching of the switching circuit and sets it in a high impedance state while the window signal from the window generation circuit is at a predetermined level.

  The back electromotive detection signal is generated at a frequency proportional to the number of rotations of the motor. Therefore, in order to detect the zero-cross point, the non-drive period in which the switching circuit is in a high impedance state is adaptively set in proportion to the period of the back electromotive detection signal, that is, in inverse proportion to the rotation speed of the motor. can do.

When the predetermined coefficient is α (α is a real number satisfying 0 <α <1), the window generation circuit outputs a back electromotive detection signal from the back electromotive detection circuit and then cycles the back electromotive detection signal. After the elapse of the period obtained by multiplying the coefficient by (1-α), the window signal is set to a predetermined level, and then, when the next back electromotive detection signal is output from the back electromotive detection circuit, It may be a level different from the level.
In this case, the switching circuit can be set to a high impedance state for a period proportional to the cycle of the back electromotive detection signal, and the timing for setting the high impedance state can be reliably set prior to detection of the zero cross point. it can.

  A window generating circuit that receives the back electromotive detection signal output from the back electromotive detection circuit and generates a pulse signal having a frequency n times (n is an integer of 2 or more) the back electromotive detection signal; After receiving a back electromotive detection signal from the back electromotive detection circuit and a pulse signal from the pulse signal generating circuit and detecting a back electromotive detection signal, m pulse signals (m is an integer satisfying m <n) And a timing setting unit that sets the window signal to a predetermined level when detected, and then sets the window signal to a level different from the predetermined level when the next back electromotive detection signal is detected.

  The timing setting unit may include an integer m adjusting unit. In this case, since the integer m can be changed according to the type of motor connected to the motor driving circuit, stable motor driving is realized.

  The pulse signal generation circuit includes a frequency counter that measures the frequency of the back electromotive detection signal, and a clock signal generation unit that generates a pulse signal having a frequency n times (n is an integer of 2 or more) the frequency measured by the frequency counter. , May be included. The frequency counter counts the clock signal of a predetermined frequency and measures the period of the back electromotive detection signal during the period from the input of a back electromotive detection signal to the input of the next back electromotive detection signal. Also good.

  The clock signal generation unit may calculate the frequency values of the past K times (K is an integer equal to or greater than 1) measured by the frequency counter, and set the frequency of the pulse signal to be generated according to the calculation result. .

  The clock signal generator may include an integer K adjusting means. In this case, since the gain of the feedback loop increases as K is reduced, the follow-up performance with respect to fluctuations in the rotational speed of the motor can be set higher. As K is increased, the gain of the feedback loop decreases. Stability can be increased. Therefore, optimum motor driving can be realized by setting the value of K according to the type of motor, the number of rotations, and the driving method.

  The pulse signal generation circuit includes a storage unit that holds frequency values for the past L times (L is an integer that satisfies L ≧ K), and a calculation unit that executes a predetermined calculation based on the frequency values held in the storage unit And may be further included. The clock signal generation unit may generate a pulse signal having a frequency corresponding to the calculation result of the calculation unit. The storage unit may be an L-stage shift register.

  The calculation unit may calculate the latest K frequency values among the L frequency values held in the storage unit to determine the frequency of the pulse signal.

  The timing setting unit receives the back electromotive detection signal output from the back electromotive detection circuit and the pulse signal output from the pulse signal generation circuit, and after detecting a back electromotive detection signal, counts m pulse signals. Then, a counter that outputs an open edge signal at a predetermined level, and a predetermined level when the open edge signal at a predetermined level is output from the counter, and then a level different from the predetermined level is detected when the next back electromotive detection signal is detected. A window signal output unit that outputs a window signal.

  The motor drive circuit may be integrated on a single semiconductor substrate. “Integrated integration” includes the case where all of the circuit components are formed on a semiconductor substrate and the case where the main components of the circuit are integrated. A resistor, a capacitor, or the like may be provided outside the semiconductor substrate. By integrating the motor drive circuit as one LSI, the circuit area can be reduced.

  Another embodiment of the present invention is a disk device. This apparatus includes a spindle motor that rotates a disk and the above-described motor drive circuit that drives the spindle motor.

  According to this aspect, the period in which the switching circuit connected to the motor coil becomes high impedance can be set as short as possible, so the period in which the current flowing in the motor coil is discontinuous can be shortened. The generated noise can be reduced.

  Yet another aspect of the present invention is a method. This method is a motor drive method for supplying a drive current to a multiphase motor, and compares the counter electromotive voltage generated in at least one coil of the multiphase motor with the midpoint voltage of the coil to detect the zero cross point. A back electromotive force detection step for outputting a back electromotive force detection signal, and applying a high-level or low-level voltage to one end of each coil of the multiphase motor in accordance with the back electromotive force detection signal, flows through the coil of the multiphase motor. Adjusting the current; and prior to detecting the zero cross point in the back electromotive detection step, setting the circuit connected to the coil in a high impedance state for a period obtained by multiplying the period of the back electromotive detection signal by a predetermined coefficient; Is provided.

  According to the present invention, the length and timing of the non-driving period can be adaptively set according to the rotation state of the motor.

  FIG. 1 is a block diagram showing a configuration of a motor drive circuit 100 according to the embodiment. The motor drive circuit 100 controls the rotation by supplying a drive current to a sensorless brushless DC motor (hereinafter simply referred to as “motor 110”). In the present embodiment, the motor 110 to be driven is a three-phase DC motor including U-phase, V-phase, and W-phase coils Lu, Lv, and Lw.

  The motor drive circuit 100 includes switching circuits 10 u, 10 v, 10 w that are collectively referred to as a switching circuit 10, a back electromotive force detection circuit 20, a switching control circuit 30, and a window generation circuit 40. The motor drive circuit 100 is integrally integrated as a functional IC on one semiconductor substrate. For example, the motor drive circuit 100 performs PWM (Pulse Width Modulation) drive so that the current flowing in the coils of each phase becomes an arch shape or a sine wave shape by a 180-degree energization method.

  The switching circuits 10u, 10v, and 10w are provided for each of the coils Lu, Lv, and Lw of the motor 110. The switching circuits 10u, 10v, and 10w include, for example, a high-side switch and a low-side switch connected in series between a power supply voltage and a ground potential, and a connection point between the two switches is connected to the coil. The drive signal DRV_H (U, V, W) and the drive signal DRV_L (U, V, W) are input to the control terminals of the high side switch and the low side switch, respectively. The switching circuits 10u, 10v, and 10w apply a high level voltage to one end of a connected coil when the high side switch is on and a low level voltage when the low side switch is on. Further, the high-side switch and the low-side switch are simultaneously turned off to set the high impedance state.

  The back electromotive force detection circuit 20 compares the back electromotive voltage generated in at least one coil of the motor 110 with the midpoint voltage of the coil to detect a zero cross point, and outputs a back electromotive force detection signal BEMF_EDGE. In the present embodiment, the back electromotive force detection circuit 20 monitors the back electromotive voltage Vu and the midpoint voltage Vcom generated in the U-phase coil Lu, and generates a back electromotive force detection signal BEMF_EDGE that is at a high level when Vu> Vcom. To do. The generated back electromotive force detection signal BEMF_EDGE is output to the switching control circuit 30 and the window generation circuit 40.

  Based on the back electromotive detection signal BEMF_EDGE output from the back electromotive detection circuit 20, the switching control circuit 30 controls the ON / OFF state sequence of the plurality of switching circuits 10u, 10v, 10w, that is, the switching state, and controls the coil of the motor 110. Adjust the flowing current. The switching control circuit 30 includes a drive timing generation circuit 32 and a drive signal synthesis circuit 34.

  The drive timing generation circuit 32 receives the back electromotive force detection signal BEMF_EDGE. The drive timing generation circuit 32 generates a drive signal DRV having a cycle that is 1/6 of the cycle Tp1 of the back electromotive detection signal BEMF_EDGE. The drive signal synthesis circuit 34 controls the drive states of the switching circuits 10u, 10v, and 10w according to the drive signal DRV. For example, the drive signal synthesis circuit 34 synthesizes a pulse signal obtained by pulse width modulation of a sine wave with the drive signal DRV, and outputs the synthesized signal to the switching circuits 10u, 10v, 10w.

  Prior to the detection of the zero cross point by the back electromotive detection circuit 20, the window generation circuit 40 has a predetermined coefficient α (α is 0 <α <1) in the cycle Tp1 of the back electromotive detection signal BEMF_EDGE output from the back electromotive detection circuit 20. The window signal WINDOW having a predetermined level is output during a period (Tp3 = Tp1 × α) multiplied by a real number satisfying In the present embodiment, the predetermined level is a high level.

  The window generation circuit 40 receives the back electromotive force detection signal BEMF_EDGE from the back electromotive force detection circuit 20. The window generation circuit 40 outputs a window signal after a period of time obtained by multiplying the cycle Tp1 of the back electromotive detection signal BEMF_EDGE by a coefficient (1-α) after a back electromotive detection signal BEMF_EDGE is output from the back electromotive detection circuit 20. WINDOW is set to high level. Thereafter, the window generation circuit 40 sets the window signal WINDOW to a level different from a predetermined level, that is, a low level when the next back electromotive detection signal BEMF_EDGE is output from the back electromotive detection circuit 20.

  The window signal WINDOW is output to the drive signal synthesis circuit 34 of the switching control circuit 30. During the period when the window signal WINDOW is at a high level, the drive signal synthesis circuit 34 stops switching of the switching circuit 10u connected to the terminal where the back electromotive voltage Vu to be monitored for detection of the zero cross point is generated, and the high impedance Set to state. That is, during the period in which the window signal WINDOW is at a high level, a phase that is not intentionally driven is set in order to detect the zero cross point. In the present embodiment, in the non-driving period Tp3, the U phase is set to a phase that is not driven.

  FIG. 2 is a block diagram illustrating a configuration example of a part of the motor drive circuit 100. The back electromotive force detection circuit 20 is a comparator, and compares the back electromotive voltage Vu appearing in the coil Lu with the midpoint voltage Vcom. The back electromotive force detection is high level when Vu> Vcom and low level when Vu <Vcom. The signal BEMF_EDGE is output.

  The window generation circuit 40 includes a pulse signal generation circuit 42 and a timing setting unit 44. The pulse signal generation circuit 42 receives the back electromotive detection signal BEMF_EDGE output from the back electromotive detection circuit 20, and generates a pulse signal PULSE having a frequency n times (n is an integer of 2 or more) the back electromotive detection signal BEMF_EDGE. .

  The timing setting unit 44 receives the back electromotive detection signal BEMF_EDGE from the back electromotive detection circuit 20 and the pulse signal PULSE from the pulse signal generation circuit 42. After the timing setting unit 44 detects a certain back electromotive detection signal BEMF_EDGE and counts m pulse signals PULSE (m is an integer satisfying m <n), the timing setting unit 44 sets the window signal WINDOW to a high level. Thereafter, when the next back electromotive detection signal BEMF_EDGE is detected, the window signal WINDOW is set to the low level.

  The integer m is preferably adjustable. For example, the motor drive circuit 100 may include a register for holding the integer m, and is configured so that the integer m can be set from the outside.

  FIG. 3 is a block diagram illustrating a configuration example of the pulse signal generation circuit 42 and the timing setting unit 44. The pulse signal generation circuit 42 includes a frequency counter 50 and a clock signal generation unit 56.

  The frequency counter 50 measures the frequency of the back electromotive detection signal BEMF_EDGE, that is, the period Tp1. For example, a clock signal (not shown) having a predetermined frequency is input to the frequency counter 50. The frequency counter 50 counts a clock signal during a period from when a back electromotive detection signal BEMF_EDGE is input to when the next back electromotive detection signal BEMF_EDGE is input, and measures the period Tp1 of the back electromotive detection signal BEMF_EDGE. . The frequency counter 50 sequentially outputs the measured count value COUNT as a frequency value.

  The clock signal generator 56 generates a pulse signal PULSE having a frequency n times (n is an integer of 2 or more) the frequency measured by the frequency counter 50. That is, the cycle Tp2 of the pulse signal PULSE is set to 1 / n of the cycle Tp1 of the back electromotive detection signal BEMF_EDGE.

  The clock signal generator 56 calculates the frequency value COUNT for the past K times (K is an integer equal to or greater than 1) measured by the frequency counter 50, and sets the frequency of the pulse signal to be generated according to the result of the calculation. . The integer K corresponding to the number of frequency values to be calculated is preferably adjustable.

  In order to realize this function, the pulse signal generation circuit 42 includes a storage unit 52 and a calculation unit 54 in the preceding stage of the clock signal generation unit 56. The storage unit 52 holds frequency values COUNT for the past L times (L is an integer satisfying L ≧ K). Storage unit 52 may be, for example, an L-stage shift register. The calculation unit 54 performs a predetermined calculation based on the frequency value held in the storage unit 52. The arithmetic processing may be a simple average or a weighted average.

  The clock signal generator 56 generates a pulse signal PULSE having a frequency corresponding to the calculation result of the calculator 54. For example, the computing unit 54 computes the latest K frequency values among the L frequency values held in the storage unit 52 to determine the frequency of the pulse signal PULSE. In the arithmetic processing, the K count values may be simply averaged or weighted averaged. As described above, the integer K is preferably variable and can be set from the outside. When K = 1, the period Tp2 of the pulse signal PULSE is set according to the period Tp1 of the immediately preceding back electromotive detection signal BEMF_EDGE.

  The timing setting unit 44 receives the back electromotive detection signal BEMF_EDGE output from the back electromotive detection circuit 20 and the pulse signal PULSE output from the pulse signal generation circuit 42. The timing setting unit 44 includes a counter 60 and a window signal output unit 62. When the counter 60 detects a certain back electromotive detection signal BEMF_EDGE and then counts m pulse signals PULSE, the counter 60 outputs an open edge signal OPEN_EDGE that becomes a high level. When the high-level open edge signal OPEN_EDGE is output from the counter 60, the window signal output unit 62 outputs a window signal WINDOW that becomes a low level when detecting the next back electromotive detection signal BEMF_EDGE.

  The operation of the motor drive circuit 100 configured as described above will be described. 4A to 4L are time charts showing the operation of the motor drive circuit 100 according to the embodiment. The vertical and horizontal axes in FIGS. 1A to 1L are enlarged or reduced as appropriate for easy understanding, and the waveforms shown are also simplified for easy understanding. Yes. FIGS. 4A to 4C are waveforms showing driving states of the U-phase, V-phase, and W-phase coils Lu, Lv, and Lw by the switching circuits 10u, 10v, and 10w. FIG. 6D shows the back electromotive detection signal BEMF_EDGE detected by the back electromotive detection circuit 20, FIG. 5E shows the drive signal DRV generated by the drive timing generation circuit 32, and FIG. The window signal WINDOW generated by the window generation circuit 40 is shown. Further, (g) to (l) in the figure show driving signals DRV_H and DRV_L for the high-side switch and the low-side switch of the switching circuits 10u to 10w.

  As shown in FIGS. 4A to 4C, in the present embodiment, the drive current is driven so as to have an arch waveform. However, the present invention is not limited to this, and may be a sine wave. In the present embodiment, the back electromotive force detection signal BEMF_EDGE is generated for each zero cross point where the back electromotive voltage Vu intersects the midpoint voltage Vcom as shown in FIG. The drive timing generation circuit 32 generates the drive signal DRV shown in FIG. 5E, which is 1/6 times the cycle Tp1 of the back electromotive detection signal BEMF_EDGE. As shown in the figure, the drive signal DRV may be given a delay Td with respect to the back electromotive force detection signal BEMF_EDGE. By adjusting the delay Td, the motor drive is optimized.

  Based on the drive signal DRV generated by the drive timing generation circuit 32, the drive signal synthesis circuit 34 controls drive signals DRV_H (U, V, W), DRV_L (U, V) for controlling on / off of the switching circuits 10u to 10w. , W). This driving sequence is appropriately set according to the energization angle and the like.

  In the drive signal DRV_HU shown in FIG. 4G, the high level corresponds to the on state of the high side switch of the switching circuit 10u, and the low level corresponds to the off state. The same applies to the drive signals DRV_H (V, W) and DRV_L (U, V, W) shown in FIGS. Further, the ON state of at least one of the high side switch and the low side switch is pulse width modulated so as to obtain the drive waveforms shown in FIGS. The side switch or low side switch alternately turns on and off at a high frequency.

  Each time the back electromotive detection signal BEMF_EDGE is output, the drive signal synthesis circuit 34 changes the on / off states of the drive signals DRV_H and DRV_L of the switching circuits 10u to 10w according to a predetermined drive sequence.

  The window signal WINDOW shown in FIG. 6F is set to the high level by the window generation circuit 40 prior to the time when the zero cross point occurs. The drive signal synthesizing circuit 34 sets the drive signals DRV_HU and DRV_LU output to the switching circuit 10u to the low level while the window generation circuit 40 is at the high level, turns off the high side switch and the low side switch, and sets the high impedance state. In the same figure (g) and (j), the period during which the high impedance state is set in order to detect the zero cross point is indicated by hatching. When the window signal WINDOW becomes high level and one end of the coil Lu is set to a high impedance state, the zero cross point can be detected, and the back electromotive detection signal BEMF_EDGE is generated. When the back electromotive detection signal BEMF_EDGE becomes high level, the window generation circuit 40 sets the window signal WINDOW to low level.

  5A to 5D are time charts showing how the window signal WINDOW is generated. 6A shows the back electromotive force detection signal BEMF_EDGE, FIG. 4B shows the pulse signal PULSE generated by the pulse signal generation circuit 42, and FIG. 4C shows the open edge generated by the counter 60. The signal OPEN_EDGE and FIG. 6D show the window signal WINDOW.

  When the back electromotive detection signal BEMF_EDGE becomes a high level, the frequency counter 50 in FIG. 3 starts counting, and then counts the count value COUNT counted until the time when the back electromotive detection signal BEMF_EDGE becomes a high level to the storage unit 52. Is output. The storage unit 52 holds at least the past count value COUNT. Assuming that the clock cycle used for counting by the frequency counter 50 is Tck, the cycle Tp1 of the back electromotive detection signal BEMF_EDGE is Tck × COUNT. The calculation unit 54 determines the period Tp2 of the pulse signal PULSE using the count values for the past K times so that Tp2 = Tp1 / n. As a result, as shown in FIG. 5B, the cycle Tp2 of the pulse signal PULSE output from the pulse signal generation circuit 42 is 1 / n of the cycle Tp1 of the back electromotive detection signal BEMF_EDGE.

  The counter 60 of FIG. 3 starts counting the pulse signal PULSE from the pulse signal generation circuit 42 when a certain back electromotive detection signal BEMF_EDGE becomes high level at time t0. When the counter 60 counts m pulse signals PULSE at time t1, it outputs a high-level open edge signal OPEN_EDGE.

  The window signal output unit 62 sets the window signal WINDOW to the high level during a period from the time when the open edge signal OPEN_EDGE becomes the high level at time t1 to the time t2 when the back electromotive detection signal BEMF_EDGE next becomes the high level.

  Thus, in the motor drive circuit 100 according to the present embodiment, a predetermined coefficient (1-m / n) is added to the cycle Tp1 of the back electromotive detection signal BEMF_EDGE output from the back electromotive detection circuit 20 prior to detection of the zero cross point. ), A window signal WINDOW that becomes a high level is generated, and a period during which the window signal WINDOW becomes a high level is set as a non-driving period Tp3 for zero cross point detection. As a result, the non-driving period Tp3 can be set adaptively according to the rotational speed of the motor. Further, when the non-driving period is fixed as in the prior art, it is necessary to set a long non-driving time in advance, but according to the present embodiment, it is not necessary to set longer than necessary. The drive current can be smoothed, and the noise generated from the motor can be reduced.

  Further, after a certain back electromotive detection signal BEMF_EDGE is output, the window generation circuit 40, after the elapse of a period (Tp2 × m) obtained by multiplying the cycle Tp1 of the back electromotive detection signal BEMF_EDGE by a coefficient (1-m / n), The window signal WINDOW is set to the high level, and then, when the next counter electromotive detection signal BEMF_EDGE is output from the counter electromotive detection circuit 20, the window signal WINDOW is set to the low level. As a result, the timing for setting the switching circuit 10u to the high impedance state can be reliably set prior to the detection of the zero cross point.

  Furthermore, in the embodiment, the timing setting unit 44 can adjust the number m of pulse signals PULSE to be counted. As a result, the length of the non-driving period Tp3 can be changed according to the type of motor to be driven, and stable motor driving is realized.

  Further, in the embodiment, the integer K can be adjusted in the pulse signal generation circuit 42. As a result, when the integer K is set small, the gain of the feedback loop increases, so that it is possible to set high followability to fluctuations in the rotational speed of the motor, and conversely, when K is set large, Since the gain of the feedback loop is lowered, the stability of the loop can be increased. Therefore, optimum motor driving can be realized by setting the value of K according to the type of motor, the number of rotations, and the driving method.

  Next, an example of application of the motor drive circuit 100 according to the present embodiment will be described. FIG. 6 is a block diagram showing a configuration of a disk device 200 on which the motor drive circuit 100 of FIG. 1 is mounted. The disk device 200 is a unit that performs recording and reproduction processing on an optical disk such as a CD or a DVD, and is mounted on an electronic device such as a CD player, a DVD player, or a personal computer. The disk device 200 includes a pickup 210, a signal processing unit 212, a disk 214, a motor 110, and a motor driving circuit 100.

  The pickup 210 writes desired data by irradiating the disk 214 with a laser, or reads the data written on the disk 214 by reading reflected light. The signal processing unit 212 performs necessary signal processing such as amplification processing, A / D conversion, or D / A conversion on data read and written by the pickup 210. The motor 110 is a spindle motor provided for rotating the disk 214. Since the disk device 200 as shown in FIG. 6 is particularly required to be downsized, a sensorless type that does not use a Hall element or the like is used as the motor 110. The motor drive circuit 100 according to the present embodiment can be suitably used to stably drive such a sensorless spindle motor.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are also within the scope of the present invention. is there.

  In the embodiment, the case of driving a three-phase motor has been described. However, the present invention can also be suitably used for driving a sensorless motor other than the three-phase motor. For example, a five-phase motor may be used. In the embodiment, a case where the zero-cross point is detected by comparing the U-phase counter electromotive voltage Vu with the midpoint voltage Vcom and the U-phase switching circuit 10u is set to high impedance in the non-driving period will be described. However, the present invention is not limited to this. For example, the back electromotive detection circuit 20 may be provided for each of the U phase, the V phase, and the W phase, the back electromotive detection signal BEMF_EDGE may be generated, and the non-driving period may be set prior to detection of each zero cross point. Even in this case, the window signal WINDOW may be set to the high level during a period obtained by multiplying the cycle Tp1 of the back electromotive detection signal BEMF_EDGE by a predetermined count.

  In the embodiment, the case where the motor is driven by the 180-degree energization PWM method has been described. However, the present invention is not limited to this, and the switching circuit 10 has a high impedance for detecting the zero cross point. It can be used for all motor drive circuits that need to be

  The high-level and low-level logic settings of the signals described in the embodiment are merely examples, and various modifications can be considered for the configuration of the logic circuit block, and such modifications are also included in the scope of the present invention.

It is a block diagram which shows the structure of the motor drive circuit which concerns on embodiment. It is a block diagram which shows the structural example of a part of motor drive circuit. It is a block diagram which shows the structural example of a pulse signal generation circuit and a timing setting part. 4A to 4L are time charts showing the operation of the motor drive circuit according to the embodiment. 5A to 5D are time charts showing how the window signal WINDOW is generated. It is a block diagram which shows the structure of the disc apparatus carrying the motor drive circuit of FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 100 Motor drive circuit, 10 Switching circuit, 20 Back electromotive force detection circuit, 30 Switching control circuit, 32 Drive timing generation circuit, 34 Drive signal synthesis circuit, 40 Window generation circuit, 42 Pulse signal generation circuit, 44 Timing setting part, 50 Frequency Counter, 52 storage unit, 54 operation unit, 56 clock signal generation unit, 60 counter, 62 window signal output unit, 110 motor, 210 pickup, 212 signal processing unit, 214 disk.

Claims (12)

A motor drive circuit that drives a multiphase motor by supplying a drive current,
A plurality of switching circuits that are provided for each coil of the multiphase motor and apply a high-level or low-level voltage to one end of the connected coils;
A back electromotive force voltage generated in at least one coil of the multiphase motor is compared with a midpoint voltage of the coil to detect a zero cross point and output a back electromotive force detection signal;
A switching control circuit for controlling a switching state of the plurality of switching circuits based on a back electromotive detection signal output from the back electromotive detection circuit and adjusting a current flowing through a coil of the multiphase motor;
A window generating circuit that outputs a window signal having a predetermined level for a period obtained by multiplying the period of the back electromotive detection signal output from the back electromotive detection circuit by a predetermined coefficient prior to detection of the zero cross point by the back electromotive detection circuit; ,
With
The switching control circuit stops switching of the switching circuit during a period when the window signal from the window generation circuit is at the predetermined level, and sets the high impedance state.
The window generation circuit includes:
A pulse signal generation circuit that receives the back electromotive detection signal output from the back electromotive detection circuit and generates a pulse signal having a frequency n times (n is an integer of 2 or more) the back electromotive detection signal;
The counter electromotive detection signal from the counter electromotive detection circuit and the pulse signal from the pulse signal generation circuit are received. (1) After detecting the electromotive detection signal, m pulse signals (m Is an integer satisfying m <n), if detected, the window signal is set to the predetermined level. (2) Thereafter, when the next back electromotive detection signal is detected, the window signal is set to a level different from the predetermined level. A repeat timing setting unit,
And the predetermined coefficient is (1-m / n) . The motor driving circuit according to claim 1 , wherein the timing setting unit includes an adjusting unit for the integer m. The pulse signal generation circuit includes:
A frequency counter for measuring the frequency of the back electromotive detection signal;
A clock signal generator for generating a pulse signal having a frequency n times (n is an integer of 2 or more) the frequency measured by the frequency counter;
The motor drive circuit according to claim 1 or 2, characterized in that it comprises a. The clock signal generator is
4. The motor drive circuit according to claim 3, wherein the frequency of the pulse signal to be generated is set based on the frequency values of the past K times (K is an integer of 1 or more) measured by the frequency counter. The motor drive circuit according to claim 4 , wherein the clock signal generation unit includes an adjusting unit for the integer K. The pulse signal generation circuit includes:
A storage unit that holds frequency values for the past L times (L is an integer satisfying L ≧ K);
An arithmetic unit that calculates the frequency of the pulse signal by simple averaging or weighted averaging of the frequency values held in the storage unit;
Further including
The motor drive circuit according to claim 4 , wherein the clock signal generation unit generates a pulse signal having a frequency corresponding to a calculation result of the calculation unit. The motor drive circuit according to claim 6 , wherein the storage unit is an L-stage shift register. The arithmetic unit, of the frequency values of L times held in the storage unit, calculates a frequency value of the latest K times, according to claim 6, characterized in that to determine the frequency of the pulse signal Motor drive circuit. The timing setting unit includes:
The counter electromotive detection signal output from the counter electromotive detection circuit and the pulse signal output from the pulse signal generation circuit are received, and after detecting a counter electromotive detection signal, counting the number of the pulse signals, A counter that outputs an open edge signal at a predetermined level;
A window signal output unit that outputs a window signal that is at a level different from the predetermined level when the next back electromotive detection signal is detected after the open edge signal of the predetermined level is output from the counter; ,
The motor drive circuit according to any one of claims 1 to 8, which comprises a. The motor drive circuit according to any one of claims 1-9, characterized in that it is integrated on a single semiconductor substrate. A spindle motor that rotates the disk;
The motor drive circuit according to any one of claims 1 to 10, which drives the spindle motor;
A disk device comprising: A motor driving method for supplying a driving current to a multiphase motor,
Back electromotive force generated in at least one coil of the multiphase motor is compared with a midpoint voltage of the coil to detect a zero cross point and output a back electromotive detection signal;
Applying a high-level or low-level voltage to one end of each coil of the multiphase motor in accordance with the back electromotive detection signal, and adjusting a current flowing through the coil of the multiphase motor;
Generating a window signal having a predetermined level for a period obtained by multiplying a period of the back electromotive detection signal by a predetermined coefficient prior to detection of a zero cross point in the back electromotive detection step;
Setting a circuit connected to the coil to a high impedance state during a period when the window signal is at the predetermined level ;
Equipped with a,
Generating the window signal comprises:
Generating a pulse signal having a frequency n times (n is an integer of 2 or more) of the back electromotive detection signal;
(1) After detecting the back electromotive detection signal, when the number of the pulse signals (m is an integer satisfying m <n) is detected, the window signal is set to the predetermined level, and (2) the next inverse Repeating the process of setting the window signal to a level different from the predetermined level when detecting the occurrence detection signal;
Including
The method is characterized in that the predetermined coefficient is (1-m / n) .

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