JP4865606B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to a method of manufacturing a semiconductor equipment, in particular to a method for manufacturing a high voltage semiconductor equipment.

2. Description of the Related Art As electronic devices have become lighter, thinner, smaller, and higher performance in recent years, semiconductor devices used in these electronic devices are required to be smaller and more functional.
Among these demands, it has been proposed to reduce the channel length in order to cope with the miniaturization in particular. However, the reduction in the breakdown voltage of the semiconductor device and the deterioration of the driving capability have been problems.

In order to solve this problem, a high voltage semiconductor device including a structure as shown in FIG. 3 has been proposed (see, for example, Patent Document 1).
A channel region 52 is formed in the first conductivity type semiconductor substrate 50, and a source region 54 and a drain region 56 made of a low concentration impurity diffusion layer are formed in the recess of the first conductivity type semiconductor substrate 50 so as to sandwich the channel region 52. Then, a high concentration impurity diffusion layer 58 and a high concentration impurity diffusion layer 60 are formed in the surface layer regions of the source region 54 and the drain region 56, respectively. Further, a gate insulating film 62 is formed on the channel region 52, the source region 54, the drain region 56, the high concentration impurity diffusion layer 58, and the high concentration impurity diffusion layer 60, and the channel is formed with the gate insulating film 62 as a boundary. A gate electrode 64 is formed on the side opposite to the region 52.
As described above, the conventional high breakdown voltage semiconductor device uses the low-concentration impurity diffusion layers as the source region 54 and the drain region 56.

In addition to the semiconductor device, a semiconductor device having a source region and a drain region made of a diffusion layer has been proposed (see, for example, Patent Document 2 and Patent Document 3).
JP-A-6-283678 JP-A-6-29477 JP 2003-338561 A

However, as described above, in the semiconductor devices described in Patent Document 1 and Patent Document 2, the source region 54 and the drain region 56 are implanted with impurities to form a low-concentration impurity diffusion layer. Since the concentration of the impurity decreases from the surface layer region to the bottom of the concentration impurity diffusion layer, the driving capability decreases. In addition, if the impurity concentration of the diffusion layer is increased for the purpose of improving the driving capability, the driving capability can be improved because the concentration in the vicinity of the surface layer is also increased, but electric field concentration is caused near the surface layer where the impurity concentration is high, The breakdown voltage of the semiconductor device is reduced. Thus, there is a significant trade-off relationship between the breakdown voltage and the driving capability of the semiconductor device, and it is required to simultaneously improve the breakdown voltage and the driving capability of the semiconductor device.
In addition, the semiconductor device described in Patent Document 3 has a structure of a low breakdown voltage semiconductor device and is difficult to use as a high breakdown voltage semiconductor device.

This invention is made | formed in view of the said problem, and makes it a subject to achieve the following objectives.
It is an object of the present invention is to provide a semiconductor equipment manufacturing method which is excellent in withstand voltage, and driving capability.

The present inventors have a result of intensive studies, by using the manufacturing method of the semiconductor equipment below, we can solve the above problems, leading to achieve the above object.

That is, the method for manufacturing a semiconductor device according to claim 1 comprises:
A method of manufacturing a semiconductor device having a M OS transistor and M OS transistor of the second conductivity type of the first conductivity type,
The surface layer region of the first conductivity type semiconductor substrate in the formation region of the M OS transistor of the first conductivity type, forming an impurity diffusion layer of the second conductivity type,
The lower region of the second conductivity type impurity diffusion layer in the formation region of the M OS transistor of the first conductivity type, forming a high concentration buried impurity diffusion layer of the second conductivity type,
With a surface layer region of the first conductivity type semiconductor substrate in the formation region of the M OS transistor of the second conductivity type, the impurity diffusion layer of the second conductivity type in the formation region of the M OS transistor of the first conductivity type the surface layer region, the second in the formation region of the M OS transistor and forming by forming a single crystal layer of the second conductivity type and the second conductivity type impurity concentration is uniformly low concentration impurity diffusion layer A first conductivity type impurity diffusion layer is formed in the second conductivity type single crystal layer so as to form a lightly doped low concentration source region and a low concentration drain region made of the conductivity type single crystal layer. simultaneously it makes a first conductivity type channel region formed of impurity diffusion layers of the formation planned M OS transistor formation region and the first conductivity type of the second conductivity type M OS transistor Forming an impurity diffusion layer of the first conductivity type in the single crystal layer of the second conductivity type so as to isolate the frequency range,
The low concentration impurity diffusion layer of the first conductivity type formed spaced in the single crystal layer of the second conductivity type in the formation region of the M OS transistor of the first conductivity type low concentration impurity diffusion of the first conductivity type Forming a low-concentration source region and a low-concentration drain region composed of layers, and forming a channel region composed of the single crystal layer of the second conductivity type;
So as to isolate the formation region of the M OS transistor formation region and the second conductivity type of said M OS transistor of the first conductivity type, a field oxide film on the surface region of the first conductivity type semiconductor substrate And a process of
It said lightly doped source region in the forming region of the M OS transistor of the first conductivity type, wherein the lightly doped drain region and the channel region, the channel region with a gate oxide film, through the gate oxide film Forming a gate electrode thereon;
It said lightly doped source region in the forming region of the M OS transistor of the second conductivity type, wherein the lightly doped drain region and the channel region, the channel region with a gate oxide film, through the gate oxide film Forming a gate electrode thereon;
The surface layer region of the lightly doped source region and the lightly doped drain region in the formation region of the M OS transistor of the second conductivity type, respectively to form a high concentration impurity diffusion layer of the second conductivity type, the second conductivity type Forming a high concentration source region and a high concentration drain region made of a high concentration impurity diffusion layer;
The surface layer region of the lightly doped source region and the lightly doped drain region in the formation region of the M OS transistor of the first conductivity type, respectively to form a high concentration impurity diffusion layer of the first conductivity type, the first conductivity type Forming a high concentration source region and a high concentration drain region made of a high concentration impurity diffusion layer;
A method for manufacturing a semiconductor device having

According to the present invention, it is possible to provide a semiconductor equipment manufacturing method which is excellent in withstand voltage, and driving capability.

Hereinafter, the best mode for carrying out the manufacturing method of the semiconductor equipment of the present invention will be described with reference to the drawings with an example. In addition, the overlapping description may be omitted.

<Semiconductor device>
FIG. 1 is a cross-sectional view of a semiconductor device 100 of a reference example .
A semiconductor device 100 shown in FIG. 1 includes a first conductivity type semiconductor substrate 10, a channel region 12 formed of a first conductivity type diffusion layer formed in a surface layer region of the first conductivity type semiconductor substrate 10, and a channel region 12. The high concentration impurity diffusion layer 18 and the high purity are formed in the source region 14 and the drain region 16 formed from the single crystal layer of the second conductivity type formed on both sides of the semiconductor layer, and the surface region of the source region 14 and the drain region 16, respectively. An impurity diffusion layer 20 is provided, and a gate electrode 24 is provided on the channel region 12 with a gate insulating film 22 interposed therebetween.
Below, each component is explained in full detail.

[Source region, drain region]
The semiconductor device 100 of the reference example has a source region 14 and a drain region 16. These regions are constituted by a single crystal layer which is a low concentration impurity diffusion layer having a uniform impurity concentration.
Here, “the impurity concentration is uniform” means that the source region 14 and the drain region 16 (hereinafter referred to as “S / D regions” as appropriate) in the film thickness direction, which are second conductivity type single crystal layers. This means that the impurity concentration is uniform.
FIG. 7 is a diagram illustrating the impurity concentration in the film thickness direction in the S / D region of the semiconductor device. As shown in the figure, the impurity concentration of the S / D region in the semiconductor device 100 of the reference example shows a constant value regardless of the film thickness. In contrast, the S / D region in the conventional semiconductor device has a high impurity concentration in a region close to the gate insulating film, and a low impurity concentration in a region away from the gate electrode.
In addition, the distribution range of the impurity concentration in the film thickness direction is preferably ± 50% to ± 70% with respect to the average value of the impurity concentration in the S / D region, from the viewpoint of breakdown voltage and driving capability.

The film thickness of the S / D region can be appropriately changed according to the specifications of the semiconductor device 100, but the single crystal layer is formed by diffusing impurities in a single crystal layer such as Si made of a conventional material. . Examples of the impurity include B and the like when the single crystal layer is a P-type diffusion layer, and P and the like when the single crystal layer is an N-type diffusion layer.
The S / D region is a layer containing a low concentration of impurities, and the concentration of impurities needs to be low from the viewpoint of improving the breakdown voltage of the semiconductor device 100. Specifically, the average value of the impurity concentration in the S / D region is preferably 1 × 10 ¹⁶ pieces / cm ³ to 1 × 10 ¹⁸ pieces / cm ³ , and 1 when the voltage specification is 40 V class. It is particularly preferable that there are × 10 ¹⁷ pieces / cm ^{3 to} 5 × 10 ¹⁷ pieces / cm ³ .
The S / D region is preferably a single crystal layer formed by epitaxial growth.

[Diffusion layer of first conductivity type]
The semiconductor device 100 of the reference example has a channel region 12 made of a first conductivity type diffusion layer formed in the surface region of the semiconductor substrate 10.
The channel region 12 is formed by a diffusion layer in which impurities are diffused. For this reason, the threshold value can be controlled regardless of the substrate, and is provided for separating a source region 14 and a drain region 16 described later. The source region 14 and the drain region 16 are opposite conductivity type diffusion layers.

  The depth of the channel region 12 is not particularly limited as long as the source region 14 and the drain region 16 can be separated from each other, but from the viewpoint of suppressing punch-through, the source region 14 and the drain region 16. The ratio of the film thickness to the channel region is preferably (film thickness of the source region and drain region) :( film thickness of the channel region) = 1: 3 to 1: 5, particularly preferably about 1: 3.

The impurity concentration in the channel region 12 can be appropriately adjusted according to the threshold value of the semiconductor device, but is preferably 1 × 10 ¹⁶ / cm ^{3 to} 5 × 10 ¹⁶ / cm ³ and has a voltage specification of 40 V class. In this case, it is particularly preferably about 2 × 10 ¹⁶ pieces / cm ³ . Further, the specific resistance of the channel region 12 depends on the concentration of the impurity, and is preferably 10 Ω · cm to 100 Ω · cm, and particularly preferably 20 Ω · cm to 30 Ω · cm.

[First conductivity type semiconductor substrate]
The semiconductor device 100 of the reference example has a first conductivity type semiconductor substrate 10.
Examples of the material of the substrate include silicon.
The thickness of the substrate is preferably 300 μm or more and 800 μm or less in order to cope with downsizing of the semiconductor device.

[Gate insulation film, gate electrode]
The semiconductor substrate 100 of the reference example has a gate insulating film 22 and a gate electrode 24.
As the gate insulating film 22 in FIG. 1, a conventional oxide such as SiO ₂ or an oxynitride film can be used. As the gate electrode 24, a conventional metal such as PolySi or W can be used.
The thickness of the gate insulating film 22 is preferably such that the electric field applied to the Gate film is 3 MV / cm or more and 6 MV / cm or less from the viewpoint of voltage specifications.

[High-concentration impurity diffusion layer]
The semiconductor device 100 of the reference example includes the high concentration impurity diffusion layer 18 and the high concentration impurity diffusion layer 20 in the surface layer regions of the source region 14 and the drain region 16.
The second conductivity type second high-concentration impurity diffusion layer 18 and the second conductivity type second high-concentration impurity diffusion layer 20 electrically connect the source region 14 and the drain region 16 to the wiring (not shown). It is a connection part for connecting to. When it has a high impurity concentration, it is easy to connect to a metal wiring.
The impurity is preferably the same element as the wiring or contained in the wiring, and examples thereof include Al and Cu.
The concentration of the impurity is preferably 100 to 1000 times the concentration of the source region 14 and the drain region 16.

[Preferred Embodiment of Semiconductor Device]
The semiconductor device of the reference example, on the first conductivity type semiconductor substrate 10, an active region where the semiconductor device 100 of the reference example is formed in addition to the active region are separated by a field insulating film, the following It is preferable to form a CMOS transistor by forming the semiconductor device 200 having a structure.
FIG. 2 is a cross-sectional view of the semiconductor device 200.
The semiconductor device 200 shown in FIG. 2 is formed so as to be in contact with the second conductivity type diffusion layer 34 formed in the surface region of the first conductivity type semiconductor substrate 10 and the bottom surface of the second conductivity type diffusion layer 34. A second conductivity type high-concentration buried impurity diffusion layer 32, a channel region 36 made of a single crystal layer formed on the convex surface of the second conductivity type diffusion layer 34, and a second conductivity type single crystal. A source region 38 and a drain region 40 made of a first conductivity type diffusion layer formed on both sides of a channel region 36 made of a layer, and a high-concentration impurity diffusion layer in the surface layer region of the source region 38 and the drain region 40, respectively. 42 and a high-concentration impurity diffusion layer 44, and a gate electrode 48 formed on the channel region 36 through a gate insulating film 46 is provided.
Below, each component is explained in full detail.

[High conductivity buried impurity diffusion layer of first conductivity type, first conductivity type diffusion layer]
The semiconductor device 200 of the reference example has the second conductivity type high-concentration buried impurity diffusion layer 32 so as to be in contact with the bottom surface of the second conductivity type diffusion layer 34.
The impurity concentration of the second conductivity type high-concentration buried impurity diffusion layer 32 is preferably higher than the impurity concentration of the second conductivity type diffusion layer 34, but the breakdown voltage of the source region 38 and the drain region 40 is reduced. It must not be reduced.
In order to satisfy this condition, the ratio of the impurity concentration of the second conductivity type high-concentration buried impurity diffusion layer 32 and the concentration of the second conductivity type diffusion layer 34 is (second conductivity type impurity diffusion layer 34). : (Second conductivity type high-concentration buried impurity diffusion layer 32) 1:10 to 1: 500 is preferable, and 1:50 to 1: 100 is particularly preferable.
Further, the second conductivity type diffusion layer 34 has a certain thickness in order to suppress a decrease in breakdown voltage of the semiconductor device 200 due to the high impurity concentration of the second conductivity type high concentration buried impurity diffusion layer 32. Is preferred. Specifically, the distance between the film thickness of the high-concentration buried impurity diffusion layer 32 and the source region 38 made of the first conductivity type diffusion layer is preferably 3 to 6 μm. The film thickness of the second conductivity type diffusion layer 34 represents the distance between the bottom surface of the source region 38 or the drain region 40 and the surface of the high concentration buried impurity diffusion layer 32.

[Source region, drain region]
The semiconductor device 200 of the reference example has a source region 38 and a drain region 40 (hereinafter referred to as “S / D region” as appropriate).
The S / D region is formed by a diffusion layer in which impurities are ion-implanted.
The impurity element and concentration are the same as those of the semiconductor device 100.

[Channel area]
The semiconductor device 200 of the reference example has a channel region 36 made of a second conductivity type single crystal layer in the surface layer region of the second conductivity type diffusion layer 34.
Since the channel region 36 is formed of a single crystal layer, the impurity concentration distribution is uniform, which is preferable in that the short channel effect is suppressed and the breakdown voltage of the semiconductor device 200 is prevented from being lowered.
The thickness of the channel region 36 is preferably 3 μm or more from the viewpoint of suppressing punch-through.
The channel region 36 is formed by diffusing impurities in a single crystal layer made of a conventional material such as Si. Examples of the impurity include B and the like when the single crystal layer is a P-type diffusion layer, and P and the like when the single crystal layer is an N-type diffusion layer.
The concentration of the impurity in the channel region 36 can be appropriately adjusted according to the threshold value of the semiconductor device, but is preferably 1 × 10 ¹⁶ pieces / cm ^{3 to} 5 × 10 ¹⁶ pieces / cm ³ .

[Semiconductor substrate, gate insulating film, gate electrode, high-concentration impurity diffusion layer]
The substrate, the mounting substrate, the gate insulating film, the gate electrode, and the high concentration impurity diffusion layer are the same as those of the semiconductor device 100.

As described above, the semiconductor device 100 of the reference example, the breakdown voltage of the semiconductor device, and has excellent drivability, the semiconductor device 200 of the reference example suppresses latchup, excellent reliability.

<Method for Manufacturing Semiconductor Device>
A method of manufacturing a semiconductor device according to a reference example includes a step of forming a first diffusion layer of a second conductivity type in a surface layer region of a first conductivity type semiconductor substrate, and a second step on the surface of the first conductivity type semiconductor substrate. A step of forming a conductive type single crystal layer; a source region and a drain region on the second conductive type single crystal layer; and a second conductive type single crystal layer on the second conductive type first diffusion layer. A step of forming a first diffusion layer of the first conductivity type so as to simultaneously form a channel region made of a crystal layer; and a first conductivity type of the first diffusion layer on the second diffusion type of the first diffusion layer. Forming a field oxide film after forming a source region and a drain region comprising two diffusion layers, forming a gate insulating film and a gate electrode in the active region, and forming a high concentration impurity diffusion layer in the source region and the drain region Forming the step.
In the semiconductor device manufacturing method of the reference example , the second conductivity type single crystal layer is separately formed on the first conductivity type semiconductor substrate, and the N channel semiconductor device and the P channel semiconductor device are simultaneously formed on the same substrate. You can also

An example of a method for manufacturing a CMOS transistor using the method for manufacturing a semiconductor device of a reference example will be described below with reference to FIG.
4A, an oxide film 102 having a thickness of 100 nm to 700 nm is formed on the first conductive type semiconductor substrate 101 by a known oxidation technique. Next, after removing the oxide film 102 in a region where the first diffusion layer 103 of the second conductivity type is formed by a photolithography etching technique, impurities such as P are removed by an implantation technique using the remaining oxide film 102 as a mask. 1 × ^{10 12} pieces / ^cm 2 to 5 × ^{10 13} pieces / cm ² implanted in 100KeV～200keV, then in an atmosphere of nitrogen, with 1100 ° C. to 1200 200 min 500 min diffusion technology ° C., the second conductive A first diffusion layer 103 of the mold is formed.

  In the step (B) of FIG. 4, it is preferable to form the second conductivity type single crystal layer 104 with a film thickness of 1 μm to 4 μm by a known single crystal growth technique after the oxide film 102 is completely removed. It is particularly preferable to form the film with a thickness of about 2 μm. The film thickness of the second conductivity type single crystal layer 104 referred to here represents the plate thickness from the surface of the second conductivity type first diffusion layer 103.

  4C, in order to isolate the source region and the drain region in the second conductivity type single crystal layer 104 and to isolate the second conductivity type first diffusion layer 103, a known photolithography process is performed. Impurities such as B are implanted by an implantation technique, and a first diffusion layer 105 of the first conductivity type is formed by a diffusion technique at 1100 ° C. to 1200 ° C. for 60 minutes to 200 minutes in a nitrogen atmosphere.

In the step (D) of FIG. 4, impurities such as B are added to the first conductive layer 103 of the second conductivity type by a known photolithographic implantation technique at 20 keV to 50 keV and 1 × 10 ¹² ions / cm ^{2 to} 5 ×. The second diffusion layer 106 of the first conductivity type, which is a low-concentration impurity diffusion layer, is formed by injecting at 10 ¹⁴ / cm ² and using a diffusion technique at 950 ° C. to 1100 ° C. for 30 minutes to 100 minutes in a nitrogen atmosphere. To do.
Thereafter, a field oxide film 107 and an active region are formed by a known LOCOS technique.

In the step (E) of FIG. 4, after the gate insulating film 108 is formed in the active region by a known technique, the gate electrode 109 is formed by a CDV / photolitho / etching technique.
Thereafter, the second conductivity type high-concentration impurity diffusion layer 110 having a high impurity concentration is formed in the surface layer region of the second conductivity type single crystal layer 104 by a known photolithographic implantation technique. A high-concentration impurity diffusion layer 111 of a first conductivity type having a high impurity concentration is formed in the surface layer region of the diffusion layer 106.
Through the steps (A) to (E), a CMOS transistor having the semiconductor device 100 of the reference example is formed.

<Method of manufacturing a semiconductor device of the present invention>
An example of a method for manufacturing a C MOS transistor of the present invention is described along Fig.
In the step (A) of FIG. 5, after the step (A) of FIG. 4 is finished, impurities such as P are again 5 × 10 ¹³ / cm ² to 1 × 10 at 1000 keV to 3000 keV by the implantation technique using the oxide film 202 as a mask. was injected at ¹⁵ / cm ^2, then, in a nitrogen atmosphere, a 60 to 300 minutes in diffusion technique at 1000 ° C. to 1200 ° C., to form a high concentration buried impurity diffusion layer 203 of the second conductivity type.
In other processes, CMOS transistors including the semiconductor device 100 of the reference example and the semiconductor device 200 of the reference example are formed through the same processes as in FIGS.

  As described above, the semiconductor device of the present invention can be manufactured with the same number of steps as a conventional semiconductor device.

  EXAMPLES Hereinafter, although an Example is given and this invention is demonstrated concretely, this invention is not restrict | limited to these.

< Reference Example 1>
A CMOS transistor as a first example of the reference example was produced as follows. This will be described with reference to FIG.
(First step)
An oxide film having a thickness of 500 nm is formed on the P-type semiconductor substrate 101 by a known oxidation technique. Next, after removing the oxide film in the region where the N-type first diffusion layer 103 is to be formed by a known photolithographic etching technique, the remaining oxide film 102 is used as a mask, and P as an impurity is 150 keV by a known implantation technique. Then, 5 × 10 ¹² ions / cm ^{2 were} implanted, and after treatment at 1200 ° C. for 300 minutes in a nitrogen atmosphere, an N-type first diffusion layer 103 was formed.

(Second step)
After removing the oxide film 102 entirely, an N-type single crystal layer 104 was formed to a thickness of 2 μm by a known single crystal growth technique. The film thickness of the N-type single crystal layer 104 referred to here represents the plate thickness from the surface of the N-type first diffusion layer 103.

(Third step)
After injecting B as an impurity into the N-type single crystal layer 104 by a known photolithographic implantation technique and treating it at 1200 ° C. for 60 minutes in a nitrogen atmosphere, the P-type first diffusion layer 105 was formed.

(4th process)
Low impurity concentration impurities are implanted into the N-type first diffusion layer 103 as impurities by a well-known photolithographic implantation technique at 30 keV at 5 × 10 ¹² ions / cm ² and processed at 1000 ° C. for 30 minutes in a nitrogen atmosphere. A P-type second diffusion layer 106 which is a diffusion layer was formed.
Thereafter, a field oxide film 107 and an active region were formed by a known LOCOS technique.

(5th process)
After forming the gate insulating film 108 in the active region by a known technique, a gate electrode 109 was formed by a CDV / photolitho / etching technique.
Thereafter, an N-type high-concentration impurity diffusion layer 110 is formed by a known diffusion technique in the surface layer region of the N-type single crystal layer 104 by a known photolithographic implantation technique. A type high-concentration impurity diffusion layer 111 was formed.

(Evaluation)
-Withstand voltage of semiconductor devices-
The breakdown voltage of the drain when the gate, source, and substrate were set to 0 V was measured using a conventional DC measuring instrument. The results are shown in Table 1.
-Drive capability-
The current value when the source and the substrate were set to 0 V and 40 V was applied to the gate and drain was measured using a conventional DC measuring instrument. The results are shown in Table 1.
-Reliability assessment-
When 100 semiconductor devices manufactured as described above were used and operated at 40 V, the current value at which Latch-up was generated was evaluated as a relative value when Example 1 was set to 1. The results are shown in Table 1.

<Example 2>
A CMOS transistor according to the second embodiment of the present invention was manufactured as follows. Referring to FIG.
After the same process as the first process of Reference Example 1 is completed, P is implanted at 5 × 10 ¹⁴ pieces / cm ² at 1500 keV as an impurity again by an implantation technique using the oxide film 202 as a mask. After processing at 60 ° C. for 60 minutes, an N-type high concentration buried impurity diffusion layer 203 was formed.
Other steps, via the second through fifth steps similar to Reference Example 1, the semiconductor device 100 of the reference example, and to form a CMOS transistor having a semiconductor device 200 of the reference example.

The CMOS transistor manufactured in this way was evaluated in the same manner as in Reference Example 1. The results are shown in Table 1.

<Comparative example>
A CMOS transistor as a comparative example was manufactured as follows. A description will be given with reference to FIG.
(Second step)
After completing the first step similar to the first step of Reference Example 1, after removing all of the oxide film 302, P as an impurity is formed at a concentration of 1 × 10 ¹³ at 180 keV by a known diffusion technique in a region where an N-channel transistor is to be formed. injected with pieces / cm ^2, then, in a nitrogen atmosphere, was treated 360 minutes at 1200 ° C., to form the N-type second diffusion layer 304, the region for forming the P-channel transistor, as an impurity by the diffusion technique B was implanted at 30 keV at 5 × 10 ¹³ pieces / cm ² , and then treated at 1000 ° C. for 60 minutes in a nitrogen atmosphere, and then a P-type first diffusion layer 305 was formed.

(Third step)
An active region and a field oxide film 306 were formed by a known LOCOS formation process.

(4th process)
After forming a gate insulating film 307 by a known technique, a gate electrode 308 was formed by a CDV / photolitho / etching technique.

(5th process)
A high-concentration impurity diffusion layer 309 having a high impurity concentration is formed in the surface layer region of the N-type second diffusion layer 304 and a high-concentration impurity diffusion is formed in the surface layer region of the P-type first diffusion layer 305 by a known photolithographic implantation technique. Layer 310 was formed.

The CMOS transistor manufactured in this way was evaluated in the same manner as in Reference Example 1. The results are shown in Table 1.

  From Table 1, it is clear that the example of the present invention is superior in the breakdown voltage and driving capability of the semiconductor device compared to the comparative example.

It is a partial sectional view of a semiconductor device in a first embodiment of a reference example . It is a partial sectional view of a semiconductor device in a 2nd embodiment of a reference example . It is a partial cross-sectional view of a semiconductor device in a conventional example. It is process drawing which shows the manufacturing process of the semiconductor device in 1st Embodiment of a reference example . It is process drawing which shows the manufacturing process of the semiconductor device of this invention . It is process drawing which shows the manufacturing process of the semiconductor device in a prior art example. It is a figure showing the impurity concentration of the film thickness direction in the S / D area | region of this invention.

Explanation of symbols

10, 50, First conductivity type semiconductor substrate 12, 36, 52 Channel region 14, 38, 54 Source region 16, 40, 56 Drain region 18, 20, 42, 44, 58, 60 High concentration impurity diffusion layer 22, 46 , 62, 108, 209, 307 Gate insulating films 24, 48, 64, 109, 210, 308 Gate electrode 32 High-concentration buried impurity diffusion layer 34 of the second conductivity type 34 Diffusion layers 100, 200, 300 of the second conductivity type Semiconductor devices 101, 201, 301 First conductivity type semiconductor substrate (P-type semiconductor substrate)
102, 202, 302 Oxide films 103, 204, 303 Second conductivity type first diffusion layer (N-type first diffusion layer)
104, 205 Second conductivity type single crystal layer (N-type single crystal layer)
105, 206, 305 First conductivity type first type diffusion layer (P type first diffusion layer)
106, 207 First conductivity type second diffusion layer (P-type second diffusion layer)
107, 208, 306 Field oxide films 110, 211, 309 Second conductivity type high concentration impurity diffusion layer (N type high concentration impurity diffusion layer)
111, 212, 310 High-concentration impurity diffusion layer of first conductivity type (P-type high-concentration impurity diffusion layer)
203 Second conductivity type high concentration buried impurity diffusion layer (N type high concentration buried impurity diffusion layer)
304 N-type second diffusion layer

Claims (1)

A method of manufacturing a semiconductor device having a M OS transistor and M OS transistor of the second conductivity type of the first conductivity type,
The surface layer region of the first conductivity type semiconductor substrate in the formation region of the M OS transistor of the first conductivity type, forming an impurity diffusion layer of the second conductivity type,
The lower region of the second conductivity type impurity diffusion layer in the formation region of the M OS transistor of the first conductivity type, forming a high concentration buried impurity diffusion layer of the second conductivity type,
Totomoni surface layer region of the first conductivity type semiconductor substrate in the formation region of the M OS transistor of the second conductivity type, the impurity diffusion layer of the second conductivity type in the formation region of the M OS transistor of the first conductivity type the surface layer region, the second in the formation region of the M OS transistor and forming by forming a single crystal layer of the second conductivity type and the second conductivity type impurity concentration is uniformly low concentration impurity diffusion layer A first conductivity type impurity diffusion layer is formed in the second conductivity type single crystal layer so as to form a lightly doped low concentration source region and a low concentration drain region made of the conductivity type single crystal layer. simultaneously it makes a first conductivity type channel region formed of impurity diffusion layers of the formation planned M OS transistor formation region and the first conductivity type of the second conductivity type M OS transistor Forming an impurity diffusion layer of the first conductivity type in the single crystal layer of the second conductivity type so as to isolate the frequency range,
The low concentration impurity diffusion layer of the first conductivity type formed spaced in the single crystal layer of the second conductivity type in the formation region of the M OS transistor of the first conductivity type low concentration impurity diffusion of the first conductivity type Forming a low-concentration source region and a low-concentration drain region composed of layers, and forming a channel region composed of the single crystal layer of the second conductivity type;
So as to isolate the formation region of the M OS transistor formation region and the second conductivity type of said M OS transistor of the first conductivity type, a field oxide film on the surface region of the first conductivity type semiconductor substrate And a process of
It said lightly doped source region in the forming region of the M OS transistor of the first conductivity type, wherein the lightly doped drain region and the channel region, the channel region with a gate oxide film, through the gate oxide film Forming a gate electrode thereon;
It said lightly doped source region in the forming region of the M OS transistor of the second conductivity type, wherein the lightly doped drain region and the channel region, the channel region with a gate oxide film, through the gate oxide film Forming a gate electrode thereon;
The surface layer region of the lightly doped source region and the lightly doped drain region in the formation region of the M OS transistor of the second conductivity type, respectively to form a high concentration impurity diffusion layer of the second conductivity type, the second conductivity type Forming a high concentration source region and a high concentration drain region made of a high concentration impurity diffusion layer;
The surface layer region of the lightly doped source region and the lightly doped drain region in the formation region of the M OS transistor of the first conductivity type, respectively to form a high concentration impurity diffusion layer of the first conductivity type, the first conductivity type Forming a high concentration source region and a high concentration drain region made of a high concentration impurity diffusion layer;
A method for manufacturing a semiconductor device comprising:

Images