CN114420645A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, wherein the manufacturing method of the semiconductor device comprises the following steps: providing a PDSOI substrate with a first device area and a second device area, wherein the PDSOI substrate comprises a lower substrate, an insulating buried layer and a semiconductor layer from bottom to top; forming an epitaxial layer on the semiconductor layer of the second device region; and forming a MOS transistor in the first device region and forming an LDMOS transistor in the second device region. The invention can improve the breakdown voltage of the LDMOS transistor.

Description

Semiconductor device and method of manufacturing the same

technical field

The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a semiconductor device and a manufacturing method thereof.

Background technique

The semiconductor-on-insulator (SOI) structure includes a lower substrate, an insulating buried layer and an upper semiconductor layer. The SOI substrate is divided into partially depleted SOI (Partially-Depleted Semiconductor-On-Insulator, PDSOI) and full Depleted SOI (Fully-Depleted Semiconductor-On-Insulator, FDSOI), generally speaking, the upper semiconductor layer of the FDSOI substrate will be relatively thin, and the cost of the substrate will be high. On the other hand, the FDSOI threshold voltage is not easy to control. The PDSOI substrate is still used. The thickness of the upper semiconductor layer of the PDSOI substrate purchased from the manufacturer is the same, but in the process of semiconductor device fabrication, different devices may need to be fabricated on the same substrate. Different devices have different requirements for breakdown voltage, and the use of upper semiconductor layers with the same thickness cannot meet the requirements for breakdown voltage of different devices at the same time.

Therefore, how to optimize the existing PDSOI structure to improve the compatibility of different devices is an urgent problem to be solved at present.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a semiconductor device and a manufacturing method thereof, which can improve the breakdown voltage of the LDMOS transistor.

To achieve the above objects, the present invention provides a method for manufacturing a semiconductor device, comprising:

providing a PDSOI substrate having a first device region and a second device region, the PDSOI substrate comprising a bottom-up underlying substrate, an insulating buried layer and a semiconductor layer;

forming an epitaxial layer on the semiconductor layer of the second device region;

A MOS transistor is formed in the first device region, and an LDMOS transistor is formed in the second device region.

Optionally, the step of forming the epitaxial layer on the semiconductor layer of the second device region includes:

forming a mask layer to cover the semiconductor layer of the first device region;

performing an epitaxial process to form an epitaxial layer on the semiconductor layer of the second device region;

The mask layer is removed.

Optionally, the step of forming the MOS transistor in the first device region includes:

forming a first gate structure on the semiconductor layer of the first device region;

A first source region and a first drain region are respectively formed in the semiconductor layers on both sides of the first gate structure.

Optionally, the step of forming the LDMOS transistor in the second device region includes:

forming a second gate structure on the epitaxial layer;

forming a drift region at least in the epitaxial layer on both sides of the second gate structure, and forming a second source region and a second drain region respectively at least in the epitaxial layer where the drift region is far from the second gate structure middle.

Optionally, the step of forming the LDMOS transistor in the second device region further includes:

forming at least one body contact region at least in the epitaxial layer of the second source region and the drift region and forming a gate ion implantation region in the second gate structure, the body contact region and the gate contact with the ion-implanted region.

所述外延层的厚度为

Optionally, the thickness of the semiconductor layer is

The thickness of the epitaxial layer is

Optionally, after forming the epitaxial layer on the semiconductor layer of the second device region and before forming the MOS transistor and the LDMOS transistor, the method for manufacturing the semiconductor device further includes:

forming a shallow trench isolation structure in the first device region and/or the second device region, and the shallow trench isolation structure of the first device region penetrates the semiconductor layer and/or the second device region The shallow trench isolation structure penetrates the epitaxial layer and the semiconductor layer.

The present invention also provides a semiconductor device, comprising:

A PDSOI substrate having a first device region and a second device region, the PDSOI substrate comprising a bottom-up lower substrate, an insulating buried layer and a semiconductor layer;

an epitaxial layer formed on the semiconductor layer of the second device region;

A MOS transistor and an LDMOS transistor, the MOS transistor is formed in the first device region, and the LDMOS transistor is formed in the second device region.

Optionally, the MOS transistor includes:

a first gate structure formed on the semiconductor layer of the first device region;

a first source region and a first drain region, respectively formed in the semiconductor layers on both sides of the first gate structure;

And, the LDMOS transistor includes:

a second gate structure formed on the epitaxial layer;

a drift region, formed at least in the epitaxial layers on both sides of the second gate structure;

A second source region and a second drain region are respectively formed at least in the epitaxial layer of the drift region away from the second gate structure.

Optionally, the LDMOS transistor further includes:

At least one body contact region and a gate ion implantation region, the body contact region formed at least in the second source region and the epitaxial layer of the drift region, the gate ion implantation region formed in the second source region In the dual gate structure, the body contact region is in contact with the gate ion implantation region.

所述外延层的厚度为

Optionally, the thickness of the semiconductor layer is

The thickness of the epitaxial layer is

Optionally, the semiconductor device further includes:

A shallow trench isolation structure, formed in the first device region and/or the second device region, the shallow trench isolation structure of the first device region penetrating the semiconductor layer, and/or the second device A shallow trench isolation structure of the region penetrates the epitaxial layer and the semiconductor layer.

Compared with the prior art, the technical scheme of the present invention has the following beneficial effects:

1. The manufacturing method of the semiconductor device of the present invention, by forming an epitaxial layer on the semiconductor layer of the second device region, and forming a MOS transistor in the first device region, and forming an LDMOS transistor in the second device region, so that The thickness of the substrate (ie, the epitaxial layer and the semiconductor layer) of the LDMOS transistor increases, thereby dispersing the electric field distribution and reducing the electric field density, thereby improving the breakdown voltage of the LDMOS transistor.

2. In the semiconductor device of the present invention, since an epitaxial layer is formed on the semiconductor layer in the second device region, the MOS transistor is formed in the first device region, and the LDMOS transistor is formed in the second device region, so that the The thickness of the substrate (ie, the epitaxial layer and the semiconductor layer) increases, so that the electric field distribution is dispersed, the electric field density is reduced, and the breakdown voltage of the LDMOS transistor is improved.

Description of drawings

1 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

2a-2e are schematic diagrams of a semiconductor device according to an embodiment of the present invention;

3a is a schematic top view of an LDMOS transistor;

3b is a schematic top view of an LDMOS transistor according to an embodiment of the present invention.

Wherein, the reference numerals in Fig. 1 to Fig. 3b are described as follows:

11-underlying substrate; 12-insulating buried layer; 13-semiconductor layer; 131-mask layer; 14-epitaxial layer; 15-shallow trench isolation structure; 161-first gate structure; 162-first source 163 - first drain region; 171 - second gate structure; 172 - first drift region; 173 - second source region; 174 - second drain region; 18 - first body contact region; 19 21-gate structure; 22-second drift region; 23-third source region; 24-third drain region; 25-second body contact region.

Detailed ways

In order to make the objects, advantages and features of the present invention clearer, the semiconductor device and its manufacturing method proposed by the present invention will be further described in detail below with reference to the accompanying drawings. It should be noted that, the accompanying drawings are all in a very simplified form and in inaccurate scales, and are only used to facilitate and clearly assist the purpose of explaining the embodiments of the present invention.

An embodiment of the present invention provides a method for manufacturing a semiconductor device. Referring to FIG. 1 , FIG. 1 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. The method for manufacturing a semiconductor device includes:

Step S1, providing a PDSOI substrate having a first device region and a second device region, the PDSOI substrate comprising a bottom-up lower substrate, an insulating buried layer and a semiconductor layer;

Step S2, forming an epitaxial layer on the semiconductor layer of the second device region;

Step S3, forming a MOS transistor in the first device region, and forming an LDMOS transistor in the second device region.

2a-2e and FIGS. 3a-3b will be described below in more detail for the manufacturing method of the semiconductor device provided in this embodiment, and FIGS. 2a-2e are schematic longitudinal cross-sectional views of the semiconductor device.

According to step S1 , a PDSOI substrate having a first device region A1 and a second device region A2 is provided, and the PDSOI substrate includes an underlying substrate 11 , an insulating buried layer 12 and a semiconductor layer 13 from bottom to top.

The underlying substrate 11 and the semiconductor layer 13 may be composed of any suitable semiconductor material, including but not limited to: silicon, germanium, silicon germanium, silicon germanium carbide, silicon carbide and other semiconductors of single crystal structure. Layer 12 is, for example, a silicon oxide layer.

The first device region A1 and the second device region A2 are pre-designed regions where corresponding devices need to be formed, and the thicknesses of the semiconductor layers 13 of the first device region A1 and the second device region A2 are equal. Wherein, for the thin film partially depleted PDSOI device, the thickness of the semiconductor layer 13 is

According to step S2 , referring to FIGS. 2 a to 2 c , an epitaxial layer 14 is formed on the semiconductor layer 13 of the second device region A2 .

The material of the epitaxial layer 14 includes, but is not limited to, silicon, germanium, silicon germanium, silicon germanium carbide, silicon carbide, and other semiconductors with a single crystal structure.

In one of the embodiments, the step of forming the epitaxial layer 14 on the semiconductor layer 13 of the second device region A2 includes: first, forming the first device region A1 and the second device region A2 of the PDSOI substrate At the same time, an epitaxial layer 14 is formed thereon, and part or all of the epitaxial layer 14 on the first device region A1 is selectively etched and removed, so that the active region on the second device region A2 is thicker.

Preferably, the step of forming the epitaxial layer 14 on the semiconductor layer 13 of the second device region A2 includes: first, as shown in FIG. 2a, forming a mask layer 131 to cover the semiconductor layer of the first device region A1 13; then, as shown in FIG. 2b, an epitaxial process is performed to form an epitaxial layer 14 on the semiconductor layer 13 of the second device region A2; then, as shown in FIG. 2c, the mask layer 131 is removed, then , the semiconductor layer 13 of the first device region A1 is exposed, and the semiconductor layer 13 of the second device region A2 is covered by the epitaxial layer 14 . The material of the mask layer 131 may be at least one of insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride.

Since the substrate used to form the device can only be of a single crystal structure (for example, single crystal silicon), the semiconductor layer 13 and the epitaxial layer 14 are both single crystal structures, so it is preferable to use an epitaxial process capable of forming a single crystal structure forming the epitaxial layer 14; and, compared with firstly adopting an epitaxial process to form the epitaxial layer 14 on the semiconductor layer 13 of the entire first device region A1 and the second device region A2, and then etching and removing the semiconductor layer of the first device region A1 The method of the epitaxial layer 14 on the 13, the method of the embodiment shown in FIGS. 2a to 2c directly adopts a selective epitaxial process to form the epitaxial layer 14 on the semiconductor layer 13 of the second device region A2, which can be used to form the epitaxial layer 14. The thickness and uniformity of the epitaxial layer 14 are better controlled, while the uniformity of the etching process is difficult to control.

以使得增加的所述外延层14的厚度能够使得后续形成的LDMOS晶体管的击穿电压得到明显提高。Preferably, the thickness of the epitaxial layer 14 is

So that the increased thickness of the epitaxial layer 14 can significantly improve the breakdown voltage of the subsequently formed LDMOS transistor.

According to step S3, referring to FIG. 2e, a MOS transistor is formed in the first device area A1, and an LDMOS transistor is formed in the second device area A2. The MOS transistor is an NMOS transistor or a PMOS transistor.

The step of forming the MOS transistor in the first device area A1 includes: first, forming a first gate structure 161 on the semiconductor layer 13 of the first device area A1; then, forming first source electrodes respectively The region 162 and the first drain region 163 are in the semiconductor layer 13 on both sides of the first gate structure 161 .

The steps of forming the LDMOS transistor in the second device region A2 include: first, forming a second gate structure 171 on the epitaxial layer 14; then, forming a first drift region 172 at least below the second gate A second source region 173 and a second drain region 174 are formed in the epitaxial layer 14 on both sides of the structure 171 , respectively, at least in the epitaxial layer 14 where the first drift region 172 is far from the second gate structure 171 .

As shown in FIG. 2e, the first drift region 172 includes a portion between the second source region 173 and the second gate structure 171, and a portion between the second drain region 174 and the second gate structure 171. The part between the second gate structures 171; in other embodiments, the first drift region 172 may only be located between the second drain region 174 and the second gate structure 171, that is, the The first drift region 172 includes at least a portion between the second drain region 174 and the second gate structure 171 .

It should be noted that the structures of the MOS transistor and the LDMOS transistor are not limited to the structures shown in FIG. 2e.

Also, the first source region 162 and the first drain region 163 may be formed in the entire thickness or part of the thickness of the semiconductor layer 13 (as shown in FIG. 2e ), the first gate structure 161 The lower region between the first source region 162 and the first drain region 163 is the channel region of the MOS transistor; the first drift region 172 and the second source region 173 and the second drain region 174 may be formed only in the epitaxial layer 14, or extend from the epitaxial layer 14 to a partial thickness of the semiconductor layer 13 (as shown in FIG. 2e), or from the epitaxial layer 14 In the semiconductor layer 13 extending to the full thickness of the epitaxial layer 14 , the region between the first drift regions 172 under the second gate structure 171 is the channel region of the LDMOS transistor.

The first gate structure 161 includes a first gate layer and a first spacer located on the sidewall of the first gate layer; the second gate structure 171 includes a second gate layer and a first spacer located on the sidewall of the first gate layer. second spacers on the sidewalls of the second gate layer.

A gate dielectric layer (not shown) is formed between the first gate structure 161 and the semiconductor layer 13 and between the second gate structure 171 and the epitaxial layer 14 , and the gate dielectric layer is The material can be silicon oxide (relative dielectric constant is 4.1) or a high-K dielectric with a relative dielectric constant greater than 7, such as but not limited to silicon oxynitride, titanium dioxide, tantalum pentoxide, etc.; or, the gate dielectric The material of the layer can also be a material with low dielectric constant, such as silicon oxycarbide (SiOC, the relative dielectric constant is 2.5), inorganic or organic spin-on glass (SOG, the relative dielectric constant is less than or equal to 3) and the like.

In addition, referring to FIG. 3b, the step of forming the LDMOS transistor in the second device region A2 may further include: forming at least one first body contact region 18 at least below the second source region 173 and the first drift region In the epitaxial layer 14 of the region 172 and the gate ion implantation region 19 is formed in the second gate structure 171, the first body contact region 18 is in contact with the gate ion implantation region 19; The integral contact region 18 may extend from the first drift region 172 into a portion of the second source region 173 or to a portion of the second source region 173 remote from the first drift region 172 . side. It should be noted that the term "contact" here means that the region boundary needs to be in contact from a top view. The two first body contact regions 18 shown in FIG. 3 b are both in contact with the two gate ion implantation regions 19 . Wherein, the first body contact region 18 is in contact with the gate ion implantation region 19 in the second gate structure 171 , so that the first body contact region 18 can connect the second gate structure 171 The lower body region is elicited. In addition, it should be noted that only the LDMOS transistor located in the second device area A2 is shown in FIG. 3b, and the MOS transistor located in the first device area A1 is not shown; The LDMOS transistor located in the second device region A2 is a cross-sectional view of the LDMOS transistor shown in FIG. 3b along the AA' direction.

3a, an LDMOS transistor formed in a bulk silicon substrate includes a gate structure 21, a second drift region 22, a third source region 23, a third drain region 24 and a second body contact region 25, The gate structure 21 is formed on a bulk silicon substrate, the second drift region 22 is formed on top of the bulk silicon substrate on both sides of the gate structure 21, the third source region 23 and the The third drain regions 24 are respectively formed on the top of the bulk silicon substrate of the second drift region 22 away from the gate structure 21, and both ends of the gate structure 21 extend to the shallow trench isolation structure (not shown in the figure). (shown), the second body contact region 25 is located at intervals on top of the bulk silicon substrate at one end of the gate structure 21, the second body contact region 25 is connected to the third source region 23, the The third drain region 24 and the second drift region 22 are separated by a shallow trench isolation structure; the body region in the bulk silicon substrate is drawn out through the second body contact region 25 .

Then, comparing the structures of the LDMOS transistors shown in FIG. 3a and FIG. 3b, it can be seen that due to the fact that the second body contact region 25, the third source region 23, the third drain region in the LDMOS transistor shown in FIG. 3a Both the pole region 24 and the second drift region 22 are separated by a shallow trench isolation structure, indicating that the second body contact region 25 occupies the area of other regions; while in the embodiment shown in FIG. 3b, the In the LDMOS transistor, since the first body contact region 18 is located in the second source region 173 and the first drift region 172, the area of other regions is not additionally occupied. Therefore, the embodiment shown in FIG. 3b Compared with the structure of the LDMOS transistor shown in Fig. 3a, the LDMOS transistor in Fig. 3 saves the device area. In addition, in the LDMOS transistor shown in FIG. 3a , in order to lead out the third source region 23 and the body region, it is necessary to make conductive electrodes on both the third source region 23 and the second body contact region 25 In the LDMOS transistor in the embodiment shown in FIG. 3b, since the first body contact region 18 is in contact with the second source region 173, the first body contact region 18 can share all The conductive plugs formed on the second source region 173 can simultaneously lead out the second source region 173 and the body region through the conductive plugs on the second source region 173, and the first body There is no need to make conductive plugs in the contact region 18. Therefore, compared with the LDMOS transistor shown in FIG. 3a, the LDMOS transistor in the embodiment shown in FIG.

In addition, the first body contact region 18 may be located at both ends of the second source region 173 and the first drift region 172 , in the middle, or at any other position.

The first body contact region 18 may be formed only in the epitaxial layer 14 , or extend from the epitaxial layer 14 to a partial thickness of the semiconductor layer 13 , or extend from the epitaxial layer 14 to the entire thickness thickness of the semiconductor layer 13 .

In addition, referring to FIG. 2d , after forming the epitaxial layer 14 on the semiconductor layer 13 of the second device region A2 and before forming the MOS transistor and the LDMOS transistor, the manufacturing method of the semiconductor device further includes: : forming a shallow trench isolation structure 15 in the first device region A1 or the second device region A2, or simultaneously forming a shallow trench isolation structure 15 in the first device region A1 and the second device region A2 , the shallow trench isolation structure 15 of the first device region A1 penetrates the semiconductor layer 13, and/or the shallow trench isolation structure 15 of the second device region A2 penetrates the epitaxial layer 14 and the semiconductor layer 13 , so that the bottom surface of the shallow trench isolation structure 15 is in contact with the buried insulating layer 12 . In other embodiments, the bottom surface of the shallow trench isolation structure 15 may not be in contact with the buried insulating layer 12 .

The shallow trench isolation structure 15 is used to enclose the first active region of the MOS transistor in the semiconductor layer 13 of the first device region A1 and the epitaxial layer 14 and the semiconductor in the second device region A2 Layer 13 encloses the second active region of the LDMOS transistor, the first source region 162 and the first drain region 163 are located in the first active region, the first drift region 172, The second source region 173 and the second drain region 174 are located in the second active region; and the shallow trench isolation structure 15 is used to isolate the MOS transistor and the LDMOS transistor.

In addition, in the boundary area between the first device area A1 and the second device area A2, the shallow trench isolation structure 15 may be located only on one side of the first device area A1, or only on the second device area A1. One side of the device area A2, or extending from the side of the first device area A1 to the side of the second device area A2 (as shown in FIG. 2e).

In the first device area A1, the top surface of the shallow trench isolation structure 15 is flush with, slightly lower than or slightly higher than the top surface of the semiconductor layer 13; in the second device area A2, the The top surface of the shallow trench isolation structure 15 is flush, slightly lower or slightly higher than the top surface of the epitaxial layer 14 . The material of the shallow trench isolation structure 15 may be silicon oxide or silicon oxynitride.

The first source region 162 , the first drain region 163 , the first drift region 172 , the second source region 173 and the second drain region 174 have the same conductivity type. The first body contact region 18 and the gate ion implantation region 19 have the same conductivity type, and the first body contact region 18 and the first drift region 172 have different conductivity types; the second source region 173 and The ion doping concentration of the second drain region 174 is greater than the ion doping concentration of the first drift region 172 . If the conductivity types of the first source region 162 , the first drain region 163 , the first drift region 172 , the second source region 173 and the second drain region 174 are N-type , the conductivity type of the first body contact region 18 and the gate ion implantation region 19 is P-type; if the first source region 162 , the first drain region 163 , the first drift region The conductivity type of the region 172 , the second source region 173 and the second drain region 174 is P type, then the conductivity type of the first body contact region 18 and the gate ion implantation region 19 is N type. The N-type ion species may include boron, indium, or gallium, etc., and the P-type ion species may include phosphorus, arsenic, or antimony, and the like.

Since LDMOS transistors have higher requirements on breakdown voltage than MOS transistors, if both the LDMOS transistor and the MOS transistor are formed in the same thickness semiconductor layer in the PDSOI substrate, and the thickness of the semiconductor layer is too thin, only The breakdown voltage requirement of the MOS transistor can be met, resulting in the accumulation of electric field, so that the LDMOS transistor is easily broken down; therefore, the manufacturing method of the semiconductor device of the present invention forms the epitaxial layer on the second device region by forming the epitaxial layer. semiconductor layer, and the MOS transistor is formed in the first device region, and the LDMOS transistor is formed in the second device region, so that the substrate of the LDMOS transistor (ie the epitaxial layer and the The thickness of the semiconductor layer) increases, so that the electric field distribution is dispersed, and the electric field density is reduced, so that the breakdown voltage of the LDMOS transistor is improved.

An embodiment of the present invention provides a semiconductor device, the semiconductor device includes: a PDSOI substrate having a first device region and a second device region, the PDSOI substrate including a bottom-up lower substrate, an insulating buried layer and a semiconductor layer; an epitaxial layer formed on the semiconductor layer in the second device region; a MOS transistor and an LDMOS transistor, the MOS transistor is formed in the first device region, and the LDMOS transistor is formed in the second device Area.

The semiconductor device provided by this embodiment will be described in more detail below with reference to FIG. 2e, FIG. 3a and FIG. 3b.

The PDSOI substrate has a first device area A1 and a second device area A2 , and the PDSOI substrate includes a bottom substrate 11 , an insulating buried layer 12 and a semiconductor layer 13 from bottom to top.

The underlying substrate 11 and the semiconductor layer 13 may be composed of any suitable semiconductor material, including but not limited to: silicon, germanium, silicon germanium, silicon germanium carbide, silicon carbide and other semiconductors of single crystal structure. Layer 12 is, for example, a silicon oxide layer.

The first device region A1 and the second device region A2 are pre-designed regions where corresponding devices need to be formed, and the thicknesses of the semiconductor layers 13 of the first device region A1 and the second device region A2 are equal. Wherein, for the thin film partially depleted PDSOI device, the thickness of the semiconductor layer 13 is

The epitaxial layer 14 is formed on the semiconductor layer 13 of the second device region A2, then, the semiconductor layer 13 of the first device region A1 is exposed, and the semiconductor layer 13 of the second device region A2 is exposed. The epitaxial layer 14 is covered, so that the active region on the second device region A2 is thicker.

The material of the epitaxial layer 14 includes, but is not limited to, silicon, germanium, silicon germanium, silicon germanium carbide, silicon carbide, and other semiconductors with a single crystal structure. Since the substrate used to form the device can only have a single crystal structure (eg, single crystal silicon), the semiconductor layer 13 and the epitaxial layer 14 are both single crystal structures.

以使得增加的所述外延层14的厚度能够使得LDMOS晶体管的击穿电压得到明显提高。Preferably, the thickness of the epitaxial layer 14 is

In order to increase the thickness of the epitaxial layer 14, the breakdown voltage of the LDMOS transistor can be significantly improved.

The MOS transistor is formed in the first device area A1, and the LDMOS transistor is formed in the second device area A2. The MOS transistor is an NMOS transistor or a PMOS transistor.

The MOS transistor includes:

The first gate structure 161 is formed on the semiconductor layer 13 of the first device region A1;

The first source region 162 and the first drain region 163 are respectively formed in the semiconductor layer 13 on both sides of the first gate structure 161 .

The LDMOS transistor includes:

The second gate structure 171 is formed on the epitaxial layer 14;

The first drift region 172 is formed at least in the epitaxial layer 14 on both sides of the second gate structure 171;

The second source region 173 and the second drain region 174 are respectively formed at least in the epitaxial layer 14 of the first drift region 172 away from the second gate structure 171 .

As shown in FIG. 2e, the first drift region 172 includes a portion between the second source region 173 and the second gate structure 171, and a portion between the second drain region 174 and the second gate structure 171. The part between the second gate structures 171; in other embodiments, the first drift region 172 may only be located between the second drain region 174 and the second gate structure 171, that is, the The first drift region 172 includes at least a portion between the second drain region 174 and the second gate structure 171 .

It should be noted that the structures of the MOS transistor and the LDMOS transistor are not limited to the structures shown in FIG. 2e.

Also, the first source region 162 and the first drain region 163 may be formed in the entire thickness or part of the thickness of the semiconductor layer 13 (as shown in FIG. 2e ), the first gate structure 161 The lower region between the first source region 162 and the first drain region 163 is the channel region of the MOS transistor; the first drift region 172 and the second source region 173 and the second drain region 174 may be formed only in the epitaxial layer 14, or extend from the epitaxial layer 14 to a partial thickness of the semiconductor layer 13 (as shown in FIG. 2e), or from the epitaxial layer 14 In the semiconductor layer 13 extending to the full thickness of the epitaxial layer 14 , the region between the first drift regions 172 under the second gate structure 171 is the channel region of the LDMOS transistor.

The first gate structure 161 includes a first gate layer and a first spacer located on the sidewall of the first gate layer; the second gate structure 171 includes a second gate layer and a first spacer located on the sidewall of the first gate layer. second spacers on the sidewalls of the second gate layer.

A gate dielectric layer (not shown) is formed between the first gate structure 161 and the semiconductor layer 13 and between the second gate structure 171 and the epitaxial layer 14 , and the gate dielectric layer is The material can be silicon oxide (relative dielectric constant is 4.1) or a high-K dielectric with a relative dielectric constant greater than 7, such as but not limited to silicon oxynitride, titanium dioxide, tantalum pentoxide, etc.; or, the gate dielectric The material of the layer can also be a material with low dielectric constant, such as silicon oxycarbide (SiOC, the relative dielectric constant is 2.5), inorganic or organic spin-on glass (SOG, the relative dielectric constant is less than or equal to 3) and the like.

In addition, referring to FIG. 3b, the LDMOS transistor may further include: at least one first body contact region 18 and a gate ion implantation region 19, the first body contact region 18 is formed at least on the second source region 173 and the gate ion implantation region 19 In the epitaxial layer 14 of the first drift region 172 , the gate ion implantation region 19 is formed in the second gate structure 171 , the first body contact region 18 and the gate ion implantation region 19 and, the first body contact region 18 may extend from the first drift region 172 into a part of the second source region 173 or extend to a part of the second source region 173 away from the One side of the first drift region 172 . It should be noted that the term "contact" here means that the region boundary needs to be in contact from a top view. The two first body contact regions 18 shown in FIG. 3 b are both in contact with the two gate ion implantation regions 19 . Wherein, the first body contact region 18 is in contact with the gate ion implantation region 19 in the second gate structure 171 , so that the first body contact region 18 can connect the second gate structure 171 The lower body region is elicited. In addition, it should be noted that only the LDMOS transistor located in the second device area A2 is shown in FIG. 3b, and the MOS transistor located in the first device area A1 is not shown; The LDMOS transistor located in the second device region A2 is a cross-sectional view of the LDMOS transistor shown in FIG. 3b along the AA' direction.

3a, an LDMOS transistor formed in a bulk silicon substrate includes a gate structure 21, a second drift region 22, a third source region 23, a third drain region 24 and a second body contact region 25, The gate structure 21 is formed on a bulk silicon substrate, the second drift region 22 is formed on top of the bulk silicon substrate on both sides of the gate structure 21, the third source region 23 and the The third drain regions 24 are respectively formed on the top of the bulk silicon substrate of the second drift region 22 away from the gate structure 21, and both ends of the gate structure 21 extend to the shallow trench isolation structure (not shown in the figure). (shown), the second body contact region 25 is located at intervals on top of the bulk silicon substrate at one end of the gate structure 21, the second body contact region 25 is connected to the third source region 23, the The third drain region 24 and the second drift region 22 are separated by a shallow trench isolation structure; the body region in the bulk silicon substrate is drawn out through the second body contact region 25 .

Then, comparing the structures of the LDMOS transistors shown in FIG. 3a and FIG. 3b, it can be seen that due to the fact that the second body contact region 25, the third source region 23, the third drain region in the LDMOS transistor shown in FIG. 3a Both the pole region 24 and the second drift region 22 are separated by a shallow trench isolation structure, indicating that the second body contact region 25 occupies the area of other regions; while in the embodiment shown in FIG. 3b, the In the LDMOS transistor, since the first body contact region 18 is located in the second source region 173 and the first drift region 172, the area of other regions is not additionally occupied. Therefore, the embodiment shown in FIG. 3b Compared with the structure of the LDMOS transistor shown in Fig. 3a, the LDMOS transistor in Fig. 3 saves the device area. In addition, in the LDMOS transistor shown in FIG. 3 a , in order to lead out the third source region 23 and the body region, it is necessary to make conductive electrodes on both the third source region 23 and the second body contact region 25 In the LDMOS transistor in the embodiment shown in FIG. 3b, since the first body contact region 18 is in contact with the second source region 173, the first body contact region 18 can share all The conductive plugs formed on the second source region 173 can simultaneously lead out the second source region 173 and the body region through the conductive plugs on the second source region 173, and the first body There is no need to make conductive plugs in the contact region 18. Therefore, compared with the LDMOS transistor shown in FIG. 3a, the LDMOS transistor in the embodiment shown in FIG. 3b has a simpler interconnect extraction structure and saves cost.

In addition, the first body contact region 18 may be located at both ends of the second source region 173 and the first drift region 172 , in the middle, or at any other position.

The first body contact region 18 may be formed only in the epitaxial layer 14 , or extend from the epitaxial layer 14 to a partial thickness of the semiconductor layer 13 , or extend from the epitaxial layer 14 to the entire thickness thickness of the semiconductor layer 13 .

In addition, the semiconductor device further includes: a shallow trench isolation structure 15, which is formed in the first device region A1 or the second device region A2, or is formed in the first device region A1 and the second device region simultaneously In the device region A2, the shallow trench isolation structure 15 of the first device region A1 penetrates the semiconductor layer 13, and/or the shallow trench isolation structure 15 of the second device region A2 penetrates the epitaxial layer 14 and all The semiconductor layer 13 is formed so that the bottom surface of the shallow trench isolation structure 15 is in contact with the buried insulating layer 12 . In other embodiments, the bottom surface of the shallow trench isolation structure 15 may not be in contact with the buried insulating layer 12 .

The shallow trench isolation structure 15 is used to enclose the first active region of the MOS transistor in the semiconductor layer 13 of the first device region A1 and the epitaxial layer 14 and the semiconductor in the second device region A2 Layer 13 encloses the second active region of the LDMOS transistor, the first source region 162 and the first drain region 163 are located in the first active region, the first drift region 172, The second source region 173 and the second drain region 174 are located in the second active region; and the shallow trench isolation structure 15 is used to isolate the MOS transistor and the LDMOS transistor.

In addition, in the boundary area between the first device area A1 and the second device area A2, the shallow trench isolation structure 15 may be located only on one side of the first device area A1, or only on the second device area A1. One side of the device area A2, or extending from the side of the first device area A1 to the side of the second device area A2 (as shown in FIG. 2e).

In the first device area A1, the top surface of the shallow trench isolation structure 15 is flush with, slightly lower than or slightly higher than the top surface of the semiconductor layer 13; in the second device area A2, the The top surface of the shallow trench isolation structure 15 is flush, slightly lower or slightly higher than the top surface of the epitaxial layer 14 . The material of the shallow trench isolation structure 15 may be silicon oxide or silicon oxynitride.

The first source region 162 , the first drain region 163 , the first drift region 172 , the second source region 173 and the second drain region 174 have the same conductivity type. The first body contact region 18 and the gate ion implantation region 19 have the same conductivity type, and the first body contact region 18 and the first drift region 172 have different conductivity types; the second source region 173 and The ion doping concentration of the second drain region 174 is greater than the ion doping concentration of the first drift region 172 . If the conductivity types of the first source region 162 , the first drain region 163 , the first drift region 172 , the second source region 173 and the second drain region 174 are N-type , the conductivity type of the first body contact region 18 and the gate ion implantation region 19 is P-type; if the first source region 162 , the first drain region 163 , the first drift region The conductivity type of the region 172 , the second source region 173 and the second drain region 174 is P type, then the conductivity type of the first body contact region 18 and the gate ion implantation region 19 is N type. The N-type ion species may include boron, indium, or gallium, etc., and the P-type ion species may include phosphorus, arsenic, or antimony, and the like.

Since LDMOS transistors have higher requirements on breakdown voltage than MOS transistors, if both the LDMOS transistor and the MOS transistor are formed in the same thickness semiconductor layer in the PDSOI substrate, and the thickness of the semiconductor layer is too thin, only The breakdown voltage requirement of the MOS transistor can be met, and the electric field is concentrated, so that the LDMOS transistor is easily broken down; therefore, in the semiconductor device of the present invention, the epitaxial layer is formed on the semiconductor layer of the second device region. layer, and the MOS transistor is formed in the first device region, and the LDMOS transistor is formed in the second device region, so that the thickness of the substrate (ie, the epitaxial layer and the semiconductor layer) of the LDMOS transistor is increase, so that the electric field distribution is dispersed, the electric field density is reduced, and the breakdown voltage of the LDMOS transistor is improved.

The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosure all belong to the protection scope of the claims.

Claims (12)

1. A method for manufacturing a semiconductor device, comprising: providing a PDSOI substrate having a first device region and a second device region, the PDSOI substrate comprising a bottom-up underlying substrate, an insulating buried layer and a semiconductor layer; forming an epitaxial layer on the semiconductor layer of the second device region; A MOS transistor is formed in the first device region, and an LDMOS transistor is formed in the second device region. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the step of forming the epitaxial layer on the semiconductor layer in the second device region comprises: forming a mask layer to cover the semiconductor layer of the first device region; performing an epitaxial process to form an epitaxial layer on the semiconductor layer of the second device region; The mask layer is removed. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the step of forming the MOS transistor in the first device region comprises: forming a first gate structure on the semiconductor layer of the first device region; A first source region and a first drain region are respectively formed in the semiconductor layers on both sides of the first gate structure. 4. The method for manufacturing a semiconductor device according to claim 1, wherein the step of forming the LDMOS transistor in the second device region comprises: forming a second gate structure on the epitaxial layer; forming a drift region at least in the epitaxial layer on both sides of the second gate structure, and forming a second source region and a second drain region respectively at least in the epitaxial layer where the drift region is far from the second gate structure middle. 5. The method for manufacturing a semiconductor device according to claim 4, wherein the step of forming the LDMOS transistor in the second device region further comprises: forming at least one body contact region at least in the epitaxial layer of the second source region and the drift region and forming a gate ion implantation region in the second gate structure, the body contact region and the gate contact with the ion-implanted region. 6. The method for manufacturing a semiconductor device according to claim 1, wherein the thickness of the semiconductor layer is

The thickness of the epitaxial layer is

7. The method of manufacturing a semiconductor device according to claim 1, wherein after forming the epitaxial layer on the semiconductor layer of the second device region and before forming the MOS transistor and the LDMOS transistor , the manufacturing method of the semiconductor device further comprises: forming a shallow trench isolation structure in the first device region and/or the second device region, and the shallow trench isolation structure of the first device region penetrates the semiconductor layer and/or the second device region The shallow trench isolation structure penetrates the epitaxial layer and the semiconductor layer. 8. A semiconductor device, comprising: A PDSOI substrate has a first device region and a second device region, and the PDSOI substrate includes a bottom-up underlying substrate, an insulating buried layer and a semiconductor layer; an epitaxial layer formed on the semiconductor layer of the second device region; A MOS transistor and an LDMOS transistor, the MOS transistor is formed in the first device region, and the LDMOS transistor is formed in the second device region. 9. The semiconductor device of claim 8, wherein the MOS transistor comprises: a first gate structure formed on the semiconductor layer of the first device region; a first source region and a first drain region, respectively formed in the semiconductor layers on both sides of the first gate structure; And, the LDMOS transistor includes: a second gate structure formed on the epitaxial layer; a drift region, formed at least in the epitaxial layers on both sides of the second gate structure; A second source region and a second drain region are respectively formed at least in the epitaxial layer of the drift region away from the second gate structure. 10. The semiconductor device of claim 9, wherein the LDMOS transistor further comprises: At least one body contact region and a gate ion implantation region are formed at least in the second source region and the epitaxial layer of the drift region, and the gate ion implantation region is formed in the second source region. In the dual gate structure, the body contact region is in contact with the gate ion implantation region. 11. The semiconductor device of claim 8, wherein the thickness of the semiconductor layer is

The thickness of the epitaxial layer is

12. The semiconductor device of claim 8, wherein the semiconductor device further comprises: A shallow trench isolation structure formed in the first device region and/or the second device region, the shallow trench isolation structure of the first device region penetrating the semiconductor layer, and/or the second device A shallow trench isolation structure of the region penetrates the epitaxial layer and the semiconductor layer.

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