JP4864245B2 - Flat panel display - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a flat display device such as an active matrix type liquid crystal or an organic EL using, for example, a thin film transistor (hereinafter referred to as TFT) as a switching element for each pixel.
[0002]
[Prior art]
Flat display devices represented by liquid crystal display devices have come to be used in various fields by taking advantage of their thinness, light weight, and low power consumption. In recent years, there has been an increasing demand for such a flat display device in particular for a large screen and high definition.
[0003]
In order to meet such a demand, it is necessary to enable transfer of a large amount of image data and processing of a large amount of image data within each horizontal scanning period as well as high definition of the display panel itself. .
[0004]
In order to enable processing of a large amount of image data, for example, when digital image data is transmitted from a liquid crystal controller, which is a control part of a liquid crystal display device, to a source driver, the following method (hereinafter referred to as this specification) has been conventionally used. (Referred to as a data inversion transmission method) has been proposed (Japanese Patent Laid-Open No. 8-248924).
[0005]
This data inversion transmission method is a method of reducing EMI by reducing switching noise when data is switched when digital data is transmitted between ICs. Hereinafter, a specific example will be described.
[0006]
As an example of this, data transmission between the liquid crystal controller IC and the source driver IC (2 port input / 24 bits) will be described.
[0007]
The image data output from the liquid crystal controller IC on the transmission side is the nth image data, and the image data to be output next is the (n + 1) th image data. When the n-th and (n + 1) -th image data are compared, and more than a majority of the bits change from 0 to 1, or from 1 to 0, the (n + 1) -th image data is output with the logic inverted. . When the image data is inverted and output in this way, a data inversion signal indicating that the image data is inverted data outputs an H level. On the other hand, when the nth and (n + 1) th image data are compared, and the majority of bits do not change from 0 to 1 or 1 to 0, the (n + 1) th image data is logically inverted. Output. A data inversion signal indicating that the image data is non-inverted data outputs an L level.
[0008]
On the other hand, on the source driver IC side which is the receiving side, the image data captured when the data inversion signal is at the H level is inverted again before being imported to the shift register inside the source driver IC and demodulated to the original image data. Then processed.
[0009]
In the data inversion transmission method as described above, in order to realize this, it is necessary to provide a data inversion circuit in a circuit on the transmission side (for example, a liquid crystal controller IC). In this case, since the data inversion circuit only operates by comparing the adjacent image data before and after, it is not controlled by other circuits.
[0010]
[Problems to be solved by the invention]
When power is supplied to a liquid crystal controller IC having a plurality of data inversion circuits as described above, the output (image data and data inversion signal) of each data inversion circuit is initially set to a different state based on the display contents at that time. Is set. This initially set state is 2 in a system having p data inversion circuits. ^p There are combinations.
[0011]
Depending on this combination, switching noise generated when the output of the liquid crystal controller IC on the transmission side changes from 1 to 0 or from 0 to 1 propagates through the drive circuit board and reaches an EMI (unwanted radiation) level. There was a problem of making it extremely worse.
[0012]
Therefore, in view of the above problems, the present invention provides a flat display device using a data inversion transmission method that can reduce switching noise.
[0013]
[Means for Solving the Problems]
The present invention includes an array substrate including a plurality of signal lines and scanning lines arranged orthogonal to each other, and pixel electrodes arranged via switch elements in the vicinity of intersections of the signal lines and the scanning lines. A signal line driving circuit connected to the signal line for supplying an image signal; and a scanning line connected to the scanning line for supplying a gate signal for turning on the switching element and writing the image signal to the pixel electrode. A circuit for outputting at least two m-bit image data in parallel to the driving circuit and the signal line driving circuit, wherein each bit of the (n + 1) -th image data corresponds to each bit of the n-th image data. When the change is more than a majority, the (n + 1) th image data is logically inverted and output, and at the same time, the data counter indicating that the (n + 1) th image data is inverted data. A signal is output, and when each bit of the (n + 1) th image data does not change more than a majority with respect to each bit of the nth image data, the (n + 1) th image data is output without being logically inverted. And a control circuit that outputs a data inversion signal indicating that the (n + 1) -th image data is non-inverted data, the control circuit outputs the two in parallel. First image data And the output of the bit of the data inversion signal and the output of the bit of the second image data and the data inversion signal are set to be opposite in the non-display period. This is a flat display device.
[0014]
In the flat display device of the present invention, 2 parallel Output with First image data And the output of the bit of the data inversion signal and the output of the bit of the second image data and the data inversion signal are set to be opposite in the non-display period. For, Electric No significant noise is generated on the source line.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a liquid crystal display device 10 according to an embodiment of the present invention will be described with reference to FIGS.
[0016]
[1] Outline of liquid crystal display device
FIG. 1 shows a schematic configuration of a liquid crystal display device 10 of the present embodiment.
[0017]
The liquid crystal display device 10 includes a liquid crystal panel 12 having color display pixels of a QUXGA (3200 × 2400) specification having an effective display area of 20.8 inches diagonal. That is, the effective display area of the liquid crystal display device 10 is configured to include 2400 horizontal pixel lines made up of display pixels of 3200 × 3 (R, G, B).
[0018]
Since the liquid crystal display device 10 includes such a large number of horizontal pixel lines L1,..., L2400, the following characteristic drive is adopted.
[0019]
That is, as shown in FIGS. 6 and 7, the effective display area is divided into upper and lower parts, and in one horizontal scanning period (1H), the horizontal pixel lines (L1 to L1200) of the upper display area and the horizontal pixel lines ( L1201 to L2400) are written in parallel, and this is sequentially repeated. For example, in this embodiment, the horizontal pixel lines L1, L2400 are sequentially written in the first horizontal scanning period (1H), and L2399, L2,... Are sequentially written in the second horizontal scanning period (1H).
[0020]
Here, the horizontal scanning period (1H) is a period during which digital image data DATA for one horizontal pixel line is transmitted from the processing device 32, and is 13 μsec in this embodiment.
[0021]
Further, here, for the sake of explanation, the effective display area of the liquid crystal panel 12 is composed of four UXGA (1600 × 1200) areas divided into upper, lower, left and right as shown in FIG. The upper right screen is the B screen, the lower left screen is the C screen, and the lower right screen is the D screen. Further, when “upper screen” is described, it refers to the A screen or B screen, and when “lower screen” is described, it refers to the C screen or D screen. Furthermore, the A screen, the B screen, the C screen, and the D screen are respectively composed of an A1 screen and an A2 screen, a B1 screen and a B2 screen, a C1 screen and a C2 screen, and a D1 screen and a D2 screen that are divided into left and right. It shall be.
[0022]
[2] Structure of liquid crystal panel
In order to realize the drive described above, the liquid crystal display device 10 is configured as follows.
[0023]
That is, the liquid crystal panel 12 includes (3200 × 3 (R, G, B)) signal lines 16 and 2400 scanning lines 18 arranged orthogonal to the signal lines 16 as shown in FIG. And an array substrate 14 including a pixel electrode 22 disposed via a TFT 20 disposed in the vicinity of the intersection of each signal line 16 and the scanning line 18, and a predetermined gap above the opposing surface of the array substrate 14. A counter electrode substrate (not shown) provided with a color filter to be arranged, and a liquid crystal (not shown) as a light modulation layer arranged between the array substrate 14 and the counter electrode substrate are provided.
[0024]
If an organic EL panel is used instead of the liquid crystal panel, an organic EL layer or the like needs to be disposed instead of the liquid crystal.
[0025]
Each of the scanning lines 18 is electrically connected to the gate of the TFT 20, each of the signal lines 16 is electrically connected to the drain of the TFT 20, and each of the pixel electrodes 22 is electrically connected to the source of the TFT 20, thereby being supplied to the scanning line 18. The analog image signal Vs from the signal line 16 is written to the pixel electrode 22 in response to the scanning pulse Vg, and display is performed based on the potential difference between the pixel electrode 22 and the counter electrode.
[0026]
By the way, as shown in FIG. 1, the signal line 16 of the liquid crystal panel 12 has an upper lead signal line 16a that is electrically drawn from the upper side of the array substrate 14 and a lower line that is electrically drawn from the lower side of the array substrate 14. The signal lines 16a and 16b are alternately arranged as shown in FIG. In other words, the odd-numbered signal lines 16 are the upper lead signal lines 16a, and the even-numbered signal lines 16 are the lower lead signal lines 16b.
[0027]
Of the odd-numbered signal lines 16a arranged on the AC screen, the upper lead signal lines 16a of R1, B1,..., G800 are upper source drivers for the first AC screen arranged on the upper side of the liquid crystal panel 12. The upper lead signal lines 16a of R801, B801,..., G1600 are electrically connected to the 24-ACU1 via the connection pads 17a, respectively, to the second AC screen upper source driver 24-ACU2. Of the even-numbered signal lines 16b arranged on the AC screen, the lower lead signal lines 16b of G1, R2,..., B800 are the lower source for the second AC screen arranged on the lower side of the liquid crystal panel 12. The lower lead signal lines 16b of G801, R802,..., B1600 are electrically connected to the driver 26-ACD1 via the connection pads 17b, respectively, to the lower source driver 26-ACD2 for the second AC screen.
[0028]
Similarly, among the odd-numbered signal lines 16a arranged on the BD screen, the upper lead signal lines 16a of R1601, B1601,... The upper lead signal lines 16a of R2401, B2401,..., G3200 are electrically connected to the driver 25-BDU1 via the connection pads 17a, respectively, to the upper source driver 25-BDU2 for the second BD screen. Of the even-numbered signal lines 16b arranged on the BD screen, the lower lead signal lines 16b of G1601, R1602,..., B2400 are the lower source for the second BD screen arranged on the lower side of the liquid crystal panel 12. The lower lead signal lines 16b of G2401, R2402,..., B3200 are electrically connected to the driver 27-BDD1 via the connection pads 17b, respectively.
[0029]
The scanning line 18 is drawn to one end of the array substrate 14 and is electrically connected to the upper screen gate driver 28 and the lower screen gate driver 30 via the connection pad 19, and scanning is performed from these gate drivers 28, 30. A pulse Vg is supplied to each scanning line 18.
[0030]
With such a configuration of the liquid crystal panel 12, each of the connection pads 17a and 17b of each signal line 16 is disposed with at least the signal line 16 therebetween, so that the connection pads 17a and 17b are spaced apart from each other. Wide enough. This facilitates electrical connection of external circuits such as the upper source drivers 24 and 25 and the lower source drivers 26 and 27 even for higher definition.
[0031]
For example, if the signal lines 16 are all pulled out to the upper side, the connection pad positions corresponding to the even-numbered lines and the odd-numbered lines can be arranged in a staggered manner so that the connection to the external circuit can be easily made. In addition to dividing into even and odd groups, it may be divided into three or more groups, and the connection pads may be arranged in a multistage staggered pattern.
[0032]
[3] Circuit configuration of liquid crystal display device
As described above (see FIG. 1), the liquid crystal display device 10 includes the liquid crystal panel 12 and upper source drivers 24 and 25 as signal line driving circuits for supplying the analog image signal Vs to the signal line 16 of the liquid crystal panel 12. , Lower source drivers 26 and 27, an upper screen gate driver 28 and a lower screen gate driver 30 as scanning line driving circuits for supplying a scanning pulse Vg to each scanning line 18 of the liquid crystal panel 12, and these source drivers 24, 25, 26, 27, and a liquid crystal controller 34 for controlling the gate drivers 28, 30.
[0033]
The circuit configuration of the liquid crystal display device 10 will be described in more detail based on FIG.
[0034]
The processing device 32 corresponds to each of the A screen, the B screen, the C screen, and the D screen of the liquid crystal panel 12, and further, a horizontal pixel line for each color of red (R), blue (B), and green (G). 24 systems of digital image data corresponding to odd and even directions R: DATA-A (o), R: DATA-A (e),..., R: DATA-B (o), R: DATA- B (e), ..., R: DATA-C (o), R: DATA-C (e), ..., R: DATA-D (o), R: DATA-D (e), B: DATA-D (e) (see FIGS. 11 to 13) is output to the liquid crystal controller 34 in parallel.
[0035]
Each digital image data DATA is composed of 8 bits in this embodiment, so that the liquid crystal display device 10 can realize 256 gradation display.
[0036]
Here, data transfer between the processing device 32 and the liquid crystal display device 10 is performed in parallel by dividing the display screen into divided odd-numbered (o) and even-numbered (e) for each color. Data transfer at 60MHz is realized. As a result, an increase in the data transfer rate is suppressed, thereby making it possible to reduce the influence of reliable data transfer and EMI.
[0037]
Further, as shown in FIGS. 10 to 12, the processing device 32 transmits to the liquid crystal display device 10 the digital image data DATA together with the horizontal synchronizing signal HSYNC, the vertical synchronizing signal VSYNC, the data enable signal ENAB, and the system clock signal NCLK, respectively. To do.
[0038]
The I / F connector 36 constituting the liquid crystal controller 34 constitutes an AC screen among the 24 systems of digital image data R: DATA-A (o),..., B: DATA-D (e). 12 digital image data R: DATA-A (o), R: DATA-A (e),..., B: DATA-A (e), R: DATA-C (o), R : DATA-C (e),..., B: DATA-C (e) in the liquid crystal controller for AC screen 38, and other 12 systems of digital image data constituting the BD screen R: DATA-B (o) , R: DATA-B (e), ..., B: DATA-B (e), R: DATA-D (o), R: DATA-D (e), ..., B: DATA-D (E) is allocated to the liquid crystal controller 40 for the BD screen.
[0039]
Each of the liquid crystal controllers 38 and 40 is an IC chip having the same configuration configured to be able to control the source drivers 24, 25, 26, 27 and the gate drivers 28, 30.
[0040]
The AC screen liquid crystal controller 38 controls the AC screen first and second upper source drivers 24-ACU1, 24-ACU2 and the AC screen first and second lower source drivers 26-ACD1, 26-ACD2. At the same time, it is wired to control the gate driver 28 for the upper screen. The BD screen liquid crystal controller 40 controls the BD screen first and second upper source drivers 25-BDU1, 25-BDU2 and the BD screen first and second lower source drivers 27-BDD1, 27-BDD2. The lower screen gate driver 30 is wired.
[0041]
The liquid crystal controller 38 for AC screen uses a vertical start signal STV-U and a vertical clock signal CPV-U based on a horizontal synchronization signal HSYNC, a vertical synchronization signal VSYNC, a data enable signal ENAB, and a system clock signal NCLK input from the processing device 32. A control signal such as a gate output enable signal OE-U is generated and transmitted to the upper screen gate driver 28. Similarly, the BD screen liquid crystal controller 40 also transmits a vertical start signal STV-D, a vertical clock signal CPV-D, and a gate output enable signal OE-D to the lower screen gate driver 30.
[0042]
Further, the AC screen liquid crystal controller 38 is supplied with 12 systems of digital image data R: DATA-A (o), R: DATA-A (e),..., B: DATA-A (e), R: DATA-C (o), R: DATA-C (e),..., B: DATA-C (e) are rearranged and timing controlled, and the rearranged 12 systems of digital images Data R: UDATA-A1C1, G: UDATA-A1C1, B: UDATA-A1C1, R: DDATA-A1C1, G: DDATA-A1C1, B: DDATA-A1C1, R: UDATA-A2C2, G: UDATA-A2C2, B : UDATA-A2C2, R: DDATA-A2C2, G: DDATA-A2C2, B: DDATA-A2C2 as horizontal clock signal CPH, horizontal The first and second upper sides via a low voltage differential signal transmission circuit 42, a low voltage differential signal reception circuit 44, and a serial / parallel controller (hereinafter referred to as "S / P controller") 46 together with the start signal HSTART. The signals are output in parallel to the source drivers 24-ACU1, 24-ACU2 and the first and second lower source drivers 26-ACD1, 26-ACD2, respectively.
[0043]
The BD screen liquid crystal controller 40 also performs substantially the same processing, and a description thereof will be omitted.
[0044]
In FIG. 3, a range surrounded by a dotted line indicates a wiring board used in the liquid crystal display device 10 and shows that each circuit is mounted on the wiring board indicated by the dotted line. Yes.
[0045]
[4] Configuration of AC screen circuit
FIG. 4 shows a block diagram of an AC screen circuit among the circuits of the liquid crystal display device 10 shown in FIG. 3, and will be described in more detail. A similar circuit is also configured for the BD screen circuit, and the description thereof is omitted here.
[0046]
As shown in FIG. 4, the AC screen liquid crystal controller 38 constituting the liquid crystal controller 34 of the liquid crystal display device 10 corresponds to the A screen and the C screen from the processing device 32, as described above. And 12 systems of digital image data for each color corresponding to the even number R: DATA-A (o), R: DATA-A (e),..., B: DATA-C (o), and B: DATA- C (e) is input in parallel.
[0047]
The AC screen liquid crystal controller 38 includes an upper screen line memory 48 and a lower screen line memory 50 corresponding to red (R), blue (B), and green (G), respectively. Are connected to one selector circuit 52.
[0048]
Timing control and data rearrangement are achieved by writing to and reading from the line memories 48 and 50 and setting the output destination by the selector circuit 52.
[0049]
[5] Driving method of liquid crystal display device
Hereinafter, it will be described in more detail with reference to the drawings.
[0050]
FIG. 12 shows the data input / output timing of the liquid crystal controller 34. The system clock signal NCLK, the horizontal synchronization signal HSYNC, the data enable signal ENAB, and the digital image data R: DATA-A (input from the processing device 32 from above are shown. o), R: DATA-A (e),..., R: DATA-C (o), R: DATA-C (e),... The output clock data CLK, the horizontal start signal HSTART, and the output image data UDATA-A1C1, DDATA-A1C1, UDATA-A2C2, and UDATA-A2C2 output from the liquid crystal controller for AC screen 38 are shown. 13 and 14 are enlarged views of the output image data UDATA-A1C1 and DDATA-A1C1.
[0051]
[5-1]
The 8-bit digital image data DATA input in parallel from the processing device 32 to the liquid crystal display device 10 is distributed to the AC screen liquid crystal controller 38 and the BD screen liquid crystal controller 40 by the I / F connector 36, respectively. . As described above, the digital image data DATA distributed in parallel to the AC screen liquid crystal controller 38 is for each color of red (R), blue (B), and green (G), and for the A screen and the C screen. In total, 12 systems of 8-bit digital image data R: DATA-A (o), R: DATA-A (e),..., B: DATA-A (e), R: DATA-C (o) , R: DATA-C (e),..., B: DATA-C (e), and the operation of the AC screen liquid crystal controller 38 will be described below as an example.
[0052]
[5-2]
Digital image data for A screen corresponding to the horizontal pixel line L1 distributed in parallel to the liquid crystal controller for AC screen 38: R: DATA-A (o), R: DATA-A (e), G: DATA-A (o ), G: DATA-A (e), B: DATA-A (o), B: DATA-A (e) are stored in the line memory 48 and the digital image data for C screen R: DATA corresponding to the horizontal pixel line L2400. -C (o), R: DATA-C (e), G: DATA-C (o), G: DATA-C (e), B: DATA-C (o), B: DATA-C (e) Are sequentially stored in the line memory 50 based on the system clock signal NCLK.
[0053]
[5-3]
In this way, the digital image data DATA corresponding to the horizontal pixel lines L1 and L2400 stored in the line memories 48 and 50 is sequentially read out based on the clock signal CLK having the same frequency as the system clock signal NCLK, and the selector circuit. At 52, the image data is rearranged.
[0054]
Specifically, the digital image data for the A screen corresponding to the horizontal pixel line L1 R: DATA-A (o), G: DATA-A (o), B: DATA-A (o) R1 to R799, R: When R2 to R800 of DATA-A (e), G: DATA-A (e), and B: DATA-A (e) are stored in the line memory 48, sequential reading is started based on the clock signal CLK. Then, the selector circuit 52 rearranges the image data.
[0055]
For example, the AC screen first upper source driver 24-ACU1 includes three parallel image data UDATA-A1C1 rearranged as shown in FIG. 13, and the AC screen first lower source driver 24-ACU1 includes The three parallel input image data UDATA-A1C1 rearranged as shown in FIG. 14 are respectively output.
[0056]
Also, digital image data for the C screen corresponding to the horizontal pixel line L2400 R: DATA-C (o), G: DATA-C (o), B: DATA-C (o) R1 to R799, R: DATA -C (e), G: DATA-C (e), and B: DATA-C (e) are stored in the line memory 50 as shown in FIG. 12, and output of image data corresponding to the A screen is performed. After completion, sequential reading is started based on the clock signal CLK, and the selector circuit 52 rearranges the image data.
[0057]
[5-4]
The first and second upper source drivers 24-ACU1, 24-ACU2, 25-BDU1, 25-BDU2 and the first and second lower source drivers 26-ACD1, 26-ACD2, 27-BDD1, 27-BDD2 Each is a 2-port input.
[0058]
For this reason, the S / P controller 46 performs control to extend the time axis of the 12 systems of digital image data rearranged by the selector circuit 52 of the AC screen liquid crystal controller 38 and guide it to each driver by two lines in parallel.
[0059]
Then, the converted image data is converted into the AC screen first and second upper source drivers 24-ACU1, 24-ACU2 and the AC screen first and second lower by using the data inversion transmission method described later in [6]. Side source drivers 24-ACD1 and 24-ACD2 are transmitted.
[0060]
[5-5]
The AC screen first and second upper side source drivers 24-ACU1 and 24-ACU2 and the AC screen first and second lower side source drivers 24-ACD1 and 24-ACD2 are respectively input from the S / P controller 46. The A screen image data UDATA-A1C1, DDATA-A1C1, UDATA-A2C2, and DDATA-A2C2 corresponding to the pixel line L1 are serial-parallel converted. The A-screen image data UDATA-A1C1, DDATA-A1C1, UDATA-A2C2, and DDATA-A2C2 corresponding to the series-parallel converted horizontal pixel line L1 are converted from digital to analog, and a 1/2 horizontal scanning period ( The desired analog image signal Vs is output to the corresponding signal line 16 over H / 2).
[0061]
Subsequently, the C screen image data UDATA-A1C1, DDATA-A1C1, UDATA-A2C2, and DDATA-A2C2 corresponding to the input horizontal pixel line L2400 are serially parallel-converted, and further converted into digital / analog. A desired analog image signal Vs is output to the corresponding signal line 16 over two horizontal scanning periods (H / 2).
[0062]
In this manner, writing to two horizontal pixel lines (L1, L2400) is performed in one horizontal scanning period (1H).
[0063]
[5-6]
In the next horizontal scanning period, digital image data for C screen R: DATA-C (o), R: DATA-C (e) corresponding to the horizontal pixel line L2399 distributed in parallel to the AC screen liquid crystal controller 38, G: DATA-C (o), G: DATA-C (e), B: DATA-C (o), B: DATA-C (e) are stored in the line memory 48 and the A screen corresponding to the horizontal pixel line L2. Digital image data R: DATA-A (o), R: DATA-A (e), G: DATA-A (o), G: DATA-A (e), B: DATA-A (o), B : DATA-A (e) is sequentially stored in the line memory 50 based on the system clock signal NCLK.
[0064]
[5-7]
The digital image data DATA corresponding to the horizontal pixel lines L2399 and L2 stored in the line memories 48 and 50 in this way is sequentially read based on the clock signal CLK having the same frequency as the system clock signal NCLK, and the selector circuit. At 52, the image data is rearranged.
[0065]
Specifically, digital image data for C screen corresponding to the horizontal pixel line L2399 R: DATA-C (o), G: DATA-C (o), B: DATA-C (o) R1 to R799, R: When R2 to R800 of DATA-C (e), G: DATA-C (e), and B: DATA-C (e) are stored in the line memory 48, sequential reading is started based on the clock signal CLK. Then, the selector circuit 52 rearranges the image data.
[0066]
Also, digital image data for A screen corresponding to the horizontal pixel line L2: R: DATA-A (o), G: DATA-A (o), B: DATA-A (o) R1 to R799, R: DATA -A (e), G: DATA-A (e), and B: DATA-A (e) are stored in the line memory 50 as shown in FIG. 12, and output of image data corresponding to the C screen is performed. After completion, sequential reading is started based on the clock signal CLK, and the selector circuit 52 rearranges the image data.
[0067]
[5-8]
The AC screen first and second upper source drivers 24-ACU1 and 24-ACU2 and the AC screen first and second lower source drivers 24-ACD1 and 24-ACD2 respectively correspond to the input horizontal pixel line L2399. Screen image data UDATA-A1C1, DDATA-A1C1, UDATA-A2C2, and DDATA-A2C2 are serial / parallel converted, and then converted to digital / analog, corresponding signal lines for 1/2 horizontal scanning period (H / 2) 16 outputs a desired analog image signal Vs.
[0068]
Subsequently, the A screen image data UDATA-A1C1, DDATA-A1C1, UDATA-A2C2, and DDATA-A2C2 corresponding to the input horizontal pixel line L2 are serially parallel-converted, and further converted to digital / analog. A desired analog image signal Vs is output to the corresponding signal line 16 over two horizontal scanning periods (H / 2).
[0069]
In this way, writing to two horizontal pixel lines (L2399, L2) is performed in one horizontal scanning period (1H).
[0070]
Thereafter, this operation is sequentially repeated.
[0071]
[6] Data inversion transmission method
Next, a method for transmitting image data from the S / P controller 46 to the AC screen first and second upper source drivers 24 and the AC screen first and second lower source drivers 24 (that is, in the present embodiment). Data inversion transmission method) will be described with reference to FIGS.
[0072]
In order to simplify the description, the source drivers are collectively referred to as the source driver 24.
[0073]
Each of the source drivers 24 is of a two-port input type capable of simultaneously capturing image data for two horizontal pixel lines, and each input port has an input terminal for a data inversion signal in addition to the data input. .
[0074]
[6-1] Conventional data inversion transmission method
First, a conventional data inversion transmission method will be described with reference to FIGS. 17 and 18, and the problems will be clarified.
[0075]
FIG. 17 is a block diagram for realizing a conventional data inversion transmission method. The S / P controller 46 is provided with a first inversion circuit 50 and a second inversion circuit 52. The image data input to the first data inversion circuit 50 and the second data inversion circuit 52 assumes, for example, that all 24 bits change in the order of 0, 1, 0, and 1.
[0076]
In this conventional method, the first data inversion circuit 50 and the second data inversion circuit 52 start operation in different states each time depending on the state of the image data (1 or 0) when the power is turned on. The output signals to the first port and the second port take four patterns (a) to (d) in FIG.
[0077]
FIG. 18A shows the case 1 where both data inverting circuits 50 and 52 are initialized to the same state when the power is turned on. In this case 1, since all the bits of the data input to the data inverting circuits 50 and 52 are changed every time, the data output to the first port and the second port holds all the bits 0. As it is, only the data inversion signal is output in the order of 0, 1, 0, and 1.
[0078]
FIG. 18B shows Case 2 in which both data inverting circuits 50 and 52 are initialized to the opposite state when the power is turned on. In case 2, the data output to the first port repeats 0, 1, 0 and 1 only for the data inversion signal while retaining all bits 0. On the other hand, the data output to the second port repeats 1, 0, 1, 0 only for the data inversion signal while keeping all the bits 1.
[0079]
FIG. 18C shows the case 3 where both data inverting circuits 50 and 52 are initialized to the opposite state when the power is turned on. In the case 3, in contrast to the case 2, the data output to the first port repeats 0, 1, 0 and 1 only for the data inversion signal while keeping all the bits 1. On the contrary, only the data inversion signal repeats 1, 0, 1, 0 while the data output to the second port holds all the bits 0.
[0080]
FIG. 18D shows the case 4 where both data inverting circuits 50 and 52 are initialized to the same state when the power is turned on. In this case 4, contrary to case 1, the data input to the data inversion circuits 50 and 52 has all the bits changed every time, so that the data output to the first port and the second port are all While bit 1 is held, only the data inversion signal repeats 0, 1, 0 and 1.
[0081]
In Case 1 and Case 4, since the first data inversion circuit 50 and the second data inversion circuit 52 operate in the same phase, relatively large switching noise is generated in the power supply line. On the other hand, in case 2 and case 3, since the first data inversion circuit 50 and the second data inversion circuit 52 operate in opposite phases, the flow of electrification is canceled in the IC on the transmission side, and the power line The switching noise generated in the case is much smaller than in cases 1 and 4.
[0082]
However, as described above, the state of cases 1 to 4 when the power is turned on depends on the state of the image data, and it is completely unknown whether the switching noise is large or extremely small. There is a problem.
[0083]
Therefore, the present embodiment was invented to remedy this problem.
[0084]
[6-2] Data inversion transmission method of this embodiment
The data inversion transmission method of the present embodiment will be described with reference to FIGS.
[0085]
FIG. 19 is a block diagram showing the relationship between the S / P controller 46 and the source driver 24 of this embodiment.
[0086]
Also in this embodiment, the S / P controller 46 is provided with a first data inversion circuit 54 and a second data inversion circuit 56. The source driver 24 is a 2-port input type capable of simultaneously capturing image data for 2 pixels (2 × RGB), and each port has an input terminal for a data inversion signal in addition to data input. Yes.
[0087]
In addition to the input of 24-bit (8 bits × RGB) image data, the first data inversion circuit 54 and the second data inversion circuit 56 receive the first control signal, the second control signal, and the vertical synchronization signal VSYNC. It has a structure.
[0088]
In the data inversion transmission method of the present embodiment, a control signal is input to periodically initialize each data inversion signal, and the output state (inversion / non-inversion) of each data inversion circuit 54, 56 is determined by this control signal. It is something to control.
[0089]
As described above, in the conventional data inversion transmission method, the states of case 2 and case 3 cannot always be realized. In this embodiment, the states of case 2 and case 3 are controlled by control signals. However, it is intended to keep switching noise low.
[0090]
FIG. 20 shows the data inversion signal of this embodiment.
[0091]
In the present embodiment, a data setting period is provided in the vertical blanking period that is not the display period of the liquid crystal panel 12, and the first port data (24 bits) and the first data inversion signal are all set to zero. The second port data (24 bits) and the second data inversion signal are all set to 1 so that their outputs are reversed. Although there is a difference in non-inverted / inverted display formats, the data of both ports express the same data. Note that both the first data inversion circuit 54 and the second data inversion circuit 56 determine the vertical blanking period based on the vertical synchronization signal VSYNC.
[0092]
When the vertical blanking period shifts to the display period, image data in which all bits change to 0, 1, 0, 1 are input to the data inversion circuits 54 and 56 in both the first port and the second port. In response to this input, the output of the first port repeats 0, 1, 0 and 1 only for the first data inversion signal while all the image data is fixed to 0.
On the other hand, the second port repeats 1, 0, 1, 0 only for the second data inversion signal while the image data is fixed at all bits 1.
[0093]
As described above, when the data inverting circuits 54 and 56 operate in opposite phases, switching noise is hardly generated in the power supply line. Therefore, the EMI level can be reduced.
[0094]
In the above description, the relationship between the S / P controller 46 and one source driver 24 is shown. However, in all of the upper source drivers 24 and 25 and the lower source drivers 26 and 27 used in the liquid crystal display device 10. The data inversion transmission method of the present embodiment is applied. This state is shown in the schematic diagram of FIG.
[0095]
In this figure, the polarity of the upper source driver is set to the opposite polarity to 1010, and the other source drivers 25, 26 and 27 are similarly set to the opposite polarity.
[0096]
As a result, the generation of switching noise can be suppressed low in the S / P controller 46 that controls the source drivers 24 to 27, and EMI can be reduced.
[0097]
[6-3] Modification example
In the above description, the vertical blanking period is provided as the data setting period, but a horizontal blanking period may be used instead. In this case, the horizontal synchronization signal HSYNC is input to the data inversion circuits 54 and 56, and based on this, the horizontal blanking period is determined.
[0098]
Further, a data setting period may be provided in the display period instead of the blanking period.
[0099]
Further, when the liquid crystal display device 10 according to the present embodiment is turned on, the liquid crystal panel 12 has a predetermined time until each circuit becomes stable regardless of the image signal input to the liquid crystal display device 10. A black image signal is output so as to perform black display. Therefore, the power-on initial period during the black display may be the data setting period described above.
[0100]
Even if the power-on initial period is not set as the data setting period in this way, a data setting period is provided in the vertical blanking period or the horizontal blanking period immediately before displaying a normal image after the end of the power-on initial period. Only the EMI level can be reduced.
[0101]
[7] Writing method
Next, a method for writing the analog image signal Vs to each pixel electrode in this embodiment will be described with reference to FIG.
[0102]
As described above, in this embodiment, the effective display area is divided into upper and lower parts (AB screen and CD screen), and driving is performed to write in the horizontal pixel lines of each area within each horizontal scanning period (1H). Yes.
[0103]
For this reason, it is necessary to consider driving so that the upper and lower division boundaries are not visually recognized.
[0104]
In addition, when a direct current component is applied to the liquid crystal for a long time, the liquid crystal deteriorates. Therefore, it is necessary to invert the voltage applied to the liquid crystal every predetermined period.
[0105]
For this reason, for example, the method of inverting the polarity of the voltage applied to the pixel electrode for each field (F) with respect to the reference voltage, the method of inverting the polarity for each horizontal pixel line (H line inversion driving), and A method of inverting the polarity for each display pixel (HV inversion driving) or the like is known, and HV inversion driving is effective for reducing flicker.
[0106]
Therefore, it is conceivable to adopt HV inversion driving also in this embodiment. However, for the convenience of controlling the alternately arranged upper lead signal lines 16a and lower lead signal lines 16b by different source drivers, FIG. As shown in FIG. 7, H2V inversion driving (every horizontal pixel line and every two vertical pixel lines) is employed.
[0107]
In this embodiment, the analog image signal Vs is inverted in polarity for each horizontal pixel line. However, by reducing the polarity inversion period of the analog image signal Vs itself, sufficient writing time can be ensured and power consumption can be reduced. The technique to do is adopted.
[0108]
That is, the analog image signal Vs including signals for the upper screen (AB screen) and the lower screen (CD screen) is output to each signal line 16 within one horizontal scanning period (H), and each horizontal scanning period (H ) Is written in the corresponding horizontal pixel line in the first half and the second half, and the polarity inversion period is the horizontal scanning period (H).
[0109]
More specifically, as shown in FIG. 6, the positive analog image signal Vs is applied to the pixel electrode connected to the signal line R1 of the horizontal pixel line L1 in the first half of one horizontal scanning period (H) and the positive polarity in the second half. The analog image signal Vs is written into the pixel electrode connected to the signal line R1 of the horizontal pixel line L2400. In the first half of the next horizontal scanning period (H), the negative analog image signal Vs is applied to the pixel electrode connected to the signal line R1 of the horizontal pixel line L2399, and the negative analog image signal Vs is applied to the horizontal pixel line L2 signal in the second half. Write to the pixel electrode connected to the line R1.
[0110]
Although the polarity is inverted for each horizontal pixel line by such an operation, the inversion cycle can be set as the horizontal scanning period.
[0111]
[8] Write state
By the way, in the above drive, there are four types of states as shown in FIG.
[0112]
First, these four types of states will be described.
[0113]
[8-1] Positive pre-writing state (P1)
A state in which the analog image signal Vs supplied in the first half of the analog image signal Vs on the positive polarity side with respect to the reference voltage is written to the pixel electrode in the period of K1 based on the corresponding scanning pulse Vg.
[0114]
[8-2] Positive polarity post-writing state (P2)
A state in which the analog image signal Vs supplied in the latter half of the analog image signal Vs on the positive polarity side with respect to the reference voltage is written to the pixel electrode in the period K2 based on the corresponding scanning pulse Vg.
[0115]
[8-3] Negative polarity pre-written state (N1)
A state in which the analog image signal Vs supplied in the first half of the negative analog image signal Vs with respect to the reference voltage is written to the pixel electrode during the period K3 based on the corresponding scanning pulse Vg.
[0116]
[8-4] Negative-polarity post-writing state (N2)
A state in which the analog image signal Vs supplied in the latter half of the analog image signal Vs on the negative polarity side with respect to the reference voltage is written into the pixel electrode during the period K4 based on the corresponding scanning pulse Vg.
[0117]
These four states cause display defects because the writing states are different. Specifically, even when the same image display is performed, writing in the positive pre-writing state (P1) is disadvantageous compared to the positive post-writing state (P2). Similarly, writing in the negative polarity pre-writing state (N1) is disadvantageous compared to the negative polarity post-writing state (N2). This is particularly noticeable under severe conditions for writing, for example, low temperature conditions.
[0118]
Also, for example, the polarity difference between the positive polarity pre-writing state (P1) and the negative polarity pre-writing state (N1), or the positive polarity post-writing state (P2) and the negative polarity post-writing state (N2). Therefore, it is impossible to realize completely the same display quality.
[0119]
As described above, in the liquid crystal display device 10 of this embodiment, when it is driven, the boundary between the upper and lower divisions is prevented from being visually recognized, and further, generation of flicker and display unevenness is suppressed, and good display quality is ensured. desired.
[0120]
[9] Scanning method
Therefore, in this embodiment, operations as shown in FIGS. 6 and 7 are performed. FIG. 6 shows an n field screen, and FIG. 7 shows an n + 1 field screen.
[0121]
In the scanning method, the upper screen (AB screen) scans from top to bottom, that is, sequentially scans from the horizontal pixel line L1 to the horizontal pixel line L1200, and the lower screen (CD screen) scans from bottom to top, that is, Scanning is sequentially performed in the reverse direction from the horizontal pixel line L2400 to the horizontal pixel line L1201.
[0122]
In the writing method to the pixel electrode, taking the signal line R1 as an example, in the nth field, the corresponding pixel electrode of the horizontal pixel line L1 in the first half of one horizontal scanning period (H) is set to the positive pre-writing state (P1). In the latter half, the corresponding pixel electrode of the horizontal pixel line L2400 is set in the post-positive writing state (P2). In the first half of the next horizontal scanning period, the corresponding pixel electrode of the horizontal pixel line L2399 is set to the negative polarity pre-writing state (N1), and in the latter half, the corresponding pixel electrode of the horizontal pixel line L2 is set to the negative polarity post-writing state (N2). ). Thereafter, the process is repeated sequentially. In the (n + 1) th field, the pixel electrode corresponding to the horizontal pixel line L1 is set to the negative polarity pre-writing state (N1) in the first half of one horizontal scanning period, and the pixel electrode corresponding to the horizontal pixel line L2400 is set to the negative polarity after the latter half. The writing state (N2) is assumed. In the first half of the next horizontal scanning period, the corresponding pixel electrode of the horizontal pixel line L2399 is set to the positive pre-writing state (P1), and the corresponding pixel electrode of the horizontal pixel line L2 is set to the positive post-writing state (P2) in the second half. And Thereafter, the process is repeated sequentially.
[0123]
By controlling such a scanning method and the polarity of the analog image signal Vs, the problems pointed out above can be solved.
[0124]
That is, the upper screen (AB screen) is scanned from the top to the bottom, and the lower screen (CD screen) is scanned from the bottom to the top, so that the writing timing to the horizontal pixel lines L1200 and L1201 in the vicinity of the division boundary is timed. As a result, the decrease in pixel potential during the holding period is substantially equal between adjacent horizontal pixel lines, so that the boundary is prevented from being visually recognized. As another method for reducing the visibility of the division boundary, for example, the upper screen (AB screen) is scanned from the bottom to the top, and the lower screen (CD screen) is scanned from the top to the bottom. It becomes possible to make the writing timing to the horizontal pixel lines L1200 and L1201 near the boundary close in time.
[0125]
In addition, since the four states related to writing are distributed between the upper screen (AB screen) and the lower screen (CD screen), the display state may be different between the upper screen (AB screen) and the lower screen (CD screen). Is prevented.
[0126]
The above-described polarity control of the analog image signal Vs is based on the polarity inversion signal POL transmitted from the respective liquid crystal controllers 38, 40 to the respective source drivers 24, 25, 26, 27. The image data input based on the inversion signal POL is digital-analog converted into a positive or negative analog image signal Vs.
[0127]
[10] Modification 1
The above-described embodiment shows an optimal example of the present invention. However, instead of the scanning shown in FIGS. 6 and 7, for example, scanning may be performed as shown in FIGS.
[0128]
[11] Modification 2
Further, the scanning method shown in FIGS. 15 and 16 may be employed. 6 and 7, the pre-written state (P1, N1) and the post-written state (P2, N2) are fixed. However, in the scanning method shown in FIGS. The embedded state (P1, N1) and the post-write state (P2, N2) are not fixed in each horizontal pixel line. Thereby, the occurrence of display unevenness in a specific display pattern such as a horizontal stripe screen is effectively reduced.
[0129]
[12] Modification 3
In addition to the above, it is also possible to sequentially scan the lower screen (CD screen) after sequentially scanning the upper screen (AB screen).
[0130]
[13] Modification 4
In the above embodiment, the four screens A, B, C, and D are realized. However, the present embodiment is not limited to this, and the present embodiment can be applied to six or eight divisions in which three or more vertically divided screens are arranged. It becomes possible. Also, the present embodiment can be applied to an upper and lower divided screen.
[0131]
[14] Modification 5
In this embodiment, the present invention is realized in a liquid crystal display device, but can be suitably used in other flat display devices such as an organic EL display device instead.
[0132]
[15] Modification 6
By the way, referring to FIG. 5, there are four states of writing, and writing in the positive pre-writing state (P1) is disadvantageous as compared with the positive post-writing state (P2), and similarly in the negative polarity It has been described that the pre-sexual writing state (N1) is disadvantageous compared to the negative post-writing state (N2).
[0133]
Therefore, in addition to the method of distributing each state to the respective screen areas as described above, the disadvantageous state is reduced, for example, the positive polarity pre-writing state (P1) and / or the negative polarity pre-writing state (N1). The amplitude of the scan pulse may be larger than that in the positive polarity post-writing state (P2) and / or the negative polarity post-writing state (N2), or the width of the scan pulse may be increased. You may use together.
[0134]
Further, prior to the positive polarity pre-writing state (P1) and / or the negative polarity pre-writing state (N1), the preliminary scanning may be performed to alleviate the writing.
[0135]
【Effect of the invention】
As described above, in the flat display device of the present invention, when the data inversion transmission method is used, the data inversion signal is controlled so that the polarities of the image data output by the two lines are inverted at a predetermined timing. , Switching noise can be prevented and EMI can be reduced.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram of a liquid crystal display device according to an embodiment of the present invention.
FIG. 2 is a diagram showing a division state of an effective display area.
FIG. 3 is a block diagram illustrating a circuit configuration of a liquid crystal display device.
FIG. 4 is a block diagram for an AC screen.
FIG. 5 is a waveform diagram of an analog image signal and a scanning pulse indicating a writing state to a pixel electrode.
FIG. 6 is a diagram illustrating a write state of an n-th field according to the present embodiment.
FIG. 7 is a diagram showing a write state of an (n + 1) th field.
FIG. 8 is a diagram illustrating a write state of an n-th field in a first modification.
FIG. 9 is a drawing of a screen showing a writing state of an (n + 1) th field in Modification Example 1;
FIG. 10 is a timing diagram of the data interface at the horizontal timing.
FIG. 11 is a timing diagram of the data interface at the vertical timing.
FIG. 12 is a data input / output timing chart of the liquid crystal controller.
FIG. 13 is an enlarged view of an upper screen data output period.
FIG. 14 is an enlarged view of a lower screen data output period.
FIG. 15 is a diagram illustrating a write state of an n-th field in modification example 2;
FIG. 16 is a drawing showing a screen showing a writing state of an (n + 1) -th field in modification example 2;
FIG. 17 is a block diagram of an S / P controller and a source driver using a conventional data inversion transmission method.
FIG. 18 is a diagram illustrating a state of a signal using a conventional data inversion transmission method.
FIG. 19 is a block diagram of an S / P controller and a source driver using the data inversion transmission method of the present embodiment.
FIG. 20 is a diagram of data transmission in the data inversion transmission method of the present embodiment.
FIG. 21 is a conceptual diagram showing a polarity state of a data inversion transmission method in the liquid crystal display device of the present embodiment.
[Explanation of symbols]
10 Liquid crystal display device
12 LCD panel
14 Array substrate
16 signal lines
18 scan lines
20 TFT
22 Pixel electrode
24 Upper source driver for AC screen
25 BD screen upper source driver
26 Lower source driver for AC screen
27 Lower source driver for BD screen
28 Gate driver for upper screen
30 Gate driver for lower screen
34 LCD controller
46 S / P controller
51 First data inversion circuit
56 Second data inversion circuit

Claims (6)

An array substrate including a plurality of signal lines and scanning lines arranged orthogonal to each other, and a pixel electrode arranged via a switch element in the vicinity of an intersection of the signal lines and the scanning lines;
A signal line driving circuit connected to the signal line and supplying an image signal;
A scanning line driving circuit that is connected to the scanning line and supplies a gate signal for writing the image signal to the pixel electrode by turning on the switching element;
A circuit for outputting at least two m-bit image data in parallel to the signal line driving circuit, wherein each bit of the (n + 1) -th image data changes more than a majority with respect to each bit of the n-th image data. In this case, the (n + 1) -th image data is logically inverted and output, and a data inversion signal indicating that the (n + 1) -th image data is inverted data is output, and the n-th image data When each bit of the (n + 1) th image data does not change by more than a majority with respect to each bit of (n + 1), the (n + 1) th image data is output without being logically inverted, and the (n + 1) th image data is A control circuit that outputs a data inversion signal indicating non-inverted data;
In a flat display device having
The control circuit includes:
Setting in the non-display period so that the output of the first image data and the bit of the data inversion signal output in parallel with the output of the second image data and the bit of the data inversion signal are opposite to each other. Characteristic flat display device. The flat display device according to claim 1, wherein the control circuit is incorporated in one chip. A control circuit for outputting image data from the first wiring in the two parallels is incorporated in the first chip, and a control circuit for outputting image data from the second wiring in the two parallels is incorporated in the second chip. The flat display device according to claim 1, wherein the first chip and the second chip are arranged close to each other. The non-display period, flat panel display device according to claim 1, characterized in that the horizontal blanking period. The non-display period, flat panel display device according to claim 1, characterized in that the vertical blanking period. The signal line drive circuit has a 2-port input, and the control circuit performs control to extend the time axis of image data and guide the image data to each port of the signal line drive circuit in parallel for 2 lines. 1. A flat display device according to 1.

Images