JP4862221B2 - N-type silicon single crystal wafer and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an n-type silicon single crystal wafer (substrate) for a semiconductor device obtained by pulling up a silicon single crystal by the Czochralski method (CZ method) and processing the silicon single crystal into a wafer, a manufacturing method thereof and the n The present invention relates to an epitaxial wafer using a silicon single crystal wafer.
[0002]
[Related technologies]
As a wafer for producing a device such as a semiconductor integrated circuit, a silicon single crystal wafer grown mainly by the CZ method is used. This silicon single crystal wafer has p-type and n-type electrical resistivity classifications according to electronic devices such as IC and LSI.
[0003]
Therefore, in order to obtain a p-type wafer, a Group 3 element such as boron, aluminum, or gallium is added as an electrical impurity to control the resistivity. In the case of n-type, group 5 elements such as phosphorus, antimony and arsenic are appropriately added to control the resistivity.
[0004]
In particular, recently, an electrical device is often manufactured by using a low resistivity wafer having a resistivity of 20 mΩcm or less as a substrate and depositing an epitaxial silicon layer of the same conductivity type thereon. For example, a high concentration boron is added, a p-type wafer having a resistivity of 20 mΩcm or less is used as a substrate (p ⁺ substrate), and a p ⁻ layer added with boron so as to obtain a resistivity of about 10 Ωcm as an epitaxial layer on the substrate is formed. One example is a p / p ⁺ epi epitaxial wafer having a deposited structure. These are ideal silicon wafers in view of the characteristics of electronic devices, which are convenient for manufacturing devices with structurally efficient operation.
[0005]
Similarly, there are n / n ⁺ wafers with addition of Group 5 element impurities, but this is not as simple as p / p ⁺ . This is because even if phosphorus and antimony among group 5 element impurities are added to the molten silicon crucible used in the CZ method, they cannot be added at such a high concentration that they sublime in the pulling process and a low resistivity wafer is obtained. Since arsenic can be added at a high concentration, it is often used to obtain an n / n ⁺ structure.
[0006]
On the other hand, an important characteristic of silicon wafers is gettering characteristics. Gettering is a general term for methods for removing heavy metal impurities that cause device characteristics to deteriorate outside the device operating area. For example, if the surface of a silicon wafer is several tens of micrometers as the device operating area, the wafer is deeper than that area. The impurity metal may be captured at the position, that is, in the bulk.
[0007]
One of the most frequently used methods is the IG method (internal gettering) using oxygen precipitates. In this method, supersaturated oxygen atoms inevitably contained in a silicon wafer produced by the CZ method are formed as precipitates at a wafer position deeper than the device operating region, and impurities are trapped in the lattice distortion created around the oxygen atoms. It is a method to do. At that time, it is necessary to control the density, size, and formation position of the oxygen precipitates by various methods.
[0008]
Regarding the formation control of this oxygen precipitate, the relationship with the Group 3 element or Group 5 element added to control the electrical resistivity has been clarified. In the case of boron, which is a typical group 3 element-added impurity, it is well known that oxygen precipitation is promoted when it is added up to the p ⁺ resistivity region. Therefore, when oxygen precipitates are used for the IG, even if the crystals have a low initial oxygen concentration, the oxygen precipitates can be formed efficiently, so that the gettering ability is enhanced, which is very advantageous.
[0009]
However, in the case of an impurity-added wafer for controlling the resistivity of Group 5 elements, it is known that oxygen precipitation is suppressed. In particular, arsenic added to obtain an n ⁺ wafer significantly suppresses oxygen precipitation, so that even when a high oxygen concentration wafer such as 20 ppma [(JEIDA: Japan Electronics Industry Promotion Association) standard] is used, oxygen precipitates are formed. It can be extremely difficult to expect a gettering effect due to.
[0010]
[Problems to be solved by the invention]
The present invention has been made in view of such a problem, and an n-type silicon single crystal wafer capable of providing gettering capability due to oxygen precipitates even in an n / n ⁺ wafer, a manufacturing method thereof, and the An object is to provide an epitaxial wafer using an n-type silicon single crystal wafer.
[0011]
[Means for Solving the Problems]
To solve the above problems, an n-type silicon single crystal wafer of the present invention is a n-type silicon single crystal wafer obtained by processing a silicon single crystal rod which is pulled by the Czochralski method on the wafer, 5 It contains two or more electrically active impurities of group elements and group 3 elements, and the impurity concentration of at least group 3 elements is 1 × 10 ¹⁸ cm ⁻³ or more.
[0012]
The method for producing an n-type silicon single crystal wafer according to the present invention is a method for producing an n-type silicon single crystal wafer obtained by processing a silicon single crystal rod pulled up by the Czochralski method into a wafer. In the production, two or more electrically active impurities of group 5 element and group 3 element are mixed, and the impurity concentration of at least group 3 element is 1 × 10 ¹⁸ cm ⁻³ or more.
[0013]
The epitaxial wafer of the present invention is obtained by using the above-described n-type silicon single crystal wafer as a substrate and forming a silicon epitaxial layer thereon.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below, but it goes without saying that various modifications other than the embodiments are possible without departing from the technical idea of the present invention.
[0015]
In the present invention, when a silicon single crystal is produced by the Czochralski method, two or more kinds of impurities for controlling electrical resistivity of group 5 elements and group 3 elements are added simultaneously. In this case, the resistivity of the silicon single crystal Can be controlled by the absolute concentration and mixing ratio of the two or more added impurities.
[0016]
When adding these elements, for example, when it is desired to obtain an n-type silicon wafer, the electrical resistivity control of the Group 3 element is not limited by the simultaneous addition of the Group 3 element and the Group 5 element compared to the group 5 element impurity added alone. Impurities have been added. For this reason, the oxygen precipitation behavior for providing a gettering effect in the subsequent process is hardly suppressed by the presence of the Group 3 element impurity. Therefore, an n / n ⁺ epitaxial wafer having a high gettering capability can be produced.
[0017]
At this time, if the wafer has an impurity concentration of at least a group 3 element of 1 × 10 ¹⁸ cm ⁻³ or more, oxygen precipitation is promoted, so that oxygen precipitates can be efficiently formed regardless of whether the wafer is p-type or n-type. Therefore, gettering ability can be enhanced.
[0018]
When the impurity concentration of the group 3 element does not reach 1 × 10 ¹⁸ cm ⁻³ , the formation of oxygen precipitates is not sufficient, and the object of the present invention cannot be achieved. If the impurity concentration of this group 3 element is 1 × 10 ¹⁸ cm ⁻³ or more, there is no particular upper limit to the limit solid solubility, but about 2 × 10 ¹⁹ cm ⁻³ is sufficient.
[0019]
【Example】
Examples of the present invention will be specifically described below with reference to comparative examples. However, these examples are shown by way of illustration, and it goes without saying that the present invention is not construed as being limited thereto. Nor.
[0020]
Example 1
A crystal rod having a diameter of 6 inches, an initial oxygen concentration of 15 ppma (JEIDA), and an orientation <100> was pulled at a normal pulling rate (1.2 mm / min) by the CZ method. At that time, in the crystal which is pulled up so as to contain 10 ¹⁸ atoms / cm ^{3 of} boron and 7 × 10 ¹⁷ atoms / cm ^{3 of} arsenic, the conductivity type is controlled to be n-type and the resistivity is 0.01 Ωcm. It was. This crystal rod was processed into a substrate wafer, and n-type, 10 Ωcm n ⁻ -layer epitaxial growth was performed on the surface. In this epitaxial growth, trichlorosilane was used as a source gas, and the film was grown at 1130 ° C. by 3 μm.
[0021]
The epitaxial wafer was subjected to oxygen precipitation heat treatment at 800 ° C., 4 hr + 1000 ° C., and 16 hr in a nitrogen atmosphere, and then the oxygen precipitate density was measured by selective etching.
[0022]
The oxygen precipitate density is measured by angle polishing, and the technique described in JP-A-9-260449 is applied to the surface (a method in which copper is deposited on the surface and then etched with an alkaline aqueous solution and observed with an optical microscope). It went by.
[0023]
As a result of the measurement, an oxygen precipitate density of 10 ⁹ cm ⁻³ was detected in the wafer to which boron and arsenic were added simultaneously.
[0024]
From this result, in the silicon single crystal wafer according to the present invention, it is possible to produce a wafer having the same resistivity and excellent gettering ability. In particular, it has been found that the simultaneous addition of the Group 3 element and the Group 5 element exerts an effect in the case of the n-type in which oxygen precipitates are difficult to form.
[0025]
(Comparative Example 1)
An epitaxial wafer was produced in the same manner as in Example 1 except that a wafer having the same resistivity by addition of arsenic alone, that is, a 0.01 Ωcm wafer, and its oxygen precipitation density was measured. As a result of the measurement, the arsenic single-added wafer had an oxygen precipitate density of 10 ⁶ cm ⁻³ or less, which was the lower limit of detection, and the oxygen precipitation characteristics were significantly different from the wafer of Example 1.
[0026]
(Example 2)
After producing a silicon wafer (electrically conductive n ⁻ type, 10 Ωcm) under the same conditions as in Example 1 except that boron to be doped is 1 × 10 ¹⁸ atoms / cm ³ and arsenic is 3 × 10 ¹⁷ atoms / cm ^3. The epitaxial growth and oxygen precipitate density were measured under the same conditions as in Example 1.
[0027]
As a result, an oxygen precipitate density of 1 × 10 ¹⁸ cm ⁻³ was detected in the wafer to which boron and arsenic were added simultaneously.
[0028]
(Comparative Example 2)
An epitaxial wafer was manufactured in the same manner as in Example 2 except that the wafer had the same resistivity (10 Ωcm) by adding arsenic alone, and the oxygen precipitation density was measured. As a result, the oxygen precipitate density of the arsenic-added wafer was 1 × 10 ⁶ cm ⁻³ or less.
[0029]
( Experimental example 1 )
A silicon wafer (electrically conductive p-type, 10 Ωcm) was prepared under the same conditions as in Example 1 except that boron to be doped was 2 × 10 ¹⁸ atoms / cm ³ and arsenic was 6 × 10 ¹⁷ atoms / cm ³ . Epitaxial growth and oxygen precipitate density were measured under the same conditions as in Example 1.
[0030]
As a result, an oxygen precipitate density of 5 × 10 ¹⁸ cm ⁻³ was detected in the wafer to which boron and arsenic were added simultaneously.
[0031]
(Comparative Example 3)
An epitaxial wafer was produced in the same manner as in Example 3 except that the wafer had the same resistivity (10 Ωcm) by adding boron alone, and the oxygen precipitate density was measured. As a result, the oxygen precipitate density of the single boron-added wafer was 1 × 10 ⁷ cm ⁻³ .
[0032]
In addition, this invention is not limited to the said embodiment and Example. The above-described embodiments and examples are merely examples, and the ones having substantially the same configuration as the technical idea described in the claims of the present invention and exhibiting the same function and effect are any. Even within the technical scope of the present invention.
[0033]
For example, in the present invention, when adding impurities of Group 3 element and Group 5 element, the range of resistivity is not limited, and even if a p-type silicon wafer is manufactured, or n / n ⁻ Even if a wafer is produced, it is within the scope of the present invention.
[0034]
【Effect of the invention】
As described above, according to the present invention, it is possible to obtain an n-type silicon single crystal wafer capable of providing a gettering capability by oxygen precipitates even in an n / n ⁺ wafer, which has been conventionally difficult.

Claims (3)

An n-type silicon single crystal wafer obtained by processing a silicon single crystal rod pulled up by the Czochralski method into a wafer, containing two or more electrically active impurities of group 5 element and group 3 element, Among them, an n-type silicon single crystal wafer, wherein an impurity concentration of at least a group 3 element is 1 × 10 ¹⁸ cm ⁻³ or more. A method for manufacturing an n-type silicon single crystal wafer obtained by processing a silicon single crystal rod pulled up by the Czochralski method into a wafer, and in the manufacture of the single crystal, the electrical properties of the Group 5 and Group 3 elements A method for producing an n-type silicon single crystal wafer, comprising mixing two or more active impurities, wherein an impurity concentration of at least a group 3 element is 1 × 10 ¹⁸ cm ⁻³ or more. An epitaxial wafer comprising the n-type silicon single crystal wafer according to claim 1 as a substrate, and an epitaxial layer formed on the surface thereof.