JP2011054654A - Method of manufacturing silicon wafer for thinned device element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a silicon wafer for a thinned device element as well as an advantageous method of manufacturing the same. <P>SOLUTION: The method of manufacturing the silicon wafer includes: a lifting stage of lifting a single crystal by a CZ method such that a carbon compound growth layer has a carbon concentration of 0.5×10<SP>16</SP>to 10×10<SP>16</SP>atoms/cm<SP>3</SP>and an oxygen concentration of 1.0×10<SP>18</SP>to 1.0×10<SP>19</SP>atoms/cm<SP>3</SP>; a wafer processing stage of slicing the lifted single crystal into silicon wafers; a 600-800°C, 0.25-3-hour pre-annealing stage of forming a composite of carbon and oxygen and forming a gettering sink; an epitaxial stage of forming a silicon epitaxial layer on a silicon wafer surface after a deposition and heat treatment stage; and a device process heat treatment stage of carrying out a heat treatment at a maximum reaching temperature of ≤900°C for ≤30 seconds. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a silicon wafer for a thinned device element, and improves the gettering ability of a silicon wafer used for manufacturing a device element that needs to be thinned, such as an MCP memory element, and also improves the device yield. It is related with a technique suitable when making it.

With the development of mobile phone equipment and digital still camera technology, the thinning of semiconductor device packages built into equipment is increasing. In order to reduce the thickness of the semiconductor device package, it is essential to reduce the thickness of the device chip.
In particular, in a device that needs to be thinned, in particular, a wafer used for manufacturing a memory for MCP (Multi Chip Package) such as NAND-FLASH or NOR-FLASH, the subsequent process of the semiconductor device process, In particular, it has a thinning process in which the back surface of the wafer is cut down to about 30 μm or less.

Such a semiconductor device is manufactured by forming a circuit or the like on a silicon wafer sliced from a silicon single crystal pulled by a CZ (Czochralski) method or the like. When heavy metal is mixed with impurities in the silicon wafer, the device characteristics are remarkably deteriorated.
Factors that cause impurities in the silicon wafer include metal contamination in the silicon wafer manufacturing process, and secondly, heavy metal contamination in the device manufacturing process.

The former uses heavy metal particles or chlorine-based gas from the epi furnace member when growing an epitaxial layer on a silicon single crystal wafer, so heavy metal particle contamination due to metal corrosion of the piping material can be considered. In recent years, metal contamination in the epitaxial process has been improved by efforts such as replacing the epi furnace member with a corrosive material, but it is difficult to completely avoid metal contamination in the epitaxial process.
Therefore, conventionally, a gettering layer is formed inside a silicon wafer or a wafer having a high gettering ability of heavy metals such as a high-concentration boron wafer is used to avoid metal contamination in the epitaxial process.

  In the latter case, there is a concern about heavy metal contamination of the silicon wafer in the ion implantation process, diffusion, oxidation heat treatment process, and thinning process in the device manufacturing process. In order to avoid heavy metal contamination in the vicinity of the device active layer, traditional gettering methods that form oxygen precipitates on silicon wafers, and exotic trickers that form gettering sites such as backside damage on the backside of silicon wafers. The ring method is used.

  Further, in the case of the gettering method formed by the above-described conventional method, for example, the intrinsic gettering method, it is necessary to form oxygen precipitates on the silicon wafer in advance, and thus a multi-step heat treatment process is required, so that the manufacturing cost is reduced. There is concern about the increase. Furthermore, since heat treatment for a long time at a high temperature is necessary, there is a concern about metal contamination of the silicon wafer. In the case of the exotic trick gettering method, backside damage or the like is formed on the back surface. However, in the wafer thinned to about 30 μm, the handling property becomes extremely worse and it is not practical, and during the device process. However, there is a disadvantage that particles are generated from the back surface to form a cause of device failure.

Patent Document 1 proposes a technique for performing IG processing, and Patent Document 2 remarkably depends on the maximum temperature reached in the CCD manufacturing process when a carbon ion implanted wafer is used as a solid-state imaging device wafer. It is described.
Patent Document 3 describes an example of the EG method in 0005 and a technique related to carbon ion implantation.
Patent Document 4 describes performing a hole injection process, and Patent Document 5 describes a wafer manufacturing technique capable of imparting gettering ability depending on pulling conditions without performing precipitation heat treatment.

JP-A-6-338507 JP 2002-353434 A JP 2006-313922 A International Publication No. 98/38675 Pamphlet JP 2006-073580 A

However, after the design rule of 90 nm and later, about 45 nm has become the standard, such a device that needs to be thinned, especially a memory for MCP (Multi Chip Package) that is considered to be NAND-FLASH or NOR-FLASH. In the wafer used for manufacturing, the thickness of the wafer is set to about 40 to 30 μm or less and about 10 to 7 μm or more at the end of the thinning process.
As mentioned above, heavy metal contamination on silicon wafers can have a significant adverse effect on the electrical characteristics of the device, so it has been a long time to control and suppress heavy metal impurity contamination in the steps after the thinning process. However, in the thinning step for thinning to about 30 μm or less and the subsequent steps, there is a problem that the reduction in device yield cannot be avoided by the conventional gettering method.
This is considered to be because, in the thinning process, if the back surface side is removed until the thickness dimension is about 30 μm, the layer containing oxygen precipitates that exhibited the gettering ability disappears.

  Furthermore, as described above, since the device has recently been thinned and the thickness is required to be about 30 μm or less, when the thickness of the device is reduced to this level, the conventional IG (intrinsic) as described above is particularly important. Among the gettering methods, in a wafer that imparts IG capability by injecting vacancies having a concentration peak immediately below the DZ layer to be close gettering by a vacancy injecting process as in Patent Document 4, vacancies are provided. Since the formation of the concentration peak is due to the outward diffusion of vacancies in the cooling stage at the end of the vacancy injection heat treatment, the position of this peak in the wafer depth direction is about 30 μm or more, and the thickness is reduced to about 30 μm or less. In the wafer, since most of the IG layer that exhibits the IG effect is removed in the thinning process, sufficient gettering capability is not exhibited and There has been a problem of forming a scan of the bad factors.

  In addition, as a conventional IG (intrinsic gettering) method, when a high-concentration boron wafer or the like can be used, even if sufficient gettering ability of heavy metal can be exhibited, the device design conditions In wafers that do not exhibit such sufficiently high gettering capability, such as wafers that use other dopants, or that have a dopant concentration setting that is set lower than the concentration that provides sufficient gettering capability, There was a problem that the failure factor could not be solved.

  Furthermore, in the past, precipitates exhibiting gettering ability have been deposited by a heat treatment in a previous process (device fabrication process) of a semiconductor device. However, recent device processes are performed in accordance with the narrowing of design rules. Since the process flexibility in the device process is narrowed after the temperature is lowered to about ℃ (500 to 800 ° C), sufficient gettering is possible, such as inability to perform heat treatment capable of sufficient precipitation in the device process. It has become difficult to exhibit performance.

  Thus, since it is difficult to use the gettering method used in the pre-process of the semiconductor device process in the post-process, if heavy metal contamination occurs in the post-process, the reliability of the device after molding (product) It has been a problem to have a significant adverse effect on sex test results.

In addition, in the case of a wafer that has been lifted without a precipitation heat treatment, that is, with a pulling condition set so as to impart IG capability to the wafer in an as-grown state such as doping with oxygen concentration Oi or carbon as a dopant, However, there is a problem that variation in the radial direction of the wafer cannot be suppressed.
This is due to the fact that the cooling temperature gradient is not constant in the radial direction when cooling a single crystal pulled up in a cylindrical shape, and the internal distribution state such as vacancies due to the temperature gradient is completely varied. However, this problem is expected to become more prominent when the diameter of the wafer becomes larger than 300 mm and becomes 400 mm or 450 mm. In this way, there is a difference in the precipitate concentration for each device region, that is, the gettering ability. However, as device miniaturization and device chip narrowing proceed, each of these devices There has been a problem that variation in the gettering ability in the chip region is not improved.

Furthermore, as silicon wafers, an intrinsic gettering method in which oxygen precipitation heat treatment is performed before epitaxial growth to form oxygen precipitates or an ion implantation method in which ions such as carbon ions are implanted into the silicon wafer are used. In both cases, there is a concern about heavy metal contamination during the manufacturing process of the silicon wafer, so it is necessary to suppress metal contamination in the silicon wafer manufacturing process.
Further, in Patent Document 2, when a high-temperature heat treatment is performed on a carbon-implanted wafer, crystal defects (crystal lattice distortion, etc.) formed by carbon implantation are alleviated, and the function as a gettering sink may be reduced. Is done. Therefore, it is expected that the gettering sink is formed naturally in the device process.

Since the gettering sink by carbon ion implantation has a limit of the gettering effect, for example, the device processing temperature after the epitaxial layer formation is devised as described above. This is a limitation in the device manufacturing process.
In addition, the fact that the gettering effect by the gettering sink by carbon ion implantation tends to decrease after the formation of the epitaxial layer is difficult to avoid the generation of particles in the device process described above. Enhancement of effects is also an important issue.

The present invention has been made in view of the above circumstances, and intends to achieve the following object.
1. To provide a wafer capable of maintaining the gettering ability in a wafer that is unprecedented in thickness reduction of 30 μm or less and about 10 μm or more.
2. In particular, it should be possible to provide gettering capability without affecting device process conditions. 3. Reduce manufacturing costs.
4). To reduce variation in IG performance for each area corresponding to individual devices in the wafer plane.
5). To provide a thin silicon wafer in which heavy metal contamination generated in a post-process of a semiconductor device process is easily and surely removed from an active region of a device and the device has a good electrical property after molding, and a method for manufacturing the same.

Therefore, in the present invention, in order to avoid unnecessary heavy metal contamination on the silicon wafer, reliably avoid a reduction in device yield, and avoid an increase in manufacturing cost, the thickness is reduced to about 40 to 30 to 10 μm. As a wafer manufacturing method capable of maintaining the gettering ability even when the device element is manufactured, the dopant concentration at the time of pulling, the setting of the pulling conditions such as the pulling speed, the setting of the dopant concentration of the epitaxial film, and the like, In combination with the precipitation heat treatment before the epitaxial layer film-forming step and the processing conditions in the target device manufacturing step, it has sufficient gettering ability and can prevent a decrease in device yield. A method for producing a silicon wafer for a thinned device element has been found.
In particular, a silicon wafer of an MCP memory device in which a gettering layer is formed immediately below the MCP memory device and the capture efficiency of heavy metals is high, and a vacancy is implanted immediately above the CZ crystal doped with carbon and epi growth. The present invention relates to a method for manufacturing an MCP memory device, characterized in that a silicon epitaxial layer is formed, precipitates due to vacancies and carbon and oxygen are formed immediately below the epitaxial layer, and a gettering sink is formed.

The method for manufacturing a silicon wafer for a thinned device element according to the present invention removes the back surface after a device is formed on the surface through a device process heat treatment step in which the highest temperature is 900 ° C. or less and the heat treatment is 30 seconds or less. A method for producing a silicon wafer for a thinned device element in which a gettering layer is formed even when the wafer thickness dimension is thinned to 30 μm to 10 μm by a thinning step and the capture efficiency of heavy metals is high,
By the CZ method, the carbon concentration of the carbon compound growth layer is 0.5 × 10 ¹⁶ to 10 × 10 ¹⁶ atoms / cm ³ , and the oxygen concentration is 1.0 × 10 ^{18 to} 1.0 × 10 ¹⁹ atoms / cm ³ . A pulling process for pulling up the single crystal so that
A wafer processing step to slice the pulled single crystal into a silicon wafer;
A pre-annealing step of 600 to 800 ° C. for 0.25 to 3 hours to form a composite of carbon and oxygen to form a gettering sink;
An epitaxial step of forming a silicon epitaxial layer on the silicon wafer surface after the precipitation heat treatment step;
A device process heat treatment step in which the highest temperature is 900 ° C. or lower and the heat treatment is 30 seconds or shorter;
By solving this problem, the above-mentioned problems were solved.
Moreover, in this invention, it can raise as a hydrogen atmosphere in the said raising process.
In the present invention, the device process heat treatment step has a series of heat treatments of 700 ° C. for 30 seconds RTA, 600 ° C. for 3 minutes RTO, 700 ° C. for 45 seconds RTA, or this series of heat treatment and silicon wafer It is desirable that the contribution to the oxygen precipitation in the interior has equivalent heat treatment conditions.
Moreover, the silicon wafer for a thinned device element of the present invention is a silicon wafer produced by any one of the production methods described above,
A device region from the surface to be a device region to a depth direction of 3 to 4 μm (about 2 μm), and a region deeper than the device region, a BMD having a size of 10 to 100 nm has a density of 1.0 × 10 ^{06 to} 1.0 × In some cases, the gettering layer exists at 10 ⁰⁹ atoms / cm ³ .

The method for manufacturing a silicon wafer for a thinned device element according to the present invention removes the back surface after a device is formed on the surface through a device process heat treatment step in which the highest temperature is 900 ° C. or less and the heat treatment is 30 seconds or less. A method for producing a silicon wafer for a thinned device element in which a gettering layer is formed even when the wafer thickness dimension is thinned to 30 μm to 10 μm by a thinning step and the capture efficiency of heavy metals is high,
By CZ method, a single crystal is formed so that the carbon concentration is 0.5 × 10 ¹⁶ to 10 × 10 ¹⁶ atoms / cm ³ and the oxygen concentration is 1.0 × 10 ^{18 to} 1.0 × 10 ¹⁹ atoms / cm ^3. A lifting process to raise;
A wafer processing step to slice the pulled single crystal into a silicon wafer;
A pre-annealing step of 600 to 800 ° C. for 0.25 to 3 hours to form a composite of carbon and oxygen to form a gettering sink;
An epitaxial step of forming a silicon epitaxial layer on the silicon wafer surface after the precipitation heat treatment step;
Even when the wafer is thinned, by setting the dopant concentration by the pulling process, so-called precipitation nuclei that will later become oxygen precipitates are injected, and the injected precipitation nuclei are pre-annealed. Even if the backside is removed and thinned by the thinning process, the gettering ability is sufficient even if the epitaxial process and subsequent heat treatments cause precipitation and stabilization to a state that does not affect the gettering ability. It becomes possible to manufacture a wafer having As a result, by adding carbon to the CZ crystal, oxygen precipitates, that is, gettering sinks can be formed immediately below the epitaxial layer before the manufacturing process (heat treatment process) of the MCP memory device, thereby removing heavy metal contamination in the device process. Quality such as electrical characteristics can be improved.

The silicon wafer according to the present invention has a deposit nucleus (heavy metal gettering sink) by carbon addition and a silicon epitaxial layer formed directly thereon.
According to the present invention, by adding carbon to the CZ crystal, oxygen precipitates, that is, gettering sinks are formed immediately below the epitaxial layer before the manufacturing process (heat treatment process) of the MCP memory device, thereby causing heavy metal contamination in the device process. Since it can be removed, quality such as electrical characteristics can be improved.
Furthermore, sufficient gettering capability can be maintained even in a heat treatment step in which minute oxygen precipitates with high density and secondary dislocations are formed immediately below the epitaxial layer in the MCP memory device device process and the temperature is lowered.
Especially when the temperature range of the precipitation process heat treatment before epitaxial growth is 600 ° C. to 700 ° C., formation of high-density oxygen precipitates can be realized directly under the epitaxial layer and high gettering ability can be expected. When an MCP memory element is manufactured, electrical characteristics can be improved. As a result, the yield of the MCP memory device can be improved.

It is front sectional drawing which shows the silicon wafer in each process in one Embodiment of the manufacturing method of the silicon substrate which concerns on this invention. It is a figure which shows the manufacture procedure of a device element. It is a flowchart which shows the manufacture procedure of the silicon substrate which concerns on this invention. It is a longitudinal cross-sectional view of a CZ pulling furnace. It is a schematic diagram which shows the change of the pulling-up speed area | region by hydrogen addition. It is a figure explaining the heat processing in the Example of this invention. It is front sectional drawing which shows each process in the thinning process in one Embodiment of the manufacturing method of the silicon substrate which concerns on this invention. It is a schematic diagram which shows a device element. It is a figure which shows the gettering ability evaluation result based on the Example of this invention. It is a flow which shows the gettering ability evaluation method based on the Example of this invention.

  The present inventors diligently studied a means for avoiding heavy metal contamination on a silicon wafer thinned to about 30 μm or less without increasing the manufacturing cost.

First, in a silicon single crystal doped with B (boron), oxygen precipitates are more likely to aggregate due to heat treatment than other dopants. This is considered to be because the interaction between B (boron) and point defects (vacancies and interstitial silicon) is promoted to promote the formation of oxygen precipitation nuclei.
Further, it has been found that the aggregation of oxygen precipitates due to the heat treatment due to boron is remarkable in high oxygen concentration silicon crystals. However, this method cannot be used except for high-concentration boron wafers, but it is possible to stabilize oxygen precipitates uniformly in the radial direction and exhibit sufficient gettering ability by carbon doping and precipitation heat treatment in the pulling process. it can.

  Further, in the present invention, in the pulling step, it is easy to pull up the grown-in defect-free single crystal by pulling up as a hydrogen atmosphere, and by adding carbon, the influence of the OSF ring can be reduced. These synergistic effects can reduce defects caused by the OSF ring when an epitaxial layer is grown on the wafer.

Here, the device process heat treatment step targeted by the wafer of the present invention is a heat treatment with a maximum temperature of 900 ° C. or less and 30 seconds or less, but is intended to contribute to the equivalent precipitation. Specifically, the device process heat treatment step includes a series of heat treatments of 700 ° C. for 30 seconds RTA, 600 ° C. for 3 minutes RTO, 700 ° C. for 45 seconds RTA, or this series of heat treatments and silicon It is assumed that the contribution to oxygen precipitation inside the wafer has an equivalent heat treatment condition, and thus, a wafer having sufficient gettering capability even for device manufacturing that has only a device process with little contribution to oxygen precipitation. Can be provided.
Specifically, a heat treatment such as a two-step heat treatment of 600 ° C. × 4 hours + 900 ° C. × 1 hour can be mentioned.

Moreover, the silicon wafer for a thinned device element of the present invention is a silicon wafer produced by any one of the production methods described above,
A device region from the surface to be a device region to a depth direction of 3 to 4 μm (about 2 μm), and a region deeper than the device region, a BMD having a size of 10 to 100 nm has a density of 1.0 × 10 ^{06 to} 1.0 × Even if the wafer thickness is reduced to 30 μm by being a gettering layer existing at 10 ⁹ atoms / cm ³ , there is sufficient BMD immediately under the device region to exhibit high gettering capability. Therefore, the electrical characteristics of the device can be improved, and thereby the yield of the MCP memory device can be improved.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, an embodiment of a silicon wafer and a manufacturing method thereof according to the invention will be described with reference to the drawings.

  1 and 2 are front sectional views showing a silicon wafer in each step of the method for manufacturing a silicon wafer according to the present embodiment, and FIG. 3 is a flowchart showing the method for manufacturing the silicon wafer in the present embodiment. In the figure, the symbol W0 is a silicon wafer.

  In the example shown in FIG. 1, first, as shown in the silicon single crystal pulling step S1 in FIG. 3, polysilicon, which is a raw material of silicon crystal, is laminated in a quartz crucible, and further graphite powder is placed on the polysilicon surface. If p-type is applied in accordance with the wafer type set at the same time, B (boron) is introduced as a dopant, and carbon added CZ crystal is necessary, for example, according to the Czochralski method (CZ method). As described later, the hydrogen atmosphere is raised. The CZ crystal is a name of a crystal manufactured by the Czochralski method including a magnetic field applied CZ crystal.

  Here, as the silicon single crystal, carbon is added at the raw material stage, a silicon single crystal is produced from the carbon-added raw material, and the oxygen concentration Oi is controlled and raised. Hereinafter, the pulling of the carbon-added CZ silicon single crystal will be described. Although a wafer having a diameter of 300 mm will be described, the invention is not limited to this.

  FIG. 4 is a longitudinal sectional view of a CZ furnace suitable for explaining the production of a silicon single crystal in the present embodiment. The CZ furnace includes a crucible (quartz crucible) 101 disposed in the center of the chamber and a heater 102 disposed outside the crucible 101. The crucible 101 has a double structure in which a quartz crucible 101 containing a raw material melt 103 is held by an outer graphite crucible 101a, and is rotated and moved up and down by a support shaft 101b called a pedestal. A cylindrical heat shield 107 is provided above the crucible 101. The heat shield 107 has a structure in which an outer shell is made of graphite and graphite felt is filled therein. The inner surface of the heat shield 107 is a tapered surface whose inner diameter gradually decreases from the upper end to the lower end. The upper outer surface of the heat shield 107 is a tapered surface corresponding to the inner surface, and the lower outer surface is formed in a substantially straight (vertical) surface so as to gradually increase the thickness of the heat shield 107 downward.

In this CZ furnace, for example, a 300 mm single crystal can be grown with a target diameter of 310 mm and a body length of, for example, 1200 mm.
An example of the specification of the thermal shield 107 is as follows. The outer diameter of the portion entering the crucible is, for example, 570 mm, the minimum inner diameter S at the lowermost end is, for example, 370 mm, and the radial width (thickness) W is, for example, 100 mm. The outer diameter of the crucible 101 is 650 mm, for example, and the height H from the melt surface at the lower end of the heat shield 107 is 60 mm, for example.

Next, a method for setting operating conditions for growing a carbon-added CZ silicon single crystal will be described.
First, a high-purity silicon polycrystal is charged into a crucible, and, for example, less dopant boron (B) than a p-type wafer is added so that the resistivity in the crystal is p-type.
In the present invention, the boron (B) concentration is a concentration corresponding to a resistivity of 8 mΩcm to 10 mΩcm, and the p-type is a concentration corresponding to a resistivity of 0.1 to 100 Ωcm. This is a concentration corresponding to a resistivity of 0.1 Ωcm to 0.01 Ωcm. Alternatively, a phosphorus (P) concentration of n + type is a concentration corresponding to a resistivity of 8 mΩcm to 10 mΩcm, an n type is a concentration corresponding to a resistivity of 0.1 to 100 Ωcm, and an n− type is a resistivity. The concentration corresponds to 0.1 Ωcm to 0.01 Ωcm.
The p / p-type means a wafer in which a p-type epitaxial layer is laminated on a p-type wafer, and the p / n-type means a p-type epitaxial layer on the n-type wafer. Means a wafer laminated.

In the present embodiment, a dopant is added to the silicon melt so that the carbon concentration is in the range described above.
Further, the crystal rotation speed, the crucible rotation speed, the heating condition, the applied magnetic field condition, the pulling speed, and the like are controlled so as to achieve the above-described oxygen concentration.

  Then, the inside of the apparatus is inert gas atmosphere, the pressure is reduced to 1.33 to 26.7 kPa (10 to 200 torr), and hydrogen gas is mixed in the inert gas (Ar gas or the like) to 3 to 20% by volume. And let it flow into the furnace. The pressure is 1.33 kPa (10 torr) or more, preferably 4 to 26.7 kPa (30 to 200 torr), and more preferably 4 to 9.3 kPa (30 to 70 torr). As the lower limit of the pressure, since the hydrogen concentration in the melt and the crystal decreases as the partial pressure of hydrogen decreases, the lower limit pressure is defined to prevent this. The upper limit of the pressure is that the gas flow rate on the melt of an inert gas such as Ar decreases as the pressure in the furnace increases, so that the carbon degassed from the carbon heater or carbon member, or the SiO evaporated from the melt As a result, it becomes difficult to exhaust the reactant gas, etc., so that the carbon concentration in the crystal becomes higher than the desired value, and SiO aggregates in the upper part of the melt in the furnace at about 1100 ° C. or at a lower temperature, Since dust is generated and dropped into the melt to cause dislocation of crystals, the upper limit pressure is defined in order to prevent these.

  Next, the silicon is melted by heating with the heater 102 to obtain a melt 103. Next, the seed crystal attached to the seed chuck 105 is immersed in the melt 103, and the crystal is pulled up while rotating the crucible 1 and the pulling shaft 4. The crystal orientation is any one of {100}, {111} or {110}, and after performing the seed squeezing for crystal dislocation, the shoulder portion is formed and the shoulder is changed to a target body diameter of, for example, 310 mm. To do.

  After that, the body part is grown up to 1200 mm, for example, at a constant pulling speed, the diameter is reduced under normal conditions, tail tailing is performed, and then the crystal growth is finished. Here, the pulling speed is appropriately selected according to the resistivity, the silicon single crystal diameter size, the hot zone structure (thermal environment) of the single crystal pulling apparatus to be used, etc., for example, qualitatively within the single crystal plane In this case, the pulling rate including the region where the OSF ring is generated can be adopted, and the lower limit thereof can be set to be higher than the pulling rate at which the OSF ring region is generated in the single crystal plane and the dislocation cluster is not generated.

  Further, the hydrogen concentration in the inert atmosphere can be set in the range of 3% to 20% with respect to the furnace pressure of 4.0 to 9.33 kPa (30 to 70 torr). The furnace pressure is 1.33 kPa (10 torr) or more, preferably 4.0 to 26.7 kPa (30 torr to 200 torr), and more preferably 4.0 to 9.3 kPa (30 torr to 70 torr). The lower limit value is defined as the lower limit pressure described above in order to prevent the hydrogen concentration in the melt and crystal from being lowered when the partial pressure of hydrogen is lowered. The upper limit value is that when the pressure in the furnace increases, the gas flow rate on the melt of an inert gas such as Ar decreases, so that carbon degassed from the carbon heater or carbon member, SiO evaporated from the melt, etc. This makes it difficult for the reactant gas to be exhausted, so that the carbon concentration in the crystal becomes higher than the desired value, and the SiO agglomerates in the upper part of the melt in the furnace at about 1100 ° C. or at a lower temperature. Is generated and dropped into the melt to cause dislocation of the crystal. Therefore, in order to prevent these, the upper limit pressure is defined. The hydrogen partial pressure is preferably 40 pa or more and 400 Pa or less.

The hydrogen concentration in the silicon single crystal during growth in an inert atmosphere containing hydrogen can be controlled by the hydrogen partial pressure in the atmosphere. When hydrogen is introduced into the crystal, hydrogen in the atmosphere is dissolved in the silicon melt to be in a steady (equilibrium) state, and the concentration in the liquid phase and the solid phase is distributed to the crystal by concentration segregation during solidification.
The hydrogen concentration in the melt is determined by Henry's law depending on the hydrogen partial pressure in the gas phase, and the hydrogen concentration in the crystal immediately after solidification is constant in the axial direction of the crystal by controlling the hydrogen partial pressure in the atmosphere. The desired concentration can be controlled.

According to such a silicon single crystal growth method, by pulling up the silicon single crystal in an inert atmosphere containing hydrogen, the COP and dislocation clusters are not included in the entire crystal diameter direction, and the interstitial silicon dominant region (PI) The range of the PI region pulling speed capable of pulling up the single crystal in the region) can be increased and pulled to make the single crystal straight body portion an interstitial silicon dominant region (PI region) that does not include dislocation clusters. At the same time, according to such a silicon single crystal growth method, since the width of the OSF ring is reduced, conventionally, when a grown-in defect-free single crystal is pulled up, it is not set in a very narrow range. It is possible to grow a Grown-in defect-free single crystal extremely easily and at a higher pulling speed than before, and to generate an OSF ring region in the crystal plane. When the silicon single crystal is pulled up under such conditions, it is possible to reduce the influence by reducing the width of the OSF ring.
Here, the PI region pulling speed range is a state in which the value of the axial temperature gradient G in the crystal immediately after solidification described above is constant and does not change when comparing in a hydrogen atmosphere and in an inert atmosphere without hydrogen. Compare with

More specifically, by setting the PI region pulling speed range in which the grown-in defect-free single crystal consisting of the interstitial silicon-type grown-in defect-free region (PI region) can be pulled to be a hydrogen atmosphere, there is no hydrogen. As shown in FIG. 5, it can be pulled up to a margin of 4.5 times or more compared to the time, and the desired single crystal can be pulled up by the pulling speed in such a range. It becomes possible.
At this time, the generation area of the OSF ring can be reduced. Note that the size of the PV region (vacancy type Grown-in defect free region) is not changed by hydrogen addition.

  In this embodiment, by performing hydrogenation as described above, it is easy to pull up the grown-in defect-free single crystal, and by adding carbon, the influence of the OSF ring can be reduced. Due to these synergistic effects, defects caused by the OSF ring can be reduced when an epitaxial layer is grown on this wafer, the above-mentioned single crystal having the desired quality can be pulled up, and work efficiency can be improved. As a result, it is possible to greatly reduce the manufacturing cost of a silicon single crystal or a silicon wafer manufactured from this silicon single crystal.

  Next to the silicon single crystal pulling step S1 shown in FIG. 3, as shown in the wafer processing step S2 in FIG. 3, the carbon-added CZ silicon single crystal is processed, and as shown in FIG. A silicon wafer W0 is obtained.

  The processing method of the silicon wafer (wafer) W0 in the wafer processing step S2 is normally performed by slicing with a cutting device such as an ID saw or a wire saw, annealing the obtained silicon wafer, and then performing a surface treatment process such as polishing / cleaning. Do it. In addition to these processes, there are various processes such as lapping, cleaning, and grinding, and the processes are changed and used as appropriate according to the purpose, such as changing the order of processes or omitting them.

The silicon wafer 1 thus obtained has a p-type dopant concentration, a carbon concentration of 0.5 × 10 ^{16 to} 10.0 × 10 ¹⁶ atoms / cm ³ , and an oxygen concentration of 1.0 ×. 10 ^{18 to} 10.0 × 10 ¹⁸ atoms / cm ³ .

  Since carbon is contained in silicon in the form of a solid solution, carbon is introduced into the silicon lattice in the form of replacing silicon. That is, since the atomic radius of carbon is smaller than that of silicon atoms, when carbon is coordinated at the substitution position, the crystal stress field becomes a compressive stress field, and interstitial oxygen and impurities are easily trapped in the compressive stress field. Starting from this substitutional carbon, for example, in the device process, precipitates with oxygen accompanying dislocations are easily developed at high density, and a high gettering effect can be imparted to the silicon wafer W0. Thereby, it becomes possible to have sufficient gettering capability also in the device fabrication step S4 described later.

It is necessary to regulate the addition concentration of such carbon within the above range. This is because when the carbon concentration is less than the above range, the formation of carbon / oxygen-based precipitates is not actively promoted, so that the formation of the above-described high-density carbon / oxygen-based precipitates cannot be realized.
On the other hand, if the above range is exceeded, the formation of carbon / oxygen-based precipitates is promoted, and a high-density carbon / oxygen-based precipitate can be obtained. The tendency to become weaker becomes stronger. Therefore, the effect of trapping impurities is reduced because the effect of distortion is weak.

Furthermore, it is necessary to regulate the oxygen concentration Oi in the silicon wafer W0 within the above range. This is because when the oxygen concentration is less than the above range, the formation of carbon / oxygen-based precipitates is not promoted, and thus the above-described high-density precipitates cannot be obtained.
On the other hand, if the above range is exceeded, the size of the oxygen precipitate is reduced, the effect of strain at the interface between the base silicon atom and the precipitate is relaxed, and there is a concern that the gettering effect due to strain is reduced.

  As shown in the wafer processing step S2 in FIG. 3, the surface of the silicon wafer W0 that is a carbon-added CZ crystal is mirror-finished, and then, for example, RCA cleaning combining SC1 and SC2 is performed.

Next, as shown in the pre-annealing step S3 in FIG. 3, in order to secure a gettering sink for gettering heavy metal, further growth promotion can be expected by giving this condition after the growth of the epitaxial layer W0a. As a temperature condition, a low-temperature heat treatment is preferably performed in a mixed atmosphere of oxygen and an inert gas such as argon or nitrogen at about 600 to 850 ° C. for about 0.25 to 4 hours. It is necessary to deposit the oxygen-based oxygen precipitate W07.
In the present invention, the carbon / oxygen-based precipitate means a precipitate that is a composite (cluster) containing carbon.

Note that if the heat treatment for providing the IG effect in the pre-annealing step S3 is lower than the above temperature range, the formation of the carbon / oxygen complex is insufficient, and sufficient gettering ability cannot be exhibited when metal contamination of the wafer occurs. It is not preferable, and if it is higher than the above temperature range, oxygen precipitates are excessively aggregated, resulting in insufficient density of the gettering sink.
Also, in this heat treatment, the temperature rise and fall and the increase / decrease of the treatment time can be set to different conditions as long as the heat treatment temperature / time is equal to or higher than that at 600 ° C. for 30 minutes. In addition, as long as the heat treatment temperature / time is equal to or lower than that at 800 ° C. for 4 hours, the temperature can be increased and decreased and the treatment time can be increased and decreased.

  Thereafter, as shown in the epitaxial layer deposition step S4 in FIG. 3, the epitaxial layer is placed in an epitaxial growth furnace to grow an epitaxial layer, and various CVD methods (chemical vapor deposition methods) are used. As shown, for example, an epitaxial layer W0a having a dopant concentration of p type is grown.

  As shown in FIG. 1C, the p / p-type silicon wafer W1 on which the epitaxial layer W0a is formed has an oxide film W1b and a nitride film W1c formed on the epitaxial layer W0a as necessary. The silicon wafer W2 can be used for subsequent processes such as a device manufacturing process.

  Here, the silicon wafer W0 in the silicon wafer W1 or silicon wafer W2 used in the device manufacturing process is a CZ crystal containing boron and solute carbon, but oxygen precipitation nuclei formed during the crystal growth, or oxygen Since the precipitates are not shrunk by the heat treatment during the epitaxial growth in the pre-annealing step S3, the oxidized precipitates that are manifested on the silicon wafer W0 at the silicon wafer W1 stage are observed with an optical microscope.

  This oxygen precipitate W07 is naturally generated over the entire silicon wafer W0 in the process of passing through the initial stage of the device manufacturing process if the silicon wafer W1 containing solute carbon after the epitaxial layer forming step S4 is used as a starting material. Therefore, a gettering sink having a high gettering capability against metal contamination in the device manufacturing step S5 can be formed over the entire thickness of the silicon wafer W0 immediately below the epitaxial layer. Accordingly, gettering in the proximity region of the epitaxial layer is realized.

In order to realize this gettering, an oxygen precipitate (BMD) W07, which is a carbon / oxygen-based composite, is added to 1.0 × 10 ⁶ to 1.0 in the silicon wafer W0 after the epitaxial layer deposition step S4. It is preferable that it exists at x10 ¹¹ pieces / cm ³ and the size is 10 to 100 nm.
In addition, the BMD size in this case means the diagonal length of the precipitate in the TEM observation image of the cross section in the thickness direction of the silicon wafer, and is represented by the average value of the precipitate in the observation field.

The size of the oxygen precipitate W07 after the epitaxial layer film forming step S4 is set to the lower limit or more in the above range by using the effect of strain generated at the interface between the base silicon atom and the oxygen precipitate (for example, heavy metal) This is to increase the probability of capturing (gettering). Further, if the size of the oxygen precipitate W07 is not less than the above range, it is not preferable because the wafer strength is reduced or the influence of the occurrence of dislocations in the epitaxial layer occurs.
The density of the oxygen precipitates W07 in the silicon wafer is such that the capture (gettering) of heavy metals in the silicon crystal is the strain generated at the interface between the base silicon atom and the oxygen precipitates and the interface state density (volume density). In order to depend, it is preferable to set it as said range.

  In the device step S5 shown in FIG. 3, a device structure is formed on the surface of the silicon wafer W2, and the silicon wafer W3 is manufactured as shown in FIG.

Specifically, as shown in FIG. 2A, a silicon substrate W2 in which a p-type epitaxial layer (high-concentration impurity-containing layer) W0a is formed on a p-type silicon substrate W0 is prepared. As shown in FIG. 2B, a low-concentration impurity-containing layer W0d having an impurity concentration lower than that of the p type is formed on the epitaxial layer W0a.

  Next, as shown in FIG. 2C, an element active region W0e is formed near the surface of the substrate by impurity implantation or the like. In addition, a laminated structure such as an oxide film and a wiring layer is formed on the surface of the substrate, and a transistor and a capacitor (not shown) are formed. Next, a surface protective film (not shown) that covers the surface of the substrate on which the element active region W0e is formed is formed as a silicon substrate W3.

The heat treatment conditions in the device process S5 correspond to the conditions shown in FIG.
Specifically, with respect to the silicon wafer W0 before the epitaxial layer W0a is formed, the processing temperature, processing time, heating / cooling speed, and atmospheric conditions shown in FIG.
30 minutes at a holding temperature of 600 ° C., 3% O ₂ -containing N ₂ atmosphere heating rate 5 ° C./min,
Holding temperature 750 ° C. for 60 minutes, N ₂ atmosphere holding temperature 900 ° C. for 10 seconds, N ₂ atmosphere cooling rate 750 ° C. to 1 ° C./min, then 8 ° C./min, N ₂ atmosphere holding temperature 900 ° C. for 30 min, drying O ₂ atmosphere temperature drop rate 3 ° C./min, N ₂ atmosphere holding temperature 650 ° C. for 30 minutes, N ₂ atmosphere.

As shown in FIG. 3, an element active region (device region) W0e having a PN junction or the like is formed in the vicinity of the surface of the silicon substrate W3. The element active region W0e is formed to a depth of about 20 μm from the surface of the lower semiconductor chip W0. In the low-concentration impurity-containing layer W0d, an impurity diffusion region in which boron contained in the high-concentration impurity-containing layer W0a is diffused into the low-concentration impurity-containing layer W0d is formed at the boundary portion. The impurity diffusion region has a thickness of about several μm.
In this manner, the substrate W3 having a portion to be a logic element formed on the surface is manufactured.

  The silicon substrate W3 on which the logic element is formed is an upper semiconductor chip, which is, for example, a memory semiconductor device other than a DRAM, a CPU, a DSP (Digital Signal Processor), or the like. Alternatively, it may be a lower semiconductor chip, which is a memory semiconductor device such as a DRAM. These lower semiconductor chip and upper semiconductor chip together with an MCP (Multi Chip Package) substrate are connected by bonding wires to form a multi-chip package.

In the device manufacturing process, the thickness T5 is set to 40 μm or less.
The final process of the device process S5 includes a thinning process for removing the back surface of the wafer to about 30 μm.

In the thinning process, first, as a grinding process, the back surface W3a of the silicon substrate W3 having the thickness T3 shown in FIG. 7A is thinned by grinding to obtain a thickness shown in FIG. 7B. The substrate W4 is T4.
The conditions at this time are set as follows.
Thickness T3: 1000 to 500 μm, 800 to 600 μm, about 700 μm (700 μm)
Thickness T4: 60 μm (50-80 μm)

Further, in the thinning process, after the grinding process, a CMP process is performed with a hard slurry made of colloidal silica, silicon crystal, or diamond-like carbon and having a hardness of about 1 μm to 10 μm, so that the thickness T5 shown in FIG. The substrate W5.
The conditions at this time are set as follows.
Thickness T5: about 30 μm or less

The CMP processing conditions are set as follows.
Abrasive grains made of colloidal silica, silicon crystal or diamond-like carbon having a hardness of about 200 HV to 1000 HV and a grain size of about 10 to 100 nm are slurried with a slurry having a weight ratio of 1% to 5% wt. The treatment is performed for cm ^{2 to} 500 g / cm ² and for a treatment time of about 10 to 60 seconds.

After that, as a polishing process, processing is performed at a pressure of 100 g / cm ^{2 to} 500 g / cm ² and a processing time of about 10 to 60 seconds.

Further, as the device process S5, a general manufacturing process of a memory element can also be adopted. One example is shown, but it is not necessary to limit to this structure / process.
In the device step S5, a MOS-FET (metal oxide semiconductor junction transistor) having a floating gate is formed. Thereby, the silicon substrate W3 having the surface to be the memory element M is manufactured.

For example, it can be used as a wafer for Multi Chip Package (MCP) such as NAND-FLASH or NOR-FLASH. Also in this case, since the device structure is CMOS, the boron (B) concentration is equivalent to a resistivity of 8 mΩcm to 10 mΩcm, the carbon concentration is 1.0 × 10 ^{16 to} 1.6 × 10 ¹⁷ atoms / cm ³ , oxygen High gettering ability by IG and EG can be maintained when the concentration is in the range of 1.4 × 10 ^{18 to} 1.6 × 10 ¹⁸ atoms / cm ³ and the back surface residual stress is in the above range.

  A thinned device element that is resistant to heavy metals can be formed by manufacturing the silicon wafer W1 used for manufacturing the device 1 as described above.

FIG. 8 shows a device 1 as an MCP which is an example of a thinned device element using a wafer of the present invention.
As shown in FIG. 8, the device 1 has one or more memory array chips 10 stacked on a mounting substrate 4 in order from the bottom, and further on the topmost memory array chip 10. One control chip 20 is laminated. When there is one memory array chip 10, it seems that there is no advantage of dividing into the control chip 20 and the memory array chip 10, but the storage capacity can be adjusted by adjusting the number of stacked memory array chips 10. Therefore, the device 1 in which one control chip 20 and one memory array chip 10 are stacked can be provided for applications where a minimum storage capacity is sufficient.

  As shown in FIG. 8, the memory array chip 10 is provided with a plurality of first through electrodes T1 penetrating the chip, and the control chip 20 is provided with a plurality of second through electrodes T2 penetrating the chip. Yes. The plurality of first through electrodes T <b> 1 are provided at the same position in each of the plurality of memory array chips 10. In the present embodiment, the plurality of memory array chips 10 are all constituted by the same chip. The plurality of second through electrodes T2 are arranged so that the through electrodes corresponding to the plurality of first through electrodes T1 are aligned at the same position when the control chip 20 is stacked on the memory array chip 10. Yes. Accordingly, in the stacked state shown in the figure, the first through electrodes T1 of each layer of the four memory array chips 10 are electrically connected to each other with the corresponding through electrodes overlapping each other, and the uppermost memory array chip 10 The first through electrode T1 and the second through electrode T2 of the control chip 20 are electrically connected to each other with the corresponding through electrodes overlapping vertically. As a result, the second through electrode T2 of the control chip 20 is electrically connected to the corresponding first through electrode T1 of the memory array chip 10 of each layer.

  Further, the control chip 20 is provided with a plurality of external connection pads T-3 for electrical connection with the outside, and the external connection pads T-3 provided on the mounting substrate 4 are provided with the external connection pads T-3. Electrically connected to -5. For the electrical connection, wire bonding is used in the embodiment shown in FIG. 8, but the present invention is not limited to wire bonding.

  The first through electrode T1 and the second through electrode T2 are formed when an insulating film is formed on the inner wall of the through hole penetrating each chip, and then the through hole is filled with an electrode material and protrudes downward from the back surface and laminated. It is configured to be able to contact the upper surface of the corresponding through electrode of the chip located on the lower side. The first through electrode T1 and the second through electrode T2 are formed by a known method.

  Such a memory array chip 10 is diced from the thinned wafer of the present invention, and the thickness dimension thereof is 10 μm to 30 μm. If it is thicker than 30 μm, it is not preferable because the device 1 cannot be sufficiently miniaturized, and if it is thinner than 10 μm, it is not preferable because handling properties such as troubles in wafer transfer are deteriorated.

Example FIG. 9 is a graph showing the gettering ability evaluation results using a silicon wafer substrate sliced from a carbon-added CZ silicon single crystal in the present invention.
As shown in FIG. 10, the flow of the gettering capability evaluation experiment is based on the epitaxial wafer preparation step S01, forced metal contamination step S02, forced metal contamination measurement step S03, metal contamination diffusion heat treatment step S04, and gettering capability measurement step S05. It was.

In the epitaxial wafer preparation step S01, polysilicon, which is a raw material for silicon crystals, is laminated in a quartz crucible, an appropriate amount of graphite powder is applied on the surface of the polysilicon, boron is added, and the Czochralski method (CZ The carbon-added CZ silicon single crystal in which carbon was added and the oxygen concentration was controlled was prepared according to (Method). At this time, the above-described p-type boron concentration, carbon concentration is 0.5 × 10 ¹⁶ to 10 × 10 ¹⁶ atoms / cm ³ , and oxygen concentration is 1.0 × 10 ^{18 to} 1.0 × 10 ¹⁹ atoms / cm. ^{It was set to 3} .

  Next, as shown in FIG. 1B, the carbon-added boron CZ silicon single crystal was used as a silicon substrate W0.

After the surface is mirror-finished, RCA cleaning combining SC1 and SC2 is performed, and thereafter, the silicon epitaxial layer is charged into an epitaxial growth furnace, and a silicon epitaxial layer having a B concentration of p-type boron concentration is formed with a film thickness of 4. A thickness of 5 μm was formed by a CVD method. The CVD method was performed using SiHCl ₃ (trichlorosilane) and SiH ₄ (monosilane) as source gases.
Next, as a heat treatment for promoting the generation of oxygen precipitates in the present invention, a pre-annealing process treatment (low temperature heat treatment) is performed at 600 to 800 ° C. for 0.25 to 3 hours to form a composite of carbon and oxygen to form a gettering sink. I did it.

  For comparison, silicon epitaxial wafers having different conditions in terms of boron concentration, carbon concentration, presence / absence of DK treatment conditions, and the like were prepared.

In the forced metal contamination step S2, the wafer surface was forcibly contaminated with metal using Ni or Cu as a contamination source. Two types of contamination levels of about 1 × 10 ¹² atoms / cm ^{2 and} about 1 × 10 ¹³ atoms / cm ² were prepared for both Ni and Cu.

  In the forced metal contamination measurement step S03, contamination was measured by atomic absorption spectrometry.

In the metal contamination diffusion heat treatment step S04, heat treatment was performed in five steps as shown in FIG. 6 in consideration of an actual device process.
The processing temperature, processing time, temperature increasing / decreasing speed, and atmospheric conditions shown in FIG.
30 minutes at a holding temperature of 600 ° C., 3% O ₂ -containing N ₂ atmosphere heating rate 5 ° C./min,
Holding temperature 750 ° C. for 60 minutes, N ₂ atmosphere holding temperature 900 ° C. for 10 seconds, N ₂ atmosphere cooling rate 750 ° C. to 1 ° C./min, then 8 ° C./min, N ₂ atmosphere holding temperature 900 ° C. for 30 min, drying O ₂ atmosphere temperature drop rate 3 ° C./min, N ₂ atmosphere holding temperature 650 ° C. for 30 minutes, N ₂ atmosphere.

In the gettering ability measurement step S05, the surface contamination level of the wafer after the heat treatment in the step shown in FIG. 6 is measured by atomic absorption spectrometry in the same manner as in the forced metal contamination measurement step S03, and the surface contamination level is detected. was determined gettering capability on whether you are reduced to the limit (Ni in 1 × ¹⁰ 10 atoms / cm ² or half about ^{5 × 10 9 atoms / cm 2} , the ^{Cu 1 × 10 9 atoms / cm} 2) .

  As a result, the gettering ability was 50% for 25 wafers with epiwafer without carbon addition, and the contamination level was reduced to the above level. On the other hand, with carbon-added epiwafer, 80%, carbon-added epiwafer + low temperature In the heat treatment, gettering ability was confirmed with 100% of the wafers. And a pre-annealing step that performs low-temperature heat treatment that promotes the precipitation of the composite formed on the silicon wafer sliced from the carbonized CZ silicon single crystal that has been pulled up, thereby forming a sufficiently high getter by forming the composite with carbon, oxygen, etc. It can be seen that a silicon wafer having a ring ability and capable of reducing the influence of metal contamination can be provided, thereby achieving an effect that problems such as manufacturing costs and generation of particles in the device process can be solved.

W0, W3 ... Silicon wafer W0a ... Epitaxial layer

Claims (4)

After the device was formed on the front surface through a device process heat treatment step where the maximum temperature reached 900 ° C. or less and a heat treatment of 30 seconds or less, the thickness of the wafer was reduced to 30 μm to 10 μm by a thinning step of removing the back surface. In particular, a method for producing a silicon wafer for a thinned device element in which a gettering layer is formed and the capture efficiency of heavy metals is high,
By the CZ method, the carbon concentration of the carbon compound growth layer is 0.5 × 10 ¹⁶ to 10 × 10 ¹⁶ atoms / cm ³ , and the oxygen concentration is 1.0 × 10 ^{18 to} 1.0 × 10 ¹⁹ atoms / cm ³ . A pulling process for pulling up the single crystal so that
A wafer processing step to slice the pulled single crystal into a silicon wafer;
A pre-annealing step of 600 to 800 ° C. for 0.25 to 3 hours to form a composite of carbon and oxygen to form a gettering sink;
An epitaxial step of forming a silicon epitaxial layer on the silicon wafer surface after the precipitation heat treatment step;
A device process heat treatment step in which the highest temperature is 900 ° C. or lower and the heat treatment is 30 seconds or shorter;
A method for producing a silicon wafer for a thinned device element, comprising:   The method of manufacturing a silicon wafer for a thinned device element according to claim 1, wherein in the pulling step, a hydrogen atmosphere is pulled up.   The device process heat treatment step includes a series of heat treatments of 700 ° C. for 30 seconds RTA, 600 ° C. for 3 minutes RTO, 700 ° C. for 45 seconds RTA, or this series of heat treatments and oxygen precipitation inside the silicon wafer. 3. The method for producing a silicon wafer for a thinned device element according to claim 1, wherein the contribution has the same heat treatment condition. A silicon wafer manufactured by the manufacturing method according to claim 1,
A device region from the surface to be a device region to a depth direction of about 2 μm, and a region deeper than the device region, a BMD having a size of 10 to 100 nm has a density of 1.0 × 10 ^{06 to} 1.0 × 10 ⁹ atoms / cm ^{3. A} silicon wafer for a thinned device element, characterized in that the gettering layer exists in ³ .

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