JP4845986B2 - Semiconductor device - Google Patents

Description

The present invention relates to a chip size package type semiconductor device .

  In recent years, CSP (Chip Size Package) has attracted attention as a three-dimensional mounting technique and a new packaging technique. The CSP refers to a small package having an outer dimension substantially the same as the outer dimension of a semiconductor chip.

  Conventionally, a BGA type semiconductor device is known as a kind of CSP. In this BGA type semiconductor device, a plurality of ball-shaped conductive terminals made of a metal member such as solder are arranged in a lattice pattern on one main surface of a package, and electrically connected to a semiconductor chip mounted on the other surface of the package. Is connected to.

  When incorporating this BGA type semiconductor device into an electronic device, each conductive terminal is crimped to a wiring pattern on the printed circuit board, thereby electrically connecting the semiconductor chip and the external circuit mounted on the printed circuit board. Connected.

  Such a BGA type semiconductor device is provided with a larger number of conductive terminals than other CSP type semiconductor devices such as SOP (Small Outline Package) and QFP (Quad Flat Package) having lead pins protruding from the side. It has the advantage that it can be reduced in size. This BGA type semiconductor device has an application as an image sensor chip of a digital camera mounted on a mobile phone, for example.

  FIG. 13 shows a schematic configuration of a conventional BGA type semiconductor device, and FIG. 13A is a perspective view of the surface side of the BGA type semiconductor device. FIG. 13B is a perspective view of the back side of the BGA type semiconductor device.

  In this BGA type semiconductor device 101, a semiconductor chip 104 is sealed between first and second glass substrates 102 and 103 via epoxy resins 105a and 105b. A plurality of conductive terminals 106 are arranged in a grid pattern on one main surface of the second glass substrate 103, that is, on the back surface of the BGA type semiconductor device 101. The conductive terminal 106 is connected to the semiconductor chip 104 via the second wiring 110. Aluminum wires drawn from the inside of the semiconductor chip 104 are connected to the plurality of second wirings 110, respectively, and electrical connection between each conductive terminal 106 and the semiconductor chip 104 is made.

  A cross-sectional structure of the BGA type semiconductor device 101 will be described in more detail with reference to FIG. FIG. 14 shows a cross-sectional view of the BGA type semiconductor device 101 divided into individual chips along the dicing line.

  A first wiring 107 is provided on the insulating film 108 disposed on the surface of the semiconductor chip 104. The semiconductor chip 104 is bonded to the first glass substrate 102 by a resin layer 105a. Further, the back surface of the semiconductor chip 104 is bonded to the second glass substrate 103 by a resin layer 105b.

  One end of the first wiring 107 is connected to the second wiring 110. The second wiring 110 extends from one end of the first wiring 107 to the surface of the second glass substrate 103. A ball-like conductive terminal 106 is formed on the second wiring extending on the second glass substrate 103.

Japanese translation of PCT publication No. 2002-512436

  However, in the above-described BGA type semiconductor device 101, since the contact area between the first wiring 107 and the second wiring 110 is very small, there is a risk of disconnection at this contact portion. There was also a problem with the step coverage of the second wiring 110. Therefore, the present invention aims to improve reliability in a semiconductor device having a BGA and a method for manufacturing the same.

  Further, in the semiconductor device described above, since the glass substrates 102 and 103 are bonded to the semiconductor chip 104 via the epoxy resin, those having different thermal expansion coefficients are bonded to each other. Among them, there was a problem that the warp of the semiconductor wafer occurred and the workability deteriorated.

The semiconductor device of the present invention includes a pad electrode formed on a first main surface of a semiconductor chip, a support bonded to the first main surface of the semiconductor chip, and a second main surface of the semiconductor chip. A via hole penetrating from the surface of the pad electrode to the surface of the pad electrode, a sidewall insulating film made of a CVD film formed on a side wall of the via hole and a side edge of the semiconductor chip, and the pad electrode through the via hole. And a wiring layer.

The wiring layer is formed by a plating method or a sputtering method.

Furthermore, a protective layer formed to cover the wiring layer and a conductive terminal formed on the wiring layer are provided.

Further, the semiconductor chip has an etched surface at a side end portion of the semiconductor chip.

Furthermore, the semiconductor chip is characterized by having etched surfaces at the side edge and the back surface of the semiconductor chip.

The support is made of a glass substrate, a metal substrate, a substrate made of an organic material, or a tape.

  According to the present invention, since the wiring from the pad electrode of the semiconductor chip to the conductive terminal is formed through the via hole, disconnection of the wiring and deterioration of the step coverage can be prevented. Thereby, a highly reliable semiconductor device can be obtained.

  Further, according to the present invention, since the side wall insulating film is formed on the side end portion of the semiconductor chip after the semiconductor substrate to which the support is bonded is separated into the individual semiconductor chips, the moisture in the semiconductor chip is absorbed. Intrusion can be prevented as much as possible.

It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the semiconductor device which concerns on embodiment of this invention, and its manufacturing method. It is a top view explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is a figure explaining the conventional semiconductor device. It is a figure explaining the conventional semiconductor device.

  Next, the present embodiment will be described in detail with reference to the drawings. First, the structure of this semiconductor device will be described. FIG. 11 is a cross-sectional view of this semiconductor device, showing a semiconductor substrate that has undergone the steps described later, that is, a silicon wafer 51 divided into individual semiconductor chips along the dicing line center DS of the dicing line region DL.

  The silicon chip 51A, which is a semiconductor chip, is, for example, a CCD (Charge Coupled Device) image sensor chip, and a pad electrode 53 is formed on the surface of the first main surface via an interlayer insulating film 52 such as BPSG. ing. The pad electrode 53 is obtained by extending a pad electrode used for normal wire bonding to the dicing line region DL, and is also called an extended pad electrode.

  The pad electrode 53 is covered with a passivation film 54 such as a silicon nitride film. A glass substrate 56 is bonded to the surface of the silicon chip 51A on which the pad electrode 53 is formed via a resin layer 55 made of, for example, an epoxy resin. The glass substrate 56 is used as a protective substrate for protecting the silicon chip 51A and as a support substrate for supporting the silicon chip 51A.

  When the silicon chip 51A is a CCD image sensor chip, it is necessary to receive light from the outside with a CCD device on the surface of the silicon chip 51A, so a transparent substrate such as a glass substrate 56 or a translucent substrate is used. There is a need. When the silicon chip 51A does not receive or emit light, it may be an opaque substrate.

  A via hole 81 reaching the pad electrode 53 is formed from the back surface which is the second main surface of the silicon chip 51A. A sidewall insulating film 59A is formed on the sidewall of the via hole 81 and the side surface of the silicon chip 51A. The side wall insulating film 59A electrically insulates a wiring layer 63 described later and the silicon chip 51A.

  In addition, a buffer layer 60 is formed on the back surface of the silicon chip 51 </ b> A in a region adjacent to the via hole 81 via a first insulating film 57.

  A wiring layer 63 that is electrically connected to the pad electrode 53 through the via hole 81 and extends from the via hole 81 to the back surface and the side surface of the silicon chip 51A is formed. The wiring layer 63 is also called a rewiring layer, and has a structure in which a barrier layer 64 such as Ni / Au is laminated on copper (Cu), for example.

  A seed layer 61 is provided below the wiring layer 63. This is a metal layer that serves as a plating electrode used when the wiring layer 63 is formed by electrolytic plating. The wiring layer 63 extends on the back surface of the silicon chip 51 </ b> A so as to cover the buffer layer 60.

  The wiring layer 63 is covered with a solder mask 65 that is a protective layer, and the solder mask 65 has an opening K in a portion on the buffer layer 60. A solder ball 66 as a conductive terminal is mounted through the opening K of the solder mask 65. Thereby, the solder ball 66 and the wiring layer 63 are electrically connected. A BGA structure can be obtained by forming a plurality of such solder balls 66.

  Thus, wiring from the pad electrode 53 of the silicon chip 51A to the solder ball 66 formed on the back surface thereof is possible. Further, since the wiring is made through the via hole 81, disconnection hardly occurs and step coverage is excellent. Furthermore, the mechanical strength of the wiring is also high.

  Further, since the side surface of the silicon chip 51A is covered with the wiring layer 63 and the solder mask 65, it is possible to prevent moisture from entering the silicon chip 51A as much as possible.

  Since the solder ball 66 is disposed on the buffer layer 60, when the semiconductor device is mounted on the printed circuit board via the solder ball 66, the buffer layer 60 acts as a kind of cushion, The solder ball 66 and the semiconductor device which is the main body are prevented from being damaged and thus damaged.

  Further, the solder ball 66 is formed at a position higher than the back surface of the silicon chip 51A by the thickness of the buffer layer 60. This prevents the solder ball 66 and the silicon chip 51A from being damaged by the stress generated by the difference in thermal expansion coefficient between the printed board and the solder ball 66 when the semiconductor device is mounted on the printed board.

  The buffer layer 60 can be made of various materials such as organic insulators, inorganic insulators, metals, silicon, and photoresists. However, in order to function as a cushion, the organic insulators and inorganic insulators that are rich in elasticity are used. Goods, photoresists, etc. are suitable.

  Further, the silicon chip 51A may be a semiconductor chip of another material such as GaAs, Ge, Si—Ge.

  Next, a method for manufacturing the semiconductor device according to the above-described embodiment will be described. As shown in FIG. 1, it is assumed that a semiconductor integrated circuit (for example, a CCD image sensor) (not shown) is formed on the first main surface, that is, the surface of a silicon wafer 51 that is a semiconductor substrate. FIG. 1 shows a cross section of the boundary between adjacent chips (that is, in the vicinity of the dicing line region DL) to be divided in a dicing process described later.

  A pair of pad electrodes 53 is formed on the surface of the silicon wafer 51 via an interlayer insulating film 52 such as BPSG. The pair of pad electrodes 53 is made of a metal layer such as aluminum, an aluminum alloy, or copper, and has a thickness of about 1 μm. Further, the pair of pad electrodes 53 is extended to the dicing line region DL, and the extended end portion is disposed before the dicing line center DS of the dicing line region DL.

  Then, a passivation film 54 such as a silicon nitride film covering the pair of pad electrodes 53 is formed, and a resin layer 55 made of, for example, an epoxy resin is applied on the passivation film 54.

  Then, the glass substrate 56 is bonded to the surface of the silicon wafer 51 through the resin layer 55. The glass substrate 56 functions as a protective substrate or support substrate for the silicon wafer 51. Note that the support substrate is not limited to the glass substrate 56, and may be, for example, a metal substrate, a substrate made of an organic material, or a tape. Then, with the glass substrate 56 adhered, the back surface etching of the silicon wafer 51, so-called back grinding, is performed as necessary, and the thickness is processed to about 150 μm.

  Thereafter, the silicon wafer 51 is etched by about 20 μm using an acid (for example, a mixed solution of HF and nitric acid) as an etchant. This is effective in removing the mechanical damage layer of the silicon wafer 51 caused by the background and improving the characteristics of the device formed on the surface of the silicon wafer 51. In the present embodiment, the final thickness of the silicon wafer 51 is about 130 μm, but this can be appropriately selected according to the type of device.

Then, a first insulating film 57 is formed on the entire back surface of the silicon wafer 51 whose back surface has been cut by the above process. The first insulating film 57 is formed by, for example, a plasma CVD method, and a PE-SiO ₂ film or a PE-SiN film is suitable. Note that the formation of the first insulating film 57 may be omitted.

  Next, as shown in FIG. 2, a photoresist layer 58 is selectively formed on the first insulating film 57. Using the photoresist layer 58 as a mask, the first insulating film 57 and the silicon wafer 51 are etched. By this etching, a via hole 81 that penetrates the silicon wafer 51 is formed, and at the same time, a groove 82 that extends along the vicinity of the dicing line center DS in the dicing line region DL and penetrates the silicon wafer 51 is formed. The step of forming the first insulating film 57 may be omitted. In this case, the silicon wafer 51 is etched using the photoresist layer 58 formed directly on the silicon wafer 51 as a mask.

In order to form the via hole 81 and the groove 82, there are a wet etching method and a dry etching method. In this embodiment, dry etching is performed using an etching gas containing at least SF _6, O _2, C ₄ F _8, or the like. About the via hole 81, the cross-sectional shape may be processed into a forward tapered shape in order to improve the coverage of the seed layer 61 described later. Thus, the via hole 81 and the groove 82 formed along the dicing line have an etched surface.

  Here, the interlayer insulating film 52 is exposed at the bottom of the via hole 81, and the pad electrode 53 is in contact therewith. The width of the via hole 81 is about 40 μm and the length is about 200 μm. The interlayer insulating film 52 is also exposed at the bottom of the trench 82. The depth of the groove 82 is the same (or approximately the same) as the length of the via hole 81. That is, the silicon wafer 51 is divided into individual silicon chips by the grooves 82 while being bonded to the glass substrate 56. As a result, when heat treatment (for example, heat treatment in a sputtering process to be described later or heat treatment in solder reflow) is performed in a process described later, the silicon wafer 51 is separated into individual pieces. The expansion and contraction according to the thermal expansion coefficient of the silicon wafer 51 is divided, the expansion and contraction according to the thermal expansion coefficient is reduced, and the expansion and contraction according to the thermal expansion coefficient of the glass substrate 56 may be considered. The degree of warpage is reduced as much as possible compared to the prior art. Moreover, reliability is further improved by considering expansion and contraction in accordance with the thermal expansion coefficient of the epoxy resin used as the adhesive.

  The positional relationship among the via hole 81, the groove 82, and the dicing line region DL formed in the silicon wafer 51 is as shown in FIG. 12, which is a plan view when viewed from the back surface of the silicon wafer 51. The pad electrode 53 is not limited to the one formed along the dicing line.

Next, as shown in FIG. 3, a second insulating film 59 is formed on the entire back surface of the silicon wafer 51 in which the via hole 81 and the groove 82 are formed. The second insulating film 59 is formed by, for example, a plasma CVD method, and a PE-SiO ₂ film or a PE-SiN film is suitable. The second insulating film 59 is formed on the bottom and side walls of the via hole 81, the bottom and side walls of the trench 82, and the first insulating film 57.

  Next, as shown in FIG. 4, a buffer layer 60 is formed on the second insulating film 59 adjacent to the via hole 81. As the buffer layer 60, a film resist can be used and can be formed in a predetermined region by mask exposure and development processing. The buffer layer 60 is not limited to this, and various materials such as an organic insulator, an inorganic insulator, a metal, silicon, and a photoresist can be used. However, in order to function as a cushion, an organic insulator rich in elasticity is used. Inorganic insulators and photoresists are suitable. The buffer layer 60 may be omitted.

  Next, as shown in FIG. 5, anisotropic dry etching is performed without using a photoresist layer. As a result, the second insulating film 59 remains only on the side wall of the via hole 81 and the side wall of the trench 82, and this becomes the side wall insulating film 59A. Further, the second insulating film 59 and the interlayer insulating film 52 located at the bottom of the via hole 81 and the groove 82 are removed by etching. At the bottom of the via hole 81, the pad electrode 53 is exposed.

  Thus, in the present embodiment, after the formation of the via hole 81, the second insulating film 59 is formed in the via hole 81, and after the formation of the buffer layer 60, the second insulating film 59 located at the bottom of the via hole 81 and The interlayer insulating film 52 is removed by etching, and the pad electrode 53 is exposed.

  On the other hand, it is possible to form the buffer layer 60 after etching the bottom of the via hole 81 to expose the pad electrode 53, but in this case, when the buffer layer 60 is formed, the exposed via hole is exposed. There is a possibility that the bottom of 81 is contaminated and the electrical connection between the wiring layer 63 to be formed in the via hole 81 later and the pad electrode 53 becomes poor. Therefore, as in this embodiment, it is preferable to etch the bottom of the via hole 81 after forming the via hole 81 in order to obtain a good electrical connection between the wiring layer 63 and the pad electrode 53.

  Further, the sidewall insulating film 59A is formed by etching the insulating film in the via hole 81 after the buffer layer 60 is formed in the step of FIG. 5, but this etching causes the surface of the buffer layer 60 to become rough, and a seed layer to be described later There is also an advantage that adhesion with 61 is improved.

  Next, a process for forming the wiring layer 63 will be described. As shown in FIG. 6, the seed layer 61 includes the inside of the via hole 81 and the inside of the groove 82 from the back surface side of the silicon wafer 51 by any method such as sputtering with heat treatment, MOCVD, or electroless plating. It is formed on the entire back surface of the silicon wafer 51. The seed layer is, for example, a copper (Cu) layer, a barrier metal layer such as a titanium tungsten (TiW) layer, a titanium nitride (TiN) layer, or a tantalum nitride (TaN) layer, or a copper (Cu) layer and a barrier metal layer. And a laminated structure. Here, in the via hole 81, the seed layer 61 is formed so as to be electrically connected to the pad electrode 53 and cover the sidewall insulating film 59A.

  The seed layer 61 also covers the buffer layer 60. Here, the barrier metal layer constituting the seed layer 61 prevents copper (Cu) from diffusing into the silicon wafer 51 through the sidewall insulating film 59A. However, in the case where the sidewall insulating film 59A is formed of a silicon nitride film (SiN film), the silicon nitride film (SiN film) serves as a barrier against copper diffusion. Absent.

  This seed layer 61 becomes a plating electrode for plating growth at the time of electrolytic plating described later. Its thickness may be about 1 μm. When the via hole 81 is processed to have a forward taper, the seed layer 61 can be formed by sputtering.

  Next, as shown in FIG. 7, a wiring layer 63 is formed by electrolytic plating of copper (Cu). The wiring layer 63 is taken out from the via hole 81 to the back surface of the silicon wafer 51 and extends over the back surface to cover the buffer layer 60. As a result, the wiring layer 63 is electrically connected to the pad electrode 53. The wiring layer 63 is formed so as to extend from the back surface of the silicon wafer 51 into the groove 82 and cover the side wall and the bottom thereof.

  In FIG. 7, the wiring layer 63 is completely embedded in the via hole 81, but may be embedded incompletely by adjusting the plating time. The wiring layer 63 is formed so as to be embedded in the bihole VH by electrolytic plating, but is not limited thereto, and may be formed by other methods. For example, the wiring layer 63 may be formed by a method of embedding a metal such as copper (Cu) or aluminum (Al) in the via hole 81 by CVD or MOCVD. Further, a desired number of wiring layers 63 can be formed in a desired region on the back surface of the silicon wafer 51.

  Thus, since the wiring layer 63 extending from the pad electrode 53 of the silicon chip 51A to the solder ball 66 is formed via the via hole 81, disconnection of the wiring layer 63 and deterioration of step coverage are reduced as compared with the conventional example. be able to. Thereby, a BGA type semiconductor device having higher reliability than the conventional example can be obtained.

  Next, as shown in FIG. 8, a barrier layer 64 made of a Ni / Au layer is formed on the wiring layer 63 by electroless plating of nickel (Ni) and gold (Au) or sputtering. Thereafter, as shown in FIG. 9, a solder mask 65 as a protective layer is deposited on the wiring layer 63. The solder mask 65 is removed from the portion on the buffer layer 60 and an opening K is provided.

  Then, as shown in FIG. 10, solder balls 66 are formed by printing solder on a predetermined region of the wiring layer 63 using a screen printing method and reflowing the solder by heat treatment. The solder ball 66 is not limited to solder, and may be formed using a lead-free low melting point metal material. Further, the solder balls 66 can be formed by freely selecting the number and formation region thereof. In addition, it is not limited only to solder, You may form by plating.

  Here, the solder ball 66 is formed at a position higher than the back surface of the silicon chip 51A by the thickness of the buffer layer 60. Thereby, the stress generated when the semiconductor device is mounted on the printed board is easily absorbed, and damage to the solder ball 66 can be prevented as much as possible. Further, since the solder ball 66 is formed on the buffer layer 60, the impact when mounting the semiconductor device on the printed circuit board is mitigated, and damage to the semiconductor device can be prevented.

  Then, as shown in FIG. 11, a dicing process is performed along the dicing line center DS of the dicing line region DL to divide the silicon wafer 51 into a plurality of silicon chips 51A. In this dicing process, cutting is performed using a dicing blade.

  Here, the groove 82 is a side surface of each silicon chip 51A. The side surface of the silicon chip 51A is covered with a sidewall insulating film 59A, a seed layer 61, a wiring layer 63, a barrier layer 64, and a solu mask 65. This makes it possible to prevent moisture from entering the silicon chip 51 as much as possible.

  Of the steps described above, the silicon wafer 51 was divided by the groove 82 in the step involving heat treatment, that is, in forming the seed layer 61 or the like by sputtering, or in forming the solder ball 66 by solder reflow. Since it is supported by the glass substrate 56 in a state (see FIG. 12), warpage caused by a difference in thermal expansion coefficient between the glass substrate 56 and the silicon wafer 51 is reduced. As a result, it is possible to smoothly carry the silicon wafer 51 when shifting to a different process, and it is possible to improve the yield of the semiconductor device.

  In the above-described embodiment, the pad electrode 53 formed by extending the pad electrode used for normal wire bonding to the dicing line region DL is formed. However, the present invention is not limited to this. Alternatively, a pad electrode used for normal wire bonding that is not extended to the dicing line region DL may be used as it is. In this case, the formation position of the via hole 81 may be aligned with this pad electrode, and the other steps are exactly the same.

  Although the present invention is applied to the BGA type semiconductor device in which the solder ball 66 is formed and the manufacturing method thereof, the present invention is not limited to this. That is, the present invention can be applied to a semiconductor device in which solder balls are not formed and a method for manufacturing the semiconductor device as long as it includes a process involving heat treatment after the process of forming a via hole penetrating a silicon wafer. For example, the present invention is also applied to an LGA (Land Grid Array) type semiconductor device and a manufacturing method thereof.

Claims (5)

A pad electrode formed on the first main surface and a surface opposite to the first main surface are shaved by back grinding, and a second main surface formed by removing mechanical damage generated in the back grinding; A semiconductor chip having
A support bonded to the first main surface of the semiconductor chip;
A via hole penetrating from the second main surface of the semiconductor chip , reaching the pad electrode and exposing the pad electrode ;
With the pad electrode at the bottom of the via hole exposed, a sidewall insulating film formed on the sidewall of the via hole;
A seed layer that is electrically connected to the pad electrode through the via hole, covers the bottom of the via hole and the sidewall insulating film, and is provided on the seed layer, and is electrically connected to the pad electrode through the via hole; A wiring layer extending to the back surface of the semiconductor chip, comprising an incompletely embedded electrolytic plating layer covering the bottom of the via hole and the side wall ;
The semiconductor device according to claim 1, wherein the wiring layer extends from the pad electrode to a solder ball formation region . A protective layer formed to cover the wiring layer;
The semiconductor device according to claim 1, further comprising: a solder ball formed on the wiring layer corresponding to the opening of the protective layer . The back surface of the semiconductor chip has a buffer layer at a position adjacent to the via hole, the wiring layer covers the buffer layer, and the solder ball is provided on the wiring layer on the buffer layer. The semiconductor device described.   The semiconductor device according to claim 1, wherein the support is made of a glass substrate.   The semiconductor device according to claim 1, wherein the support is made of a metal substrate, a substrate made of an organic material, or a tape.

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