JP4794545B2 - Semiconductor device - Google Patents

Description

  In a semiconductor device having a power MOSFET (MOS field effect transistor) configuration, a trench gate structure is widely applied to various power sources such as a DC-DC converter in recent years. In a semiconductor device including a trench gate type MOSFET, the breakdown voltage is improved by improving the structure related to the gate electrode. In general, in a MOSFET, a parasitic diode is formed by a PN junction between a drain layer and a base diffusion layer.

FIG. 11 shows a cross-sectional structure of a conventional semiconductor device 2 having a trench gate type MOS structure. A semiconductor device having such a structure is described in Patent Document 1, for example. An N epitaxial layer 202 containing N-type impurities is formed on a P ⁺ substrate 201 containing high-concentration P-type impurities. On the N epitaxial layer 202, an N ⁻ epitaxial layer 203 containing an N-type impurity at a concentration lower than that of the N epitaxial layer 202 is formed. P wells 204 and 204 a containing P-type impurities are formed in the surface region of N ⁻ epitaxial layer 203, and an N ⁺ emitter region 205 containing high-concentration N-type impurities is formed in the vicinity of the surface of P well 204. ing.

A plurality of trenches 206 having a rectangular cross section are formed on the surface of the N ⁻ epitaxial layer 203. A gate insulating film 207 is formed on the inner surface of the trench 206 (including the side wall surface 206a and the bottom surface 206b). Inside the trench 206, a gate electrode 208 made of polysilicon surrounded by a gate insulating film 207 and the like is formed. In semiconductor device 2, a parasitic diode is formed between P wells 204 and 204 a and N epitaxial layer 202. An emitter electrode film 209 made of metal is formed on the top of the above structure. A collector electrode film 210 made of metal is formed on the back surface of the P ⁺ substrate 201.

The P ⁺ substrate 201, N epitaxial layer 202, N ⁻ epitaxial layer 203, P well 204, N ⁺ emitter region 205, gate electrode 208, emitter electrode film 209, and collector electrode film 210 constitute a MOS structure. A plurality of MOS structures are formed in the active region. FIG. 11 shows the structure around the outer edge of the active region. The P well 204a is for reducing the electric field strength at the corner of the outermost trench 206 where electric field concentration is likely to occur, and is formed so as to be in contact with the outermost trench 206 around the outer periphery of the outermost trench 206. Has been.

When the emitter electrode film 209 is grounded, a positive voltage is applied to the collector electrode film 210, and a positive voltage is applied to the gate electrode 208, an inversion layer is formed at the interface between the P well 204 and the trench 206. A current flows toward the emitter electrode film 209. Structure shown in FIG. 11 is a structure of only ^{P +} IGBT of such N epitaxial layer 202 on the substrate 201 is formed (Insulated Gate Bipolar Transistor), there is no P layer corresponding to the ^{P +} substrate 201 MOSFET Minority carriers are injected in the same manner in the structure of only the structure or the composite structure of the IGBT and the MOSFET in which the P layer does not partially exist. In the case of a MOSFET-only structure or a composite structure of IGBT and MOSFET, when the gate electrode 208 and the collector electrode film 210 are grounded and a positive voltage is applied to the emitter electrode film 209, the P wells 204 and 204a and the N ^- PN junction between the epitaxial layer 203 becomes forward biased. At this time, minority carriers are injected into the N ⁻ epitaxial layer 203 from the P wells 204 and 204a.

In this state, when the voltage between the emitter electrode film 209 and the collector electrode film 210 is inverted, minority carriers injected into the N ⁻ epitaxial layer 203 flow into the P wells 204 and 204a. Minority carriers injected into the N ⁻ epitaxial layer 203 outside the outermost trench 206 (the rightmost trench 206 in FIG. 11) move horizontally along the N ⁻ epitaxial layer 203 and flow into the P well 204a. For this reason, minority carriers concentrate in the P well 204a. Further, in the structure of only the IGBT, when the IGBT is turned off, the same minority carrier concentration occurs. Therefore, in any structure, not only the electric field strength at the corner of the outermost trench 206 is relaxed around the outer edge of the active region, but also the active region is actively exposed to the outside without locally concentrating minority carriers. A structure to be pulled out is required.

As described above, in a semiconductor device such as a trench gate type MOSFET, a parasitic diode may be used as a part of a circuit. However, carriers are concentrated on the parasitic diode located at the outer edge of the active region, and element breakdown is likely to occur. There was a problem. Patent Document 2 discloses a technique for preventing element destruction due to carrier concentration by providing a fixed potential diffusion layer into which carriers flow in a planar MOSFET.
JP-A-6-45612 JP 2001-7322 A

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a semiconductor device capable of improving the breakdown voltage and reducing the occurrence of element breakdown.

  The present invention includes a first semiconductor layer having first and second main surfaces facing each other and made of a first conductivity type semiconductor, and the first semiconductor layer exposed on the first main surface. A second semiconductor layer made of a first conductivity type semiconductor having a low impurity concentration, a plurality of grooves formed on the surface of the second semiconductor layer, a gate insulating film formed in the groove, and the gate A gate electrode surrounded by an insulating film; a surface of the second semiconductor layer; a first region of a second conductivity type formed between two trenches; and a surface of the first region. A first conductivity type second region having a higher impurity concentration than the second semiconductor layer, and a surface of the second semiconductor layer in contact with the groove in contact with the first region; A third region of the second conductivity type adjacent to the first region, and a surface of the third region; A second conductivity type fourth region having an impurity concentration higher than that of the third region; a second conductivity type carrier extraction region in contact with the third region on the surface of the second semiconductor layer; An insulating layer made of an insulating material, formed on the surface of the carrier extraction region, and formed on the surface of the insulating layer, and seen from the direction perpendicular to the first main surface, is identical to the carrier extraction region. A gate electrode pad having overlapping portions, a first electrode made of metal in contact with the second region and the fourth region, and a second electrode made of metal in contact with the second main surface. This is a semiconductor device.

  The present invention includes a first semiconductor layer having first and second main surfaces facing each other and made of a first conductivity type semiconductor, and the first semiconductor layer exposed on the first main surface. A second semiconductor layer made of a first conductivity type semiconductor having a low impurity concentration, a plurality of grooves formed on the surface of the second semiconductor layer, a gate insulating film formed in the groove, and the gate A gate electrode surrounded by an insulating film; a surface of the second semiconductor layer; a first region of a second conductivity type formed between two trenches; and a surface of the first region. A first conductivity type second region having a higher impurity concentration than the second semiconductor layer, and a surface of the second semiconductor layer in contact with the groove in contact with the first region; A third region of the second conductivity type adjacent to the first region, and a surface of the third region; A second conductivity type fourth region having an impurity concentration higher than that of the third region; a second conductivity type carrier extraction region in contact with the third region on the surface of the second semiconductor layer; An insulating layer made of an insulating material, formed on the surface of the carrier extraction region, and formed on the surface of the insulating layer, and seen from the direction perpendicular to the first main surface, is identical to the carrier extraction region. A gate electrode pad having overlapping portions, a first electrode made of metal in contact with the second region and the fourth region, and a second conductive type semiconductor exposed on the second main surface. And a second electrode made of metal in contact with the third semiconductor layer.

  The depth of the carrier extraction region from the surface of the second semiconductor layer may be smaller than the depth of the groove from the surface of the second semiconductor layer.

  In the region where the depth of the carrier extraction region from the surface of the second semiconductor layer in the vicinity of the third region overlaps with the gate electrode pad when viewed from the direction perpendicular to the first main surface. It may be smaller than the depth of the carrier extraction region from the surface of the second semiconductor layer.

  The depth of the carrier extraction region from the surface of the second semiconductor layer in the vicinity of the third region is smaller than the depth of the groove from the surface of the second semiconductor layer. When viewed from the direction perpendicular to the surface, the depth of the carrier extraction region from the surface of the second semiconductor layer in the region overlapping with the gate electrode pad is the depth of the groove from the surface of the second semiconductor layer. It may be larger than this.

  In the gate insulating film, the thickness of the portion formed on the bottom surface of the trench may be larger than the thickness of the portion formed on the sidewall surface of the trench.

  According to the present invention, it is possible to improve the breakdown voltage and reduce the occurrence of element breakdown.

FIG. 1 is a sectional view showing a sectional structure of a semiconductor device 1a according to the first embodiment of the present invention. FIG. 2A is a plan view of the semiconductor device 1a. FIG. 2B is a plan view of the semiconductor device 1a. FIG. 3A is a plan view of the semiconductor device 1a. FIG. 3B is a plan view of the semiconductor device 1a. FIG. 4 is a cross-sectional view for explaining a method for forming the carrier extraction region 112. FIG. 5 is a cross-sectional view for explaining a method for forming the carrier extraction region 112. FIG. 6 is a cross-sectional view for explaining a method for forming the carrier extraction region 112. FIG. 7 is a cross-sectional view for explaining a method for forming the carrier extraction region 112. FIG. 8 is a sectional view showing a sectional structure of a semiconductor device 1b according to the second embodiment of the present invention. FIG. 9 is a sectional view showing a sectional structure of a semiconductor device 1c according to the third embodiment of the present invention. FIG. 10 is a sectional view showing a sectional structure of a semiconductor device 1d according to the fourth embodiment of the present invention. FIG. 11 is a cross-sectional view showing a cross-sectional structure of a conventional semiconductor device 2.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1a, 1b, 2 ... Semiconductor device, 101 ... Drain layer, 102 ... Drift layer, 103, 110, 133, 140 ... P-type body region, 104, 111, 134, 141 ... P ⁺ -type diffusion region, 105, 205... N ⁺ -type source region, 106, 136, 206... Trench, 106a, 136a, 206a... Side wall surface, 106b, 136b, 206b. , 137, 207... Gate insulating film, 108, 138, 208... Gate electrode, 109, 115, 116, 126, 139, 145, 146, 153... Interlayer insulating film, 112, 112a, 142. .... Carrier extraction region, 113, 143 ... P-type well, 114, 121, 144, 151 ... insulating film, 117, 147 ... polysilicon 118 ... Source electrode film, 119, 149 ... Gate electrode pad, 120, 150 ... Zener diode, 122 ... Drain electrode film, 123, 124 ... Oxide film, 125 ... Injection 131, high concentration layer, 132, low concentration layer, 135, N ⁺ type emitter region, 148, emitter electrode film, 152, collector electrode film, 154, collector layer , P ⁺ 201 ... substrate, 202 ... N epitaxial layer, 203 ... N ^- epitaxial layer, 204, 204a ... P well, 205 ... N ⁺ emitter region, 209 ... emitter electrode Membrane 210 ... collector electrode membrane 301, 302, 303, 304 ... principal surface.

The best mode for carrying out the present invention will be described below with reference to the drawings. FIG. 1 shows a cross-sectional structure of a semiconductor device 1a according to the first embodiment of the present invention. The semiconductor device 1a is a MOSFET. The drain layer 101 containing a high-concentration N-type impurity has two main surfaces 301 and 302 facing each other, and constitutes an N ⁺ -type silicon substrate. On the main surface 301 of the drain layer 101, a drift layer 102 containing a low concentration N-type impurity is formed. A P-type body region 103 containing P-type impurities is formed on the drift layer 102. In the vicinity of the surface of the P-type body region 103, a P ⁺ -type diffusion region 104 containing P-type impurities at a higher concentration than the P-type body region 103 is formed. An N ⁺ type source region 105 containing a high concentration N type impurity is also formed on the surface of the P type body region 103 so as to sandwich the P ⁺ type diffusion region 104.

In a region from the surface of the P-type body region 103 to the drift layer 102, a plurality of trenches 106 having a rectangular cross-sectional shape are formed. A gate insulating film 107 and an interlayer insulating film 126 are formed on the inner surface (including the side wall surface 106 a and the bottom surface 106 b) of the trench 106. Inside the trench 106, a gate electrode 108 made of polysilicon surrounded by a gate insulating film 107 and an interlayer insulating film 126 is formed. An insulating interlayer insulating film 109 made of BPSG (Boro-Phosphosilicate glass) is formed on the trench 106 and the N ⁺ type source region 105. The gate insulating film 107 may be formed such that the thickness of the portion formed on the bottom surface 106 b of the trench 106 is larger than the thickness of the portion formed on the sidewall surface 106 a of the trench 106. In this way, the on-resistance capacitance can be kept low.

A P-type body region 110 containing a P-type impurity is also formed on the surface of the drift layer 102. P-type body region 103 and P-type body region 110 are adjacent to each other through trench 106. On the surface of the P-type body region 110, a P ⁺ -type diffusion region 111 containing a P-type impurity having a higher concentration than the P-type body region 110 is formed. A carrier extraction region 112 containing a P-type impurity is formed on the surface of the drift layer 102 so as to be in contact with the P-type body region 110.

The depth of the carrier extraction region 112 from the surface of the drift layer 102 (distance X ₁ in the drawing) is smaller than the depth of the trench 106 from the surface of the drift layer 102 (distance X ₂ in the drawing). The carrier extracting region 112 is formed by impurity diffusion, the distance X ₁ same as the distance X _2, or if the distance X ₂ is made larger than, the greater diffusion in the lateral direction. When the diffusion in the lateral direction increases, the area of the carrier extraction region 112 increases, so that the area of the semiconductor device 1a needs to be increased. Therefore, if the size of the semiconductor device 1a is particularly necessary, as in the present embodiment, it is desirable to be smaller than the distance X ₁ distance X _2. Minority carriers injected into the drift layer 102 during the operation of the semiconductor device 1a flow into the carrier extraction region 112. Thereby, the concentration of minority carriers can be alleviated and element breakdown can be prevented.

A P-type well 113 containing a P-type impurity is provided on the surface of the drift layer 102 so as to be adjacent to the carrier extraction region 112 in order to reduce the gate-drain capacitance. An insulating film 114 made of SiO ₂ is formed on the surface of the carrier extraction region 112 and the P-type well 113. The insulating film 114 covers a part of the carrier extraction region 112. On this insulating film 114, interlayer insulating films 115 and 116 made of BPSG are formed, and a polysilicon film 117 made of polysilicon is also formed.

A source electrode film 118 made of metal is formed on the top of the above structure. The source electrode film 118 is electrically connected to the N ⁺ type source region 105 and the P ⁺ type diffusion region 111, and is insulated from the gate electrode 108. The source electrode film 118 forms an ohmic junction with the N ⁺ type source region 105 and the P ⁺ type diffusion region 111. The carrier extraction region 112 is electrically connected to the source electrode film 118 through the P-type body region 110 and the P ⁺ -type diffusion region 111. A gate electrode pad 119 for applying a voltage to the gate electrode 108 from the outside is formed on the interlayer insulating film 116. Although not shown, the gate electrode pad 119 is electrically connected to the gate electrode 108. When the semiconductor device 1a is viewed from a direction perpendicular to the main surface 301, the carrier extraction region 112 and the gate electrode pad 119 are formed so as to partially overlap each other.

  Between the source electrode film 118 and the gate electrode pad 119, along the surface of the insulating film 114, a high concentration N-type layer, a P-type layer, a high concentration N-type layer, a P-type layer, and a high concentration N A Zener diode 120 in which mold layers are arranged in order is formed. When a voltage is applied between the source electrode film 118 and the gate electrode pad 119, no current flows through the Zener diode 120 until the voltage value reaches a predetermined value, but if the voltage value exceeds the predetermined value, A current flows between the source electrode film 118 and the gate electrode pad 119. Thereby, it is possible to prevent the gate electrode pad 119 from being broken by applying a high voltage. An insulating film 121 is formed on the Zener diode 120.

A drain electrode film 122 made of metal is formed on the main surface 302 of the drain layer 101. The drain electrode film 122 forms an ohmic junction with the drain layer 101. The drain layer 101, the drift layer 102, the P-type body region 103, the N ⁺ -type source region 105, the gate electrode 108, the source electrode film 118, and the drain electrode film 122 constitute a MOSFET. A plurality of MOSFET structures are formed in the active region. FIG. 1 shows the structure around the outer edge of the active region.

In the structure described above, the drift layer 102 is formed by epitaxially growing silicon containing N-type impurities on the surface of the drain layer 101. P-type body region 103 and P-type body region 110 are formed by implanting P-type impurities from the surface of drift layer 102 and diffusing the impurities at a high temperature within a predetermined depth from the surface. The P ⁺ -type diffusion region 104 is formed by selectively injecting a P-type impurity from the surface of the P-type body region 103 and diffusing the impurity at a high temperature within a predetermined depth from the surface. Similarly, the P ⁺ -type diffusion region 111 is formed by selectively injecting a P-type impurity from the surface of the P-type body region 110 and diffusing the impurity at a high temperature within a predetermined depth from the surface. Yes.

The N ⁺ type source region 105 is formed by selectively injecting an N type impurity from the surface of the P type body region 103 and diffusing the impurity at a high temperature within a predetermined depth from the surface. In FIG. 1, the heights of the surfaces of the P-type body region 103, the P ⁺ -type diffusion region 104, and the N ⁺ -type source region 105 that are in contact with the source electrode film 118 are equal, and the surfaces are in the same plane. A mesa structure is formed.

  The trench 106 is formed by etching the drift layer 102 and reaches the drift layer 102 from the surface of the P-type body region 103. The gate insulating film 107 is formed by oxidizing the surface of the trench 106 in a high-temperature oxygen atmosphere. The gate electrode 108 is formed by depositing polysilicon containing N-type impurities on the surface of the gate insulating film 107.

  The carrier extraction region 112 is formed by injecting a P-type impurity from the surface of the drift layer 102 and diffusing the impurity at a high temperature within a predetermined depth from the surface. The source electrode film 118 and the drain electrode film 122 are formed, for example, by sputtering an electrode material.

The impurity concentration of the drain layer 101 is, for example, 10 ¹⁹ to 10 ²⁰ cm ⁻³ . The impurity concentration on the surfaces of the P-type body region 103 and the P-type body region 110 is, for example, 10 ¹⁷ to 10 ¹⁸ cm ⁻³ . The impurity concentration on the surfaces of the P ⁺ -type diffusion region 104 and the P ⁺ -type diffusion region 111 is, for example, 10 ¹⁸ to 10 ¹⁹ cm ⁻³ . The impurity concentration on the surface of the N ⁺ -type source region 105 is, for example, 10 ¹⁹ to 10 ²⁰ cm ⁻³ . The impurity concentration on the surface of the carrier extraction region 112 is, for example, 10 ¹⁷ to 10 ¹⁸ cm ⁻³ .

  2A to 3B are plan views of the semiconductor device 1a according to the present embodiment as viewed from a direction perpendicular to the main surface 301. FIG. In these drawings, the source electrode film 118, the gate electrode pad 119, and the like are not shown. FIG. 1 shows a part of a cross-sectional structure taken along line A-A ′ in FIG. 2A. 2A to 2B show an example of the arrangement of the carrier extraction region 112 and the P-type well 113. FIG. 3A to 3B show an example in which the carrier extraction region 112a is formed so as to surround the periphery of the P-type well 113 and the guard ring region 112b is formed so as to surround the outside thereof.

  Next, the operation of the semiconductor device 1a will be described. When the source electrode film 118 is grounded, a positive voltage is applied to the drain electrode film 122, and a positive voltage is applied to the gate electrode 108, an inversion layer is formed at the interface between the P-type body region 103 and the trench 106, and the drain electrode film A current flows from 122 toward the source electrode film 118. When a ground voltage is applied to the gate electrode 108 from this state, the inversion layer formed at the interface between the P-type body region 103 and the trench 106 disappears and the current is cut off.

In addition, when a voltage higher than that of the drain electrode film 122 is applied to the source electrode film 118, a parasitic diode formed by the drift layer 102, the P-type body region 103, and the P ⁺ -type diffusion region 104, and the drift layer 102, the P-type body region 110, and the parasitic diode formed by the P ⁺ -type diffusion region 111 are forward-biased, and current flows through these parasitic diodes. Minority carriers are injected into the drift layer 102 by the current. In this state, when the voltage between the source electrode film 118 and the drain electrode film 122 is inverted, minority carriers injected into the drift layer 102 flow into the P-type body regions 103 and 110 connected to the source electrode film 118.

  Minority carriers tend to concentrate on the P-type body regions 103 and 110 located on the outermost periphery at the end of the active region where the MOSFET structure is formed, but the carrier extraction region 112 electrically connected to the source electrode film 118 is formed. By being formed, minority carriers flow into the carrier extraction region 112, so that minority carriers do not concentrate. Therefore, the breakdown voltage can be improved and the element breakdown can be reduced.

Next, a method for forming the carrier extraction region 112 will be described with reference to FIGS. First, the drift layer 102 is formed by epitaxial growth on the drain layer 101, and an oxide such as SiO ₂ is deposited on the drift layer 102 to form an oxide film 123 (FIG. 4). Subsequently, a resist is applied on the oxide film 123, and a resist pattern is formed by a photographic process (exposure and development). The oxide film 123 is etched using the resist pattern as a mask to expose the surface of the drift layer 102, and then the resist is removed (FIG. 5).

  Subsequently, thermal oxidation is performed in a high-temperature oxygen atmosphere to form a thin oxide film 124 on the surface of the drift layer 102 other than the portion covered with the oxide film 123. A P-type impurity such as B (boron) is implanted into the surface of the drift layer 102 so as to pass through the oxide film 124, thereby forming an implantation layer 125 (FIG. 6). When annealing is performed in a high-temperature oxygen atmosphere, B in the injection layer 125 diffuses into the drift layer 102, and a carrier extraction region 112 and a P-type well 113 are formed (FIG. 7).

Next, a second embodiment of the present invention will be described. FIG. 8 shows a cross-sectional structure of the semiconductor device 1b according to the present embodiment. Structures having the same functions as those shown in FIG. 1 are given the same reference numerals. The semiconductor device 1b is a MOSFET. In this semiconductor device 1b, the depth of the carrier extraction region 112 (distance X ₃ in the figure) from the surface of the drift layer 102 in the vicinity of the P-type body region 110 is viewed from the direction perpendicular to the main surface 301. The depth is smaller than the depth (distance X ₄ in the drawing) of the carrier extraction region 112 from the surface of the drift layer 102 in the region overlapping with the gate electrode pad 119 and the Zener diode 120. That is, the carrier extraction region 112 is formed such that a portion in the vicinity of the P-type body region 110 is shallower than a portion located below the gate electrode pad 119 and the Zener diode 120.

In other words, the depth of the carrier extraction region 112 (distance X ₃ in the figure) from the surface of the drift layer 102 in the vicinity of the P-type body region 110 is the depth of the trench 106 from the surface of the drift layer 102 (in the figure). small distance X ₅₎ than when seen in a direction perpendicular to the main surface 301, the depth of the carrier extracting region 112 from the surface of the drift layer 102 in the region overlapping with the gate electrode pad 119 and the Zener diode 120 (in FIG. The distance X ₄ ) is smaller than the depth of the trench 106 from the surface of the drift layer 102 (distance X ₅ in the figure). That is, in the carrier extraction region 112, a portion in the vicinity of the P-type body region 110 is shallower than the trench 106, and a portion located below the gate electrode pad 119 and the Zener diode 120 is formed deeper than the trench 106.

  The carrier extraction region 112 concentrates carriers on the parasitic diode constituted by the P-type body region 110 and the drift layer 102 adjacent to the trench 106 located on the outermost side of the active region when a reverse voltage is applied to the parasitic diode. ease. In order to sufficiently exhibit this action, it is desirable that the carrier extraction region 112 is formed wide and deep toward the outside of the outermost trench 106 in the active region.

  However, when the carrier extraction region 112 expands so as to cover the outermost trench 106 in the active region, the carrier with respect to the P-type body region 103 between the outermost trench 106 and the inner trench 106 is in a carrier state. The extraction region 112 partially overlaps, affecting the concentration of impurities in the vicinity. Of course, an undesirable effect is exerted on the operation of the MOSFET in the outermost trench 106. In order to avoid this, even if there is a slight process variation, the portion near the outermost trench 106 in the carrier extraction region 112 is formed shallower than the trench 106, and the carrier extraction region 112 is formed in the outermost trench. It is desirable not to cover 106.

  With the above structure, minority carriers generated in a region outside the active region in the drift layer 102 can be more efficiently caused to flow into the carrier extraction region 112. Further, by forming the carrier extraction region 112 to a deeper region of the drift layer 102, the radius of curvature of the end of the carrier extraction region 112 is increased, so that the concentration of the electric field at the end is reduced and the breakdown voltage is improved. Can do.

  In order to form the carrier extraction region 112, it is necessary to inject B twice or more. That is, B is implanted separately into the surface region of the drift layer 102 immediately below the gate electrode pad 119 and the Zener diode 120 and the surface region of the drift layer 102 in the vicinity of the P-type body region 110.

Next, a third embodiment of the present invention will be described. FIG. 9 shows a cross-sectional structure of the semiconductor device 1c according to the present embodiment. The semiconductor device 1c is an IGBT. A high-concentration layer 131 containing a high-concentration N-type impurity formed by epitaxial growth has two main surfaces 303 and 304 facing each other. On the main surface 303 of the high concentration layer 131, a low concentration layer 132 containing a low concentration N-type impurity is formed. A P-type body region 133 containing P-type impurities is formed on the low concentration layer 132. In the vicinity of the surface of the P-type body region 133, a P ⁺ -type diffusion region 134 containing a P-type impurity having a higher concentration than the P-type body region 133 is formed. An N ⁺ type emitter region 135 containing a high concentration N type impurity is also formed on the surface of the P type body region 133 so as to sandwich the P ⁺ type diffusion region 134.

In the region from the surface of the P-type body region 133 to the low concentration layer 132, a plurality of trenches 136 having a rectangular cross section are formed. A gate insulating film 137 and an interlayer insulating film 153 are formed on the inner surface (including the side wall surface 136a and the bottom surface 136b) of the trench 136. A gate electrode 138 made of polysilicon surrounded by a gate insulating film 137 and an interlayer insulating film 153 is formed inside the trench 136. On the trench 136 and the N ⁺ -type emitter region 135, an insulating interlayer insulating film 139 made of BPSG is formed. The gate insulating film 137 may be formed such that the thickness of the portion formed on the bottom surface 136b of the trench 136 is larger than the thickness of the portion formed on the side wall surface 136a of the trench 136. In this way, the on-resistance capacitance can be kept low.

A P-type body region 140 containing P-type impurities is also formed on the surface of the low concentration layer 132. P-type body region 133 and P-type body region 140 are adjacent to each other through trench 136. On the surface of the P-type body region 140, a P ⁺ -type diffusion region 141 containing a P-type impurity having a higher concentration than the P-type body region 140 is formed. A carrier extraction region 142 containing a P-type impurity is formed on the surface of the low concentration layer 132 so as to be in contact with the P-type body region 140.

Similar to the semiconductor device 1a according to the first embodiment, the depth of the carrier extraction region 142 from the surface of the low concentration layer 132 (distance X ₆ in the drawing) is the depth of the trench 136 from the surface of the low concentration layer 132. It is smaller than the distance (distance X ₇ in the figure). Minority carriers injected into the low concentration layer 132 during the operation of the semiconductor device 1 c flow into the carrier extraction region 142. Thereby, the concentration of minority carriers can be alleviated and element breakdown can be prevented.

On the surface of the low-concentration layer 132, a P-type well 143 containing a P-type impurity for reducing the gate-collector capacitance is provided adjacent to the carrier extraction region 142. An insulating film 144 made of SiO ₂ is formed on the surfaces of the carrier extraction region 142 and the P-type well 143. The insulating film 144 covers a part of the carrier extraction region 142. On this insulating film 144, interlayer insulating films 145 and 146 made of BPSG are formed, and a polysilicon film 147 made of polysilicon is also formed.

An emitter electrode film 148 made of metal is formed on the top of the above structure. The emitter electrode film 148 is electrically connected to the N ⁺ type emitter region 135 and the P ⁺ type diffusion region 141, and is insulated from the gate electrode 138. The emitter electrode film 148 forms an ohmic junction with the N ⁺ -type emitter region 135 and the P ⁺ -type diffusion region 141. Carrier extraction region 142 is electrically connected to emitter electrode film 148 through P-type body region 140 and P ⁺ -type diffusion region 141. On the interlayer insulating film 146, a gate electrode pad 149 for applying a voltage to the gate electrode 138 from the outside is formed. Although not shown, the gate electrode pad 149 is electrically connected to the gate electrode 138. When the semiconductor device 1c is viewed from a direction perpendicular to the main surface 303, the carrier extraction region 142 and the gate electrode pad 149 are formed so as to partially overlap each other.

  Between the emitter electrode film 148 and the gate electrode pad 149, along the surface of the insulating film 144, a high-concentration N-type layer, a P-type layer, a high-concentration N-type layer, a P-type layer, and a high-concentration N A Zener diode 150 in which mold layers are arranged in order is formed. An insulating film 151 is formed on the Zener diode 150.

On the main surface 304 of the high concentration layer 131, a collector layer 154 containing a high concentration P-type impurity is formed. The collector layer 154 constitutes a P ⁺ type silicon substrate. A collector electrode film 152 made of metal is formed on the collector layer 154. The collector electrode film 152 forms an ohmic junction with the collector layer 154. The low concentration layer 131, the high concentration layer 132, the P-type body region 133, the N ⁺ -type emitter region 135, the gate electrode 138, the emitter electrode film 148, the collector layer 154, and the collector electrode film 152 constitute an IGBT. A plurality of IGBT structures are formed in the active region. FIG. 9 shows the structure around the outer edge of the active region.

  At the end of the active region where the IGBT structure is formed, minority carriers tend to concentrate on the P-type body regions 133 and 140 located on the outermost periphery, but there are carrier extraction regions 142 electrically connected to the emitter electrode film 148. Due to the formation, minority carriers flow into the carrier extraction region 142, so that minority carriers do not concentrate. Therefore, the breakdown voltage can be improved and the element breakdown can be reduced.

Next, a fourth embodiment of the present invention will be described. FIG. 10 shows a cross-sectional structure of the semiconductor device 1d according to the present embodiment. Structures having the same functions as those shown in FIG. 9 are given the same reference numerals. This semiconductor device 1d is an IGBT. In this semiconductor device 1 d, the depth of the carrier extraction region 142 (distance X ₈ in the figure) from the surface of the low concentration layer 132 in the vicinity of the P-type body region 140 is viewed from a direction perpendicular to the main surface 303. The depth of the carrier extraction region 142 from the surface of the low concentration layer 132 in the region overlapping with the gate electrode pad 149 and the Zener diode 150 (distance X ₉ in the drawing) is smaller. That is, the carrier extraction region 142 is formed such that a portion in the vicinity of the P-type body region 140 is shallower than a portion located below the gate electrode pad 149 and the Zener diode 150.

In other words, the depth of the carrier extraction region 142 (distance X ₈ in the figure) from the surface of the low concentration layer 132 in the vicinity of the P-type body region 140 is the depth of the trench 136 from the surface of the low concentration layer 132 ( The depth of the carrier extraction region 142 from the surface of the low-concentration layer 132 in the region overlapping with the gate electrode pad 149 and the Zener diode 150 when viewed from the direction perpendicular to the main surface 303 and smaller than the distance X ₁₀ in the figure ( The distance X ₉ ) in the figure is smaller than the depth of the trench 136 from the surface of the low concentration layer 132 (distance X ₁₀ in the figure). That is, the carrier extraction region 142 is formed such that a portion in the vicinity of the P-type body region 140 is shallower than the trench 136, and a portion located below the gate electrode pad 149 and the Zener diode 150 is formed deeper than the trench 136.

  The carrier extraction region 142 is a concentration of carriers with respect to the parasitic diode constituted by the P-type body region 140 and the low-concentration layer 132 adjacent to the trench 136 located on the outermost side of the active region when a reverse voltage is applied to the parasitic diode. To ease. In order to sufficiently exhibit this effect, it is desirable that the carrier extraction region 142 is formed wide and deep toward the outside of the outermost trench 136 in the active region.

  However, when the carrier extraction region 142 expands to cover the outermost trench 136 in the active region, the carrier type region 133 is located between the outermost trench 136 and the innermost trench 136. The extraction region 142 partially overlaps, which affects the impurity concentration in the vicinity. Of course, this has an undesirable effect on the operation of the IGBT in the outermost trench 136. In order to avoid this, even if there is a slight variation in process, the portion near the outermost trench 136 in the carrier extraction region 142 is formed shallower than the trench 136, and the carrier extraction region 142 is formed in the outermost trench. It is desirable not to cover 136.

  With the above structure, minority carriers generated in a region outside the active region in the low concentration layer 132 can be more efficiently caused to flow into the carrier extraction region 142. Further, by forming the carrier extraction region 142 to a deeper region of the low concentration layer 132, the radius of curvature of the end portion of the carrier extraction region 142 is increased, so that the concentration of the electric field at the end portion is relaxed and the breakdown voltage is improved. be able to.

  As described above, the embodiments of the present invention have been described in detail with reference to the drawings, but the specific configuration is not limited to these embodiments, and includes design changes and the like within a scope not departing from the gist of the present invention. It is. For example, a composite structure of MOSFET and IGBT is also included in the scope of the present invention.

  The breakdown voltage can be improved and the occurrence of element breakdown can be reduced.

Claims (7)

A first semiconductor layer having first and second main surfaces facing each other and made of a first conductivity type semiconductor;
A second semiconductor layer made of a first conductivity type semiconductor having an impurity concentration lower than that of the first semiconductor layer exposed at the first main surface;
A plurality of grooves formed on the surface of the second semiconductor layer;
A gate insulating film formed in the trench;
A gate electrode surrounded by the gate insulating film;
A first region of a second conductivity type formed between the two grooves on the surface of the second semiconductor layer;
A first conductivity type second region having a higher impurity concentration than the second semiconductor layer on the surface of the first region;
On the surface of the second semiconductor layer, a third region of a second conductivity type that is in contact with the groove that is in contact with the first region on the outermost periphery and is adjacent to the first region through the groove;
A fourth region of a second conductivity type having a higher impurity concentration than the third region on the surface of the third region;
On the surface of the second semiconductor layer, the second conductivity type carrier extraction region that does not contact the fourth region and contacts the third region;
An insulating layer made of an insulating material formed on the surface of the carrier extraction region;
A gate electrode pad formed on the surface of the insulating layer and partially overlapping with the carrier extraction region when viewed from a direction perpendicular to the first main surface;
A first electrode made of metal in contact with the second region and the fourth region;
A second electrode made of metal in contact with the second main surface;
Equipped with a,
The groove extends from the surface of the first region in the surface of the second semiconductor layer to the second semiconductor layer,
The depth of the carrier extracting region from the surface of the second semiconductor layer, said have rot smaller than the depth of the groove from the surface of the second semiconductor layer,
The carrier extracting region, said third region and said fourth region semiconductors devices you characterized by being electrically connected to the first electrode through the. A first semiconductor layer having first and second main surfaces facing each other and made of a first conductivity type semiconductor;
A second semiconductor layer made of a first conductivity type semiconductor having an impurity concentration lower than that of the first semiconductor layer exposed at the first main surface;
A plurality of grooves formed on the surface of the second semiconductor layer;
A gate insulating film formed in the trench;
A gate electrode surrounded by the gate insulating film;
A first region of a second conductivity type formed between the two grooves on the surface of the second semiconductor layer;
A first conductivity type second region having a higher impurity concentration than the second semiconductor layer on the surface of the first region;
On the surface of the second semiconductor layer, a third region of a second conductivity type that is in contact with the groove that is in contact with the first region on the outermost periphery and is adjacent to the first region through the groove;
A fourth region of a second conductivity type having a higher impurity concentration than the third region on the surface of the third region;
On the surface of the second semiconductor layer, the second conductivity type carrier extraction region that does not contact the fourth region and contacts the third region;
An insulating layer made of an insulating material formed on the surface of the carrier extraction region;
A gate electrode pad formed on the surface of the insulating layer and partially overlapping with the carrier extraction region when viewed from a direction perpendicular to the first main surface;
A first electrode made of metal in contact with the second region and the fourth region;
A third semiconductor layer made of a semiconductor of the second conductivity type exposed on the second main surface;
A second electrode made of metal in contact with the third semiconductor layer;
Equipped with a,
The groove extends from the surface of the first region in the surface of the second semiconductor layer to the second semiconductor layer,
The depth of the carrier extracting region from the surface of the second semiconductor layer, said have rot smaller than the depth of the groove from the surface of the second semiconductor layer,
The carrier extracting region, said third region and said fourth region semiconductors devices you characterized by being electrically connected to the first electrode through the. A first semiconductor layer having first and second main surfaces facing each other and made of a first conductivity type semiconductor;
A second semiconductor layer made of a first conductivity type semiconductor having an impurity concentration lower than that of the first semiconductor layer exposed at the first main surface;
A plurality of grooves formed on the surface of the second semiconductor layer;
A gate insulating film formed in the trench;
A gate electrode surrounded by the gate insulating film;
A first region of a second conductivity type formed between the two grooves on the surface of the second semiconductor layer;
A first conductivity type second region having a higher impurity concentration than the second semiconductor layer on the surface of the first region;
On the surface of the second semiconductor layer, a third region of a second conductivity type that is in contact with the groove that is in contact with the first region on the outermost periphery and is adjacent to the first region through the groove;
A fourth region of a second conductivity type having a higher impurity concentration than the third region on the surface of the third region;
On the surface of the second semiconductor layer, the second conductivity type carrier extraction region that does not contact the fourth region and contacts the third region;
An insulating layer made of an insulating material formed on the surface of the carrier extraction region;
A gate electrode pad formed on the surface of the insulating layer and partially overlapping with the carrier extraction region when viewed from a direction perpendicular to the first main surface;
A first electrode made of metal in contact with the second region and the fourth region;
A second electrode made of metal in contact with the second main surface;
Equipped with a,
The groove extends from the surface of the first region in the surface of the second semiconductor layer to the second semiconductor layer,
In the region where the depth of the carrier extraction region from the surface of the second semiconductor layer in the vicinity of the third region overlaps with the gate electrode pad when viewed from the direction perpendicular to the first main surface. and rot smaller than the depth of the carrier extracting region from the surface of the second semiconductor layer,
The carrier extracting region, said third region and said fourth region semiconductors devices you characterized by being electrically connected to the first electrode through the. A first semiconductor layer having first and second main surfaces facing each other and made of a first conductivity type semiconductor;
A second semiconductor layer made of a first conductivity type semiconductor having an impurity concentration lower than that of the first semiconductor layer exposed at the first main surface;
A plurality of grooves formed on the surface of the second semiconductor layer;
A gate insulating film formed in the trench;
A gate electrode surrounded by the gate insulating film;
A first region of a second conductivity type formed between the two grooves on the surface of the second semiconductor layer;
A first conductivity type second region having a higher impurity concentration than the second semiconductor layer on the surface of the first region;
On the surface of the second semiconductor layer, a third region of a second conductivity type that is in contact with the groove that is in contact with the first region on the outermost periphery and is adjacent to the first region through the groove;
A fourth region of a second conductivity type having a higher impurity concentration than the third region on the surface of the third region;
On the surface of the second semiconductor layer, the second conductivity type carrier extraction region that does not contact the fourth region and contacts the third region;
An insulating layer made of an insulating material formed on the surface of the carrier extraction region;
A gate electrode pad formed on the surface of the insulating layer and partially overlapping with the carrier extraction region when viewed from a direction perpendicular to the first main surface;
A first electrode made of metal in contact with the second region and the fourth region;
A third semiconductor layer made of a semiconductor of the second conductivity type exposed on the second main surface;
A second electrode made of metal in contact with the third semiconductor layer;
Equipped with a,
The groove extends from the surface of the first region in the surface of the second semiconductor layer to the second semiconductor layer,
In the region where the depth of the carrier extraction region from the surface of the second semiconductor layer in the vicinity of the third region overlaps with the gate electrode pad when viewed from the direction perpendicular to the first main surface. and rot smaller than the depth of the carrier extracting region from the surface of the second semiconductor layer,
The carrier extracting region, said third region and said fourth region semiconductors devices you characterized by being electrically connected to the first electrode through the. A first semiconductor layer having first and second main surfaces facing each other and made of a first conductivity type semiconductor;
A second semiconductor layer made of a first conductivity type semiconductor having an impurity concentration lower than that of the first semiconductor layer exposed at the first main surface;
A plurality of grooves formed on the surface of the second semiconductor layer;
A gate insulating film formed in the trench;
A gate electrode surrounded by the gate insulating film;
A first region of a second conductivity type formed between the two grooves on the surface of the second semiconductor layer;
A first conductivity type second region having a higher impurity concentration than the second semiconductor layer on the surface of the first region;
On the surface of the second semiconductor layer, a third region of a second conductivity type that is in contact with the groove that is in contact with the first region on the outermost periphery and is adjacent to the first region through the groove;
A fourth region of a second conductivity type having a higher impurity concentration than the third region on the surface of the third region;
On the surface of the second semiconductor layer, the second conductivity type carrier extraction region that does not contact the fourth region and contacts the third region;
An insulating layer made of an insulating material formed on the surface of the carrier extraction region;
A gate electrode pad formed on the surface of the insulating layer and partially overlapping with the carrier extraction region when viewed from a direction perpendicular to the first main surface;
A first electrode made of metal in contact with the second region and the fourth region;
A second electrode made of metal in contact with the second main surface;
Equipped with a,
The groove extends from the surface of the first region in the surface of the second semiconductor layer to the second semiconductor layer,
The depth of the carrier extraction region from the surface of the second semiconductor layer in the vicinity of the third region is smaller than the depth of the groove from the surface of the second semiconductor layer. When viewed from the direction perpendicular to the surface, the depth of the carrier extraction region from the surface of the second semiconductor layer in the region overlapping with the gate electrode pad is the depth of the groove from the surface of the second semiconductor layer. and rot size than of,
The carrier extracting region, said third region and said fourth region semiconductors devices you characterized by being electrically connected to the first electrode through the. A first semiconductor layer having first and second main surfaces facing each other and made of a first conductivity type semiconductor;
A second semiconductor layer made of a first conductivity type semiconductor having an impurity concentration lower than that of the first semiconductor layer exposed at the first main surface;
A plurality of grooves formed on the surface of the second semiconductor layer;
A gate insulating film formed in the trench;
A gate electrode surrounded by the gate insulating film;
A first region of a second conductivity type formed between the two grooves on the surface of the second semiconductor layer;
A first conductivity type second region having a higher impurity concentration than the second semiconductor layer on the surface of the first region;
On the surface of the second semiconductor layer, a third region of a second conductivity type that is in contact with the groove that is in contact with the first region on the outermost periphery and is adjacent to the first region through the groove;
A fourth region of a second conductivity type having a higher impurity concentration than the third region on the surface of the third region;
On the surface of the second semiconductor layer, the second conductivity type carrier extraction region that does not contact the fourth region and contacts the third region;
An insulating layer made of an insulating material formed on the surface of the carrier extraction region;
A gate electrode pad formed on the surface of the insulating layer and partially overlapping with the carrier extraction region when viewed from a direction perpendicular to the first main surface;
A first electrode made of metal in contact with the second region and the fourth region;
A third semiconductor layer made of a semiconductor of the second conductivity type exposed on the second main surface;
A second electrode made of metal in contact with the third semiconductor layer;
Equipped with a,
The groove extends from the surface of the first region in the surface of the second semiconductor layer to the second semiconductor layer,
The depth of the carrier extraction region from the surface of the second semiconductor layer in the vicinity of the third region is smaller than the depth of the groove from the surface of the second semiconductor layer. When viewed from the direction perpendicular to the surface, the depth of the carrier extraction region from the surface of the second semiconductor layer in the region overlapping with the gate electrode pad is the depth of the groove from the surface of the second semiconductor layer. and rot size than of,
The carrier extracting region, said third region and said fourth region semiconductors devices you characterized by being electrically connected to the first electrode through the. 7. The gate insulating film according to claim 1, wherein a thickness of a portion formed on a bottom surface of the groove is larger than a thickness of a portion formed on a side wall surface of the groove . The semiconductor device according to any one of the above.

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