JPH01192174A - Manufacturing method of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to semiconductor devices, particularly power MO3FET (metal oxide semiconductor field effect transistor) alone or MOS incorporating a power MO3FET.
It relates to semiconductor devices such as ICs.

[Conventional technology]

Power MO3FETs have been used in many industrial fields in recent years because they have many features such as excellent frequency characteristics, high switching speed, and can be driven with low power. For example, "Nikkei Electronics" May 19, 1986 issue, published by Nikkei McGraw-Hill, P165-P1
No. 88 states that the focus of the development of power MO3FETs is shifting to low-voltage products and high-voltage products. In addition, this document also describes the power MO3F with a withstand voltage of 100 V or less.
It has been stated that the on-resistance of ET chips has been lowered to the 10 mΩ level, and the reason for this is that the use of LSI microfabrication in the manufacture of power MOSFETs and the devising of the cell shape. It is stated that this is due to the fact that the channel width per unit area can be increased.

Additionally, this document states, ``The on-resistance of a low-voltage MO3FET is almost determined by the resistance of the channel part.The resistance of the channel part is
It can be made smaller by increasing the number of cells connected in parallel. For this reason, microfabrication comes into play. ” is also stated.

Furthermore, regarding the method of increasing cell density, there is the following description. In other words, ``A trench-type MO3FET is an effective method for increasing cell density.■ The trench-type MO3FET has been around for a long time.The sides of the trench serve as channels, and current flows in the vertical direction.Matsushita has developed a method to reduce the electric field at the tip of the trench. Therefore, a U-groove with a rounded tip of the V-groove is used to increase cell density and reduce on-resistance.

To further increase the cell density, trenches can be dug perpendicular to the St substrate. The U groove was not vertical. In this way, we developed a 171M03FET in which the pitch of adjacent vertical grooves was 17 μm. The on-resistance of a 50V (7) MOSFET with withstand voltage is 13 mΩ, and the product of on-resistance and area is 187 mΩ・mm. If the pitch of the grooves is set to 10 μm or less or the grooves are made deeper, the on-resistance will be further reduced. has been done.

On the other hand, in MOS memories, a trench capacitor, in which a capacitor is formed using a deep trench, has been developed as a structure that provides higher integration. For example, trench capacitors are covered in the monthly Semiconductor World published by Press Journal Co., Ltd.
emicon-ductor World)” 19B
October 1986 issue, published September 15, 1986, P65-P
69. This document describes the following problems in gate oxide film formation technology. In other words, ``The gate oxide film formation technology for trench capacitors boils down to how to suppress leakage current at the convex or concave corners that always exist.

There are two main reasons for the increase in leakage current at corners.

One is electric field concentration due to the corner itself, and the other is
One reason is that the oxide film formed at the corners becomes thinner. This can be countered by rounding off sharp corners immediately after trench processing by RIH. At rounded corners, thinning of the gate oxide film formed thereon is suppressed, and electric field concentration is also alleviated.

”.

[Problem to be solved by the invention]

In recent years, as power MOSFETs have progressed in miniaturization technology,
On-resistance has been reduced to the 10mΩ level. This miniaturization technology reduces the unit cell size of MOS FET to 20
This was achieved by reducing the size to about Iln. All companies are trending toward lower on-resistance (RoN) with lower withstand voltage 60
Although this is noticeable in the V to 100V class, due to miniaturization, there is a limit to cell reduction due to constraints on ensuring breakdown voltage characteristics in shallow junctions and photoresist of planar structure (DSA type).

FIG. 13 shows a cross-sectional structure of a conventional planar vertical MO3F'ET. A cell 1 of the 0M03FET is formed on a semiconductor substrate 2 of a first conductivity type, for example, n+ type silicon (St). A plurality of them are formed in regular alignment in the vertical and horizontal directions on the surface layer of the --shaped epitaxial layer 3.

A p-type well region 4 having a substantially rectangular shape is provided in the surface layer portion of the epitaxial layer 3. A plurality of well regions 4 are formed on the main surface of the semiconductor substrate 2 at regular intervals (C) in the vertical and horizontal directions. Therefore, on the main surface of the semiconductor substrate 2, the epitaxial layer 3 is formed with a width of C and in a lattice pattern.
becomes exposed, forming the drain surface layer portion 5.

Further, in the surface region of the well region 4, the well region 4
An n1 type source region 6 is provided in a ring shape along the periphery of the source region. Further, on the outer peripheral part of the well region 4, that is, in the lattice part along the drain surface layer part 5, a gate oxide wA7, a gate electrode 8 provided on this gate oxide film 7, and a gate electrode 8 and a gate oxide [! 7
An insulator 1II9 is provided to cover the. Further, a source electrode 10 is provided on the main surface of the semiconductor substrate 2, and a drain electrode (not shown) is provided on the back surface. The source electrode 10 has a structure in which it is in electrical contact with the source region 6 and the drain surface layer portion 5.

In such a MOS FET cell, the parts that restrict the cell size can be broadly divided into a to d.

a is the insulation distance between the gate and source, b is the channel length, and C
is the length of the drain region between the base junctions, and d is the length of the source contact. Among these, a and d are in the shortening direction due to miniaturization, but b.

C has an optimum length and is subject to restrictions due to element characteristics (breakdown voltage, on-resistance, etc.).

Therefore, the inventor of the present invention realized that if a power MOSFET cell is formed using a trench having the narrowest trench width, the size of the -layer cell can be reduced.

However, when a power MOSFET cell is directly formed using a conventional trench, the following problem occurs.

That is, as shown in FIG. 14, a gate oxide film (insulating film) 7 is formed on the inner wall of a trench 11 provided in a semiconductor substrate 2.
is provided, and then the gate electrode 8 is provided so as to overlap the gate oxide film 7 and fill the trench 11,
As mentioned above, in the trench 11 according to the conventional technology, the growth state of the insulating film is poor at the bottom corner (corner E) of the trench 11, and the quality of the film provided at the portion E is poor. (And the film thickness is also thin.)

As a result, the withstand voltage of the insulating film decreases, and breakdown occurs between the gate electrode 8 and the drain formed of the semiconductor substrate 2.

In addition, when a voltage is applied between the drain and the gate, the electric field concentrates on the substrate portion Et at the bottom corner of the trench, resulting in a decrease in breakdown voltage characteristics, which is the same problem as the conventional VMO3 structure, such as a decrease in breakdown strength as a whole. occurs.

An object of the present invention is to provide a semiconductor device having a structure that allows miniaturization of MOSFET cell dimensions.

Another object of the present invention is to provide a power MO3F with high breakdown resistance.
The goal is to provide ET.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the present invention Φ trench type vertical power MO3FET
In addition to providing a channel forming layer for forming a channel on the main surface of a semiconductor substrate serving as a drain,
A source region is provided in the surface layer of this channel forming layer. Further, a trench reaching the drain region is provided in the center of the source region, and a gate oxide film is provided on the inner wall of this trench. In this gate oxide film, the film thickness at the bottom of the trench is thicker than at the trench sidewalls. Furthermore, a gate electrode is provided on the gate oxide film so as to fill the trench. Furthermore, the surface of the gate electrode is covered with a tIA edge film, and a source electrode is provided on this insulating film to contact the source region and the channel forming layer.

[Effect]

According to the above-mentioned means, in the trench type vertical power MOSFET of the present invention, a trench reaching the drain is provided in the center of the source region provided on a partial surface of the channel forming layer provided on the drain. , and because this trench has a structure in which a gate electrode is provided with a gate oxide film interposed, the cell can be made smaller, the on-resistance can be lowered, and the chip size can be made smaller or higher. A high degree of integration can be achieved. Furthermore, in the trench type vertical power MOSFET of the present invention, the thickness of the gate oxide film provided on the inner wall of the trench is 4 to 6 times thicker than the thickness of the side wall of the trench. Even if the quality of the film is not necessarily good, the dielectric breakdown voltage is improved and the electric field concentration at the bottom corner of the trench is alleviated, thereby improving the dielectric breakdown voltage.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a vertical power MOSFE according to an embodiment of the present invention.
A perspective view showing a part of T, Figure 2 is the same (vertical power MO
Flowchart showing the manufacturing process of SFET, FIGS. 3 to 12 are diagrams showing each manufacturing step of vertical power MOSFET, FIG. 3 is a cross-sectional view of the wafer on which the source region is formed, and FIG. 5 is a cross-sectional view of a wafer with a trench provided therein, FIG. 5 is a cross-sectional view of a wafer with two layers of insulating films, and FIG. 6 is a cross-sectional view of a wafer showing a state in which the upper layer of the insulating film has been etched in a different direction. , FIG. 7 is a cross-sectional view of the wafer showing a state in which the insulating film at the bottom of the trench has been thickened by the LOCO3 method, FIG. FIG. 9 is a cross-sectional view of the wafer showing a state in which a gate oxide film is formed, FIG. 10 is a cross-sectional view of a wafer showing a state in which a polysilicon film is formed, and FIG.
The figure is a cross-sectional view of the wafer with gate electrodes formed.
FIG. 2 is a cross-sectional view of the wafer with a source electrode formed thereon.

The main part of the trench-type vertical power MOSFET of this embodiment, that is, the cell part, has a structure as shown in FIG. In the same figure, between - dotted chain line W
is the single cell 1 portion (cell length) in cross section, and the region surrounded by the dashed-dotted line frame is the single cell 1 portion seen in a plan view. Such a cell 1 consists of a single vertical power MO3
A large number of FETs are regularly arranged vertically and horizontally.

The cell 1 is provided on the main surface (upper surface) of a semiconductor substrate 2 made of silicon of the nx type (first conductivity type) and having a thickness of about 100 μm and an impurity concentration of about 10 cm −′. The main surface of 2 has an impurity concentration of 10"cm-
An N7 type epitaxial layer 3 with a thickness of about 5 am to 10 μm is provided on the epitaxial layer 3, and a 31 m thick p type epitaxial layer with an impurity concentration of about 10'7 cm-'' is provided on this epitaxial layer 3. A channel forming layer 20 is provided.The main surface of the semiconductor substrate 2, that is, the surface layer of the channel forming layer 20 has an impurity concentration of 1O"cm.
A source region 6 of about -' is provided. The source region 6 is provided in a grid pattern on the main surface of the semiconductor substrate 2. Further, the width of the source region 6 is about 7 μm, and the pitch of the source region is about 10 tIm. Further, the source region 6 has a depth of 0.5 μm.

On the other hand, a trench (deep groove) 11 is provided along the center of the source region 6. This trench 11 has a width of 1 μm and a depth of the channel forming layer 2.
The thickness is, for example, 5 μm so as to penetrate through 0 and reach the epitaxial layer 3 on the surface layer of the semiconductor substrate 2. Also,
A gate oxide film 7 is provided in this trench 11 so as to cover the inner wall of the trench 11 . This gate oxide film 7 has a thickness of 500 on the side walls of the trench 11 and 2000 on the bottom of the trench 11.
There are o people. Furthermore, a gate electrode 8 made of polysilicon is provided in the trench 11 so as to overlap the gate oxide film 7 and fill the trench 11. Further, an insulating film 21 is formed on the trench 11 with a certain width.
is provided.

This insulating film 21 has a thickness of 6,000 people, for example.
It is made of (phosphosilicate glass) and covers the gate electrode 8 as well as extends slightly from the edge of the trench 11 to cover a part of the source region 6 as well. In addition, the insulation II! 21 and source area 6
Also, on the surface of the exposed channel forming layer 20, aluminum (Au) having a thickness of about 3 μm to 3.5 μm is coated.
A source electrode 10 is provided. Further, a drain electrode 22 having a thickness of several μm is provided on the back surface (lower surface) of the semiconductor substrate 2.

In such a trench type vertical power MOSFET, a gate oxide film 7 is provided on the side wall of the trench 11,
Moreover, since the gate electrode 8 is embedded in the trench 11, the cell size (W) can be set to 10 μm. As a result, the on-resistance of the low voltage power MO3FET can be reduced to 2 to 3 mΩ. Further, by reducing the cell size, the power MO3FET chip can be made smaller or more highly integrated (increase in the number of cells).

Further, in this trench type vertical power MO3FET, the gate electrode 8 is provided in the narrow and deep trench 11, but the gate oxide film 7 provided on the inner wall surface of the trench 11 is
Trench 1 other than the gate oxide film directly involved in ET operation
The bottom part of the gate oxide film 1 (hereinafter also referred to as the thick film insulating film 19 for convenience of explanation) has a thickness of 4 to 6 times as large as that of the gate oxide film 7, which is directly involved in FET operation. Since the thickness is increased to 2,000 to 3,000 layers, the withstand voltage of the gate oxide film is improved. Generally, the intrinsic oxide film breakdown voltage is 8 MV/cm to 10 MV/c
However, it is expected that the withstand voltage will be reduced by half or less at the bottom of the trench due to the deterioration of the film quality. Therefore, simply doubling the film thickness can bring the withstand voltage close to that of the intrinsic oxide film. In this example, the thickness of the gate oxide film 7 at the bottom of the trench 11 is four to six times thicker than the thickness of the side wall of the trench 11, so that the intrinsic oxide film breakdown voltage is sufficient.

Further, according to this structure, the electric field between the gate and the drain is relaxed by increasing the thickness of the gate oxide film at the bottom of the trench, and as a result, the drain breakdown voltage is improved.

Furthermore, in this example, the breakdown resistance is also improved due to the increase in the gate breakdown voltage and the drain breakdown voltage.

Next, such a trench-type vertical power MOSFE
The method for manufacturing T will be explained.

The cell part of the trench type vertical power MOSFET is
As shown in the flowchart in the figure, the semiconductor device is manufactured through the following steps: epitaxial growth, source region formation, trench formation, trench bottom insulating film thickening, gate oxide film formation, gate electrode formation, and drain 1i electrode formation.

In manufacturing a trench type vertical power MOS FET, as shown in FIG. A thin plate) 23 is prepared. The semiconductor substrate 2 has a thickness of about 400 μm and an impurity concentration of 10” cm−’. The epitaxial layer 3 has a thickness of 5 μm−10 cm−1.
The impurity concentration is about 10”c.
m-''.A channel forming layer 20 with a thickness of 3 μm is provided on the main surface of this semiconductor substrate 2, that is, on the epitaxial layer 3.

Further, in the surface layer part of this channel forming layer 20, n
A ◆-shaped source region 6 is provided. This source region 6 has a width of 7 μm and a depth of 0.5 μm.
m. Further, the impurity concentration of this source region 6 is 10"cm-". Further, the pitch (W) of the source regions 6 provided in a lattice shape is 10 μm. This pitch W becomes the length of a single cell 1.

Next, as shown in FIG. 4, an insulating film 24 is provided on the main surface of the wafer 23, and a trench (deep groove) 11 is formed along the center of the source region 6 by conventional photolithography. Ru. This trench 11 is
Since they are provided along the center of the source region 6, they are provided in a grid pattern on the main surface of the wafer 23. Then, a region surrounded by this trench 11, strictly speaking, a width region W extending over the center of the trench 11 becomes a single cell 1. The trench 11 has a groove width of 1 μm and a depth of 5 μm.
m, penetrates through the channel forming layer 20 below the source region 6 and reaches the epitaxial layer 3. Note that when forming this trench 11, etching conditions were selected so that a portion of the bottom corner of the trench 11 was rounded.
The insulating film to be formed later is to be prevented as much as possible from becoming thinner at some corners or from deteriorating in film quality.

Next, the insulating film 24 is removed. Thereafter, as shown in FIG. 5, the main surface of the wafer 23 is provided with a 400-thick Si, N4 film 25 and a 1200-thick Si, N4 film 26 overlaid on the 5iO1 film 25. Thereafter, the Si, N, and film 26 portions along the main surface of the wafer 23 are etched by anisotropic etching (plasma etching). As a result, as shown in Figure 6,
5t3N on the main surface of the wafer 23 and the bottom surface of the trench 11
The 5isN4 film 26 is removed, and the 5isN4 film 26 remains only on the substantially vertically extending sidewall surfaces of the trench 11.

Next, oxidation treatment (LOCO3 method) is performed in this state. That is, as a result of the oxidation treatment, the wafer 23 is
As shown in the figure, the main surface of the wafer 23 and the bottom surface of the trench 11 have SiO of 200.0 to 3000.
g film is formed. Because this thick Sing film portion (thick film insulating film 19) is processed by Lacos, both ends thereof, that is, a portion of the bottom corner of the trench 11, have a bird's beak structure, and the portion extending from the side surface of the trench 11 to the bottom of the trench 11 has a bird's beak structure. The thickness of the 5isN4 film 26 gradually increases.

Note that this structure in which the insulating film gradually thickens from the sides of the trench to the bottom remained even when the SisNm film 26 and the top 26 iO□ film 25 on the sides of the trench 11 were removed and the gate oxide film was formed again. This arises from a balance with the thick insulating film 19, and this leads to an improvement in the withstand voltage at the bottom corner of the trench 11.

Next, as shown in FIG.
126 and side surfaces of trench 11 (7) Stow film 25
Remove by etching. The Si, N, and film 26 are etched using a hot phosphoric acid etchant, and the thick insulating film 19 is etched using a hydrofluoric acid etchant. As a result of this series of etching, the thick insulating film 19 at the bottom of the trench 11 and the S i O*ll 1125 on the main surface of the wafer 23 remain.

Next, as shown in FIG. 9, an insulating film made of a Si film having a thickness of 500 nm is again formed over the entire main surface of the wafer 23. The side surfaces of the trench 11 of this insulating film are used as the gate oxide film 7. The thickness of the thick insulating film 19 at the bottom of the trench 11 is 2000 to 3000, and is 4 to 6 times as thick as the gate oxide film 7 portion on the side surface of the trench 11. Also, from the side of trench 11, trench l
The gate oxide film 7 at a portion of the corner reaching the bottom of the gate oxide film 7 has a so-called bird's beak structure that gradually becomes thicker toward the bottom.

Next, as shown in FIG. 10, a polysilicon (Poly Si) film is deposited over the entire main surface of the wafer 23. At this time, boron (B♦) is doped at the same time. As a result, this polysilicon film 27 has a low electrical resistance value. Further, the polysilicon film 27 is formed in an amount sufficient to fill the trench 11 having a width of a little less than 1 μm.

Next, as shown in FIG. 11, the source region 6
The polysilicon film 27 on the Sing film 25 existing above the upper surface of the polysilicon film 25 is removed by etching. As a result, gate electrode 8 is formed in trench 11 using polysilicon film 27. Thereafter, as shown in FIG.
An insulating film 21 made of an SG (phosphosilicate glass) film is formed by CVD technology and conventional photolithography. Both sides of this insulating film 21 protrude beyond the edge of the trench 11 and extend over the source region 6 on the trench 11 side.

Next, as shown in FIG. 12, aluminum (
AIL) is deposited to form a source electrode 10 made of AIL. Thereafter, the back surface (lower surface) of the wafer 23 is etched. By this etching, the semiconductor substrate 2
has a thickness of about 100 μm.

Next, a drain electrode is formed on the back surface of the wafer 23. This allows trench-type vertical power MOSF
Manufacturing of ET cell 1 is completed.

Such a trench-type vertical power MO3FET has the following effects. (1) The trench-type vertical power MO3FET of the present invention has the following advantages: The trench has a structure in which a gate electrode is provided at the bottom, and the side surface of the trench is used as a channel, and the width of the trench is 1 μm.
m and extremely narrow, the cell size can be reduced to 10 μm.
This has the advantage that it can be made smaller.

(2) According to the above (1), since the trench type vertical power MO3FET of the present invention can have a cell size as small as 10 μm, it is possible to reduce the on-resistance to 2 to 3 mΩ.

(3) According to (1) above, the trench-type vertical power MOSFET of the present invention has the effect that the cell size can be reduced, so that the vertical power MOSFET chip can be made smaller.

(4) According to the above (1), the trench type vertical power MOSFET of the present invention has the effect that the cell size can be reduced, and therefore, the vertical power MOSFET can be highly integrated.

(5) The trench type vertical power MOSFET of the present invention is
The structure has a gate oxide film in the trench, but
The thickness of the gate oxide film at the bottom of the trench, that is, the insulating film, is 4 to 6 times the thickness of the gate oxide film that effectively operates the FET, so if a part of the bottom corner of the trench is Even if the quality of the insulating film is poor, it can be compensated for by changing the thickness, resulting in the effect that a desired intrinsic oxide film breakdown voltage can be obtained.

(6) According to (5) above, the trench-type vertical power MO3FET of the present invention has a gate oxide film at the bottom of the trench that is several thousand thicker, and the edge of the insulating film at the bottom has a bird's beak. Because of this structure, the thickness of the insulating film at a portion of the corner is thick, which results in the effect that electric field concentration is alleviated and deterioration of withstand voltage is less likely to occur.

(7) According to (1) and (6) above, the trench-type vertical power MOS FET of the present invention has the effect of improving the breakdown strength as a whole by improving the breakdown voltage of the gate oxide film and improving the breakdown voltage due to electric field concentration. can get.

(8) According to the above (1) to (7), according to the present invention, a synergistic effect can be obtained in that a small vertical power MO3FET with high electrostatic breakdown resistance and low on-resistance can be provided.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, a method of increasing the thickness of the gate oxide film (insulating film) at the bottom of the trench may be to directly implant oxygen into the bottom of the trench 11.

In the above explanation, we have mainly explained the case where the invention made by the present inventor is applied to the manufacturing technology of trench-type vertical power MOSFET, which is the field in which the invention has become popular, but it is not limited to this. The present invention can be applied to manufacturing semiconductor devices using such trenches, such as trench capacitors.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

Since the trench type vertical power MO3FET of the present invention has a structure in which a gate electrode is provided with a gate oxide film interposed in the trench, the cell can be made smaller and the on-resistance can be reduced. Further, since this vertical power MOSFET allows the cell to be made smaller, it is possible to achieve smaller chip size or higher integration of the power MOSFET chip. In addition, in the trench type vertical power MOSFET of the present invention, the thickness of the gate oxide film provided on the inner wall of the trench is 4 to 6 times thicker than the thickness of the side wall of the trench. At the same time, electric field concentration at the bottom corner of the trench is alleviated, and the dielectric breakdown strength is improved as a whole.

[Brief explanation of the drawing]

FIG. 1 shows a vertical power MO3FE according to an embodiment of the present invention.
FIG. 2 is a flowchart showing the manufacturing process of a vertical power MOSFET, FIG. 3 is a cross-sectional view of a wafer in manufacturing the cell part of a vertical power MO3FET, and FIG. 5 is a cross-sectional view of a wafer similarly provided with a trench, FIG. 5 is a cross-sectional view of a wafer similarly provided with two layers of insulating film, and FIG. 6 is a wafer showing a state in which the upper insulating film has been etched in a different direction. Figure 7 is a cross-sectional view of the trench '
Figure 8 is a cross-sectional view of the wafer showing the state where the insulating film on the bottom has become thicker. Figure 10 is a cross-sectional view of the wafer with a polysilicon film formed thereon, Figure 11 is a cross-sectional view of the wafer with a gate electrode formed, and Figure 12 is the same. A cross-sectional view of a wafer with a source electrode formed thereon, FIG. 13 is a schematic cross-sectional view showing the main parts of a conventional horizontal power MOSFET, and FIG. 14 is a trench-type vertical power MOSFET attempted by the present inventor.
FIG. 2 is a schematic diagram illustrating the breakdown of the trench bottom of SFET. DESCRIPTION OF SYMBOLS 1... Cell, 2... Semiconductor substrate, 3... Epitaxial layer, 4... Well region, 5... Drain surface layer part, 6... Source region, 7... Gate oxide film, 8・
... Gate electrode, 9... Insulating film, 10... Source electrode, 11... Trench, 19... Thick film insulating film, 20
... Channel forming layer, 21 ... Insulating film, 22 ...
Drain electrode, 23... wafer, 24... insulating film,
25...S i Oz film, 26... Si, N, film,
27...Polysilicon film.

Claims (1)

[Scope of Claims] 1. A semiconductor device having a trench provided on the main surface of a semiconductor substrate and an insulating film covering the inner wall surface of the trench, wherein the insulating film at the bottom of the trench is the same as the insulating film on the side wall of the trench. A semiconductor device characterized by being formed thicker than a film. 2. The insulating film at the bottom of the trench is at least 1.5 to 2 times thicker than the insulating film at the side wall of the trench. Semiconductor equipment. 3. A source consisting of a semiconductor substrate of a first conductivity type, a channel formation layer of a second conductivity type provided on the main surface of the semiconductor substrate, and a source of the second conductivity type provided partially on the surface of the channel formation layer. a trench provided in the center of the source region and reaching the substrate through the channel forming layer; a gate oxide film covering an inner wall surface of the trench; and a gate oxide film overlapping the gate oxide film and extending over the trench. a buried gate electrode, an insulating film covering the gate electrode and the trench, and a source region at the periphery of the trench, a source electrode in electrical contact with the source region and the channel forming region, and a source electrode provided on the back surface of the substrate. A semiconductor device characterized by having a drain electrode. 4. Claims characterized in that a layer with a low impurity concentration is provided over a certain thickness on the surface of the semiconductor substrate, and the channel forming layer is provided on this layer with a low impurity concentration. The semiconductor device according to item 3.