JP4783601B2 - Optoelectronic integrated circuit and manufacturing method thereof - Google Patents

Description

The present invention relates to a technique for manufacturing an optical element and a semiconductor integrated circuit on the same substrate, and in particular, an optical element such as a photodiode or an optical modulator and an InP heterojunction bipolar transistor as a semiconductor element on the same substrate. The present invention relates to an optoelectronic integrated circuit and a manufacturing method thereof .

  As an applied technology of a semiconductor device, there is a so-called opto-electronic integrated circuit (OEIC) in which a semiconductor element (electronic element) and an optical element are provided on the same substrate. As a specific example, there is an OEIC in which a heterojunction bipolar transistor (HBT) which is a kind of electronic element and an optical element are integrated on a semi-insulating substrate made of InP.

  In general, InP-based materials have excellent electronic properties such as high electron transport mobility and various band designs. In addition, the HBT has characteristics unique to bipolar, such as high current drive and a compact element size. Therefore, an InP-based HBT, which is an HBT provided on an InP substrate, combines the characteristics of the InP-based material and the bipolar transistor described above, and is an electronic device that is excellent in high speed and high integration.

  Further, InP-based semi-insulating substrates are generally used when manufacturing long-wavelength optical elements. Accordingly, the InP-based HBT has an advantage that it can be integrated with an optical element for a long wavelength on an InP-based crystal substrate manufactured by an epitaxial growth method.

  In recent years, research on OEIC in which the above-described InP-based HBT and optical elements are integrated on an InP-based substrate has been actively conducted. For example, an OEIC in which an InP-based HBT and a photodiode (Photodiode: PD) are integrated on an InP substrate has been reported (for example, see Patent Document 1). FIG. 7 shows a cross-sectional view of the OEIC 101 in which the InP-based HBT 103 and the PD 102 are integrated on this semi-insulating InP substrate. In the OEIC 101, the left side in FIG. 7 is a semiconductor element formation region (HBT formation region), and the right side is an optical element formation region (PD formation region). The OEIC 101 has the following configuration and characteristics.

  As shown in FIG. 7, in the OEIC 101, an InP-based HBT 103 and a UTC (Uni-Travelling-Carrier) -PD 102 share a semi-insulating InP substrate 104. The InP-based HBT 103 is provided on the semi-insulating InP substrate 104 via a collector contact layer 110 made of n-type InP. The InP-based HBT 103 has a collector layer 111 made of n-type InP, a base layer 112 made of p-type InGaAs, and an emitter layer 113 made of n-type InP. The collector contact layer 110 is provided with a collector electrode 114, the base layer 112 is provided with a base electrode 115, and the emitter layer 113 is provided with an emitter electrode 116.

  As shown in FIG. 7, the PD 102 includes an anode contact layer 107 made of p-type InGaAs, a light absorption layer 106a made of p-type InGaAs, and an electron transit layer 106b made of n-type InP.

  This OEIC is characterized by a full regrowth technique for InP-based HBTs. First, an epitaxial structure of PD is grown on an InP substrate, and mesa etching is selectively performed. The cathode contact layer is exposed and an InP-based HBT collector layer, base layer, and emitter layer are regrown on the entire surface. Thereafter, HBT and UTC-PD are formed. Since the epitaxial layers of InP-based HBT and PD are grown separately, it is possible to optimize each epitaxial layer structure independently. Further, since the entire surface regrowth is used, there is almost no composition transition region of the epitaxial layer which becomes a problem in the selective regrowth.

Therefore, the physical closest distance between the HBT and PD can be shortened to about 5 μm. In other words, the OEIC can be integrated while optimizing the performance of the HBT and PD, so that the operation speed is high and the light receiving sensitivity is high.
Japanese Patent Application No. 2005-024116

  However, in the above-described OEIC, since the HBT is provided in the [01-1] direction with respect to the PD, a reverse mesa-shaped groove is formed between the HBT and the PD. The groove has a height of about 1 μm and a width of several tens of μm.

  Although an interlayer insulating film 118 (BCB: Benzocyclobutene) is applied by about 1 μm, it is difficult to achieve sufficient planarization because the step and width of the groove are in units of μm. Therefore, there is a problem of reflection of an electric signal due to disconnection or a step of the wiring 117 formed on the BCB. Furthermore, the HBT needs to be separated from the PD by a distance equal to or larger than the width of the groove, which causes a problem of wiring delay.

  The present invention has been made in order to solve the above-described problems. The object of the present invention is to achieve a high degree of integration, which is a feature of full-surface regrowth in which HBT and PD are connected without deterioration of electrical signals. An object of the present invention is to provide an OEIC excellent in operating speed and light receiving sensitivity without impairing the above.

According to the optoelectronic integrated circuit of the present invention, a plurality of semiconductor layers epitaxially grown on a semi-insulating InP substrate having a plane orientation of (100) are selectively etched to a depth at which the semi-insulating InP substrate is exposed. An optical element formed; an electronic element formed in the [011] direction of the semi-insulating InP substrate with respect to the optical element; and an interlayer insulating film that fills and planarizes the optical element and the electronic element. A wiring connected to the electronic element from an anode electrode or a cathode electrode provided on the uppermost semiconductor layer of the optical element and formed on the interlayer insulating film, and between the optical element and the electronic element wherein the semi-insulating InP substrate surface area of the (111) plane is exposed cross section is formed V-shaped groove, the electron said wiring is formed in [011] direction with respect to the optical element Contact the element It is characterized by Tei Rukoto.
Further, according to an aspect of the method for manufacturing an optoelectronic integrated circuit of the present invention, a semiconductor layer common to an optical element and an electronic element and a semiconductor layer for forming an optical element are formed on the surface of a semi-insulating InP substrate having a plane orientation of (100). A first step of forming an optical element forming region by selectively removing the semiconductor layer for forming the optical element by etching so that the common semiconductor layer is exposed except in a predetermined region, A semiconductor layer for forming an electronic device is epitaxially grown on the exposed semiconductor layer of the common layer, and then the semiconductor layer for forming an electronic device is etched to form an electrode, and the optical device forming region is A second step of forming an electronic element in the [011] direction of the semi-insulating InP substrate; and a third step of etching the semiconductor layer in the optical element formation region to form an electrode to form an optical element. A step of selectively removing the common semiconductor layer by etching to expose the semi-insulating InP substrate in order to electrically isolate the optical element and the electric element; and Forming an interlayer insulating film for embedding the element and the electronic element to planarize the surface, and then connecting the electrode provided on the uppermost semiconductor layer of the optical element and the electronic element on the surface of the interlayer insulating film And a fifth step of forming a wiring to be formed in the [011] direction.

  In the OEIC, the wiring connecting the HBT and the PD is formed without disconnection and without signal deterioration due to electric signal reflection, and at the same time, by providing the HBT in the [011] direction with respect to the PD, the HBT and the PD are formed. It is possible to make the physical closest distance of 5 μm to about 5 μm, and there is almost no possibility of causing a wiring delay.

  An optoelectronic integrated circuit (OEIC) according to the present invention will be described with reference to FIGS. FIG. 1 is a cross-sectional view of an OEIC 1 according to an embodiment of the present invention, and FIGS.

  In the present embodiment, the HBT is provided in the [011] direction with respect to the PD, thereby realizing a technique for realizing wiring reliability and shortening. With this technology, high reliability and high speed of the optical integrated circuit are achieved.

  That is, as shown in FIG. 1, in the OEIC 1, the right side of FIG. A photodiode (PD) 2 is provided as an optical element, and an HBT 3 is provided as a semiconductor element.

  PD2 and HBT3 are integrated on the same semi-insulating substrate 4 made of InP. The PD 2 includes a cathode contact layer 5 made of n-type InP, an active layer 6, and an anode contact layer 7 made of p-type InGaAs.

  The active layer 6 is composed of a traveling layer 6a made of gradient composition InGaAsP and n-type InP on the lower side and a light absorption layer 6b made of p-type InGaAs on the upper side. The cathode contact layer 5 is provided with a cathode electrode 8, and the anode contact layer 7 is provided with an anode electrode 9.

  On the other hand, the HBT 3 is integrated on the semi-insulating InP substrate 4 through the conductive layer 10 provided independently of the cathode contact layer 5 using the same material as the cathode contact layer 5. The conductive layer 10 becomes a collector contact layer.

  The HBT 3 includes a collector layer 11 made of inclined InGaAsP and n-type InP, a base layer 12 made of p-type InGaAs, and an emitter layer 13 made of n-type InP. The collector contact layer 10 is provided with a collector electrode 14, the base layer 12 is provided with a base electrode 15, and the emitter layer 13 is provided with an emitter electrode 16.

  The HBT 3 is provided in the [011] direction with respect to the PD 2, that is, in a direction perpendicular to the orientation flat (orientation flat) when the substrate orientation is (100). In the etching in the [011] direction, since the (111) plane that is difficult to etch is exposed, the substrate is hardly shaved in the lateral direction, and flattening by BCB is easy. Therefore, the wiring on the BCB is flattened and there is no concern about wiring disconnection.

  Next, the manufacturing process of the OEIC will be described with reference to FIGS. As shown in FIG. 2, on the semi-insulating InP substrate 4, a cathode contact layer 5 for forming PD2, an active layer 6 composed of a traveling layer 6a and a light absorption layer 6b, and an anode contact layer 7 are sequentially grown. Each of these layers is grown by at least one of a metal organic chemical vapor deposition method and a molecular beam epitaxial growth method. Next, a photoresist pattern (not shown) is formed on the anode contact layer 7 and dry etching and wet etching are performed to expose a part of the surface of the cathode contact layer 5. As a result, the anode contact layer 7, the light absorption layer 6b, and the traveling layer 6a are selectively removed sequentially to form an optical element formation region (photodiode formation region) A, that is, a region that defines PD2.

  Thereafter, the collector layer 11, the base layer 12, and the emitter layer 13 for forming the HBT 3 are sequentially grown on the exposed cathode contact layer 5. These layers are formed by overall regrowth. As a growth method, an MOCVD method or an MBE method is used.

  As shown in FIG. 3, after the emitter / base / collector mesa is formed in the semiconductor element formation region (HBT formation region) B, that is, the region defining the HBT 3, the emitter electrode 16, the base electrode 15, and the collector electrode 14 are formed. Form.

  As shown in FIGS. 4 and 5, a photoresist pattern 17 is formed in a region A that defines PD2, and anode / cathode mesa formation is performed by wet etching, so that an anode electrode 9 and a cathode electrode 8 are formed.

  At this time, a part of the substrate without the photoresist pattern between the HBT 3 and the PD 2 is exposed to the etching solution, but is hardly etched because the (111) surface that is difficult to be etched is exposed.

  Next, as shown in FIG. 5, in order to electrically separate HBT3 and PD2, a photoresist pattern 17-2 is formed, and the cathode contact layer 5 is selectively removed with a hydrochloric acid-based etchant. Thereby, the cathode contact layer 5 is etched in a V shape.

  Further, as the etching proceeds, the substrate 4 is also etched in a V shape as shown in FIG. 6, and a V-shaped groove 21 is formed. In general, InP-based materials have a reverse mesa shape in the [01-1] direction, that is, a direction parallel to the orientation flat (orientation flat), and a forward mesa shape in the [011] direction. This is because the [011] direction is etched in a V shape.

  Although a portion of the substrate 4 between the HBT 3 and the PD 2 has a region exposed to the etching solution, the (111) plane is exposed, so that the etching is performed only in the vertical direction of about 0.2 μm at most. Moreover, the lateral etching hardly progresses.

  Finally, as shown in FIG. 1, BCB is applied to the thickness of about 1 μm as the interlayer insulating film 18 and cured. Electrode through holes are formed, and wirings 19 are formed by Au plating. When the HBT 3 is provided in the [011] direction with respect to the PD 2, the substrate 4 therebetween is hardly etched (even if etched, about 0.2 μm in the vertical direction and hardly etched in the horizontal direction). It is sufficient, and high reliability of the wiring 19 can be expected. Furthermore, compared to the [01-1] direction, the width of the groove by etching is remarkably small, and the physical closest distance between the HBT 3 and the PD 2 can be shortened to 5 μm, which speeds up the optoelectronic integrated circuit. realizable.

  As is clear from the above-described embodiments, the OEIC according to the present invention is excellent in the high reliability of the wiring connecting the HBT and the PD and the high integration of the HBT and the PD.

  The optoelectronic integrated circuit according to the present invention is not limited to the above-described embodiment. Within a range that does not depart from the present invention, a part of the configuration and the like can be changed to various settings, or various settings can be appropriately combined and used.

  In the above-described embodiment, the wiring of the PD and the HBT has been described. However, the present invention is not limited to this. For example, the present invention may be applied to wiring connecting a PD and a resistor, and a PD and a MIM (Metal-Insulator-Metal) capacitor.

1 is a cross-sectional view illustrating an optoelectronic integrated circuit according to an embodiment of the present invention. It is process sectional drawing which shows the manufacturing method of the optoelectronic integrated circuit by embodiment of this invention. It is process sectional drawing which shows the manufacturing method of the optoelectronic integrated circuit by embodiment of this invention. It is process sectional drawing which shows the manufacturing method of the optoelectronic integrated circuit by embodiment of this invention. It is process sectional drawing which shows the manufacturing method of the optoelectronic integrated circuit by embodiment of this invention. It is process sectional drawing which shows the manufacturing method of the optoelectronic integrated circuit by embodiment of this invention. It is sectional drawing which shows the optoelectronic integrated circuit by a prior art.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Optoelectronic integrated circuit (OEIC), 2 ... Photodiode (PD), 3 ... Heterojunction bipolar transistor (HBT), 4 ... Semi-insulating substrate, 5 ... Cathode contact layer, 6 ... Active layer, 7 ... Anode contact layer 8 ... Cathode electrode, 9 ... Anode electrode, 10 ... Collector contact layer, 11 ... Collector layer, 12 ... Base layer, 13 ... Emitter layer, 14 ... Collector electrode, 15 ... Base electrode, 16 ... Emitter electrode, 17 ... Photo Resist pattern, 18 ... interlayer insulating film, 19 ... wiring, 21 ... groove

Claims (6)

An optical element formed by selectively etching a plurality of semiconductor layers epitaxially grown on a semi-insulating InP substrate having a plane orientation of (100) to a depth at which the semi-insulating InP substrate is exposed, and the optical element In contrast, an electronic element formed in the [011] direction of the semi-insulating InP substrate, an interlayer insulating film that fills and planarizes the optical element and the electronic element, and is formed on the interlayer insulating film. A wiring connected to the electronic element from an anode electrode or a cathode electrode provided in the uppermost semiconductor layer of the optical element ,
On the surface of the semi-insulating InP substrate in the region between the optical element and the electronic element, a groove having a V-shaped cross section with the (111) plane exposed is formed,
Optoelectronic integrated circuit in which the wiring is characterized in [011] Tei Rukoto connected are formed in a direction to the electronic device relative to the optical element. 2. The optoelectronic integrated circuit according to claim 1, wherein the electronic element is one selected from an InP heterojunction bipolar transistor, an InP heterojunction field effect transistor, a resistor, and a capacitor.   2. The optoelectronic integrated circuit according to claim 1, wherein the optical element is a photodiode or an optical modulator. A semiconductor layer common to the optical element and the electronic element and a semiconductor layer for forming the optical element are sequentially epitaxially grown on the surface of the semi-insulating InP substrate having a plane orientation of (100), and then the common layer except for a predetermined region is A first step of selectively etching away the semiconductor layer for forming an optical element so as to expose the semiconductor layer to form an optical element forming region;
A semiconductor layer for forming an electronic element is epitaxially grown on the exposed semiconductor layer of the common layer, then the semiconductor layer for forming an electronic element is etched to form an electrode, and the half of the semiconductor layer for forming the electronic element is formed with respect to the optical element forming region. A second step of forming an electronic element in the [011] direction of the insulating InP substrate;
Etching the semiconductor layer in the optical element formation region to form an electrode to form an optical element;
A fourth step of selectively removing the common semiconductor layer by etching to expose the semi-insulating InP substrate in order to electrically separate the optical element and the electric element;
Forming an interlayer insulating film for embedding the optical element and the electronic element to planarize the surface, and then forming an electrode provided on the uppermost semiconductor layer of the optical element on the surface of the interlayer insulating film; and the electronic element; A fifth step of forming a wiring for connecting in the [011] direction;
A method for manufacturing an optoelectronic integrated circuit, comprising: 5. The method of manufacturing an optoelectronic integrated circuit according to claim 4, wherein the electronic element is an InP heterojunction bipolar transistor or an InP heterojunction field effect transistor. 5. The method of manufacturing an optoelectronic integrated circuit according to claim 4, wherein the optical element is a photodiode or an optical modulator .

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