JP3705013B2 - Semiconductor element - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor element , and more particularly to a semiconductor element such as a semiconductor light receiving element having excellent high frequency characteristics .
[0002]
[Prior art]
Many semiconductor elements take the form of diodes or transistors, and electrodes are used to connect the semiconductor elements and external circuits. For example, there is a connection method using a bonding wire. However, in a semiconductor element that operates at a high frequency, a high-frequency signal is easily affected by an inductance generated by the bonding wire. In addition, the wire bonding method requires connection of wires for each electrode, resulting in variations in operating characteristics.
On the other hand, by changing to flip-chip mounting, it is possible to reduce the deterioration and variation of the operation characteristics at the electrode connection portion and to omit the wire bonding step. Therefore, the flip chip type mounting method is a particularly effective method for easily mounting a semiconductor element operating at a high frequency.
[0003]
As a feature of the semiconductor element corresponding to such flip-chip mounting, the p-type electrode and the n-type electrode are configured on the same plane.
[0004]
However, when a semiconductor element manufactured on a conductive substrate is used for flip chip mounting, degradation of frequency characteristics due to generation of parasitic capacitance becomes a problem. For example, when a semiconductor element is mounted as shown in FIG. 8, the parasitic capacitance is generated between the semiconductor element 801 and the ground plane 803 of the mounting circuit via the chip carrier 802.
As shown in the equivalent circuit of FIG. 9, the capacitance generated at this time is arranged in parallel with a capacitance 903 equivalent to the parasitic capacitance with respect to the semiconductor device 904 between the output terminal 901 to the external semiconductor device and the ground plane 905. As a result, the high frequency operation of the semiconductor element 904 is deteriorated.
[0005]
As a conventional technique of a semiconductor element that supports high-frequency operation and flip-chip mounting, there is a semiconductor light receiving element as shown in FIG. This semiconductor light-receiving element has a structure that is avoided by reducing the size of the operating element by forming the semiconductor element on the semi-insulating substrate 701 and removing the crystal growth layer other than the operating part of the semiconductor element by etching. Have.
[0006]
This semiconductor light receiving element includes a high-concentration p-type layer 702, a light absorption layer 703, a low-concentration n-type layer 704, an n-type cap layer 705, and an n-type contact layer 706 in order from the surface of the semi-insulating InP substrate 701. . The p-electrode 707 is drawn to the surface by step wiring, and corresponds to flip chip mounting. The pn junction area of this semiconductor light receiving element is formed at about 5 [μm] × 30 [μm], and the depletion layer thickness (the sum of the thicknesses of the light absorption layer and the low-concentration n-type layer) is about 0.5 [μm]. In this case, the element capacitance is about 0.03 [pF]. In this case, even a slight parasitic capacitance will affect the device characteristics. In order to avoid this, after the crystal growth on the semi-insulating substrate 701, the crystal growth layer other than the element operating portion is removed. As a result, a semiconductor element that is compatible with flip chip mounting and has a small parasitic capacitance generated during mounting can be obtained.
[0007]
[Problems to be solved by the invention]
However, in the semiconductor light receiving element as shown in the prior art, since the semi-insulating semiconductor substrate 701 and the high-concentration p-type layer 702 are adjacent to each other, the semi-insulating impurities in the semi-insulating semiconductor substrate 701 are high-concentration p. It diffuses into the mold layer 702. In particular, when zinc (Zn) is used as the p-type dopant and iron is used as the semi-insulating dopant, mutual diffusion is large, and the degree of diffusion of the semi-insulating dopant into the p-type layer 702 becomes remarkable. In such a case, there is a problem that the p-type conduction effect of the p-type layer 702 is impaired, the resistance is increased, and the frequency characteristics are impaired.
[0008]
The present invention has been made in view of the above problems, suppresses diffusion of semi-insulating impurities into a high-concentration p-type layer on a semi-insulating semiconductor substrate, and reduces the p-type conduction effect of the p-type layer. An object of the present invention is to provide a semiconductor device capable of preventing and improving the performance of a semiconductor device using a p-type layer .
[0009]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor device according to claim 1 is a semiconductor device having a p-type III-V group semiconductor layer on a semi-insulating InP substrate, and the semi-insulating InP substrate and the p-type III-V. A p-type buffer layer having an impurity concentration lower than that of the p-type group III-V semiconductor layer is interposed between the group-type semiconductor layer.
(However, the semi-insulating substrate uses Fe as a dopant, and the p-type buffer layer uses Be having a concentration of 1 × 10 ¹⁶ (/ cm ³ ) or less as a dopant , and the layer thickness is d [μm]. When the p-type impurity concentration is N (/ cm ³ ), the relationship of log ₁₀ (N) ≦ 16−ln (d) / ln (0.5) is satisfied.
[0012]
The semiconductor element according to claim 2 is configured to support flip-chip mounting.
[0017]
According to the invention having such a configuration, a crystal growth layer is formed on a semi-insulating semiconductor substrate, impurities on the surface of the semi-insulating semiconductor substrate are diffused into the crystal growth layer, and then the crystal growth layer is removed. A low-concentration semi-insulating doping layer with reduced impurities can be easily formed on the surface of the semi-insulating semiconductor substrate. Thus, a high-concentration p-type layer is provided on the semi-insulating semiconductor substrate, and a semi-insulating impurity from the semi-insulating semiconductor substrate to the high-concentration p-type layer is formed by a low-concentration semi-insulating doping layer interposed therebetween. Therefore, excellent high frequency characteristics can be provided.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of a semiconductor device of the present invention will be described with reference to the drawings.
[0019]
<First Embodiment>
FIG. 1 shows a cross-sectional structure of the semiconductor device according to the first embodiment of the present invention.
This semiconductor element is a semiconductor light receiving element having excellent high frequency characteristics. A low-concentration p-type layer 102 is formed on a semi-insulating semiconductor substrate 101, and a high-concentration p-type layer 103, a light absorption layer 104, a low-concentration n-type layer 105, an n-type cap layer 106, and an n-type contact layer 107 are formed thereon. Are stacked in this order.
The low-concentration p-type layer 102 is a buffer layer interposed between the semi-insulating semiconductor substrate 101 and the high-concentration p-type layer 103, and the high-concentration p-type layer 103 of semi-insulating impurities from the semi-insulating semiconductor substrate 101. It has a function to suppress diffusion to
[0020]
The semiconductor element is provided with a light receiving portion mesa 121, a p-electrode mesa 122, and an n-electrode mesa 123. The upper surface of the p-electrode mesa 122 is connected to the high-concentration p-type layer 103 where the p-electrode 108 is exposed. A SiNx film 110 is interposed between the p-electrode 108 and the side surface of the p-electrode mesa 122. An n electrode 109 is provided in contact with the n-type contact layer 107 on the light receiving portion mesa 121, and the n electrode 109 is separated from the other layers of the light receiving portion mesa 121 by a SiNx110 layer. Has been drawn to. Thus, the n-electrode 109 and the p-electrode 108 are provided on the surface side and have a structure corresponding to flip chip mounting.
[0021]
A method for manufacturing the semiconductor device of the first embodiment will be described.
As an apparatus for manufacturing, the MOVPE method (metal organic vapor phase epitaxy) or the MBE method (molecular beam epitaxy method) can be considered. The MBE method is suitable for preventing the influence of dopant diffusion because the growth temperature can be lowered.
[0022]
In the first embodiment, a low concentration p-type layer 102 is first grown on a semi-insulating semiconductor substrate 101. In the case where the substrate 101 is a Group III-group compound semiconductor, zinc, beryllium, magnesium, carbon, or the like can be considered as the p-type dopant.
Next, a high-concentration p-type layer 103 is formed, and then a light absorption layer 104, a low-concentration n-type layer 105, an n-type cap layer 106, and an n-type contact layer 107 are formed. The crystal growth layer in a region other than the operating portion of the semiconductor element is removed by etching. A mesa is formed by etching up to the high-concentration p-type layer 103, leaving the p-electrode mesa 120 drawn out by the light receiving region and the step wiring, and the high-concentration p-type layer 103 is exposed. The n-type contact layer 107 is formed by forming a light receiving portion mesa 121 by etching.
Finally, an n electrode 109 and a p electrode 108 are formed. The p-electrode 108 is drawn to the surface side by step wiring. As a result, the n-electrode 109 and the p-electrode 108 are configured in the same plane, and have a configuration corresponding to flip chip mounting.
[0023]
In the first embodiment, the diffusion amount of the semi-insulating dopant in the substrate can be reduced by forming the low concentration p-type layer 102 between the substrate 101 and the high concentration p-type layer 103. As the semi-insulating dopant, iron, ruthenium, cobalt, titanium and the like are conceivable when the substrate is a Group III-V compound semiconductor.
[0024]
In FIG. 2, the concentration of the p-type layer on the semi-insulating semiconductor substrate is changed (a: 1 × 10 ¹⁸ , b: 1 × 10 ¹⁷ , c: 1 × 10 ¹⁶ , d: 1 × 10 ¹⁵ / cm ³ ). The distribution map of the semi-insulating dopant concentration in the case where the layers are stacked together is shown.
The layer thickness of the p-type layer is 2 [μm]. The vertical axis indicates the concentration of the semi-insulating dopant and is logarithmic. It can be seen that as the concentration of the p-type layer is lowered, the degree of diffusion of the semi-insulating dopant from the semi-insulating substrate decreases.
Referring to this result, the condition of the low-concentration p-type buffer layer for preventing the influence on the upper high-concentration p-type layer is a layer having a P concentration of 1 × 10 ¹⁶ / cm ³ (c in the figure) or less. It can be concluded that a thickness of 0.5 [μm] or more is effective at a thickness of 1 [μm] or more, or a P concentration of 1 × 10 ¹⁵ / cm ³ (d in the figure) or less.
[0025]
If this condition is expressed by an equation, log ₁₀ (N) ≦ 16−ln (d) / ln (0.5) where N (/ cm ³ ) and the thickness of the low-concentration p-type layer are d [μm]. The combination of the density N and the layer thickness d is such that Of the materials lattice-matched to the material substrate of the low-concentration p-type layer, a wide gap material is preferable.
[0026]
The photodiode manufactured in this manner does not deteriorate the p-type conduction effect of the P concentration layer due to the diffusion of the semi-insulating dopant, reduces the series resistance component, and improves the frequency characteristics. In addition, since the upper electrode of the mesa forming the semiconductor element can be made n-type, even if the area of the element is reduced, an increase in contact resistance can be suppressed as compared with the case where the p-type electrode is on the upper part of the mesa. Good operating characteristics can be obtained.
[0027]
Next, examples of the first embodiment will be described.
AsH3 the group V material as a growth apparatus (arsine) were used PH ₃ (phosphine) GS-MBE method using a (gas source molecular beam epitaxy method). The growth temperature is 500 ° C. ± 20 ° C. As the semiconductor substrate 101, an iron-doped InP substrate is used. First, InP (layer thickness 2 [μm]) is formed as a low-concentration p-type layer 102 on the InP substrate 101. The P concentration is set to 5 × 10 ¹⁵ / cm ³ using Be as a dopant.
[0028]
Next, high-concentration p-type layer 103 (InAlAs, Be concentration: 1 × 10 ¹⁸ / cm ³ , layer thickness: 2 [μm]), light absorption layer 104 (InGaAs, undoped, layer thickness: 0.3 [μm]) , Low-concentration n-type layer 105 (InAlAs, undoped, 0.5 [μm]), n-type cap layer 106 (InAlAs, concentration: 2 × 10 ¹⁸ / cm ³ layer thickness: 1 [μm]), n-type contact layer 107 (InGaAs, concentration: 1 × 10 ¹⁹ / cm ³ , layer thickness: 0.5 [μm]) is formed. The crystal growth layer other than the operating portion of the element is removed by etching. Bromine / methanol is used as an etchant.
[0029]
Next, the light receiving portion mesa 121, the p-electrode mesa 122, and the n-electrode mesa 123 are formed by etching. The etching depth is up to the high concentration p-type layer 103. The size of the light receiving portion mesa 121 is 5 [μm] in width and 30 [μm] in length.
Next, a nitride film 110 is formed by plasma CVD. The nitride film 110 is opened with hydrofluoric acid for electrodes from the n-type contact layer 107 and the high-concentration p-type layer 103.
Finally, an n electrode 109 and a p electrode 108 are formed. In order to support flip chip mounting, both electrodes are stepped and pulled out to the surface.
[0030]
The photodiode manufactured in this manner has the same external dimensions as the device, and the crystal growth layer other than the device operating portion is removed by etching, so that parasitics generated between the device and the mounting substrate are generated. The capacity is small. Further, iron diffusion to the high-concentration p-type layer 103 on the substrate was suppressed, the p-type conduction effect was not deteriorated, the series resistance component was reduced, and the frequency characteristics during flip chip mounting were improved.
[0031]
Second Embodiment
FIG. 3 shows a cross-sectional structure of a semiconductor device according to the second embodiment of the present invention.
This semiconductor element is a semiconductor light receiving element having excellent high frequency characteristics. On the semi-insulating semiconductor substrate 201, a low-concentration semi-insulating doping layer 202, a high-concentration p-type layer 203, a light absorption layer 204, a low-concentration n-type layer 205, an n-type cap layer 206, and an n-type contact layer 207 are arranged in this order. Are stacked. The low-concentration semi-insulating doping layer 202 is a buffer layer interposed between the semi-insulating semiconductor substrate 201 and the high-concentration p-type layer 203, and the high-concentration p-type of semi-insulating impurities from the semi-insulating semiconductor substrate 201. It has a function of suppressing diffusion to the layer 203.
[0032]
The semiconductor element is provided with a light receiving portion mesa 221, a p-electrode mesa 222, and an n-electrode mesa 223. An upper surface of the p-electrode mesa 222 is provided connected to the high-concentration p-type layer 203 where the p-electrode 108 is exposed. A SiNx film 210 is interposed between the p-electrode 208 and the side surface of the p-electrode mesa 222. The n-electrode 209 is provided in contact with the n-type contact layer 207 on the light-receiving unit mesa 221, and the n-electrode 209 is separated from the other layers of the light-receiving unit mesa 221 by the SiNx210 layer, and the upper surface of the n-electrode mesa 223 Has been drawn to.
Thus, the n-electrode 209 and the p-electrode 208 are provided on the surface side, and have a structure corresponding to flip chip mounting.
[0033]
In this structure, the diffusion of the semi-insulating dopant into the high-concentration p-type layer 203 is suppressed by inserting the low-concentration semi-insulating doping layer 202 between the high-concentration p-type layer 203 and the semi-insulating semiconductor substrate 201. can do.
[0034]
FIG. 4 shows the state of diffusion of the semi-insulating dopant from the crystal growth layer to the substrate when the semi-insulating doping layer is grown on the p-type substrate. The vertical axis indicates the concentration of the semi-insulating dopant and is logarithmic. As the semi-insulating doping concentration is lowered (semi-insulating dopant concentration, a: 1 × 10 ¹⁷ , b: 5 × 10 ¹⁶ , c: 1 × 10 ¹⁶ , d: 5 × 10 ¹⁵ / cm ³ ) It can be seen that the diffusion of the semi-insulating dopant is suppressed. The thickness of the semi-insulating doping layer is 2 [μm].
[0035]
Referring to this result, in order to avoid the influence of the high-concentration p-type layer from the low-concentration semi-insulating doping layer, a high semi-insulating doping concentration of 1 × 10 ¹⁶ / cm ³ (c in the figure) is high. The layer thickness of the high-concentration p-type layer is 0.5 [μm] or more at a semi-insulating doping concentration of 1 × 10 ¹⁵ / cm ³ (d in the figure) at a layer thickness of 1 [μm] or more for the concentration p-type layer. It can be concluded that is particularly effective.
[0036]
As a result, the degree of interdiffusion of the semi-insulating dopant into the high-concentration p-type layer in the semiconductor element or the thermal diffusion of the semi-insulating dopant can be reduced, and the effect of p-type conduction of the high-concentration p-type layer can be reduced. Can be secured.
[0037]
A method for manufacturing a semiconductor device according to the second embodiment will be described.
As a method for forming the low-concentration semi-insulating doping layer 202, the MOVPE method or the MBE method can be considered. As the semi-insulating dopant, iron, ruthenium, cobalt, titanium and the like are conceivable when the substrate is a Group III-V compound semiconductor. As the material of the low-concentration semi-insulating doping layer 202, a semiconductor material lattice-matched to the substrate is used. The steps following the high concentration p-type layer 203 are the same as those in the first embodiment.
[0038]
An example of the second embodiment will be described.
As the semiconductor substrate 201, an iron-doped InP substrate is used. First, iron-doped InP is formed as a low concentration semi-insulating doping layer 202 on an InP substrate. The growth apparatus used was the MOVPE method. The iron-doped InP is formed with an iron concentration of 1 × 10 ¹⁶ / cm ³ and a layer thickness of 1 [μm]. Next, high-concentration p-type layer 203 (InAlAs, Be concentration: 1 × 10 ¹⁸ / cm ³ , layer thickness, 2 [μm]), light absorption layer 204 (InGaAs, undoped, layer thickness: 0.3 [μm]) , Low-concentration n-type layer 205 (InAlAs, undoped, 0.5 [μm]), n-type cap layer 206 (InAlAs, concentration 2 × 10 ¹⁸ / cm ³ layer thickness, 1 [μm]), n-type contact layer 207 (InGaAs, concentration 1 × 10 ¹⁹ / cm ³ , layer thickness 0.5 [μm]) is formed. The crystal growth layer other than the operating portion of the element is removed by etching. Bromine / methanol is used as an etchant.
[0039]
Next, the light receiving portion mesa 221, the p-electrode mesa 222, and the n-electrode mesa 223 are formed by etching. The etching depth is up to the high concentration p-type layer 203. The size of the light receiving portion mesa 221 is 5 [μm] in width and 30 [μm] in length.
Next, a nitride film 210 is formed by plasma CVD. The nitride film is opened with hydrofluoric acid for electrodes from the n-type contact layer 206 and the high-concentration p-type layer. Finally, an n electrode 209 and a p electrode 208 are formed. In order to support flip chip mounting, both electrodes are stepped and pulled out to the surface.
[0040]
The photodiode manufactured in this manner has the same external dimensions as the device, and the crystal growth layer other than the device operating portion is removed by etching, so that parasitics generated between the device and the mounting substrate are generated. The capacity is small. Further, iron diffusion to the P concentration layer on the substrate was suppressed, the p-type conduction effect was not deteriorated, the series resistance component was reduced, and the frequency characteristics during flip chip mounting were improved.
[0041]
<Third Embodiment>
FIG. 5 shows a cross-sectional structure of a semiconductor device according to the third embodiment of the present invention. This semiconductor element is a semiconductor light receiving element having excellent high frequency characteristics. On the semi-insulating semiconductor substrate 301, a low-concentration semi-insulating doping layer 302, a low-concentration p-type layer 303, a high-concentration p-type layer 304, a light absorption layer 305, a low-concentration n-type layer 306, an n-type cap layer 307, The n-type contact layers 308 are stacked in this order. The low-concentration semi-insulating doping layer 302 and the low-concentration p-type layer 303 are buffer layers interposed between the high-concentration p-type layer 304 and the semi-insulating semiconductor substrate 301, and semi-insulating from the semi-insulating semiconductor substrate 301. It has a function of suppressing the diffusion of conductive impurities into the high-concentration p-type layer 304.
[0042]
This semiconductor element is provided with a light receiving portion mesa 321, a p-electrode mesa 322, and an n-electrode mesa 323. The upper surface of the p-electrode mesa 322 is connected to the high-concentration p-type layer 304 where the p-electrode 309 is exposed. An SiNx film 311 is interposed between the p electrode 309 and the side surface of the p electrode mesa 322. An n-electrode 310 is provided in contact with the n-type contact layer 308 on the light-receiving unit mesa 321, and the n-electrode 310 is separated from other layers of the light-receiving unit mesa 321 by a SiNx311 layer, and an upper surface of the n-electrode mesa 323. Has been drawn to. Thus, the n-electrode 310 and the p-electrode 309 are provided on the surface side, and have a structure corresponding to flip chip mounting.
[0043]
A method for manufacturing a semiconductor device according to the third embodiment will be described.
This manufacturing method is characterized by a step of reducing the semi-insulating doping concentration on the surface of the substrate 301. A process diagram is shown in FIG. First, the crystal growth layer A340 is formed on the substrate 301 (FIG. 6A). A material that lattice-matches with the substrate 301 is used for the crystal growth layer A340. A material with a small band gap is desirable to promote diffusion. Zn (zinc) may be introduced as a dopant. Thereby, the diffusion of the semi-insulating dopant 350 into the crystal growth layer A340 can be promoted.
Next, heating is performed in a hydrogen atmosphere or a nitrogen atmosphere using a diffusion furnace, an alloy furnace, a crystal growth apparatus, or the like to diffuse the semi-insulating dopant 350 into the crystal growth layer A340 (FIG. 6B). In the case of crystal growth of a material having a large interdiffusion or a material in which the semi-insulating dopant is easily diffused, the diffusion step is not necessary. Next, the crystal growth layer A340 is removed by an etching process (FIG. 6c).
[0044]
On the surface of the semi-insulating substrate 301 that has been treated in this manner, the concentration of the semi-insulating dopant 350 decreases, and a low-concentration semi-insulating doping layer 302 is formed. After performing such processing, a semiconductor element is formed on the upper portion in the same manner as in the first and second embodiments, so that a parasitic capacitance generated at the time of flip chip mounting is small and a p-type series resistance is small. Can be obtained.
[0045]
Example 3 of the third embodiment will be described.
As the semiconductor substrate 301, an iron-doped InP substrate is used. As the crystal growth layer A340, p-type InGaAs is used. First, a crystal of p-type InGaAs 340 is grown on the InP substrate 301. The crystal growth apparatus uses a MOVPE apparatus, and the growth temperature is about 610 ° C. The thickness of the InGaAs layer is 2 [μm], the p-type concentration is 2 × 10 ¹⁸ / cm ³ , and the dopant is zinc (Zn). Next, the InGaAs layer is etched using nitric acid and hydrofluoric acid to remove the crystal growth layer.
[0046]
A low-concentration semi-insulating doping layer 302 is formed on the surface of the semi-insulating InP substrate 301 that has been treated in this manner. This time, the low concentration p-type layer 303 is formed using an MBE apparatus. The layer thickness is 2 [μm] and the concentration is 5 × 10 ¹⁵ / cm ³ . Next, high-concentration p-type layer 304 (InAlAs, Be concentration 1 × 10 ¹⁸ / cm ³ , layer thickness: 2 [μm]), light absorption layer 305 (InGaAs, undoped, layer thickness: 0.3 [μm]), Low concentration n-type layer 306 (InAlAs, undoped, 0.5 μm]), n-type cap layer 307 (InAlAs, concentration 2 × 10 ¹⁸ / cm ³ layer thickness, 1 [μm]), n-type contact layer 308 (InGaAs, Concentration 1 × 10 ¹⁹ / cm ³ and layer thickness 0.5 [μm]). The crystal growth layer other than the operating portion of the element is removed by etching. Bromine / methanol is used as an etchant.
[0047]
Next, a light receiving portion mesa 321, a p-electrode mesa 322, and an n-electrode mesa 323 are formed by etching. The etching depth is up to the high concentration p-type layer 304. The size of the light receiving portion mesa 321 is 5 [μm] in width and 30 [μm] in length.
Next, a nitride film 311 is formed by plasma CVD. The nitride film 311 is opened with hydrofluoric acid so as to be in contact with the n-type contact layer 308 and the high-concentration p-type layer 304 portion.
Finally, an n electrode 310 and a p electrode 309 are formed. In order to support flip chip mounting, both electrodes are stepped and pulled out to the surface.
[0048]
The photodiode manufactured in this manner has the same external dimensions as the device, and the crystal growth layer other than the device operating portion is removed by etching, so that parasitics generated between the device and the mounting substrate are generated. The capacity is small. Further, iron diffusion to the P concentration layer on the substrate was suppressed, the p-type conduction effect was not deteriorated, the series resistance component was reduced, and the frequency characteristics during flip chip mounting were improved.
[0049]
In the first to third embodiments, the semiconductor element portion above the p-type layer is a light receiving element. However, semiconductor elements such as a semiconductor optical modulator, a semiconductor laser, and a semiconductor optical amplifier are formed. Even in this case, the frequency characteristics during operation can be improved.
[0050]
【The invention's effect】
According to the semiconductor device of the present invention, by providing the buffer layer between the semi-insulating semiconductor substrate and the high-concentration p-type layer, the semi-insulating impurities in the semi-insulating semiconductor substrate are transferred to the high-concentration p-type layer. It is possible to suppress diffusion and prevent an increase in resistance of the p-type layer. As a result, the frequency characteristics are good.
[Brief description of the drawings]
FIG. 1 is a configuration diagram showing a cross-sectional structure of a first embodiment of a semiconductor device of the present invention.
FIG. 2 is a graph showing the degree of diffusion of a semi-insulating dopant from a substrate to a crystal growth layer on a semi-insulating semiconductor substrate in the first embodiment.
FIG. 3 is a configuration diagram showing a cross-sectional structure of a second embodiment of the semiconductor element of the present invention.
FIG. 4 is a graph showing the degree of diffusion of a semi-insulating dopant from a semi-insulating doping layer onto a substrate on a p-type semiconductor substrate in a second embodiment.
FIG. 5 is a configuration diagram showing a cross-sectional structure of a third embodiment of a semiconductor element of the present invention.
FIGS. 6A to 6C are flowcharts showing a process of forming a semi-insulating impurity doping layer according to a third embodiment.
FIG. 7 is a configuration diagram showing a cross-sectional structure of a conventional semiconductor element.
FIG. 8 is a perspective view showing flip chip mounting.
FIG. 9 is an equivalent circuit diagram for explaining generation of parasitic capacitance.
[Explanation of symbols]
101, 201, 301 Semi-insulating semiconductor substrate 102, 303 Low-concentration p-type layer 103, 203, 304 High-concentration p-type layer 104, 204, 305 Light absorption layer 105, 205, 306 Low-concentration n-type layer 107, 207, 308 n-type contact layers 108, 208, 309 P electrodes 109, 209, 310 n electrodes 110, 210, 311 SiNx films 202, 302 Semi-insulating doping layer

Claims (2)

In a semiconductor element having a p-type III-V semiconductor layer on a semi-insulating InP substrate,
A p-type buffer layer having an impurity concentration lower than that of the p-type group III-V semiconductor layer is interposed between the semi-insulating InP substrate and the p-type group III-V semiconductor layer. element.
(However, the semi-insulating substrate uses Fe as a dopant, and the p-type buffer layer uses Be having a concentration of 1 × 10 ¹⁶ (/ cm ³ ) or less as a dopant , and the layer thickness is d [μm]. When the p-type impurity concentration is N (/ cm ³ ), the relationship of log ₁₀ (N) ≦ 16−ln (d) / ln (0.5) is satisfied. The semiconductor device according to claim 1 , wherein the semiconductor device corresponds to flip chip mounting.

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