JP4782070B2 - Semiconductor integrated circuit device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effective when applied to a semiconductor integrated circuit device having a plurality of types of field effect transistors having different gate insulating film thicknesses.

  One of the technologies that support high integration of semiconductor memories is element isolation. In the element isolation of a semiconductor integrated circuit device using 0.25 micron technology such as a 64 Mbit random access memory (hereinafter abbreviated as DRAM), the conventional LOCOS (Local Oxidation Of Silicon) element isolation is different from that of a silicon substrate. So-called groove-type element isolation, in which a groove is formed in the element isolation region and a buried insulating film is formed in the groove to insulate and isolate the element formation regions, is being adopted in earnest. According to this groove type element isolation, it is possible to design an element isolation length of 0.3 microns or less, which was impossible in LOCOS element isolation, and to achieve a significant improvement in memory integration.

  On the other hand, due to the rapid penetration of portable devices such as PDA (Personal Digital Assistants) and electronic still cameras, in addition to conventional market needs such as low voltage and low power consumption, devices that have been conventionally formed on different chips At the same time, there is a growing demand for on-chip integration. As an example, a microcomputer incorporating a flash memory, a microcomputer incorporating a medium capacity DRAM, and the like have been commercialized.

  In these semiconductor integrated circuit devices in which devices having different functions are mixedly mounted, a plurality of types of field effect transistors having different operating voltages are mounted. For example, since a high voltage of 15 to 20 [V] is necessary for writing / erasing information to / from a flash memory, a part of the peripheral circuit has a thickness of 15 to 25 [nm] that can withstand the voltage application. A field effect transistor having a gate insulating film is used. A field effect transistor having a gate insulating film with a thickness of 7 to 10 [nm] is used in a logic circuit portion of a microcomputer that operates at a normal 3.3 [V]. Furthermore, in recent microcomputers with built-in flash memory using 0.25 micron technology, in order to realize high-speed operation with a low power supply voltage of about 1.8 [V], the thickness of the logic circuit section is 4 to 5 [nm]. When the field effect transistor having the gate insulating film is used and the input / output part can be adapted to 3.3 [V], the gate insulating film having a thickness of 3 levels and 4 to 5 [nm] is obtained as a result. A film (for 1.8 [V]), a gate insulating film having a thickness of 7 to 10 [nm] (for 3.3 [V]), and a gate insulating film having a thickness of 15 to 25 [nm] (for a flash memory) Need to form.

  The problems in the case where two types of gate insulating films having different thicknesses are separately formed on the two element forming regions of the silicon substrate insulated and isolated by the above-described trench type element separation are shown in FIGS. I will explain. 40 to 44 are cross-sectional views for explaining the prior art, FIGS. 40 to 42 are cross-sectional views along the gate length direction of the field effect transistor, and FIGS. 43 and 44 are the gate widths of the field effect transistor. It is sectional drawing which follows a direction. FIG. 45 is a diagram comparing the breakdown voltage distribution of the capacitor in the trench type element isolation and the breakdown voltage distribution of the capacitor in the LOCOS element isolation. FIG. 46 is a diagram comparing the sub-shresh characteristics of a field effect transistor in trench element isolation and the sub-shresh characteristics of a field effect transistor in LOCOS element isolation. In FIG. 45, the horizontal axis represents the capacitor gate applied voltage, and the vertical axis represents the cumulative number of defects. In FIG. 46, the horizontal axis represents the gate voltage, and the vertical axis represents the drain current.

  First, as shown in FIG. 40A, a groove 152 that defines the periphery of each of the first element formation region and the second element formation region is formed in the element isolation region of the main surface of the silicon substrate 151, and then Then, a buried insulating film 153 made of a silicon oxide film is formed in the trench 152 to perform trench type element isolation, and then, for introducing impurities into the first element forming region and the second element forming region. A channel insulating layer 155A for controlling a threshold voltage of a field effect transistor on each surface layer portion of the first element formation region and the second element formation region, Each of 155B is formed.

Next, after removing the buffer insulating film 154, a thermal oxidation process is performed, and as shown in FIG. 40B, 20 [nm] is formed on the first element formation region and the second element formation region. A gate insulating film 156 made of a thermal oxidation (SiO ₂ ) film having a thickness of about 1 is formed.

  Next, a mask 157 that covers the first element formation region and has an opening on the second element formation region is formed using a photolithography technique.

  Next, using the mask 157 as an etching mask, as shown in FIG. 41C, the gate insulating film 156 on the second element formation region is removed by a wet etching method using a hydrofluoric acid aqueous solution.

Next, after removing the mask 157, thermal oxidation treatment is performed, and as shown in FIG. 41D, thermal oxidation (SiO ₂ ) having a thickness of about 5 nm is formed on the second element formation region. A gate insulating film 158 made of a film is formed. By this step, the gate insulating film 156 and the gate insulating film 158 having different thicknesses are separately formed on the first element formation region and the second element formation region, which are insulated and separated by the trench type element separation. be able to.

  Next, a gate electrode 159 made of a polycrystalline silicon film into which an impurity is introduced is formed on each of the first element formation region and the second element formation region, and then, the first element formation region By forming a pair of semiconductor regions 160 as source and drain regions in the surface layer portion of the semiconductor device, and then forming a pair of semiconductor regions 161 as source and drain regions in the surface layer portion of the second element formation region. 42, field effect transistors Q12 and Q13 having different gate insulating film thicknesses are formed. The gate electrodes 159 of the field effect transistors Q12 and Q13 are formed in a shape in which both ends in the gate width direction are drawn out on the buried insulating film 153 as shown in FIGS.

  In the conventional gate insulating film formation according to the above-described prior art, when the gate insulating film 156 formed on the second element formation region is removed by the wet etching method, as shown in FIG. Since the buried insulating film 153 buried in the trench is also etched at the same time, a gap that exposes the side surface of the second element formation region at the end of the element isolation region between the second element formation region and the element isolation region. Will occur. According to the experiments by the present inventors, a step of 25 [nm] occurred with respect to the thickness of 4.5 [nm] of the gate insulating film formed on the second element formation region. There are two major problems due to this step.

  The first point is due to the concentration of mechanical stress at the stepped portion, and at the end of the element isolation region between the second element formation region and the element isolation region, as indicated by an arrow 162 in FIG. This is a problem that the gate insulating film 158 is thinned and the reliability of the gate insulating film 158 is deteriorated as a result. As shown in FIG. 45, 5 to 10% breakdown voltage deterioration was observed in the trench type element isolation.

  The second point is that, as indicated by an arrow 163 in FIG. 44, the channel implantation concentration in the vicinity of the bottom of the step on the side surface of the second element formation region is lower than the channel implantation layer 155B in the flat portion. This is a problem that the characteristics of the effect transistor Q13 fluctuate. As shown in FIG. 46, in the trench type element isolation, a phenomenon in which voltage-current characteristics commonly called kink change in the middle is seen, resulting in a decrease in threshold voltage of the field effect transistor Q13, The variation becomes a problem.

An object of the present invention is to provide a technique capable of improving the reliability of a semiconductor integrated circuit device having a plurality of types of field effect transistors having different gate insulating film thicknesses.
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
A first field effect transistor in which a gate insulating film is formed on a first element formation region on a main surface of a semiconductor substrate, and the first field effect on a second element formation region on a main surface of the semiconductor substrate. A method for manufacturing a semiconductor integrated circuit device, comprising: a second field effect transistor having a gate insulating film formed with a thickness smaller than that of a transistor gate insulating film, wherein the first element is formed on the main surface of the semiconductor substrate. Forming a thermal oxide film on the region and the second element formation region; then, forming a deposited film on the main surface of the semiconductor substrate including the thermal oxide film; and then forming the second element formation region The deposited film and the thermal oxide film on the top are removed, and then a thermal oxide film is formed on the second element formation region, and then on the first element formation region and the second element formation region. Forming a gate insulating film on each of the

  Each of the first element formation region and the second element formation region is insulated and isolated by a groove formed in an element isolation region on the main surface of the semiconductor substrate and a buried insulating film embedded in the groove. ing.

  According to the above-described means, when removing the deposited film and the thermal oxide film formed on the second element formation region, the buried insulating film is covered with the deposited film and is buried until the deposited film is removed. Since the buried insulating film is not etched, the etching amount of the buried insulating film can be reduced by an amount corresponding to the thickness of the deposited film 9. Therefore, the step generated at the end of the element isolation region between the second element formation region and the element isolation region can be alleviated, and deterioration of the gate breakdown voltage and characteristic variation of the field effect transistor due to the step can be avoided. As a result, the reliability of the semiconductor integrated circuit device can be improved.

  Further, as the ratio of the thickness of the deposited film to the thickness of the gate insulating film formed on the first element formation region is increased, the thermal oxide film formed on the second element formation region is increased. Since the thickness is reduced, the etching amount of the buried insulating film can be reduced. The etching amount of the buried insulating film increases in proportion to the thickness of the thermal oxide film.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
The reliability of a semiconductor integrated circuit device having a plurality of types of field effect transistors having different gate insulating film thicknesses can be improved.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment of the invention, and the repetitive description thereof is omitted.
(Embodiment 1)
In the present embodiment, an example in which the present invention is applied to a semiconductor integrated circuit device having two types of field effect transistors having different gate insulating film thicknesses will be described.

  FIG. 1 is a schematic plan view showing the configuration of two types of field effect transistors mounted on a semiconductor integrated circuit device according to the first embodiment of the present invention, and FIG. 2 is at the position of the AA line shown in FIG. 3 is a cross-sectional view taken along the line BB shown in FIG. 1, and FIG. 4 is a cross-sectional view taken along the line CC shown in FIG. In FIG. 1, the interlayer insulating film 19, the wiring 20, and the like, which will be described later, are not shown for easy viewing.

  As shown in FIGS. 1 and 2, the semiconductor integrated circuit device according to the present embodiment is configured mainly by a p-type semiconductor substrate 1 made of, for example, single crystal silicon.

  A plurality of element formation regions are formed on the main surface of the p-type semiconductor substrate 1. Each of the plurality of element formation regions is defined by a groove 4 formed in the element isolation region on the main surface of the p-type semiconductor substrate 1 and a buried insulating film 5 embedded in the groove 4 so as to be insulated from each other. Has been.

  Of the plurality of element formation regions, an n-type well region 7 is formed in the first element formation region, and a p-type well region 6 is formed in the second element formation region.

  A p-channel conductivity type field effect transistor Q1 is formed in the first element formation region of the main surface of the semiconductor substrate. The field effect transistor Q1 is formed of, for example, a p-channel type MISFET (Metal Insulator Semiconductor Field Effect Transistor), and mainly includes a channel implantation layer C1 for controlling a threshold voltage, a gate insulating film 10, a gate electrode 12, The source region and the drain region are a pair of p-type semiconductor regions 14 and a pair of p-type semiconductor regions 17.

  In the field effect transistor Q1, the channel implantation layer C1 is formed in the surface layer portion of the n-type well region 7 which is a channel formation region. The gate insulating film 10 is formed on the n-type well region 7, and the gate electrode 12 is formed on the gate insulating film 10. The gate electrode 12 is formed of a polycrystalline silicon film into which an impurity for reducing the resistance value is introduced. The pair of p-type semiconductor regions 14 are formed in the surface layer portion of the n-well region 7. The pair of p-type semiconductor regions 14 is composed of impurities introduced in a self-aligned manner with respect to the gate electrode 12. The pair of p-type semiconductor regions 17 is formed in the surface layer portion of the pair of p-type semiconductor regions 14. The pair of p-type semiconductor regions 17 is composed of impurities introduced in a self-aligned manner with respect to the sidewall spacers 16 formed on the side surfaces of the gate electrode 12 in the gate length direction. Compared to a higher impurity concentration.

  In the second element formation region on the main surface of the p-type semiconductor substrate 1, an n-channel conductivity type field effect transistor Q2 is formed. The field effect transistor Q2 is composed of, for example, an n-channel MISFET and mainly includes a channel implantation layer C2, a gate insulating film 11, a gate electrode 12, a source region and a drain region for controlling a threshold voltage. N-type semiconductor region 15 and a pair of n-type semiconductor regions 18.

  In the field effect transistor Q2, the threshold voltage control layer C2 is formed in the surface layer portion of the p-type well region 6 which is a channel formation region. The gate insulating film 11 is formed on the p-type well region 6, and the gate electrode 12 is formed on the gate insulating film 11. The gate electrode 12 is formed of a polycrystalline silicon film into which an impurity for reducing the resistance value is introduced. The pair of n-type semiconductor regions 15 is formed in the surface layer portion of the p-well region 6. The pair of n-type semiconductor regions 15 is composed of impurities introduced in a self-aligned manner with respect to the gate electrode 12. The pair of n-type semiconductor regions 18 is formed in the surface layer portion of the pair of n-type semiconductor regions 16. The pair of n-type semiconductor regions 18 is composed of impurities introduced by self-alignment with respect to the sidewall spacers 16 formed on the side surfaces of the gate electrode 12 in the gate length direction. Compared to a higher impurity concentration.

  In the field effect transistor Q1, for example, the operating voltage is set to 15 [V], and the thickness of the gate insulating film 10 is set to about 20 [nm]. The gate insulating film 10 is formed of a thermal oxide film 8 having a thickness of about 3 [nm] and a deposited film 9 having a thickness of about 17 [nm]. Thermal oxide film 8 is formed of a silicon oxide film formed by oxidizing the main surface of p-type semiconductor substrate 1. The deposited film 9 is formed of a silicon oxide film formed on the thermal oxide film 8 by using a chemical vapor deposition (CVD) method.

  In the field effect transistor Q2, for example, the operating potential is set to 1.8 [V], and the thickness of the gate insulating film 11 is set to about 5 [nm]. Unlike the gate insulating film 10, the gate insulating film 11 is formed of a thermal oxide film. This thermal oxide film is formed of a silicon oxide film formed by oxidizing the main surface of the p-type semiconductor substrate 1.

  As described above, the gate insulating film 10 of the field effect transistor Q1 is formed with a film thickness larger than that of the gate insulating film 11 of the field effect transistor Q2. Further, the field strength applied to the field effect transistor Q1 is configured to be higher than the field strength applied to the gate insulating film 11 of the field effect transistor Q2.

  A first-layer metal wiring 20 is electrically connected to each of the pair of p-type semiconductor regions 17 which are the source region and the drain region of the field effect transistor Q1 through a connection hole formed in the interlayer insulating film 19. ing. A first-layer metal wiring 20 is electrically connected to each of the pair of n-type semiconductor regions 18 which are a source region and a drain region of the field effect transistor Q2 through a connection hole formed in the interlayer insulating film 19. ing.

  As shown in FIG. 3, the gate electrode 12 of the field effect transistor Q1 is formed on the buried insulating film 5 at both ends in the gate width direction, and is formed on the interlayer insulating film 19 on one end side. The first-layer metal wiring 20 is electrically connected through the connection hole. As shown in FIG. 4, the gate electrode 12 of the field effect transistor Q2 is formed on the buried insulating film 5 at both ends in the gate width direction, and is formed on the interlayer insulating film 19 on one end side. The metal wiring 20 is electrically connected through the connection hole.

  Next, a method for manufacturing the semiconductor integrated circuit device will be described with reference to FIGS. 5 to 14 (cross-sectional views for explaining the manufacturing method).

  First, a p-type semiconductor substrate 1 made of, for example, single crystal silicon is prepared. The p-type semiconductor substrate 1 is formed with a resistivity of 10 [Ωcm].

  Next, a thermal oxidation process is performed to form a silicon oxide film 2 </ b> A on the entire main surface of the p-type semiconductor substrate 1.

  Next, a mask 3 made of a silicon nitride film is selectively formed in a region on the silicon oxide film 2A facing the first element forming region and the second element forming region on the main surface of the p-type semiconductor substrate 1. To do. The steps up to here are shown in FIG.

  Next, using the mask 3 as an etching mask, the element isolation region on the main surface of the silicon oxide film 2A and the p-type semiconductor substrate 1 is subjected to an etching process, so that a first element formation region and a second element formation region are obtained. Grooves 4 that define the perimeter of each are formed. The etching process is performed by anisotropic dry etching such as RIE (Reactive Ion Etching). The groove 4 is formed with a depth of about 0.3 [μm]. The steps up to here are shown in FIG.

  Next, a thermal oxidation process is performed to oxidize the inner surface of the groove 4 to form a silicon oxide film (not shown). This thermal oxidation treatment is performed for the purpose of removing crystal defects generated during the processing of the grooves 4.

  Next, a silicon oxide film 5A is formed on the entire surface of the p-type semiconductor substrate 1 so as to fill the trench 4 by a low pressure chemical vapor deposition (LPCVD) method. The steps up to here are shown in FIG.

  Next, by using a chemical mechanical polishing (CMP) method, the silicon oxide film 5A on the main surface of the p-type semiconductor substrate 1 is removed, and the buried insulating film 5 is formed in the trench 4. Form. In this step, the mask 3 is used as a stopper during chemical mechanical polishing.

  Next, a heat treatment for densifying the buried insulating film 5 is performed. This heat treatment is performed, for example, in an oxidizing atmosphere or an inert gas atmosphere. By this densification, the etching rate of the buried insulating film 5 approaches the etching rate of the thermal oxide film.

  Next, the mask 3 is removed by a wet etching method using a hot phosphoric acid solution, and then on the first element formation region on the main surface of the p-type semiconductor substrate 1 by a wet etching method using a hydrofluoric acid aqueous solution. Then, the silicon oxide film 2A remaining on the second element formation region is removed. Through this process, each of the first element formation region and the second element formation region includes the groove 4 formed in the element isolation region of the main surface of the p-type semiconductor substrate 1 and the buried portion embedded in the groove 4. The insulating film 5 is insulated and separated (electrically separated).

  Next, for example, a thermal oxidation process is performed, and a silicon oxide film having a thickness of about 10 [nm] is formed on the first element formation region and the second element formation region on the main surface of the p-type semiconductor substrate 1. A buffer insulating film 2B for introducing impurities is formed.

  Next, an impurity (for example, boron) is selectively introduced into the second element formation region on the main surface of the p-type semiconductor substrate 1 by ion implantation to form the p-type well region 6, and then the p-type An n-type well region 7 is formed by selectively introducing an impurity (for example, phosphorus) into the first element formation region on the main surface of the semiconductor substrate 1 by ion implantation. The steps so far are shown in FIG.

  Next, an impurity is selectively introduced into the surface layer portion of the p-type well region 6 by an ion implantation method to form a channel implantation layer C2 for controlling the threshold voltage, and then the n-type well region Impurities are selectively introduced into the surface layer portion 7 by ion implantation to form a channel implantation layer C1 for controlling the threshold pressure. The steps up to here are shown in FIG.

  Next, the buffer insulating film 2B is removed by a wet etching method using a hydrofluoric acid aqueous solution, and the surfaces of the first element formation region and the second element formation region on the main surface of the p-type semiconductor substrate 1 are exposed. .

  Next, thermal oxidation is performed to form a thermal oxide film 8 having a thickness of about 3 [nm] on the first element formation region and the second element formation region on the main surface of the p-type semiconductor substrate 1. To do. The thermal oxidation treatment is performed by a dry oxidation method that can control a thin film thickness and can generate a high-quality oxide film.

  Next, immediately after the formation of the thermal oxide film 8 using chemical vapor deposition, 17 [nm] is formed on the entire surface of the p-type semiconductor substrate 1 including the thermal oxide film 8 and the buried insulating film 5. ] A deposited film 9 made of a silicon oxide film having a thickness of about a thickness is formed. By this step, the gate insulating film 10 composed of the thermal oxide film 8 and the deposited film 9 is formed on the first element formation region. The steps up to here are shown in FIG.

  Next, a mask M10 is formed which covers the first element formation region of the main surface of the p-type semiconductor substrate 1 and has an opening on the second element formation region. The mask M10 is formed by a photolithography technique using a photoresist film. For example, as shown in FIGS. 1 and 11, the mask M <b> 10 is formed so that the end thereof is positioned on the buried insulating film 5.

  Next, using the mask M10 as an etching mask, the deposited film 9 and the thermal oxide film 8 on the second element formation region on the main surface of the p-type semiconductor substrate 1 are removed by a wet etching method. In this step, since the buried insulating film 5 is covered with the deposited film 9, the buried insulating film 5 is not etched until the deposited film 9 is removed. In normal wet etching, overetching of at least 10% of the film thickness is performed. Therefore, when the film thickness to be etched is 20 [nm], the etching amount is 22 [nm]. In the conventional technique, a step of 22 [nm] is generated at the end of the element isolation region between the second element formation region and the element isolation region. However, in this embodiment, the deposited film 9 is removed. Since the buried insulating film 5 is not etched until the step is completed, the level difference can be reduced to 5 [nm]. That is, by covering the buried insulating film 5 with the deposited film 9, the etching amount of the buried insulating film 5 can be reduced by an amount corresponding to the thickness of the deposited film 9. The steps up to here are shown in FIG.

  Next, after removing the mask M10 by ashing, a thermal oxidation process is performed by a dry oxidation method, and a thickness of about 5 nm is formed on the second element formation region of the main surface of the p-type semiconductor substrate 1. A gate insulating film 11 made of a thermal oxide film is formed. In this step, an extremely thin thermal oxide film is generated between the first element formation region on the main surface of the p-type semiconductor substrate 1 and the thermal oxide film 8. By this step, the gate insulating film 10 and the gate insulating film 11 having different thicknesses are formed. Further, the deposited film 9 is densified by this thermal oxidation treatment. A heat treatment for densifying the deposited film 9 may be applied in a separate process. This heat treatment is performed, for example, in an inert or oxidizing atmosphere. Thereby, the film quality of the gate insulating film 10 can be improved.

Next, the entire surface of the p-type semiconductor substrate 1 including the gate insulating film 11 and the gate insulating film 10 has a thickness of about 200 [nm] and an impurity concentration of about 4 × 10 ²⁰ [atoms / cm ³ ]. A polycrystalline silicon film is formed by chemical vapor deposition, and then a silicon oxide film 13 having a thickness of about 50 [nm] is formed on the entire surface of the polycrystalline silicon film by chemical vapor deposition.

  Next, the silicon oxide film 13 and the polycrystalline silicon film are sequentially patterned to form the gate electrode 12 on the gate insulating film 11 and the gate electrode 12 on the gate insulating film 10. To do. Each of the gate electrodes 12 is formed in a shape in which both end portions in the gate width direction are drawn out on the buried insulating film 5.

Next, boron as an impurity is selectively introduced into the first element formation region of the main surface of the p-type semiconductor substrate 1 by ion implantation, and then heat treatment is performed at 900 degrees Celsius for 20 minutes. A pair of p-type semiconductor regions 14 which are a source region and a drain region are formed. Boron is introduced under the condition that the final introduction amount is about 1 × 10 ¹³ [atoms / cm ² ] and the energy amount at the introduction is 50 [KeV]. The pair of p-type semiconductor regions 14 are formed in self alignment with the gate electrode 12 and the buried insulating film 5.

Next, phosphorus as an impurity is selectively introduced into the second element formation region on the main surface of the p-type semiconductor substrate 1 by ion implantation to form a pair of n-type semiconductor regions 15 as a source region and a drain region. To do. The introduction of phosphorus is performed under the condition that the final introduction amount is about 7 × 10 ¹² [atoms / cm ² ] and the energy amount at the introduction is 60 [KeV]. The pair of n-type semiconductor regions 14 are formed in self alignment with the gate electrode 12 and the buried insulating film 5. The steps so far are shown in FIG.

  Next, sidewall spacers 16 that cover the side surfaces of the gate electrode 12 are formed. The sidewall spacer 16 is formed by forming an insulating film made of a silicon oxide film on the entire surface of the p-type semiconductor substrate 1 by a CVD method, and then performing anisotropic etching such as RIE on the insulating film.

  Next, boron as an impurity is selectively introduced into the first element formation region on the main surface of the p-type semiconductor substrate 1 by ion implantation to form a pair of p-type semiconductor regions 17 as a source region and a drain region. To do. The pair of p-type semiconductor regions 17 are formed in a self-aligned manner with respect to the sidewall spacers 16 and the buried insulating film 5. By this step, the field effect transistor Q1 is almost completed.

  Next, phosphorus as an impurity is selectively introduced into the second element formation region on the main surface of the p-type semiconductor substrate 1 by ion implantation to form a pair of n-type semiconductor regions 18 as a source region and a drain region. To do. The pair of n-type semiconductor regions 18 are formed in a self-aligned manner with respect to the sidewall spacers 16 and the buried insulating film 5. By this step, the field effect transistor Q2 is almost completed. The steps so far are shown in FIG.

  Next, an interlayer insulating film 19 is formed on the entire main surface of the p-type semiconductor substrate 1, a connection hole is formed in the interlayer insulating film 19, and then a first layer is formed on the interlayer insulating film 19. By forming the wiring 20, the state shown in FIGS. 2, 3, and 4 is obtained.

Thus, according to the present embodiment, the following operational effects can be obtained.
Field effect transistor Q1 in which gate insulating film 10 is formed on the first element formation region on the main surface of p-type semiconductor substrate 1, and field effect on the second element formation region on the main surface of p-type semiconductor substrate 1 A method of manufacturing a semiconductor integrated circuit device having a field effect transistor Q2 in which a gate insulating film 11 is formed with a thickness thinner than that of the gate insulating film 10 of the transistor Q1, The thermal oxide film 8 is formed on the element formation region and the second element formation region, and then the deposition film 9 is formed on the main surface of the p-type semiconductor substrate 1 including the thermal oxide film 8, and then The deposited film 9 and the thermal oxide film 8 on the second element formation region are removed, and then the thermal oxide film is formed on the second element formation region, so that the gate insulating film 10 and the gate insulating film having different thicknesses are formed. 11 is formed. Each of the first element formation region and the second element formation region is formed by a groove 4 formed in the element isolation region on the main surface of the p-type semiconductor substrate 1 and a buried insulating film 5 embedded in the groove 4. Isolated.

  With this configuration, when removing the deposited film 9 and the thermal oxide film 8 formed on the second element formation region, the buried insulating film 5 is covered with the deposited film 9, and the deposited film 9 is removed. Since the buried insulating film 5 is not etched, the etching amount of the buried insulating film 5 can be reduced by an amount corresponding to the thickness of the deposited film 9. Therefore, the step generated at the end of the element isolation region between the second element formation region and the element isolation region can be alleviated, and deterioration of the gate breakdown voltage and characteristic variation of the field effect transistor due to the step can be avoided. As a result, the reliability of the semiconductor integrated circuit device can be improved.

  Further, as the ratio of the thickness of the deposited film 9 to the thickness of the gate insulating film 10 formed on the first element formation region increases, the thermal oxidation formed on the second element formation region Since the thickness of the film 8 is reduced, the etching amount of the buried insulating film 5 can be reduced. The etching amount of the buried insulating film 5 increases in proportion to the thickness of the thermal oxide film 8.

  Further, the gate insulating film 10 formed on the first element formation region is formed by the thermal oxide film 8 and the deposited film 9, and the gate insulating film 11 formed on the second element formation region is formed by the thermal oxide film. By forming, the buried insulating film 5 can be covered with the deposited film 9, so that the etching amount of the buried insulating film 5 can be reduced.

  In this embodiment, the thermal oxide film 8 is formed on the first element formation region and the second element formation region, and then the deposition film 9 is formed on the entire surface of the substrate including the thermal oxide film 8. However, the thermal oxide film 8 may be eliminated and the deposited film 9 may be formed directly on the first element formation region. The deposited film formed by the chemical vapor deposition method has a poor film quality (film quality at the interface between the deposited film and the substrate) compared to the thermal oxide film, and leak current is likely to occur, but the gate is formed on the second element formation region. When the thermal oxide film that is the insulating film 10 is formed, a thermal oxide film is also generated between the first element formation region (substrate 1) and the deposited film 9, and this thermal oxide film generates a leak current. Can be suppressed. The film thickness of the thermal oxide film generated between the first element formation region and the deposited film 9 is such that the thermal oxidation process when forming the thermal oxide film as the gate insulating film 10 on the second element formation region. Since it depends on time, a gate insulating film with little leakage current can be formed depending on the thickness of the thermal oxide film formed on the second element formation region. Therefore, the deposition film 9 is formed on the entire surface of the substrate including the first element formation region and the second element formation region, and then the deposition film 9 on the second element formation region is removed. A gate oxide film 11 and a gate insulating film 10 having different thicknesses may be formed by forming a thermal oxide film on the second element formation region. In this case, since the thermal oxide film 8 is not formed, the number of manufacturing steps can be reduced. In addition, when the deposited film 9 on the second element formation region is removed, only the deposited film 9 needs to be removed, so that the etching amount of the buried insulating film 5 can be further reduced.

  In this embodiment, the example in which the buried insulating film 5 is formed in the trench 4 by using the chemical mechanical polishing (CMP) method has been described. However, the buried insulating film 5 is formed by using the etch back method. May be.

(Embodiment 2)
In the present embodiment, an example in which the present invention is applied to a semiconductor integrated circuit device having three types of field effect transistors having different gate insulating film thicknesses will be described.

  FIG. 15 is a cross-sectional view showing the configuration of three types of field effect transistors mounted on the semiconductor integrated circuit device according to the second embodiment of the present invention.

  As shown in FIG. 15, the semiconductor integrated circuit device of the present embodiment has a configuration mainly including a p-type semiconductor substrate 21 made of, for example, single crystal silicon.

  A first element formation region, a second element formation region, and a third element formation region are formed on the main surface of the p-type semiconductor substrate 21. Each of the first, second, and third element formation regions is surrounded by a groove 24 formed in an element isolation region on the main surface of the p-type semiconductor substrate 21 and a buried insulating film 25 embedded in the groove 24. Are isolated from each other (electrically separated).

  A p-type well region 26 is formed in each of the first, second, and third element formation regions.

  An n-channel conductivity type field effect transistor Q3 is formed in the first element formation region. The field effect transistor Q3 is composed of, for example, an n-channel MISFET and mainly includes a p-type well region 26 used as a channel formation region, a gate insulating film 31, a gate electrode 34, a pair of source and drain regions. An n-type semiconductor region 36 and a pair of n-type semiconductor regions 40 are included. The n-type semiconductor region 40 is set to a higher impurity concentration than the n-type semiconductor region 36. In this field effect transistor Q3, the thickness of the gate insulating film 31 is set to about 25 [nm]. The gate insulating film 31 is formed of a thermal oxide film 27, a deposited film 28 and a deposited film 30.

  In the second element formation region, an n-channel conductivity type field effect transistor Q4 is formed. The field effect transistor Q4 is formed of, for example, an n-channel MISFET and mainly includes a p-well region 26 used as a channel formation region, a gate insulating film 32, a gate electrode 34, a pair of n regions that are a source region and a drain region. It comprises a type semiconductor region 37 and a pair of n type semiconductor regions 41. The n-type semiconductor region 41 is set to a higher impurity concentration than the n-type semiconductor region 37. In the field effect transistor Q4, the thickness of the gate insulating film 32 is set to about 12 [nm]. The gate insulating film 32 is formed of a thermal oxide film 29 and a deposited film 30.

  An n-channel conductivity type field effect transistor Q5 is formed in the third element formation region. The field effect transistor Q5 is composed of, for example, an n-channel MISFET and mainly includes a p-type well region 26 used as a channel formation region, a gate insulating film 33, a gate electrode 34, a pair of source and drain regions. An n-type semiconductor region 38 and a pair of n-type semiconductor regions 42 are included. The n-type semiconductor region 42 is set to a higher impurity concentration than the n-type semiconductor region 38. In the field effect transistor Q5, the thickness of the gate insulating film 33 is set to about 4 [nm]. The gate insulating film 33 is formed of a thermal oxide film.

  As described above, the gate insulating film 31 of the field effect transistor Q3 is formed to be thicker than the gate insulating film 32 of the field effect transistor Q4, and the gate insulating film 32 of the field effect transistor Q4 is formed of the gate of the field effect transistor Q5. The insulating film 33 is thicker than the insulating film 33. Further, the electric field strength applied to the gate insulating film 31 of the field effect transistor Q3 is configured to be higher than the electric field strength applied to the gate insulating film 32 of the field effect transistor Q4. The electric field strength applied to the film 32 is configured to be higher than the electric field strength applied to the gate insulating film 33 of the field effect transistor Q5.

  Next, a method for manufacturing the semiconductor integrated circuit device will be described with reference to FIGS. 16 to 22 (cross-sectional views for explaining the manufacturing method).

First, a p-type semiconductor substrate 21 made of, for example, single crystal silicon is prepared.
Next, using the method described in the first embodiment, the trench 24 is formed in the element isolation region of the main surface of the semiconductor substrate 21, and then the buried insulating film 25 is formed in the trench 24. The first element forming region, the second element forming region, and the third element forming region on the main surface of the p-type semiconductor substrate 21 are insulated and separated.

  Next, an impurity introducing buffer insulating film 22 is formed on the first element formation region, the second element formation region, and the third element formation region, and then the first, second, and second The n-type well region 26 is formed in each of the three element formation regions. The steps so far are shown in FIG.

  Next, the buffer insulating film 22 is removed by a wet etching method using a hydrofluoric acid aqueous solution, and the first element formation region, the second element formation region, and the third element on the main surface of the p-type semiconductor substrate 21 are removed. The surface of the formation area is exposed.

  Next, a thermal oxidation process is performed by a dry oxidation method, and a thermal oxide film 27 having a thickness of about 5 nm is formed on the first, second, and third element formation regions of the main surface of the p-type semiconductor substrate 1. Form.

  Next, immediately after the formation of the thermal oxide film 27 by using chemical vapor deposition, 13 [nm] is formed on the entire surface of the p-type semiconductor substrate 21 including the thermal oxide film 27 and the buried insulating film 25. ] A deposited film 28 made of a silicon oxide film having a thickness of about a thickness is formed. The steps so far are shown in FIG.

  Next, a mask M20 is formed which covers the first element formation region of the main surface of the p-type semiconductor substrate 21 and has openings on the second and third element formation regions. The mask M20 is formed by a photolithography technique using a photoresist film. For example, the mask M20 is formed so that the end thereof is positioned on the buried insulating film 25.

  Next, using the mask M20 as an etching mask, the deposited film 28 and the thermal oxide film 27 on the second and third element formation regions on the main surface of the p-type semiconductor substrate 1 are removed by wet etching. In this step, since the buried insulating film 5 is covered with the deposited film 28, the buried insulating film 25 is not etched until the deposited film 28 is removed. The steps so far are shown in FIG.

  Next, after removing the mask M20 by ashing, a thermal oxidation process is performed by a dry oxidation method, and about 5 [nm] is formed on the second and third element formation regions of the main surface of the p-type semiconductor substrate 1. A thermal oxide film 29 having a thickness of 5 mm is formed. In this thermal oxidation treatment step, the deposited film 28 is densified to improve the film quality. In addition, an extremely thin thermal oxide film is generated between the first element formation region on the main surface of the p-type semiconductor substrate 21 and the thermal oxide film 27.

  Next, immediately after forming the thermal oxide film 29 by using chemical vapor deposition, the entire surface on the p-type semiconductor substrate 21 including the deposited film 28, the thermal oxide film 29, and the buried insulating film 25. Then, a deposited film 30 made of a silicon oxide film having a thickness of about 7 [nm] is formed. By this step, the gate insulating film 31 including the thermal oxide film 27, the deposited film 28, and the deposited film 30 is formed on the first element formation region, and the thermal oxide film 29 and the deposited film 30 are formed on the second element formation region. A gate insulating film 32 made of is formed. The steps so far are shown in FIG.

  Next, a mask M21 is formed which covers the first and second element formation regions of the main surface of the p-type semiconductor substrate 21 and is open on the third element formation region. The mask M21 is formed by a photolithography technique using a photoresist film. For example, the mask M21 is formed so that the end thereof is positioned on the buried insulating film 25.

  Next, using the mask M21 as an etching mask, the deposited film 30 and the thermal oxide film 29 on the third element formation region on the main surface of the p-type semiconductor substrate 1 are removed by a wet etching method. In this step, since the buried insulating film 25 is covered with the deposited film 30, the buried insulating film 25 is not etched until the deposited film 30 is removed. The steps so far are shown in FIG.

  Next, after removing the mask M21 by ashing, a thermal oxidation process is performed by a dry oxidation method, and about 4.5 [nm] is formed on the third element formation region of the main surface of the p-type semiconductor substrate 1. A gate insulating film 33 made of a thermal oxide film having a thickness is formed. In this step, an extremely thin thermal oxide film is generated between the first element formation region and the thermal oxide film 27 and between the second element formation region and the thermal oxide film 29. Further, the deposited film 28 and the deposited film 30 are densified to improve the film quality. By this step, gate insulating films 31, 32, and 33 having different thicknesses are formed.

Next, a thickness of about 200 [nm] and 4 × 10 ²⁰ [atoms / cm ³ ] are formed on the entire surface of the p-type semiconductor substrate 21 including the gate insulating film 31, the gate insulating film 32, and the gate insulating film 33. A polycrystalline silicon film having an impurity concentration of about 50 nm is formed by chemical vapor deposition, and then a silicon oxide film 35 having a thickness of about 50 nm is formed on the entire surface of the polycrystalline silicon film by chemical vapor deposition. Form with.

  Next, the silicon oxide film 35 and the polycrystalline silicon film are sequentially patterned to form gate electrodes 34 on the gate insulating film 31, the gate insulating film 32, and the gate insulating film 33, respectively. . Each of the gate electrodes 34 is formed in a shape in which both end portions in the gate width direction are drawn out on the buried insulating film 25.

  Next, a pair of n-type semiconductor regions 36 is selectively formed by ion implantation in the first element formation region, and then a pair of n-type semiconductor regions 37 are ionized in the second element formation region. After selectively forming by the implantation method, a pair of n-type semiconductor regions 38 is selectively formed in the third element formation region by the ion implantation method. The steps so far are shown in FIG.

  Next, after forming a sidewall spacer 39 covering the side surface of the gate electrode 34, a pair of n-type semiconductor regions 40 is selectively formed in the first element formation region by an ion implantation method, and then A pair of n-type semiconductor regions 41 are selectively formed in the second element formation region by ion implantation, and then a pair of n-type semiconductor regions 42 are selected in the third element formation region by ion implantation. Form. By this step, the field effect transistors Q3, Q4 and Q5 are almost completed. The steps so far are shown in FIG.

  Next, an interlayer insulating film 43 is formed on the entire surface of the p-type semiconductor substrate 21, a connection hole is formed in the interlayer insulating film 43, and then a first layer wiring is formed on the interlayer insulating film 43. By forming 44, the state shown in FIG. 15 is obtained.

  In the present embodiment, the step generated at the end of the element isolation region between the third element formation region and the buried insulating film 25 was 15 [nm]. When the gate insulating films of the field effect transistors Q3 and Q4 are formed of normal thermal oxide films, the step in the element isolation region between the third element formation region and the buried insulating film 25 is 40 [nm]. Therefore, it was possible to reduce to about one third by the present invention. As a result, it was found that the threshold voltage drop of 0.3 [V] due to the kink seen in the sub-shresh characteristic of the field effect transistor Q5 can be suppressed, and the normal operation of the field effect transistor Q5 can be realized.

(Embodiment 3)
In the present embodiment, an example in which the present invention is applied to a microcomputer (semiconductor integrated circuit device) incorporating a flash memory will be described.

  FIG. 23 is a block diagram showing a schematic configuration of a microcomputer according to the third embodiment of the present invention.

  As shown in FIG. 23, the microcomputer 80 has a central processing unit, a control unit, a calculation unit, a storage unit, an input / output unit, and the like mounted on the same substrate. The central processing unit, the control unit, and the calculation unit are configured by a processor unit (CPU) 81. The input / output unit includes a data input / output circuit unit (I / O) 83. The storage unit includes a RAM unit 84 and a ROM unit 85. The RAM unit 84 is equipped with DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory). The ROM unit 85 is equipped with a flash memory. These units are connected to each other via an input / output data bus (I / O BUS) 87. The microcomputer 80 includes a power supply unit 86 and a clock oscillator 82.

  The processor unit 81 uses a field effect transistor that operates at 1.8 [V], and the data input / output circuit unit 83 operates at a field effect transistor that operates at 1.8 [V] and operates at 3.3 [V]. A field effect transistor is used, and a field effect transistor operating at 15 [V] is used for the power supply unit.

  Next, a specific structure of the microcomputer will be described with reference to FIG. 24 (sectional view). FIG. 24 shows a nonvolatile memory element (memory cell) constituting a flash memory of the ROM unit, a field effect transistor operating at 15 [V], and a field effect transistor operating at 1.8 [V].

  As shown in FIG. 24, the microcomputer 80 is mainly composed of a p-type semiconductor substrate 51 made of, for example, single crystal silicon.

  A plurality of element formation regions are formed on the main surface of the p-type semiconductor substrate 51. The periphery of each of the plurality of element formation regions is defined by a groove 54 formed in the element isolation region on the main surface of the p-type semiconductor substrate 51 and a buried insulating film 55 embedded in the groove 54. (Electrically separated).

  Of the plurality of element formation regions, a deep n-type well region 56 and a p-type well region 57 are formed in a first element formation region, and an n-type well region 58 is formed in a second element formation region. A p-type well region 57 is formed in the third element formation region.

  In the first element formation region, a nonvolatile memory element QF1 that performs a write operation and an erase operation by the tunnel effect is configured. The nonvolatile memory element QF1 mainly includes a p-type well region 57 used as a channel formation region, a gate insulating film (tunnel insulating film) 59, a floating gate electrode (floating gate electrode) 70, an interlayer insulating film 61, a control It comprises a gate electrode (control gate electrode) 66 and a pair of n-type semiconductor regions 71 which are a source region and a drain region.

  For example, data is written to the nonvolatile memory element QF1 by applying a predetermined voltage between the control gate electrode 66 and the drain region (one n-type semiconductor region 71) and stored in the floating gate electrode 70. The electrons are transferred by electron tunneling through the gate insulating film 59 from the floating gate electrode 70 to the drain region. For example, data in the nonvolatile memory element QF1 is erased by applying a predetermined voltage to the control gate electrode 66 to invert the channel formation region to n-type, and transferring the electrons in the inverted channel formation region to the floating gate electrode 70. Electron tunneling through the gate insulating film 59 is performed.

  In the second element formation region, a p-channel conductivity type field effect transistor Q6 operating at 15 [V] is formed. This field effect transistor Q6 is composed of, for example, a p-channel type MISFET, and mainly includes an n-type well region 58 used as a channel formation region, a gate insulating film 64, a gate electrode 68, a pair of source and drain regions. A p-type semiconductor region 72 and a pair of p-type semiconductor regions 75 are included. The p-type semiconductor region 75 is set to a higher impurity concentration than the p-type semiconductor region 72. In the field effect transistor Q6, the thickness of the gate insulating film 31 is set to about 20 [nm]. The gate insulating film 64 is formed of a thermal oxide film 62 and a deposited film 63.

  In the third element formation region, an n-channel conductivity type field effect transistor Q7 operating at 1.8 [V] is formed. The field effect transistor Q7 is composed of, for example, an n-channel MISFET and mainly includes a p-type well region 57 used as a channel formation region, a gate insulating film 65, a gate electrode 68, a pair of source and drain regions. An n-type semiconductor region 73 and a pair of n-type semiconductor regions 76 are included. The n-type semiconductor region 76 is set to a higher impurity concentration than the n-type semiconductor region 73. In the field effect transistor Q7, the thickness of the gate insulating film 65 is set to about 12 [nm]. The gate insulating film 65 is formed of a thermal oxide film.

  As described above, the gate insulating film 64 of the field effect transistor Q6 is formed with a film thickness larger than that of the gate insulating film 65 of the field effect transistor Q7. Further, the electric field strength applied to the gate insulating film 64 of the field effect transistor Q6 is configured to be higher than the electric field strength applied to the gate insulating film 65 of the field effect transistor Q7.

  Next, a manufacturing method of the microcomputer will be described with reference to FIGS. 25 to 32 (cross-sectional views for explaining the manufacturing method).

First, a p-type semiconductor substrate 51 made of, for example, single crystal silicon is prepared.
Next, using the method described in the first embodiment, a trench 54 is formed in the element isolation region on the main surface of the p-type semiconductor substrate 51, and then a buried insulating film 55 is formed in the trench 54. Then, the first element formation region, the second element formation region, and the third element formation region on the main surface of the p-type semiconductor substrate 51 are insulated and separated (electrically separated).

  Next, a thermal oxidation process is performed, and a thickness of about 10 nm is formed on the first element formation region, the second element formation region, and the third element formation region on the main surface of the p-type semiconductor substrate 51. An impurity introducing buffer insulating film 52 made of a silicon oxide film is formed.

Next, the deep n-type well region 56 is formed by selectively introducing phosphorus as an impurity into the first element formation region by an ion implantation method. The introduction of phosphorus is performed under the condition that the final introduction amount is about 1 × 10 ¹³ [atoms / cm ² ] and the energy amount at the introduction is 3000 [KeV].

Next, boron as an impurity is selectively introduced into the first element formation region and the third element formation region by an ion implantation method to form a p-type well region 57. Boron will be introduced in three steps. The first introduction is performed under the condition that the final introduction amount is about 1 × 10 ¹³ [atoms / cm ² ] and the energy amount at the introduction is 350 [KeV]. The second introduction is performed under the condition that the final introduction amount is about 3 × 10 ¹² [atoms / cm ² ] and the energy amount at the introduction is 130 [KeV]. The third introduction is performed under the condition that the final introduction amount is about 1.2 × 10 ¹² [atoms / cm ² ] and the energy amount at the introduction is 50 [KeV].

Next, phosphorus and boron as impurities are selectively introduced into the second element formation region by ion implantation to form an n-type well region 58. Phosphorus is introduced in three steps, and then boron is introduced. The first introduction of phosphorus is performed under the condition that the final introduction amount is about 1.5 × 10 ¹³ [atoms / cm ² ] and the energy amount at the introduction is 700 [KeV]. The second introduction of phosphorus is performed under the condition that the final introduction amount is about 3 × 10 ¹³ [atoms / cm ² ] and the energy amount at the introduction is 370 [KeV]. The third introduction of phosphorus is performed under the condition that the final introduction amount is about 1 × 10 ¹² [atoms / cm ² ] and the energy amount at the introduction is 180 [KeV]. Boron is introduced under the condition that the final introduction amount is about 1.5 × 10 ¹² [atoms / cm ² ] and the energy amount during introduction is 20 [KeV]. The steps up to here are shown in FIG.

  Next, the buffer insulating film 52 is removed by a wet etching method using a hydrofluoric acid aqueous solution, and the first element formation region, the second element formation region, and the third element on the main surface of the p-type semiconductor substrate 51 are removed. The surface of the formation area is exposed.

  Next, a thermal oxidation process is performed by a dry oxidation method, and a gate insulating film 59 made of a thermal oxide film having a thickness of about 10 [nm] is formed on the first element formation region on the main surface of the p-type semiconductor substrate 1. Form. In this step, a thermal oxide film is also formed on the second element formation region and the third element formation region.

Next, a floating layer made of a polycrystalline silicon film having a thickness of about 50 [nm] and an impurity concentration of about 4 × 10 ²⁰ [atoms / cm ³ ] is formed on the entire surface of the p-type semiconductor substrate 51 including the element formation region. The gate material 60 is formed by chemical vapor deposition.

  Next, using chemical vapor deposition, an oxide film having a thickness of about 4 [nm], a nitride film having a thickness of about 7 [nm], and a 4 [nm] on the entire surface of the floating gate material 60 are used. An interlayer insulating film 61 is formed by sequentially forming an oxide film having a thickness of about 1 nm and a nitride film having a thickness of about 11 nm. The steps so far are shown in FIG.

  Next, a mask M50 is formed, covering the first element formation region and opening the second and third element formation regions. The mask M50 is formed by a photolithography technique using a photoresist film.

  Next, using the mask M50 as an etching mask, the interlayer insulating film 61 and the floating gate material 60 are sequentially patterned. The steps so far are shown in FIG.

  Next, after removing the mask M50 by ashing, the thermal oxide film (gate insulating film 59) on the second element formation region and the third element formation region is removed by a wet etching method.

  Next, a thermal oxidation process is performed by a dry oxidation method, and a thermal oxide film 62 having a thickness of about 3 [nm] is formed on the second and third element formation regions. Thereafter, a chemical vapor deposition method is used to deposit a 17 nm thick silicon oxide film on the entire surface of the p-type semiconductor substrate 51 including the thermal oxide film 62 and the buried insulating film 55. 63 is formed. By this step, a gate insulating film 64 composed of the thermal oxide film 62 and the deposited film 63 is formed on the second element formation region. The steps so far are shown in FIG.

  Next, a mask M51 is formed which covers the second element formation region and is open on the first and third element formation regions. The mask M51 is formed by a photolithography technique. For example, the mask M51 is formed so that the end thereof is positioned on the buried insulating film 55.

  Next, using the mask M51 as an etching mask, the deposited film 63 and the thermal oxide film 62 on the third element formation region and the deposited film 63 on the interlayer insulating film 61 are removed by a wet etching method. In this step, since the buried insulating film 55 is covered with the deposited film 63, the buried insulating film 55 is not etched until the deposited film 63 is removed. The steps so far are shown in FIG.

  Next, after the mask M51 is removed by ashing, a thermal oxidation process is performed by a dry oxidation method, and a gate insulating film made of a thermal oxide film having a thickness of about 5 nm is formed on the third element formation region. 65 is formed. In this step, an extremely thin thermal oxide film is generated between the second element formation region on the main surface of the p-type semiconductor substrate 51 and the thermal oxide film 62. Further, the deposited film 63 is densified to improve the film quality. By this step, the gate insulating film 64 and the gate insulating film 65 having different thicknesses are formed.

Next, the entire surface of the p-type semiconductor substrate 51 including the gate insulating film 64 and the gate insulating film 65 has a thickness of about 200 [nm] and an impurity concentration of about 4 × 10 ²⁰ [atoms / cm ³ ]. A polycrystalline silicon film is formed by chemical vapor deposition, and then a silicon oxide film 69 having a thickness of about 50 [nm] is formed on the entire surface of the polycrystalline silicon film by chemical vapor deposition.

  Next, the silicon oxide film 69 and the polycrystalline silicon film are sequentially patterned to form a control gate electrode 66 on the interlayer insulating film 61, a dummy wiring 67 on the element isolation region, and the gate. A gate electrode 68 is formed on the insulating film 64 and the gate insulating film 65. The steps so far are shown in FIG.

  Next, a mask M52 is formed which covers the second and third element formation regions and is open on the first region. The mask M52 is formed by a photolithography technique using a photoresist film.

Next, using the mask M52 as an etching mask, the interlayer insulating film 61 and the floating gate material 70 are sequentially dry-etched to form the floating gate electrode 70. Thereafter, the mask M51 is used as an impurity introduction mask, and arsenic is selectively introduced into the first element formation region by an ion implantation method as a pair of n-type semiconductor regions serving as a source region and a drain region. 71 is formed. Arsenic is introduced under the condition that the final introduction amount is about 1 × 10 ¹⁵ [atoms / cm ² ] and the energy amount at the introduction is 50 [KeV]. By this step, the nonvolatile memory element QF1 is almost completed.

  Next, boron is selectively introduced into the second element formation region by an ion implantation method to form a pair of p-type semiconductor regions 72 as a source region and a drain region, and then the third element formation is performed. As an impurity, phosphorus is selectively introduced into the region by an ion implantation method to form a pair of n-type semiconductor regions 73 which are a source region and a drain region. The steps so far are shown in FIG.

  Next, sidewall spacers 74 that cover the side surfaces of the gate electrode 68 are formed, and sidewall spacers 74 that cover the electrode side surfaces of the nonvolatile memory element QF1 are formed. The sidewall spacer 74 is formed by forming an insulating film made of a silicon nitride film on the entire surface of the p-type semiconductor substrate 1 and then performing anisotropic etching such as RIE on the insulating film.

  Next, boron as an impurity is selectively introduced into the second element formation region by an ion implantation method to form a pair of p-type semiconductor regions 75 which are a source region and a drain region. Thereafter, phosphorus as an impurity is selectively introduced into the third element formation region by an ion implantation method to form a pair of n-type semiconductor regions 76 which are a source region and a drain region. Become.

  Thereafter, the microcomputer is formed by forming an interlayer insulating film, connection holes, metal wirings, and the like.

  In the present embodiment, the step at the edge of the element isolation region between the third element formation region and the buried insulating film 55 is 5 [nm]. The gate breakdown voltage and sub-shresh characteristics of the field effect transistor Q7 were not deteriorated, and were consistent with the characteristics when the high-voltage field effect transistor was not formed, confirming the effectiveness of the present invention.

  In the present embodiment, in the step shown in FIG. 30, the gate insulating film 65 made of a thermal oxide film having a thickness of 5 [nm] is formed on the third element formation region by performing the thermal oxidation process. Immediately after that, by adding a nitriding treatment at 900 ° C. in nitric oxide (NO), the reliability of the gate insulating film 65 can be further improved.

(Embodiment 4)
In this embodiment, an example in which the present invention is applied to a semiconductor integrated circuit device having two types of field effect transistors and nonvolatile memory elements having different gate insulating film thicknesses will be described with reference to FIGS. This will be described using a cross-sectional view).

  First, in FIG. 33, a trench 94 is formed in an element isolation region on the main surface of the p-type semiconductor substrate 91 and a buried insulating film 95 is formed in the trench 94 to insulate and isolate the element formation regions. A deep n-type well region 96 is formed in the first element formation region of the main surface of the substrate 91, and then a p-type well region 97 is formed in the first and third element formation regions of the main surface of the p-type semiconductor substrate 91. After that, an n-type well region 98 is formed in a second element formation region on the main surface of the p-type semiconductor substrate 91, and then a thermal oxidation process is performed to store nonvolatile memory on the first element formation region. A state in which a gate insulating film (tunnel insulating film) 99 of the element is formed is shown.

Next, a floating layer made of a polycrystalline silicon film having a thickness of about 50 [nm] and an impurity concentration of about 4 × 10 ²⁰ [atoms / cm ³ ] on the entire surface of the p-type semiconductor substrate 91 including the element formation region. A gate material 100 is formed by a chemical vapor deposition method, and then a mask M90 made of a photoresist film covering the first element formation region and having openings on the second and third element formation regions is formed. Thereafter, the floating gate material 100 is etched using the mask M90, and then the gate insulating film 99 on the second and third element formation regions is removed by a wet etching method. The steps so far are shown in FIG.

  Next, after removing the mask M90 by ashing, a thermal oxidation process is performed to form a thermal oxide film 101 having a thickness of 4 [nm] on the second and third element formation regions. A deposited film (interlayer insulating film) 102 made of a silicon oxide film having a thickness of 16 [nm] is formed on the entire surface of the p-type semiconductor substrate 91 including the thermal oxide film 101 by chemical vapor deposition. In this step, the gate insulating film 103 made of the thermal oxide film 101 and the deposited film 102 is formed on the second element formation region, and the interlayer insulating film made of the deposited film 102 is formed on the floating gate material 100. .

  Next, a mask M91 made of a photoresist film covering the first and second element formation regions and having an opening on the third element formation region is formed, and then, on the third element formation region The deposited film 102 and the thermal oxide film 101 are removed by a wet etching method. In this step, since the buried insulating film 95 is covered with the deposited film 102, the buried insulating film 95 is not etched until the deposited film 102 is removed. For example, the mask M91 is formed so that the end thereof is positioned on the buried insulating film 95. The steps so far are shown in FIG.

Next, after removing the mask M91 by ashing, a thermal oxidation process is performed to form a gate insulating film 104 made of a thermal oxide film having a thickness of 5 nm on the third element formation region. Polycrystal having a thickness of about 200 [nm] and an impurity concentration of about 4 × 10 ²⁰ [atoms / cm ³ ] over the entire surface of the p-type semiconductor substrate 91 including the gate insulating film 103 and the gate insulating film 104. A silicon film 105 is formed by chemical vapor deposition, and then a silicon oxide film 106 having a thickness of about 50 [nm] is formed on the entire surface of the polycrystalline silicon film by chemical vapor deposition. The steps so far are shown in FIG.

  Next, the silicon oxide film 106 and the polycrystalline silicon film 105 are patterned to form a control gate electrode 107 on the interlayer insulating film (deposited film 102), and on the gate insulating film 103 and the gate insulating film. A gate electrode 108 is formed on the film 104, and then a mask M92 made of a photoresist film covering the second and third element formation regions and having an opening on the first element formation region is formed. The steps so far are shown in FIG.

  Next, using the mask M92 as an etching mask, the deposited film 102 and the floating gate material 100 are sequentially patterned to form the floating gate electrode 109.

  Next, an impurity is selectively introduced into the first element formation region by an ion implantation method to form a pair of n-type semiconductor regions 110 which are a source region and a drain region. In this step, the nonvolatile memory element QF2 is formed. Thereafter, sidewall spacers 111 made of a nitride film having a thickness of 80 [nm] are formed on the side surfaces of the gate electrode 108 and the electrode side surfaces of the nonvolatile memory element QF2.

  Next, an impurity is selectively introduced into the second element formation region by ion implantation to form a pair of p-type semiconductor regions 112, thereby forming a field effect transistor Q8.

  Next, by selectively introducing impurities into the third element formation region by ion implantation to form a pair of n-type semiconductor regions 113, a field effect transistor Q9 is formed as shown in FIG. The Thereby, the main part of the semiconductor integrated circuit device of this embodiment is completed. Thereafter, the interlayer insulating film, the connection hole, and the metal wiring are formed to complete the manufacturing process of this embodiment.

  In the present embodiment, the step in the element isolation region between the third element formation region and the buried insulating film 25 is 10 [nm], which is reduced to about one third of that in the prior art. Further, even when the gate insulating film 103 of the field effect transistor Q8 and the interlayer insulating film of the nonvolatile memory element QF2 are formed of the same deposited film, normal transistor operation and memory cell operation without deterioration in reliability can be realized. .

  In the present embodiment, since the deposited film 102 which is the gate insulating film 103 of the field effect transistor Q8 and the interlayer insulating film (deposited film 102) of the nonvolatile memory element QF2 are formed in the same process, the semiconductor integrated circuit device The number of manufacturing steps can be reduced.

(Embodiment 5)
In the present embodiment, an example in which the present invention is applied to a DRAM (semiconductor integrated circuit device) using a 0.25 micron manufacturing technique will be described.

  FIG. 39 is a cross-sectional view showing a schematic configuration of a DRAM which is Embodiment 5 of the present invention, and shows a memory cell storing 1-bit information and a field effect transistor constituting a peripheral circuit.

  As shown in FIG. 39, the DRAM of this embodiment has a configuration mainly including a p-type semiconductor substrate 121 made of single crystal silicon.

  A plurality of element formation regions are formed on the p-type semiconductor substrate 121. Each of the plurality of element formation regions is defined by a groove 124 formed in the element isolation region on the main surface of the p-type semiconductor substrate 121 and a buried insulating film 125 embedded in the groove 124, and is insulated from each other. (Electrically separated). A deep n-type well region 126 and a p-type well region 127 are formed in the memory cell portion of the p-type semiconductor substrate 121, and a p-type well region 127 is formed in the peripheral circuit portion of the p-type semiconductor substrate 121.

  A memory cell for storing 1-bit information is composed of a series circuit of a field effect transistor Q10 for selecting a memory cell and a capacitor element MC for storing information, and is arranged in a region where the word line WL and the data line DL intersect. Has been.

  The field effect transistor Q10 is configured in the first element formation region on the main surface of the p-type semiconductor substrate 1. The field effect transistor Q10 is composed of an n-channel MISFET and mainly includes a p-type well region 127 used as a channel formation region, a gate insulating film 130, a gate electrode 132, a pair of n regions that are a source region and a drain region. A type semiconductor region 133 is formed.

  The capacitive element MC has a stack structure in which a dielectric film 141 and an electrode 142 are sequentially stacked on an electrode 140. The electrode 140 is electrically connected to one n-type semiconductor region 133 of the field effect transistor Q10 through a conductive plug 139 embedded in the interlayer insulating film 138 and a conductive plug 136 embedded in the interlayer insulating film 135. . The other n-type semiconductor region 133 of the field effect transistor Q10 is electrically connected to the data line DL via the conductive plug 136.

  The field effect transistor Q11 constituting the peripheral circuit is configured in the second element formation region on the main surface of the p-type semiconductor substrate 121. The field effect transistor Q11 is composed of an n-channel MISFET and mainly includes a p-type well region 127 used as a channel formation region, a gate insulating film 131, a gate electrode 132, a pair of n regions that are a source region and a drain region. A type semiconductor region 134 is formed. Each of the wirings 137 is electrically connected to each of the pair of n-type semiconductor regions 134 through a conductive plug 136 embedded in the interlayer insulating film 135.

  The gate insulating film 130 of the field effect transistor Q10 of the memory cell is formed of a thermal oxide film 128 and a deposited film 129. The thermal oxide film 128 is formed with a thickness of about 2 [nm], and the deposited film 129 is formed with a thickness of about 6 [nm]. The gate insulating film 131 of the field effect transistor Q11 constituting the peripheral circuit is formed of a thermal oxide film having a thickness of about 4.5 [nm]. Each of the gate insulating film 130 and the gate insulating film 131 is formed by the manufacturing method described in the above embodiment.

In the present embodiment, the step in the element isolation region between the second element formation region and the buried insulating film 125 is 4 [nm]. When the gate insulating film of the field effect transistor of the memory cell is formed of a normal thermal oxide film, the step at the end of the element isolation region between the second element formation region and the buried insulating film 125 is 10 [nm]. Therefore, it was reduced to a half by the present invention. As a result, the gate defect density of the low-voltage field-effect transistor Q11 can be greatly reduced from the conventional 0.8 / cm ² to 0.3 / cm ² , resulting in a 20% improvement in the memory manufacturing yield. We were able to. Further, the gate breakdown voltage of the low voltage field effect transistor Q11 was also improved by 15%. According to this embodiment, the effectiveness of the DRAM of the present invention can be confirmed, and it has been found that the industrial influence is very large.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Of course.

  For example, the present invention can be applied to a semiconductor integrated circuit device having four or more types of field effect transistors having different gate insulating film thicknesses.

1 is a schematic plan view showing a schematic configuration of two field effect transistors mounted on a semiconductor integrated circuit device that is Embodiment 1 of the present invention. It is sectional drawing cut in the position of the AA line shown in FIG. It is sectional drawing cut in the position of the BB line shown in FIG. It is sectional drawing cut | disconnected in the position of CC line shown in FIG. It is sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is sectional drawing which shows schematic structure of the three field effect transistors mounted in the semiconductor integrated circuit device which is Embodiment 2 of this invention. It is sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is a block diagram which shows schematic structure of the microcomputer (semiconductor integrated circuit device) which is Embodiment 3 of this invention. It is sectional drawing which shows schematic structure of the three field effect transistors mounted in the said microcomputer. It is sectional drawing for demonstrating the manufacturing method of the said microcomputer. It is sectional drawing for demonstrating the manufacturing method of the said microcomputer. It is sectional drawing for demonstrating the manufacturing method of the said microcomputer. It is sectional drawing for demonstrating the manufacturing method of the said microcomputer. It is sectional drawing for demonstrating the manufacturing method of the said microcomputer. It is sectional drawing for demonstrating the manufacturing method of the said microcomputer. It is sectional drawing for demonstrating the manufacturing method of the said microcomputer. It is sectional drawing for demonstrating the manufacturing method of the said microcomputer. It is sectional drawing for demonstrating the manufacturing method of the semiconductor integrated circuit device which is Embodiment 4 of this invention. It is sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is sectional drawing which shows schematic structure of DRAM (semiconductor integrated circuit device) which is Embodiment 5 of this invention. It is sectional drawing for demonstrating the prior art. It is sectional drawing for demonstrating the prior art. It is sectional drawing for demonstrating the prior art. It is sectional drawing for demonstrating the prior art. It is sectional drawing for demonstrating the prior art. It is the figure which compared the breakdown voltage distribution of the capacitor in trench type element isolation, and the breakdown voltage distribution of the capacitor in LOCOS element isolation. It is the figure which compared the subshesh characteristic of the field effect transistor in trench type element isolation, and the subshesh characteristic of the field effect transistor in LOCOS element isolation.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... P-type semiconductor substrate, 2 ... Thermal silicon oxide film, 3 ... Mask, 4 ... Groove, 5 ... Embedded insulating film, 6 ... P-type well region, 7 ... N-type well region, 8 ... Thermal oxide film, 9 ... Deposited film, 10, 11 ... Gate insulating film, 12 ... Gate electrode, 13 ... Silicon oxide film, 14, 17 ... Pair of p-type semiconductor regions, 15, 18 ... Pair of n-type semiconductor regions, 16 ... Side wall spacers , 19 ... interlayer insulating film, 20 ... wiring, Q1, Q2 ... field effect transistor, 21 ... p-type semiconductor substrate, 22 ... thermal silicon oxide film, 24 ... groove, 25 ... buried insulating film, 26 ... p-type well region 27, 29 ... thermal oxide film, 28, 30 ... deposited film, 31, 32, 33 ... gate insulating film, 34 ... gate electrode, 35 ... silicon oxide film, 36, 37, 38, 40, 41, 42 ... pair. N-type semiconductor region, 39 ... sidewall spacer, 43 ... interlayer break Film 44, wiring, Q3, Q4, Q5 ... field effect transistor, 51 ... p-type semiconductor substrate, 52 ... thermal oxide film, 54 ... groove, 55 ... buried insulating film, 56, 58 ... n-type well region, 57 ... p-type well region, 59 ... gate insulating film, 60 ... polycrystalline silicon film, 61 ... interlayer insulating film, 62 ... thermal oxide film, 63 ... deposited film, 64,65 ... gate insulating film, 66 ... control gate electrode , 67 ... dummy wiring, 68 ... gate electrode, 69 ... silicon oxide film, 70 ... floating gate electrode, 71, 73, 76 ... pair of n-type semiconductor regions, 72, 75 ... pair of p-type semiconductor regions, 74 ... side Wall spacer, 80 ... microcomputer, 81 ... processor unit, 82 ... clock oscillator, 83 ... data input / output circuit unit, 84 ... RAM unit, 85 ... ROM unit, 86 ... power supply unit, 87 ... input Data bus, QF1... Nonvolatile memory element, Q6, Q7... Field effect transistor, 91... P-type semiconductor substrate, QF2. ... field effect transistor, C ... capacitor element.

Claims (6)

A first field effect transistor in which a gate insulating film is formed on a first element formation region of a main surface of a semiconductor substrate;
A semiconductor integrated circuit having a second field effect transistor having a gate insulating film formed on the second element formation region of the main surface of the semiconductor substrate with a thickness smaller than that of the gate insulating film of the first field effect transistor; A circuit device manufacturing method comprising:
(A) A trench is formed in an element isolation region on a main surface of the semiconductor substrate to isolate each of the first element formation region and the second element formation region, and the semiconductor substrate including the inside of the trench Depositing an insulating film on the main surface by vapor deposition, and forming the buried insulating film in the trench by polishing the deposited insulating film;
(B) forming a thermal oxide film on the first element formation region and the second element formation region of the semiconductor substrate;
(C) A deposited film having a thickness larger than that of the thermal oxide film is formed on the main surface of the semiconductor substrate including the thermal oxide film in the first element formation region and the second element formation region. Forming by a growth method;
(D) The deposited film and the thermal oxide film on the second element formation region are etched by etching using a mask that exposes the second element formation region and the surrounding region on the buried insulating film. Removing, and
(E) After the step (d), a thermal oxide film having a thickness larger than that of the thermal oxide film in the first element formation region is formed on the second element formation region, and the second element formation region is formed. Forming a gate insulating film of the second field-effect transistor on the element formation region;
Have
The gate insulating film of the first field effect transistor has a thermal oxide film on the first element formation region and a deposited film having a thickness thicker than the thermal oxide film,
The method of manufacturing a semiconductor integrated circuit device, wherein the gate insulating film of the first field effect transistor is formed to be thicker than the gate insulating film of the second field effect transistor. In the manufacturing method of the semiconductor integrated circuit device according to claim 1,
The first field effect transistor constitutes a memory cell selection field effect transistor of a memory cell,
The method of manufacturing a semiconductor integrated circuit device, wherein the memory cell is configured by connecting the first field effect transistor and a capacitive element in series. In the manufacturing method of the semiconductor integrated circuit device according to claim 1,
A method of manufacturing a semiconductor integrated circuit device, wherein an operating potential of the second field effect transistor is lower than an operating potential of the first field effect transistor. A first field effect transistor in which a gate insulating film is formed on a first element formation region of a main surface of a semiconductor substrate;
A semiconductor integrated circuit having a second field effect transistor having a gate insulating film formed on the second element formation region of the main surface of the semiconductor substrate with a thickness smaller than that of the gate insulating film of the first field effect transistor; In the circuit device,
Each of the first element formation region and the second element formation region is insulated and isolated by a groove formed in an element isolation region on the main surface of the semiconductor substrate and a buried insulating film embedded in the groove. ,
The first gate insulating film of a field effect transistor is made of a thermal oxide film and the deposited film, and the thickness of the thermal oxide film of the first field effect transistor, from the deposited film of the first field effect transistor Is also made thin,
The gate insulating film of the second field effect transistor is made of a thermal oxide film, and the film thickness of the second thermal oxide film of a field effect transistor, the thickness of the thermal oxide film of the first field effect transistor A semiconductor integrated circuit device characterized in that it is configured to be thicker. The semiconductor integrated circuit device according to claim 4,
The first field effect transistor constitutes a memory cell selection field effect transistor of a memory cell,
2. The semiconductor integrated circuit device according to claim 1, wherein the memory cell is configured by connecting the first field effect transistor and a capacitive element in series. The semiconductor integrated circuit device according to claim 4,
2. The semiconductor integrated circuit device according to claim 1, wherein an operating potential of the second field effect transistor is lower than an operating potential of the first field effect transistor.

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